Electrostatic protection structure and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to an electrostatic protection structure and a memory. The electrostatic protection structure comprises: a substrate, and a first well region, a second well region and a third well region which are sequentially arranged in the substrate; a first reverse type doped region and a first same type doped region which are arranged in the first well region; a second reverse type doped region, a third reverse type doped region and a second same type doped region which are arranged in the second well region; a fourth reverse type doped region and a third same type doped region which are arranged in the third well region; wherein the first reverse type doped region and the third reverse type doped region are used for connecting a first signal end, the second reverse type doped region and the fourth reverse type doped region are used for connecting a second signal end, and the first same type doped region, the second same type doped region and the third same type doped region are electrically connected, so as to design an electrostatic protection structure with small design area, low trigger voltage and strong electrostatic protection capability, thereby meeting the electrostatic protection requirements of low-voltage high-speed memory products.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to an electrostatic discharge (ESD) protection structure and a memory. Background Technology

[0002] To protect integrated circuits from the damage caused by static electricity, electrostatic discharge (ESD) protection is usually applied. For Dynamic Random Access Memory (DRAM), the increasingly advanced manufacturing processes of modern semiconductors have resulted in shorter and shallower channel lengths and junction depths for transistors in the memory.

[0003] In addition, due to the application of silicides and LDD structures (LDD structure is a low-doped drain region set near the drain in the channel, so that the low-doped drain region also bears part of the voltage, this structure can prevent the hot electron degradation effect), the oxide layer of transistors in memory is becoming thinner and thinner, the window for designing electrostatic discharge protection circuits in memory is becoming smaller and smaller, and the design of electrostatic discharge protection circuits faces increasing challenges.

[0004] For advanced semiconductor manufacturing processes, conventionally used electrostatic discharge (ESD) protection devices are no longer sufficient to further reduce capacitance. Low-voltage, high-speed integrated circuit products, such as next-generation DRAM, require ESD protection devices with low trigger voltage, low capacitance, and fast startup speed. To meet these requirements, a new ESD protection structure must be designed. Summary of the Invention

[0005] This disclosure provides an electrostatic discharge (ESD) protection structure and memory, which integrates a thyristor and a diode in the same well region structure. This design results in a small area, low trigger voltage, and strong ESD protection capability, meeting the ESD protection requirements of low-voltage high-speed integrated circuit products.

[0006] One embodiment of this disclosure provides an electrostatic discharge (ESD) protection structure, including: a substrate, and a first well region, a second well region, and a third well region continuously disposed in the substrate, wherein the doping type of the first well region is different from that of the second well region, and the doping type of the first well region is the same as that of the third well region; a first inversion doped region and a first homotype doped region are disposed within the first well region, and the doping concentration of the first inversion doped region is greater than that of the first well region, and the doping concentration of the first homotype doped region is greater than that of the first well region; a second inversion doped region, a third inversion doped region, and a second homotype doped region are disposed within the second well region, and the doping concentration of the second inversion doped region is greater than that of the first well region. The doping concentration of the first inversion doped region is greater than that of the second well region, the doping concentration of the third inversion doped region is greater than that of the second well region, and the doping concentration of the second homotype doped region is greater than that of the second well region; the fourth inversion doped region and the third homotype doped region are disposed within the third well region, and the doping concentration of the fourth inversion doped region is greater than that of the third well region, and the doping concentration of the third homotype doped region is greater than that of the third well region; wherein, the first inversion doped region and the third inversion doped region are used to connect to the first signal terminal, the second inversion doped region and the fourth inversion doped region are used to connect to the second signal terminal, and the first homotype doped region, the second homotype doped region and the third homotype doped region are electrically connected.

[0007] In addition, the first well region, the second well region, and the third well region are continuously arranged in the first direction; the first inversion doped region, the second inversion doped region, the third inversion doped region, and the fourth inversion doped region are spaced apart in the first direction; and the first homotype doped region, the second homotype doped region, and the third homotype doped region are spaced apart in the first direction.

[0008] In addition, the first isomorphic doped region, the second isomorphic doped region, and the third isomorphic doped region are spaced apart in the first direction, including: the first isomorphic doped region is located on the side of the first inversion doped region away from the second well region in the first direction; the second isomorphic doped region is located between the second inversion doped region and the third inversion doped region in the first direction; and the third isomorphic doped region is located on the side of the fourth inversion doped region away from the second well region in the first direction.

[0009] In addition, the first isomorphic doped region, the second isomorphic doped region, and the third isomorphic doped region are spaced apart in the first direction, including: the first isomorphic doped region is disposed in the first direction on the side of the first inversion doped region near the second well region; the second isomorphic doped region is disposed in the first direction between the second inversion doped region and the third inversion doped region; and the third isomorphic doped region is disposed in the first direction on the side of the fourth inversion doped region near the second well region.

[0010] In addition, the first well region, the second well region, and the third well region are continuously arranged in the first direction; the first inversion doped region, the second inversion doped region, the third inversion doped region, and the fourth inversion doped region are spaced apart in the first direction; the first homotype doped region and the first inversion doped region are adjacent to each other in the second direction; the second homotype doped region, the second inversion doped region, and the third inversion doped region are adjacent to each other in the second direction; and the third homotype doped region and the fourth inversion doped region are adjacent to each other in the second direction.

[0011] In addition, the first homomorphic doped region, the second homomorphic doped region, and the third homomorphic doped region are spaced apart in the first direction.

[0012] In addition, the electrostatic discharge (ESD) protection structure also includes: a fourth isomorphic doped region disposed in the first well region, with a doping concentration greater than that of the first well region; a fifth isomorphic doped region disposed in the second well region, with a doping concentration greater than that of the second well region; and a sixth isomorphic doped region disposed in the third well region, with a doping concentration greater than that of the third well region; wherein the fourth, fifth, and sixth isomorphic doped regions are electrically connected. A diode is formed by the fourth isomorphic doped region in parallel with the first isomorphic doped region, a diode is formed by the fifth isomorphic doped region in parallel with the second isomorphic doped region, and a diode is formed by the sixth isomorphic doped region in parallel with the third isomorphic doped region, thereby reducing the current / voltage required for the diode circuit in the ESD protection circuit to conduct, and further reducing the trigger voltage required for the ESD protection structure to perform ESD protection.

[0013] Furthermore, the first and fourth isomorphic doped regions are symmetrically arranged based on the first inversion doped region; the second and fifth isomorphic doped regions are symmetrically arranged based on the second and third inversion doped regions; and the third and sixth isomorphic doped regions are symmetrically arranged based on the fourth inversion doped region. By symmetrically arranging the first and fourth isomorphic doped regions, diodes with identical device parameters and connected in parallel are formed based on the first and fourth isomorphic doped regions, facilitating the control of the electrostatic discharge (ESD) performance of the ESD device through diode parameters during design. Similarly, by symmetrically arranging the second and fifth isomorphic doped regions, diodes with identical device parameters and connected in parallel are formed based on the second and fifth isomorphic doped regions, facilitating the control of the ESD performance of the ESD device through diode parameters during design. Likewise, by symmetrically arranging the third and sixth isomorphic doped regions, diodes with identical device parameters and connected in parallel are formed based on the third and sixth isomorphic doped regions, facilitating the control of the ESD performance of the ESD device through diode parameters during design.

[0014] In addition, the first and fourth homomorphic doped regions are electrically connected, and the third and sixth homomorphic doped regions are electrically connected.

[0015] In addition, the second and fifth isomorphic doped regions are electrically connected.

[0016] Furthermore, the doping concentrations of the first and fourth isomorphic doped regions are the same; the doping concentrations of the second and fifth isomorphic doped regions are the same; and the doping concentrations of the third and sixth isomorphic doped regions are the same. By setting the doping concentrations of the first and fourth isomorphic doped regions to be the same, diodes with identical device parameters and connected in parallel can be formed based on the first and fourth isomorphic doped regions. This facilitates the control of the electrostatic discharge (ESD) protection performance of the ESD protection device through diode parameters during design. Similarly, by setting the doping concentrations of the second and fifth isomorphic doped regions to be the same, diodes with identical device parameters and connected in parallel can be formed based on the second and fifth isomorphic doped regions. This facilitates the control of the ESD protection performance of the ESD protection device through diode parameters during design. And similarly, by setting the doping concentrations of the third and sixth isomorphic doped regions to be the same, diodes with identical device parameters and connected in parallel can be formed based on the third and sixth isomorphic doped regions. This facilitates the control of the ESD protection performance of the ESD protection device through diode parameters during design.

[0017] In addition, the first and third well regions are N-type wells, and the second well region is a P-type well; the first isotype doped region, the third isotype doped region, the second inversion doped region, and the third inversion doped region are N-type doped regions; the second isotype doped region, the first inversion doped region, and the fourth inversion doped region are P-type doped regions.

[0018] In addition, the electrostatic discharge protection structure also includes a deep well region disposed in the substrate, and the first well region, the second well region and the third well region are disposed in the deep well region; by disposing the electrostatic discharge protection structure in the deep well region, the noise impact on the electrostatic discharge protection structure during operation is reduced.

[0019] In addition, the deep well region is an N-type well.

[0020] Another embodiment of this disclosure also provides a memory, including an electrostatic protection circuit disposed based on the electrostatic protection structure provided in the above embodiments.

[0021] The electrostatic discharge (ESD) protection structure provided in this embodiment has the following effects: the ESD protection function circuit is based on the increased voltage difference after the diode path is turned on, thereby reducing the trigger voltage required for the ESD protection structure to perform ESD protection; and the ESD protection structure is used to protect against bidirectional static electricity between the first signal terminal A and the second signal terminal B, with strong ESD protection capability; this embodiment also further reduces the layout area of ​​the ESD protection structure by designing the thyristor and diode in the same well region. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figures 1-5 This is a schematic diagram of the layout structure of an electrostatic protection structure provided in an embodiment of the present disclosure;

[0024] Figure 6 This is a schematic diagram of the circuit structure of an electrostatic protection structure provided in an embodiment of the present disclosure;

[0025] Figure 7 A schematic cross-sectional view of an electrostatic protection structure provided in an embodiment of the present disclosure in the first direction x.

[0026] Figure 8 A schematic diagram of the circuit structure of the electrostatic protection structure provided in an embodiment of the present disclosure, showing the cross-sectional structure in the first direction x.

[0027] Figure 9 A schematic diagram of the electrostatic discharge protection circuit in a memory provided in another embodiment of this disclosure;

[0028] Figure 10 and Figure 11 This is a schematic diagram of the clamping circuit in an electrostatic protection circuit provided in another embodiment of the present disclosure. Detailed Implementation

[0029] As the background technology shows, conventionally used electrostatic discharge (ESD) protection devices are no longer sufficient to further reduce capacitance. Low-voltage, high-speed integrated circuit products, such as next-generation DRAM, require ESD protection devices to have characteristics such as low trigger voltage, low capacitance, and fast startup speed. To meet these requirements, a new ESD protection structure must be designed.

[0030] One embodiment of this disclosure provides an electrostatic discharge (ESD) protection structure that integrates a thyristor and a diode within the same well region structure. This structure features a small design area, low trigger voltage, and strong ESD protection capability, meeting the ESD protection requirements of low-voltage, high-speed integrated circuit products.

[0031] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0032] Figures 1-5 This is a schematic diagram of the layout structure of the electrostatic protection structure provided in this embodiment. Figure 6 This is a schematic diagram of the circuit structure of the electrostatic protection structure provided in this embodiment. Figure 7 This is a schematic cross-sectional view of the electrostatic protection structure provided in this embodiment along the first direction x. Figure 8 The circuit structure diagram of the electrostatic protection structure provided in this embodiment is shown in the cross-sectional view along the first direction x. The electrostatic protection structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0033] refer to Figures 1-5 Electrostatic protection structure, including:

[0034] The substrate 100, and a first well region 101, a second well region 102 and a third well region 103 are continuously disposed in the substrate 100, wherein the doping type of the first well region 101 is different from that of the second well region 102, and the doping type of the first well region 101 is the same as that of the third well region 103.

[0035] In one example, if the first well region 101 is N-type doped, i.e., an N-type well region, then the second well region 102 is P-type doped, i.e., a P-type well region, and the third well region 103 is N-type doped, i.e., an N-type well region; if the first well region 101 is P-type doped, i.e., a P-type well region, then the second well region 102 is N-type doped, i.e., an N-type well region, and the third well region 103 is P-type doped, i.e., a P-type well region.

[0036] A first inversion-doped region 201 and a first homo-doped region 301 are disposed within a first well region 101, wherein the doping concentration of the first inversion-doped region 201 is greater than the doping concentration of the first well region 101, and the doping concentration of the first homo-doped region 301 is greater than the doping concentration of the first well region 101. Specifically, the doping type of the first inversion-doped region 201 is different from the doping type of the first well region 101, while the doping type of the first homo-doped region 301 is the same as the doping type of the first well region 101.

[0037] The second inversion-doped region 202, the third inversion-doped region 203, and the second isomorphic-doped region 302 are disposed within the second well region 102. The doping concentration of the second inversion-doped region 202 is greater than that of the second well region 102, the doping concentration of the third inversion-doped region 203 is greater than that of the second well region 102, and the doping concentration of the second isomorphic-doped region 302 is greater than that of the second well region 102. Specifically, the doping type of the second inversion-doped region 202 is different from that of the second well region 102, the doping type of the third inversion-doped region 203 is different from that of the second well region 102, and the doping type of the second isomorphic-doped region 302 is the same as that of the second well region 102.

[0038] A fourth inversion-doped region 204 and a third isomorphic-doped region 303 are disposed within the third well region 103, with the doping concentration of the fourth inversion-doped region 204 being greater than that of the third well region 103, and the doping concentration of the third isomorphic-doped region 303 being greater than that of the third well region 103. Specifically, the doping type of the fourth inversion-doped region 204 is different from that of the third well region 103, while the doping type of the third isomorphic-doped region 303 is the same as that of the third well region 103.

[0039] The first inversion doped region 201 and the third inversion doped region 203 are used to connect to the first signal terminal A, the second inversion doped region 202 and the fourth inversion doped region 204 are used to connect to the second signal terminal B, and the first isotype doped region 301, the second isotype doped region 302 and the third isotype doped region 303 are electrically connected.

[0040] In this embodiment, the first well region 101 and the third well region 103 are N-type wells, the second well region 102 is a P-type well, and the first isotype doped region 301, the third isotype doped region 303, the second inversion doped region 202, and the third inversion doped region 203 are N-type doped regions; the second isotype doped region 302, the first inversion doped region 201, and the fourth inversion doped region 204 are P-type doped regions. The following description of this embodiment will use the above type as an example for specific explanation; it should be noted that in other embodiments, the first well region and the third well region can also be set as P-type wells, the second well region as an N-type well, the first isotype doped region, the third isotype doped region, the second inversion doped region, and the third inversion doped region as P-type doped regions; and the second isotype doped region, the first inversion doped region, and the fourth inversion doped region as N-type doped regions.

[0041] For the electrostatic discharge protection structure provided in this embodiment, please refer to the specific circuit diagram. Figure 6 The principle is as follows:

[0042] The first inversion-doped region 201, the first well region 101, and the second well region 102 constitute a PNP-type first transistor 401, and the second inversion-doped region 202, the first well region 101, and the second well region 102 constitute an NPN-type second transistor 402. The gate of the first transistor 401 is connected to one terminal of the source / drain of the second transistor 402, and the gate of the second transistor 402 is connected to one terminal of the source / drain of the first transistor 401. The other terminal of the source / drain of the first transistor 401 is a first signal terminal A, and the other terminal of the source / drain of the second transistor 402 is a second signal terminal B, thereby achieving… Figure 6 The thyristor circuit from the first signal terminal A to the second signal terminal B is shown.

[0043] The first inversion-doped region 201 and the first well region 101 constitute a first diode 501. Since the first well region 101 and the first homomorphic doped region 301 are of the same type of doped region, the current loss from the first well region 101 to the first homomorphic doped region 301 is small (negligible). Furthermore, the first homomorphic doped region 301 and the second homomorphic doped region 302 are electrically connected. The second homomorphic doped region 302 and the second well region 102 are of the same type of doping, therefore the current loss from the second homomorphic doped region 302 to the second well region 101 is small (negligible). The second well region 102 and the second inversion-doped region 202 constitute a second diode 502, thereby achieving… Figure 6 The diode circuit shown is connected from the first signal terminal A to the second signal terminal B.

[0044] The fourth inversion-doped region 204, the third well region 103, and the second well region 102 constitute a PNP-type third transistor 403, and the third inversion-doped region 202, the third well region 103, and the second well region 102 constitute an NPN-type fourth transistor 404. The gate of the third transistor 403 is connected to one terminal of the source / drain of the fourth transistor 404, and the gate of the fourth transistor 404 is connected to one terminal of the source / drain of the third transistor 403. The other terminal of the source / drain of the third transistor 403 is the second signal terminal B, and the other terminal of the source / drain of the fourth transistor 404 is the first signal terminal A, thereby achieving… Figure 6 The thyristor circuit from the second signal terminal B to the first signal terminal A is shown.

[0045] The fourth inversion-doped region 204 and the third well region 103 constitute the third diode 503. Since the third well region 103 and the third homo-doped region 303 are of the same type of doped region, the current loss from current transfer from the third well region 103 to the third homo-doped region 303 is small (negligible). Furthermore, the third homo-doped region 303 and the second homo-doped region 302 are electrically connected. The second homo-doped region 302 and the second well region 102 are of the same type of doping, therefore the current loss from current transfer from the second homo-doped region 302 to the second well region 101 is small (negligible). The second well region 102 and the third inversion-doped region 203 constitute the fourth diode 504, thereby achieving… Figure 6 The diode circuit shown connects the second signal terminal B to the first signal terminal A.

[0046] for Figure 6 As shown in the circuit analysis, the electrostatic discharge (ESD) protection structure provided in this embodiment, when there is static electricity between the first signal terminal A and the second signal terminal B, means that since the diode path only requires current to pass through two PN junctions, while the transistor path requires current to pass through four PN junctions, the conduction voltage of the diode path is less than that of the transistor path. Therefore, the current will preferentially conduct the diode path, and then conduct the transistor path based on the voltage difference after the diode path is turned on. Specifically, when there is static electricity in the A→B direction, the current first conducts the path containing the first diode 501 and the second diode 502. After the diode path is turned on, the voltage difference between the first signal terminal A and the second signal terminal B is increased, thereby turning on the path containing the third transistor 403 and the fourth transistor 404, thus achieving the ESD protection effect. When there is static electricity in the B→A direction, the current first conducts the path containing the third diode 503 and the fourth diode 504. After the diode path is turned on, the voltage difference between the second signal terminal B and the first signal terminal A is increased, thereby turning on the path containing the first transistor 401 and the second transistor 402, thus achieving the ESD protection effect.

[0047] Therefore, it can be seen that in the electrostatic discharge (ESD) protection structure provided in this embodiment, the ESD protection function circuit is based on the increased voltage difference after the diode path is turned on, thereby reducing the trigger voltage required for the ESD protection structure to perform ESD protection; and the ESD protection structure is used to protect against bidirectional static electricity between the first signal terminal A and the second signal terminal B, with strong ESD protection capability; this embodiment also further reduces the layout area of ​​the ESD protection structure by designing the thyristor and diode in the same well region.

[0048] This embodiment also provides several layout configuration methods for electrostatic protection structures, as follows:

[0049] In some embodiments, reference Figure 1 and Figure 2The first well region 101, the second well region 102 and the third well region 103 are continuously arranged in the first direction x, the first inversion doped region 201, the second inversion doped region 202, the third inversion doped region 203 and the fourth inversion doped region 204 are spaced apart in the first direction x, and the first homotype doped region 301, the second homotype doped region 302 and the third homotype doped region 303 are spaced apart in the first direction x.

[0050] Specifically, refer to Figure 1 In one example, the first isomorphic doped region 301, the second isomorphic doped region 302, and the third isomorphic doped region 303 are spaced apart in the first direction x, including: the first isomorphic doped region 301 is disposed on the side of the first inversion doped region 302 away from the second well region 102 in the first direction x; the second isomorphic doped region 302 is disposed between the second inversion doped region 202 and the third inversion doped region 203 in the first direction x; and the third isomorphic doped region 303 is disposed on the side of the fourth inversion doped region 204 away from the second well region 102 in the first direction x. (See reference) Figure 2 In one example, the first isomorphic doped region 301, the second isomorphic doped region 302, and the third isomorphic doped region 303 are spaced apart in the first direction x, including: the first isomorphic doped region 301 is disposed in the first direction x on the side of the first inversion doped region 201 near the second well region 102; the second isomorphic doped region 302 is disposed in the first direction x between the second inversion doped region 202 and the third inversion doped region 203; and the third isomorphic doped region 303 is disposed in the first direction x on the side of the fourth inversion doped region 204 near the second well region 102.

[0051] In some embodiments, reference Figures 3-5 The first well region 101, the second well region 102, and the third well region 103 are continuously arranged in the first direction x, and the first inversion doped region 201, the second inversion doped region 202, the third inversion doped region 203, and the fourth inversion doped region 204 are spaced apart in the first direction x; the first isomorphic doped region 301 and the first inversion doped region 201 are adjacent to each other in the second direction y; the second isomorphic doped region 302, the second inversion doped region 202, and the third inversion doped region 203 are adjacent to each other in the second direction; the third isomorphic doped region 303 and the fourth inversion doped region 204 are adjacent to each other in the second direction y.

[0052] Further, refer to Figure 3 The first, second, and third isomorphic doped regions are spaced apart from each other along the first direction x. It should be noted that in other embodiments, the first, second, and third isomorphic doped regions may also be disposed on either side of the first, second, third, and fourth inversion doped regions along the first direction x.

[0053] In some embodiments, reference Figure 4 and Figure 5 The electrostatic discharge (ESD) protection structure further includes: a fourth isomorphic doped region 304 disposed in the first well region 101, wherein the doping concentration of the fourth isomorphic doped region 304 is greater than the doping concentration of the first well region 101; specifically, the doping type of the fourth isomorphic doped region 304 is the same as the doping type of the first well region 101. A fifth isomorphic doped region 305 disposed in the second well region 102, wherein the doping concentration of the fifth isomorphic doped region 305 is greater than the doping concentration of the second well region 102; specifically, the doping type of the fifth isomorphic doped region 305 is the same as the doping type of the second well region 102. A sixth isomorphic doped region 306 disposed in the third well region 103, wherein the doping concentration of the sixth isomorphic doped region 306 is greater than the doping concentration of the third well region 103; specifically, the doping type of the sixth isomorphic doped region 306 is the same as the doping type of the third well region 103. The fourth isomorphic doped region 304, the fifth isomorphic doped region 305, and the sixth isomorphic doped region 306 are electrically connected. A diode is formed in parallel with the first isomorphic doped region 301 through the fourth isomorphic doped region 304, a diode is formed in parallel with the second isomorphic doped region 302 through the fifth isomorphic doped region 305, and a diode is formed in parallel with the third isomorphic doped region 303 through the sixth isomorphic doped region 306. This reduces the current / voltage required for the diode circuit to conduct in the electrostatic discharge (ESD) protection circuit, thereby further reducing the trigger voltage required for the ESD protection structure to perform ESD protection.

[0054] in, Figure 4 In the electrostatic discharge protection structure shown, the first isomorphic doped region 301 and the fourth isomorphic doped region 304 are symmetrically arranged based on the first inversion doped region 201; the second isomorphic doped region 302 and the fifth isomorphic doped region 305 are symmetrically arranged based on the second inversion doped region 202 and the third inversion doped region 203; and the third isomorphic doped region 303 and the sixth isomorphic doped region 306 are symmetrically arranged based on the fourth inversion doped region 204. By symmetrically arranging the first and fourth isomorphic doped regions 301 and 304, diodes with identical device parameters and connected in parallel are formed based on the first and fourth isomorphic doped regions 301 and 304, facilitating the control of the electrostatic discharge (ESD) performance of the ESD device through diode parameters during design. Similarly, by symmetrically arranging the second and fifth isomorphic doped regions 302 and 305, diodes with identical device parameters and connected in parallel are formed based on the second and fifth isomorphic doped regions 302 and 305, facilitating the control of the ESD performance of the ESD device through diode parameters during design. Furthermore, by symmetrically arranging the third and sixth isomorphic doped regions 303 and 306, diodes with identical device parameters and connected in parallel are formed based on the third and sixth isomorphic doped regions 303 and 306, facilitating the control of the ESD performance of the ESD device through diode parameters during design.

[0055] It should be noted that, in other embodiments, the first and fourth homomorphic doped regions can be disposed in the first well region at any position, the second and fifth homomorphic doped regions can be disposed in the second well region at any position, and the third and sixth homomorphic doped regions can be disposed in the third well region at any position.

[0056] Furthermore, in some embodiments, reference is made to... Figure 6 The first homomorphic doped region 301 and the fourth homomorphic doped region 304 are electrically connected, and the third homomorphic doped region 303 and the sixth homomorphic doped region 306 are electrically connected.

[0057] Furthermore, in some embodiments, the second homo-doped region 302 is electrically connected to the fifth homo-doped region 305.

[0058] In some embodiments, the doping concentration of the first homomorphic doped region 301 is the same as that of the fourth homomorphic doped region 304, the doping concentration of the second homomorphic doped region 302 is the same as that of the fifth homomorphic doped region 305, and the doping concentration of the third homomorphic doped region 303 is the same as that of the sixth homomorphic doped region 306. By setting the doping concentration of the first homomorphic doped region 301 and the fourth homomorphic doped region 304 to be the same, diodes with identical device parameters and connected in parallel are formed based on the first homomorphic doped region 301 and the fourth homomorphic doped region 304. This facilitates the control of the electrostatic protection performance of the electrostatic protection device through diode parameters during design. Similarly, by setting the doping concentration of the second homomorphic doped region 302 and the fifth homomorphic doped region 305 to be the same, diodes with identical device parameters and connected in parallel are formed based on the second homomorphic doped region 302 and the fifth homomorphic doped region 305. This facilitates the control of the electrostatic protection performance of the electrostatic protection device through diode parameters during design. Furthermore, by setting the doping concentration of the third homomorphic doped region 303 and the sixth homomorphic doped region 306 to be the same, diodes with identical device parameters and connected in parallel are formed based on the third homomorphic doped region 303 and the sixth homomorphic doped region 306. This facilitates the control of the electrostatic protection performance of the electrostatic protection device through diode parameters during design.

[0059] In some embodiments, reference Figure 7 , Figure 7 for Figures 1-5 A cross-sectional view of the first inversion doped region 201, the second inversion doped region 202, the third inversion doped region 303, and the fourth inversion doped region 304 in the first direction x. The transistor circuit formed by the first inversion doped region 201, the second inversion doped region 202, the third inversion doped region 303, the fourth inversion doped region 304, the first well region 101, the second well 102, and the third well region 103 is shown below. Figure 8As shown; the first inversion-doped region 201, the first well region 101, and the second well region 102 constitute a PNP-type first transistor 401, and the second inversion-doped region 202, the first well region 101, and the second well region 102 constitute an NPN-type second transistor 402; wherein, the gate of the first transistor 401 is connected to one terminal of the source / drain of the second transistor 402, and the gate of the second transistor 402 is connected to one terminal of the source / drain of the first transistor 401; the other terminal of the source / drain of the first transistor 401 is the first signal terminal A, and the other terminal of the source / drain of the second transistor 402 is the second signal terminal B, thereby realizing... Figure 6 The diagram shows a thyristor circuit from the first signal terminal A to the second signal terminal B. The fourth inversion-doped region 204, the third well region 103, and the second well region 102 constitute a PNP-type third transistor 403, and the third inversion-doped region 202, the third well region 103, and the second well region 102 constitute an NPN-type fourth transistor 404. The gate of the third transistor 403 is connected to one terminal of the source / drain of the fourth transistor 404, and the gate of the fourth transistor 404 is connected to one terminal of the source / drain of the third transistor 403. The other terminal of the source / drain of the third transistor 403 is the second signal terminal B, and the other terminal of the source / drain of the fourth transistor 404 is the first signal terminal A, thereby achieving… Figure 6 The thyristor circuit from the second signal terminal B to the first signal terminal A is shown.

[0060] Continue to refer to Figure 7 In some embodiments, the electrostatic discharge (ESD) protection structure further includes a deep well region 200 disposed in the substrate 100, wherein the first well region 101, the second well region 102, and the third well region 103 are disposed in the deep well region 200. By disposing the ESD protection structure in the deep well region 200, the noise impact on the ESD protection structure during operation is reduced. Further, based on the foregoing description in this embodiment, the first well region 101 and the third well region 103 are N-type wells, the second well region 102 is a P-type well, the first isotype doped region 301, the third isotype doped region 303, the second inversion doped region 202, and the third inversion doped region 203 are N-type doped regions; the second isotype doped region 302, the first inversion doped region 201, and the fourth inversion doped region 204 are P-type doped regions; correspondingly, in this embodiment, the substrate is a P-type substrate, and the deep well region 200 is an N-type well.

[0061] It should be noted that in other embodiments, if the first well region and the third well region are set as P-type wells, the second well region is set as an N-type well, the first isotype doped region, the third isotype doped region, the second inversion doped region and the third inversion doped region are set as P-type doped regions, and the second isotype doped region, the first inversion doped region and the fourth inversion doped region are set as N-type doped regions, then the substrate can also be set as an N-type substrate, and the deep well region is set as a P-type well.

[0062] The electrostatic protection structure provided in this embodiment is composed of... Figure 6 As shown in the circuit analysis, the electrostatic discharge (ESD) protection structure provided in this embodiment can achieve the following effect: when there is static electricity between the first signal terminal A and the second signal terminal B, since the diode path only requires current to pass through two PN junctions, while the transistor path requires current to pass through four PN junctions, the conduction voltage of the diode path is less than the conduction circuit of the transistor path. At this time, the current will preferentially conduct the diode path, and then conduct the transistor path based on the voltage difference after the diode path is turned on. Specifically, when there is static electricity in the A→B direction, the current first conducts the path where the first diode 501 and the second diode 502 are located. After the diode path is turned on, the voltage difference between the first signal terminal A and the second signal terminal B is increased, thereby turning on the path where the third transistor 403 and the fourth transistor 404 are located, so as to achieve the effect of ESD protection. When static electricity exists in the B→A direction, the current first conducts the path containing the third diode 503 and the fourth diode 504. After the diode path is turned on, the voltage difference between the second signal terminal B and the first signal terminal A is increased, thereby turning on the path containing the first transistor 401 and the second transistor 402 to achieve the effect of electrostatic discharge protection. In summary, the electrostatic discharge protection circuit is based on the increased voltage difference after the diode path is turned on, thereby reducing the trigger voltage required for the electrostatic discharge protection structure to perform electrostatic discharge protection. Moreover, the electrostatic discharge protection structure is used to protect against bidirectional static electricity between the first signal terminal A and the second signal terminal B, and has strong electrostatic discharge protection capability. In this embodiment, by designing the thyristor and diode in the same well region, the layout area of ​​the electrostatic discharge protection structure is further reduced.

[0063] It should be noted that the features disclosed in the electrostatic protection structure provided in the above embodiments can be arbitrarily combined without conflict to obtain new electrostatic protection structure embodiments.

[0064] Another embodiment of this disclosure provides a memory, including an electrostatic protection circuit based on the electrostatic protection structure provided in the above embodiments, to meet the electrostatic protection requirements of low-voltage high-speed memory products.

[0065] Figure 9 This is a schematic diagram of the electrostatic discharge (ESD) protection circuit in the memory provided in this embodiment. Figure 10 and Figure 11 This is a schematic diagram of the clamping circuit in the electrostatic discharge protection circuit provided in this embodiment. The memory provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0066] refer to Figure 9The electrostatic discharge (ESD) protection circuit includes: a high-level power supply terminal Vdd, a low-level power supply terminal Vss, a signal transmission terminal, and a core processing circuit CT. The signal transmission terminal includes a signal output terminal OUT and a signal input terminal IN. In this exemplary embodiment, the chip may include a first ESD protection structure ESD1, a second ESD protection structure ESD2, a third ESD protection structure ESD3, and a fourth ESD protection structure ESD4. The first ESD protection structure ESD1, the second ESD protection structure ESD2, the third ESD protection structure ESD3, and the fourth ESD protection structure ESD4 are configured based on the ESD protection structures provided in the above embodiments.

[0067] like Figure 9 As shown, the electrostatic discharge (ESD) protection circuit also includes a clamping circuit PCP, which is used to improve the ESD protection effect of the ESD protection circuit.

[0068] For the clamping circuit PCP, in one example, refer to Figure 10 The system includes a capacitor C, a resistor R, and an N-type transistor NM. The capacitor C is connected between the high-level power supply terminal Vdd and node M, the resistor R is connected between node M and the low-level power supply terminal Vss, the gate of the N-type transistor NM is connected to node M, the first terminal of the N-type transistor NM is connected to the high-level power supply terminal Vdd, and the second terminal of the N-type transistor NM is connected to the low-level power supply terminal Vss. The semiconductor substrate of the N-type transistor NM can be connected to the second terminal of the N-type transistor NM. When static electricity occurs at the high-level power supply terminal Vdd, the voltage at Vdd increases. Under the coupling effect of capacitor C, the potential of node M increases, and the N-type transistor NM turns on. The high-level power supply terminal Vdd can release static electricity to the low-level power supply terminal Vss through the N-type transistor NM. It should be understood that in other exemplary embodiments, the semiconductor substrate of the N-type transistor NM can also be connected to the gate of the N-type transistor NM, so that the N-type transistor NM can form a substrate driving transistor, which can be used to release a large electrostatic current. (Reference) Figure 11The clamping circuit may include a capacitor C, a resistor R, a P-type transistor PM, a first N-type transistor NM1, and a second N-type transistor NM2. The resistor R is connected between the high-level power supply terminal Vdd and the first node G1; the capacitor C is connected between the first node G1 and the low-level power supply terminal Vss; the first terminal of the P-type transistor PM is connected to the high-level power supply terminal Vdd, the second terminal is connected to the second node G2, and the gate is connected to the first node G1; the first terminal of the first N-type transistor NM1 is connected to the second node G2, the second terminal is connected to the low-level power supply terminal Vss, and the gate is connected to the first node G1; the first terminal of the second N-type transistor NM2 is connected to the high-level power supply terminal Vdd, the second terminal is connected to the low-level power supply terminal Vss, and the gate is connected to the second node G2. When static electricity occurs at the high-level power supply terminal Vdd, a high-frequency alternating current is formed between the high-level power supply terminal Vdd and the low-level power supply terminal Vss. Under the action of the high-frequency alternating current, the impedance of capacitor C decreases, the first node G1 is pulled low by the low-level power supply terminal Vss, the P-type transistor PM is turned on, the high-level power supply terminal Vdd inputs a high-level signal to the second node G2, the second N-type transistor NM2 is turned on, and the high-level power supply terminal Vdd releases static electricity to the low-level power supply terminal Vss through the second N-type transistor NM2.

[0069] Specifically, memory can be a storage cell or device based on a semiconductor device or component. For example, a memory device can be volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), etc.

[0070] In the memory provided in this embodiment, the electrostatic discharge (ESD) protection circuit is based on the increased voltage difference after the diode path is turned on, thereby reducing the trigger voltage required for the ESD protection structure to perform ESD protection; and the ESD protection structure is used to protect against bidirectional static electricity between the first signal terminal and the second signal terminal, with strong ESD protection capability; this embodiment also further reduces the layout area of ​​the ESD protection structure by designing the thyristor and diode in the same well region.

[0071] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. An electrostatic protection structure, characterized in that, include: A substrate, and a first well region, a second well region, and a third well region continuously disposed in the substrate, wherein the doping type of the first well region is different from that of the second well region, and the doping type of the first well region is the same as that of the third well region; A first inversion doped region and a first homotype doped region are disposed within the first well region, wherein the doping concentration of the first inversion doped region is greater than the doping concentration of the first well region, and the doping concentration of the first homotype doped region is greater than the doping concentration of the first well region. A second inversion doped region, a third inversion doped region, and a second homotype doped region are disposed within the second well region, wherein the doping concentration of the second inversion doped region is greater than the doping concentration of the second well region, the doping concentration of the third inversion doped region is greater than the doping concentration of the second well region, and the doping concentration of the second homotype doped region is greater than the doping concentration of the second well region. A fourth inversion doped region and a third homotype doped region are disposed within the third well region, wherein the doping concentration of the fourth inversion doped region is greater than the doping concentration of the third well region, and the doping concentration of the third homotype doped region is greater than the doping concentration of the third well region. The first inversion doped region and the third inversion doped region are used to connect to the first signal terminal, the second inversion doped region and the fourth inversion doped region are used to connect to the second signal terminal, and the first isomorphic doped region, the second isomorphic doped region and the third isomorphic doped region are electrically connected.

2. The electrostatic protection structure according to claim 1, characterized in that, include: The first well region, the second well region, and the third well region are arranged continuously in a first direction; The first inversion doped region, the second inversion doped region, the third inversion doped region, and the fourth inversion doped region are spaced apart in the first direction; The first isomorphic doped region, the second isomorphic doped region, and the third isomorphic doped region are spaced apart in the first direction.

3. The electrostatic protection structure according to claim 2, characterized in that, The first homomorphic doped region, the second homomorphic doped region, and the third homomorphic doped region are spaced apart in the first direction, including: The first isomorphic doped region is disposed on the side of the first inverse doped region away from the second well region in the first direction; The second isomorphic doped region is disposed between the second inversion doped region and the third inversion doped region in the first direction; The third isomorphic doped region is disposed in the first direction on the side of the fourth inverse doped region away from the second well region.

4. The electrostatic protection structure according to claim 2, characterized in that, The first homomorphic doped region, the second homomorphic doped region, and the third homomorphic doped region are spaced apart in the first direction, including: The first isomorphic doped region is disposed in the first direction on the side of the first inverse doped region near the second well region; The second isomorphic doped region is disposed between the second inversion doped region and the third inversion doped region in the first direction; The third isomorphic doped region is disposed in the first direction on the side of the fourth inverse doped region near the second well region.

5. The electrostatic protection structure according to claim 1, characterized in that, include: The first well region, the second well region, and the third well region are arranged continuously in a first direction; The first inversion doped region, the second inversion doped region, the third inversion doped region, and the fourth inversion doped region are spaced apart in the first direction; The first homotype doped region and the first inversion doped region are arranged adjacent to each other in the second direction; The second isomorphic doped region is disposed adjacent to the second inverse doped region and the third inverse doped region in a second direction; The third isomorphic doped region and the fourth inverse doped region are arranged adjacent to each other in the second direction.

6. The electrostatic protection structure according to claim 5, characterized in that, The first isomorphic doped region, the second isomorphic doped region, and the third isomorphic doped region are spaced apart in the first direction.

7. The electrostatic protection structure according to any one of claims 1 to 6, characterized in that, Also includes: A fourth isomorphic doped region is disposed in the first well region, and the doping concentration of the fourth isomorphic doped region is greater than the doping concentration of the first well region. A fifth isomorphic doped region is disposed in the second well region, wherein the doping concentration of the fifth isomorphic doped region is greater than the doping concentration of the second well region; A sixth isomorphic doped region is disposed in the third well region, and the doping concentration of the sixth isomorphic doped region is greater than the doping concentration of the third well region. The fourth isomorphic doped region, the fifth isomorphic doped region, and the sixth isomorphic doped region are electrically connected.

8. The electrostatic protection structure according to claim 7, characterized in that, include: The first isomorphic doped region and the fourth isomorphic doped region are symmetrically arranged based on the first inverse doped region; The second isomorphic doped region and the fifth isomorphic doped region are symmetrically arranged based on the second inversion doped region and the third inversion doped region; The third and sixth isomorphic doped regions are symmetrically arranged based on the fourth inverse doped region.

9. The electrostatic protection structure according to claim 7, characterized in that, The first homomorphic doped region and the fourth homomorphic doped region are electrically connected, and the third homomorphic doped region and the sixth homomorphic doped region are electrically connected.

10. The electrostatic protection structure according to claim 9, characterized in that, The second isomorphic doped region and the fifth isomorphic doped region are electrically connected.

11. The electrostatic protection structure according to claim 7, characterized in that, include: The doping concentration of the first isomorphic doped region is the same as the doping concentration of the fourth isomorphic doped region; The doping concentration of the second isomorphic doped region is the same as that of the fifth isomorphic doped region; The doping concentration of the third isomorphic doped region is the same as that of the sixth isomorphic doped region.

12. The electrostatic protection structure according to claim 1, characterized in that, include: The first well region and the third well region are N-type wells, and the second well region is a P-type well; The first isotype doped region, the third isotype doped region, the second inversion doped region, and the third inversion doped region are N-type doped regions; The second isotype doped region, the first inversion doped region, and the fourth inversion doped region are P-type doped regions.

13. The electrostatic protection structure according to claim 1 or 12, characterized in that, Also includes: A deep well region is disposed in the substrate, and the first well region, the second well region and the third well region are disposed in the deep well region.

14. The electrostatic protection structure according to claim 13, characterized in that, The deep well region is an N-type well.

15. A memory, characterized in that, Includes an electrostatic protection circuit based on the electrostatic protection structure described in any one of claims 1 to 14.

Images