Display panel and preparation method thereof

Abstract

The application discloses a display panel and a preparation method thereof. The display panel comprises a substrate, a first electrode arranged on the substrate, an active layer arranged on the first electrode, the active layer comprising a first contact part, a second contact part and a channel part, the channel part being arranged between the first contact part and the second contact part, wherein the first contact part is connected to the first electrode, and a part of the first electrode corresponding to the channel part serves as a light shielding part; a gate electrode arranged on the active layer and corresponding to the channel part; and a second electrode arranged on the gate electrode and connected to the second contact part; wherein the resistance values of the first contact part and the second contact part are both smaller than the resistance value of the channel part, so that a high electric field between the gate electrode of a TFT device and the first contact part can be avoided when the driving voltage is increased, the existence of hot carriers is reduced, and the threshold voltage (Vth) of the TFT is prevented from changing.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the same. Background Technology

[0002] Mini / Micro LED (MLED) display technology is entering a phase of accelerated development and can be used in small to medium-sized, high-value-added display applications. Compared to OLED screens, MLED displays offer superior performance in terms of cost, contrast, high brightness, and slim form factor.

[0003] In MLED display technology, backplane technology is a key technology. The RC load of the bottom gate is 1.5x to 3x or more than that of the top gate. The top-gate structure has a capacitor with a three-layer metal sandwich structure, which can achieve a larger capacitance in a smaller space. On the one hand, the backplane of the Micro-LED top-gate structure usually requires 10 mask layers, which greatly increases the cost of the backplane and is not conducive to the mass production of micro-LED display technology. On the other hand, because LEDs require high current, as the driving voltage of the thin-film transistor (TFT) increases, a high electric field is generated between the gate and drain regions, which excites hot carriers. Due to the influence of hot carriers, the threshold voltage (Vth) of the TFT changes.

[0004] Existing top-gate self-aligned devices can be mainly divided into top-gate top contact (gate and source / drain are located on the same side of the active layer) and top-gate bottom contact (gate and source / drain are located on opposite sides of the active layer). However, when the source and drain use the same metal material, their linewidth and line spacing are greatly affected by the manufacturing process. In particular, most metals are etched using wet etching, and the difference between the etched dimensions and the photolithographic dimensions is large. Even with methods such as ion implantation, it is difficult to achieve narrow-channel devices within the precision limits of the exposure machine. Therefore, as the driving voltage increases, the electric field in the gate and drain regions of the TFT device is relatively large, and due to the presence of hot carriers, it is easy to cause threshold voltage drift. Summary of the Invention

[0005] The purpose of this invention is to provide a display panel and its manufacturing method to solve the technical problem of threshold voltage drift caused by the generation of a high electric field between the gate and drain regions due to the increase of driving voltage, which excites hot carriers.

[0006] To achieve the above objectives, the present invention provides a display panel, comprising: a substrate; a first electrode disposed on the substrate; an active layer disposed on the first electrode, the active layer including a first contact portion, a second contact portion, and a channel portion, the channel portion being disposed between the first contact portion and the second contact portion, wherein the first contact portion is connected to the first electrode, and the portion of the first electrode corresponding to the channel portion serves as a light-shielding portion; a gate electrode disposed on the active layer and corresponding to the channel portion; and a second electrode disposed on the gate electrode and connected to the second contact portion; wherein the resistance values ​​of the first contact portion and the second contact portion are both less than the resistance value of the channel portion.

[0007] Furthermore, the first contact portion is a drain contact portion, and the second contact portion is a source contact portion; the first electrode is a drain electrode, and the second electrode is a source electrode; the resistance of the second contact portion is less than the resistance of the channel portion, and the resistance of the first contact portion is less than the resistance of the second contact portion.

[0008] Furthermore, the display panel further includes: a buffer layer disposed on the first electrode and extending to the surface of the substrate, wherein the buffer layer has a first through-hole for exposing the first electrode, and the first contact portion is connected to the first electrode through the first through-hole; a gate insulating layer disposed on the active layer, wherein the gate is disposed on the gate insulating layer; a dielectric layer covering the gate and extending to the surface of the buffer layer, wherein the dielectric layer has a second through-hole for exposing the second contact portion; a second electrode disposed on the dielectric layer, and the second electrode is connected to the second contact portion through the second through-hole; a passivation layer covering the second electrode and extending to the surface of the dielectric layer; a third through-hole penetrating the passivation layer and the dielectric layer for exposing the first contact portion; and a pixel electrode disposed on the second electrode and connected to the first contact portion through the third through-hole.

[0009] Furthermore, the orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the second electrode on the substrate; the orthographic projection of the gate on the substrate falls entirely within the orthographic projection range of the pixel electrode on the substrate; the second electrode extends toward the first electrode and is flush with the side of the gate near the first electrode.

[0010] Furthermore, the first contact portion is a source contact portion, and the second contact portion is a drain contact portion; the first electrode is a source electrode, and the second electrode is a drain electrode; the resistance of the first contact portion is less than the resistance of the channel portion, and the resistance of the second contact portion is less than the resistance of the first contact portion.

[0011] Furthermore, the display panel further includes: a buffer layer disposed on the first electrode and extending to the surface of the substrate, wherein the buffer layer has a first through-hole for exposing the first electrode, and the first contact portion is connected to the first electrode through the first through-hole; a gate insulating layer disposed on the active layer, wherein the gate is disposed on the gate insulating layer; a dielectric layer covering the gate and extending to the surface of the buffer layer, wherein the dielectric layer has a second through-hole for exposing the second contact portion; a second electrode disposed on the dielectric layer, and the second electrode is connected to the second contact portion through the second through-hole; a passivation layer covering the second electrode and extending to the surface of the dielectric layer; a fourth through-hole penetrating the passivation layer for exposing the second electrode; and a pixel electrode disposed on the second electrode and connected to the second electrode through the fourth through-hole.

[0012] Furthermore, the orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the second electrode on the substrate; the second electrode extends toward the first electrode and is flush with the side of the gate near the first electrode.

[0013] To achieve the above objectives, the present invention also provides a method for manufacturing a display panel, comprising the following steps:

[0014] A first metal layer is deposited on a substrate, and the first metal layer is patterned to form a first electrode;

[0015] An active layer thin film is deposited on the first electrode, and the active layer thin film is patterned to form an active layer; the active layer includes a first contact portion, a second contact portion, and a channel portion, the channel portion being disposed between the first contact portion and the second contact portion, wherein the first contact portion is connected to the first electrode, and the portion of the first electrode corresponding to the channel portion is a light-shielding portion.

[0016] A second metal layer is deposited on the active layer, and the second metal layer is patterned to form a gate. The gate is disposed on the active layer and is disposed corresponding to the channel portion.

[0017] Plasma treatment is performed on the first contact portion and the second electrode contact portion of the active layer that are not covered by the gate, so that the active layer achieves the first conductor formation.

[0018] A third metal layer is deposited on the gate, and the third metal layer is patterned to form a second electrode. The second electrode is disposed on the gate and connected to the second contact portion.

[0019] The active layer not covered by the first or second electrode is subjected to ion implantation, thereby enabling the active layer to achieve a second conductor.

[0020] Furthermore, the first contact portion is a drain contact portion, and the second contact portion is a source contact portion; the first electrode is a drain electrode, and the second electrode is a source electrode; the resistance of the source contact portion is less than the resistance of the channel portion, and the resistance of the drain contact portion is less than the resistance of the source contact portion; wherein, in the step of achieving the second conductor formation of the active layer, the active layer not covered by the second electrode is subjected to ion implantation treatment, so that the active layer achieves the second conductor formation; wherein, the method for fabricating the display panel further includes: depositing a pixel electrode on the second electrode, and the pixel electrode is connected to the first contact portion; wherein, the orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the second electrode on the substrate; the second electrode extends toward the first electrode and is flush with the side of the gate near the first electrode.

[0021] Furthermore, the first contact portion is a source contact portion, and the second contact portion is a drain contact portion; the first electrode is a source electrode, and the second electrode is a drain electrode; the resistance of the source contact portion is less than the resistance of the channel portion, and the resistance of the drain contact portion is less than the resistance of the source contact portion; wherein, in the step of achieving the second conductor formation of the active layer, the active layer not covered by the first electrode is subjected to ion implantation treatment, so that the active layer achieves the second conductor formation; wherein, the method for fabricating the display panel further includes: depositing a pixel electrode on the second electrode, and the pixel electrode being connected to the second electrode; wherein, the orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the second electrode on the substrate; the second electrode extends toward the first electrode and is flush with the side of the gate electrode near the first electrode.

[0022] The technical advantage of this invention lies in providing a display panel and its fabrication method, wherein the source and drain are formed of different metal layers and are located on opposite sides of the active layer, such that the drain is in contact with the bottom of the active layer and the source is in contact with the top of the active layer; or, the source is in contact with the bottom of the active layer and the drain is in contact with the top of the active layer. A certain amount of ion implantation is performed on the drain contact portion of the active layer to achieve re-conductivity, thereby reducing the resistance of the drain contact portion and making the resistance of the source contact portion less than the resistance of the channel portion, and the resistance of the drain contact portion less than the resistance of the source contact portion. Thus, as the driving voltage of the TFT increases, a high electric field is avoided between the gate and drain contact portions of the TFT device, reducing the presence of hot carriers and thereby preventing fluctuations in the threshold voltage (Vth) of the TFT. Attached Figure Description

[0023] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0024] Figure 1 This is a schematic diagram of the structure of the display panel provided in Embodiment 1 of this application.

[0025] Figure 2 This is a flowchart of a method for preparing a display panel according to Embodiment 1 of this application.

[0026] Figure 3 This is a schematic diagram of the formation structure of the first electrode provided in Embodiment 1 of this application.

[0027] Figure 4 This is a schematic diagram of the formation structure of the first through hole provided in Embodiment 1 of this application.

[0028] Figure 5 This is a schematic diagram of the formation structure of the active layer provided in Embodiment 1 of this application.

[0029] Figure 6 This is a schematic diagram of the formation structure of the gate insulating layer and the gate provided in Embodiment 1 of this application.

[0030] Figure 7 This is a schematic diagram of the formation structure of the second through hole provided in Embodiment 1 of this application.

[0031] Figure 8 This is a schematic diagram of the formation structure of the second electrode provided in Embodiment 1 of this application.

[0032] Figure 9 This is a schematic diagram of the formation structure of the third through hole provided in Embodiment 1 of this application.

[0033] Figure 10 This is a schematic diagram of the structure of the display panel provided in Embodiment 2 of this application.

[0034] Figure 11 This is a flowchart of a method for preparing a display panel according to Embodiment 2 of this application.

[0035] Figure 12 This is a schematic diagram of the formation structure of the fourth through hole provided in Embodiment 2 of this application.

[0036] The components in the attached diagram are labeled as follows:

[0037] 1. Substrate; 21. First electrode; 22. Light-shielding portion; 3. Buffer layer; 4. Active layer; 5. Gate insulating layer; 6. Gate; 7. Dielectric layer; 81. Second electrode; 82. Bonding terminal; 9. Passivation layer; 10. Pixel electrode; 41. First contact portion; 42. Second contact portion; 43. Channel portion; 101. First through hole; 102. Second through hole; 103. Third through hole; 104. Fourth through hole. Detailed Implementation

[0038] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0039] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0040] This application provides a display panel in some embodiments, including a substrate 1, a first electrode 21, an active layer 4, a gate 6, and a second electrode 81. The first electrode 21 is disposed on the substrate 1. The active layer 4 is disposed on the first electrode 21, and includes a first contact portion 41, a second contact portion 42, and a channel portion 43. The channel portion 43 is disposed between the first contact portion 41 and the second contact portion 42. The first contact portion 41 is connected to the first electrode 21, and the portion of the first electrode 21 corresponding to the channel portion 43 serves as a light-shielding portion. The gate 6 is disposed on the active layer 4 and is disposed corresponding to the channel portion 43. The second electrode 81 is disposed on the gate 6 and is connected to the second contact portion 41. In some embodiments of this application, the resistance values ​​of the first contact portion 41 and the second contact portion 42 are both less than the resistance value of the channel portion 43. Thus, as the driving voltage of the TFT increases, a high electric field is avoided between the gate and drain contacts of the TFT device, reducing the presence of hot carriers and thereby preventing fluctuations in the threshold voltage (Vth) of the TFT. The following will provide a detailed description using specific embodiments.

[0041] Example 1

[0042] like Figure 1 As shown, this embodiment provides a display panel 1, including a substrate 1, a first electrode 21, a buffer layer 3, an active layer 4, a gate insulating layer 5, a gate 6, a dielectric layer 7, a second electrode 81, a passivation layer 9, and a pixel electrode 10.

[0043] Specifically, the first electrode 21 is disposed on the substrate 1, and the first electrode 21 is the drain electrode. The substrate 1 can be a glass substrate 1, and the material used for the first electrode 21 can be any one of the following materials: Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO. In this embodiment, the first electrode 21 is the drain electrode.

[0044] A buffer layer 3 is disposed on the first electrode 21 and extends to the upper surface of the substrate 1. The buffer layer 3 has a first through-hole 101 for exposing the first electrode 21. The buffer layer 3 can be made of SiOx or a SiNx / SiOx stack.

[0045] An active layer 4 is disposed on the first electrode 21. The active layer 4 includes a first contact portion 41, a second contact portion 42, and a channel portion 43, with the channel portion 43 disposed between the first contact portion 41 and the second contact portion 42. The active layer 4 can be made of a high-leakage-stability crystalline oxide semiconductor, amorphous oxide semiconductor, or other types of semiconductors, such as IGZO, IGTO, IGZO, IGO, IZO, AlZO, TZO, and other metal oxides with low leakage current. The first contact portion 41 is the drain contact portion, and the second contact portion 42 is the source contact portion.

[0046] In this embodiment, the first contact portion 41 is connected to the first electrode 21 through the first through hole 101, and the portion of the first electrode 21 corresponding to the channel portion 43 serves as the light-shielding portion 22.

[0047] The gate insulating layer 5 is disposed on the active layer 4. The material used for the gate insulating layer 5 can be any of the following materials: SiOx, SiNx, Al2O3 / SiNx / SiOx, SiOx / SiNx / SiOx.

[0048] The gate 6 is disposed on the gate insulating layer 5 and is disposed corresponding to the channel portion 43. In this embodiment, the gate 6 and the channel portion 43 are directly opposite each other. The material used for the gate 6 can be any of the following materials: Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO.

[0049] The dielectric layer 7 covers the gate 6 and extends to the upper surface of the buffer layer 3. The dielectric layer 7 has a second via 102 for exposing the second contact portion 42. The dielectric layer 7 can be made of SiOx or a SiOx / SiNx / SiOx stack.

[0050] The second electrode 81 is disposed on the dielectric layer 7, and the second electrode 81 is connected to the second contact portion 42 through the second through hole 102. In this embodiment, the second electrode 81 is the source electrode.

[0051] In this embodiment, the display panel 1 further includes bonding terminals 82, and a plurality of bonding terminals 82 are spaced apart on the dielectric layer 7 and are disposed on the same layer as the second electrode 81.

[0052] The materials used for the second electrode 81 and the bonding terminal 82 can be any one of the following materials: Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO.

[0053] In this embodiment, the resistance of the second contact portion 42 is less than the resistance of the channel portion 43, and the resistance of the first contact portion 41 is less than the resistance of the second contact portion 42. In other words, the resistance of the source contact portion is less than the resistance of the channel portion 43, and the resistance of the drain contact portion is less than the resistance of the source contact portion.

[0054] Therefore, in the display panel 1 provided in this embodiment, the source and drain are formed of different metal layers and are located on opposite sides of the active layer 4, respectively. The drain is in contact with the bottom of the active layer 4, while the source is in contact with the top of the active layer 4. The gate 6 is correspondingly disposed with the channel portion 43 of the active layer 4, and the source extends toward the drain, with its edge flush with the edge of the gate near the drain. Simply put, the left side of the source is flush with the left side of the gate. During the first conductor formation, the source and drain contacts of the active layer 4 are plasma-treated using the gate 6 as a photomask. During the second conductor formation, the drain contacts of the active layer 4 are re-conducted by ion implantation based on the source pattern. This reduces the resistance of the drain contacts and makes the resistance of the source contacts less than that of the channel 43, and the resistance of the drain contacts less than that of the source contacts. As the driving voltage of the TFT increases, a high electric field is avoided between the gate 6 and the drain contacts of the TFT device, reducing the presence of hot carriers and thus preventing fluctuations in the threshold voltage (Vth) of the TFT.

[0055] The passivation layer 9 covers the second electrode 81 and the bonding terminal 82, and extends to the upper surface of the dielectric layer 7. The material used for the passivation layer 9 can be SiOx or a SiOx / SiNx / SiOx stack.

[0056] In this embodiment, the display panel 1 further includes a third via 103, which penetrates the passivation layer 9 and the dielectric layer 7 to expose the first contact portion 41. The pixel electrode 10 is disposed on the second electrode 81 and is connected to the first contact portion 41 through the third via 103. The orthographic projection of the pixel electrode 10 on the substrate 1 at least partially overlaps with the orthographic projection of the second electrode 81 on the substrate 1, and the orthographic projection of the gate electrode 6 on the substrate 1 completely falls within the orthographic projection of the pixel electrode 10 on the substrate 1. In this embodiment, the pixel electrode 10 extends towards the source, and the orthographic projection of the pixel electrode 10 on the substrate 1 at least partially overlaps with the orthographic projection of the source electrode on the substrate 1. Thus, the channel portion 43 of the active layer 4 is completely enveloped by the drain, source, and pixel electrode 10, blocking external moisture from diffusing into the channel of the active layer 4 and improving device reliability.

[0057] In this embodiment, the passivation layer 9 has an opening for exposing the bonding terminal 82, which is used to place the LED chip (not shown) so that the bonding terminal 82 and the LED chip are electrically connected.

[0058] like Figure 2 As shown, this embodiment also provides a method for preparing a display panel 1, including the following steps S1-S7.

[0059] S1. A first metal layer is deposited on the substrate, and the first metal layer is patterned to form a first electrode 21. (See below) Figure 3 .

[0060] Specifically, a first metal layer is formed by depositing a metal material on a substrate 1, and the first metal layer is patterned to form a first electrode 21. The substrate 1 can be a glass substrate 1, and the metal material can be any of the following materials: Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO. The first electrode 21 is a drain electrode.

[0061] S2. An active layer thin film is deposited on the first electrode 21, and the active layer thin film is patterned to form active layer 4. (See below) Figure 5 .

[0062] The active layer 4 includes a first contact portion 41, a second contact portion 42, and a channel portion 43. The channel portion 43 is disposed between the first contact portion 41 and the second contact portion 42. The first contact portion 41 is connected to the first electrode 21, and the portion of the first electrode 21 corresponding to the channel portion 43 is a light-shielding portion 22. The first contact portion 41 is a drain contact portion, and the second contact portion 42 is a source contact portion.

[0063] Specifically, after the formation of the first electrode 21 and before the formation of the active layer 4, the process also includes:

[0064] A buffer layer 3 is deposited on the first electrode 21 and the light-shielding portion 22, and the buffer layer 3 extends to the upper surface of the substrate 1, see [reference]. Figure 4 .

[0065] The buffer layer 3 is perforated to create a first through hole 101, see [reference]. Figure 4 The first through hole 101 is used to expose the first electrode 21, and the first contact portion 41 is connected to the first electrode 21 through the first through hole 101. See [reference needed] Figure 5 .

[0066] In this embodiment, the active layer 4 is formed on the buffer layer 3. The first electrode 21 and the light-shielding part 22 are an integral structure. The material used for the buffer layer 3 can be SiOx or a SiNx / SiOx stack. The material used for the active layer 4 can be a crystalline oxide semiconductor with high migration and high stability, an amorphous oxide semiconductor, or other types of semiconductors, such as IGZO, IGTO, IGZO, IGO, IZO, AlZO, TZO, and other metal oxides with low leakage current.

[0067] S3. A second metal layer is deposited on the active layer 4, and the second metal layer is patterned to form a gate 6. The gate 6 is disposed on the active layer 4 and corresponds to the channel portion 43. (See below) Figure 6 .

[0068] The material used for the second metal layer can be any of the following: Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO.

[0069] After the formation of buffer layer 3 and before the formation of the second metal layer, the process also includes:

[0070] A gate insulating layer 5 is deposited on the active layer 4, and the gate insulating layer 5 is patterned using a top gate 6 self-alignment process. See [link to relevant documentation]. Figure 6 In this embodiment, the second metal layer is formed on the gate insulating layer 5. The material used for the gate insulating layer 5 can be any of the following materials: SiOx, SiNx, Al2O3 / SiNx / SiOx, SiOx / SiNx / SiOx.

[0071] S4. Plasma treatment is performed on the first contact portion 41 and the second electrode contact portion 42 of the active layer 4 that are not covered by the gate 6. The direction of the arrow in the figure is the direction of plasma treatment, so that the active layer 4 achieves the first conductor. Specifically, plasma treatment is performed on the active layer 4 from the top of the substrate 1 to its bottom, or in other words, plasma treatment is performed on the active layer 4 from the front side of the substrate 1 to the back side of the substrate 1, thereby achieving the first conductor of the active layer 4.

[0072] S5. A third metal layer is deposited on the gate 6 and patterned to form a second electrode 81. The second electrode 81 is disposed on the gate 6 and connected to the second contact portion 42. The second electrode 81 is the source electrode.

[0073] During the patterning process of the third metal layer, bonding terminals 82 are also formed on the same layer as the second electrode 81. Multiple bonding terminals 82 are spaced apart on the dielectric layer 7. (See [reference]). Figure 8 .

[0074] The material used for the third metal layer can be any one of the following: Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO.

[0075] After forming gate 6 and before forming the third metal layer, the process also includes:

[0076] A dielectric layer 7 is deposited on the gate 6, and vias are drilled in the dielectric layer 7, see [link to documentation]. Figure 7 .

[0077] The dielectric layer 7 covers the gate 6 and extends to the upper surface of the substrate 1. The dielectric layer 7 has a second via 102 for exposing the second contact portion 42. (See [reference]). Figure 7 The dielectric layer 7 can be made of SiOx or a SiOx / SiNx / SiOx stack.

[0078] S6. Ion implantation is performed on the active layer 4 not covered by the second electrode 8, so that the active layer 4 achieves a second conductor formation. See [link to documentation]. Figure 8 Specifically, ion implantation is performed on the active layer 4 from the top of the substrate 1 downwards. The arrow in the figure indicates the direction of ion implantation. In other words, ion implantation is performed on the active layer 4 from the front side of the substrate 1 to the back side of the substrate 1, thereby enabling the active layer 4 to achieve a second conductor.

[0079] During the first conductor formation, the source and drain contacts of the active layer 4 are plasma-treated using the gate 6 as a photomask. During the second conductor formation, the drain contacts of the active layer 4 are re-conducted by ion implantation based on the source pattern. This reduces the resistance of the drain contacts and makes the resistance of the source contacts less than that of the channel 43, and the resistance of the drain contacts less than that of the source contacts. As the driving voltage of the TFT increases, a high electric field is avoided between the gate 6 and the drain contacts of the TFT device, reducing the presence of hot carriers and thus preventing fluctuations in the threshold voltage (Vth) of the TFT.

[0080] S7. A pixel electrode 10 is deposited on the second electrode 81, and the pixel electrode 10 is connected to the first contact portion 41. (See below) Figure 1 .

[0081] After forming the second electrode 81 and the bonding terminal 82 and before forming the pixel electrode 10, the process also includes:

[0082] A passivation layer 9 is formed, which covers the second electrode 81 and the bonding terminal 82, and extends to the upper surface of the dielectric layer 7. See [reference needed]. Figure 9 .

[0083] A third via 103 is formed by drilling through the passivation layer 9 and the dielectric layer 7. (See below) Figure 9 The third through-hole 103 penetrates the passivation layer 9 and the dielectric layer 7, and the third through-hole 103 is used to expose the first contact portion 41.

[0084] In this process, a conductive layer is formed on the second electrode 81 by physical vapor deposition; then, the conductive layer is patterned to form the pixel electrode 10, see [link to documentation]. Figure 1 The pixel electrode 10 is connected to the first contact portion 41 through the third via 103. The orthographic projection of the pixel electrode 10 on the substrate 1 at least partially overlaps with the orthographic projection of the second electrode 81 on the substrate 1, and the orthographic projection of the gate 6 on the substrate 1 completely falls into the orthographic projection of the pixel electrode 10 on the substrate 1. Specifically, the pixel electrode 10 extends towards the source, and the orthographic projection of the pixel electrode 10 on the substrate 1 at least partially overlaps with the orthographic projection of the source on the substrate 1. Thus, the channel portion 43 of the active layer 4 is completely enveloped by the drain, source, and pixel electrode 10, blocking the diffusion path of external moisture into the channel of the active layer 4 and improving device reliability. It should be noted that this conductive layer can also serve as an oxide protective layer terminal of the COF bonding region, which will not be elaborated here.

[0085] In this embodiment, the passivation layer 9 can be made of SiOx or a SiOx / SiNx / SiOx stack. The pixel electrode 10 includes, but is not limited to, indium tin oxide.

[0086] In this embodiment, the resistance of the second contact portion 42 is less than the resistance of the channel portion 43, and the resistance of the first contact portion 41 is less than the resistance of the second contact portion 42. In other words, the resistance of the source contact portion is less than the resistance of the channel portion 43, and the resistance of the drain contact portion is less than the resistance of the source contact portion.

[0087] Therefore, in the display panel 1 provided in this embodiment, the source and drain are formed of different metal layers and are located on opposite sides of the active layer 4, respectively. The drain is in contact with the bottom of the active layer 4, while the source is in contact with the top of the active layer 4. The gate 6 is correspondingly disposed with the channel portion 43 of the active layer 4, and the side of the source extending towards the drain is flush with the side of the gate near the drain. Simply put, the left side of the source is flush with the left side of the gate. During the first conductor formation, the source and drain contacts of the active layer 4 are plasma-treated using the gate 6 as a photomask. During the second conductor formation, the drain contacts of the active layer 4 are re-conducted by ion implantation based on the source pattern. This reduces the resistance of the drain contacts and makes the resistance of the source contacts less than that of the channel 43, and the resistance of the drain contacts less than that of the source contacts. As the driving voltage of the TFT increases, a high electric field is avoided between the gate 6 and the drain contacts of the TFT device, reducing the presence of hot carriers and thus preventing fluctuations in the threshold voltage (Vth) of the TFT.

[0088] The display panel can be a Mini-LED display panel, a Micro-LED display panel, etc.

[0089] Example 2

[0090] This embodiment provides a display panel 1 and its manufacturing method, which includes most of the technical solutions of embodiment 1. The difference is that the first contact portion 41 is a source contact portion and the second contact portion 42 is a drain contact portion; the first electrode 21 is a source electrode and the second electrode 81 is a drain electrode; the pixel electrode 10 is disposed on the second electrode 81 and connected to the second electrode 81; the resistance of the first contact portion 41 is less than the resistance of the channel portion 43, and the resistance of the second contact portion 42 is less than the resistance of the first contact portion 41.

[0091] like Figure 10 As shown, the first electrode 21 is disposed on the substrate 1, and the first electrode 21 is the source electrode.

[0092] A buffer layer 3 is disposed on the first electrode 21 and extends to the upper surface of the substrate 1. The buffer layer 3 is provided with a first through hole 101 for exposing the first electrode 21.

[0093] An active layer 4 is disposed on the first electrode 21. The active layer 4 includes a first contact portion 41, a second contact portion 42, and a channel portion 43, with the channel portion 43 disposed between the first contact portion 41 and the second contact portion 42. The first contact portion 41 is the source contact portion, and the second contact portion 42 is the drain contact portion.

[0094] In this embodiment, the first contact portion 41 is connected to the first electrode 21 through the first through hole 101, and the portion of the first electrode 21 corresponding to the channel portion 43 serves as the light-shielding portion 22. The orthographic projection of the first electrode 21 on the substrate 1 does not overlap with the orthographic projection of the second contact portion 42 on the substrate 1.

[0095] The gate insulating layer 5 is disposed on the active layer 4.

[0096] The gate 6 is disposed on the gate insulating layer 5 and is disposed corresponding to the channel portion 43. In this embodiment, the gate 6 and the channel portion 43 are directly opposite each other.

[0097] The dielectric layer 7 covers the gate 6 and extends to the upper surface of the substrate 1. The dielectric layer 7 is provided with a second via 102 for exposing the second contact portion 42.

[0098] The second electrode 81 is disposed on the dielectric layer 7, and the second electrode 81 is connected to the second contact portion 42 through the second through hole 102. The second electrode 81 is the drain electrode.

[0099] In this embodiment, the display panel 1 further includes bonding terminals 82, and a plurality of bonding terminals 82 are spaced apart on the dielectric layer 7 and are disposed on the same layer as the second electrode 81.

[0100] In this embodiment, the resistance of the first contact portion 41 is less than the resistance of the channel portion 43, and the resistance of the second contact portion 42 is less than the resistance of the first contact portion 41. In other words, the resistance of the source contact portion is less than the resistance of the channel portion 43, and the resistance of the drain contact portion is less than the resistance of the source contact portion.

[0101] Therefore, in the display panel 1 provided in this embodiment, the source and drain are formed of different metal layers and are located on opposite sides of the active layer 4, respectively. The source is in contact with the bottom of the active layer 4, while the drain is in contact with the top of the active layer 4. The gate 6 is correspondingly disposed with the channel portion 43 of the active layer 4, and the drain extends toward the source, with its side flush with the side of the gate near the drain. Simply put, the left side of the drain is flush with the left side of the gate. During the first conductor formation, the source and drain contacts of the active layer 4 are plasma-treated using the gate 6 as a photomask. During the second conductor formation, the drain contacts of the active layer 4 are re-conducted by ion implantation based on the source pattern, thereby reducing the resistance of the drain contacts. The resistance of the source contacts is less than that of the channel 43, and the resistance of the drain contacts is less than that of the source contacts. In this way, as the driving voltage of the TFT increases, a high electric field is avoided between the gate 6 and the drain contacts of the TFT device, reducing the presence of hot carriers and thus preventing the threshold voltage (Vth) of the TFT from changing.

[0102] The passivation layer 9 covers the second electrode 81 and the bonding terminal 82, and extends to the upper surface of the dielectric layer 7.

[0103] In this embodiment, the display panel 1 further includes a fourth through-hole 104 that penetrates the passivation layer 9 to expose the second electrode 81. A pixel electrode 10 is disposed on the second electrode 81 and connected to the second electrode 81 through the fourth through-hole 104. The orthographic projection of the pixel electrode 10 on the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 21 on the substrate 1, and the orthographic projection of the pixel electrode 10 on the substrate 1 at least partially overlaps with the orthographic projection of the second electrode 81 on the substrate 1. The orthographic projection of the gate electrode 6 on the substrate 1 completely falls within the orthographic projection of the pixel electrode 10 on the substrate 1. In this embodiment, the pixel electrode 10 extends towards the source, and the orthographic projection of the pixel electrode 10 on the substrate 1 at least partially overlaps with the orthographic projection of the source electrode on the substrate 1. This ensures that most of the channel portion 43 of the active layer 4 is enveloped by the drain, source, and pixel electrode 10, blocking the diffusion path of external moisture into the channel of the active layer 4 and improving device reliability.

[0104] like Figure 11 As shown, this embodiment also provides a method for preparing a display panel 1 for manufacturing the display panel of embodiment 2, including the following steps S11-S17.

[0105] S11. A first metal layer is deposited on the substrate, and the first metal layer is patterned to form a first electrode 21. (See below) Figure 3 .

[0106] S12. An active layer thin film is deposited on the first electrode 21, and the active layer thin film is patterned to form active layer 4. (See below) Figure 5 .

[0107] The active layer 4 includes a first contact portion 41, a second contact portion 42, and a channel portion 43. The channel portion 43 is disposed between the first contact portion 41 and the second contact portion 42. The first contact portion 41 is connected to the first electrode 21, and the portion of the first electrode 21 corresponding to the channel portion 43 is a light-shielding portion 22. The first contact portion 41 is the source contact portion, and the second contact portion 42 is the drain contact portion.

[0108] Specifically, after the formation of the first electrode 21 and before the formation of the active layer 4, the process also includes:

[0109] A buffer layer 3 is deposited on the first electrode 21 and the light-shielding portion 22, and the buffer layer 3 extends to the upper surface of the substrate 1, see [reference]. Figure 4 .

[0110] The buffer layer 3 is perforated to create a first through hole 101, see [reference]. Figure 4 The first through hole 101 is used to expose the first electrode 21, and the first contact portion 41 is connected to the first electrode 21 through the first through hole 101. See [reference needed] Figure 5 .

[0111] In this embodiment, the active layer 4 is formed on the buffer layer 3. The first electrode 21 and the light-shielding part 22 are an integral structure.

[0112] S13. A second metal layer is deposited on the active layer 4, and the second metal layer is patterned to form a gate 6. The gate 6 is disposed on the active layer 4 and corresponds to the channel portion 43. (See below) Figure 6 .

[0113] After the formation of buffer layer 3 and before the formation of the second metal layer, the process also includes:

[0114] A gate insulating layer 5 is deposited on the active layer 4, and the gate insulating layer 5 is patterned using a top gate 6 self-alignment process. See [link to relevant documentation]. Figure 6 .

[0115] S14. Plasma treatment is performed on the first contact portion 41 and the second electrode contact portion 42 of the active layer 4 that are not covered by the gate 6. The direction of the arrow in the figure is the direction of plasma treatment, so that the active layer 4 achieves the first conductor. Specifically, plasma treatment is performed on the active layer 4 from the top of the substrate 1 to its bottom, or in other words, plasma treatment is performed on the active layer 4 from the front side of the substrate 1 to the back side of the substrate 1, thereby achieving the first conductor of the active layer 4.

[0116] S15. A third metal layer is deposited on the gate 6 and patterned to form a second electrode 81. The second electrode 81 is disposed on the gate 6 and connected to the second contact portion 42. The second electrode 81 is the drain electrode.

[0117] During the patterning process of the third metal layer, bonding terminals 82 are also formed on the same layer as the second electrode 81. Multiple bonding terminals 82 are spaced apart on the dielectric layer 7. (See [reference]). Figure 12 .

[0118] After forming gate 6 and before forming the third metal layer, the process also includes:

[0119] A dielectric layer 7 is deposited on the gate 6, and vias are drilled in the dielectric layer 7, see [link to documentation]. Figure 7 .

[0120] The dielectric layer 7 covers the gate 6 and extends to the upper surface of the substrate 1. The dielectric layer 7 has a second through-hole 102 for exposing the second contact portion 42.

[0121] S16. Ion implantation is performed on the active layer 4 not covered by the first electrode 21, so that the active layer 4 achieves a second conductor formation. See [link to documentation]. Figure 12 Specifically, ion implantation is performed on the active layer 4 from below the substrate 1 upwards. The arrows in the figure indicate the direction of ion implantation. Alternatively, ion implantation can be performed on the active layer 4 from the back side of the substrate 1 towards the front side. Furthermore, the orthographic projection of the first electrode 21 on the substrate 1 does not overlap with the orthographic projection of the second contact portion 42 on the substrate 1, thereby enabling the active layer 4 to achieve a second conductor. See [link to documentation]. Figure 12 .

[0122] During the first conductor formation, the source and drain contacts of the active layer 4 are plasma-treated using the gate 6 as a photomask. During the second conductor formation, the drain contacts of the active layer 4 are re-conducted by ion implantation based on the source pattern. This reduces the resistance of the drain contacts and makes the resistance of the source contacts less than that of the channel 43, and the resistance of the drain contacts less than that of the source contacts. As the driving voltage of the TFT increases, a high electric field is avoided between the gate 6 and the drain contacts of the TFT device, reducing the presence of hot carriers and thus preventing fluctuations in the threshold voltage (Vth) of the TFT.

[0123] S17. A pixel electrode 10 is deposited on the second electrode 81, and the pixel electrode 10 is connected to the second electrode 81.

[0124] After forming the second electrode 81 and the bonding terminal 82 and before forming the pixel electrode 10, the process also includes:

[0125] A passivation layer 9 is formed, which covers the second electrode 81 and the bonding terminal 82, and extends to the upper surface of the dielectric layer 7. See [reference needed]. Figure 9 .

[0126] The passivation layer 9 is perforated to form a fourth through hole 104, see [reference]. Figure 12 The fourth through-hole 104 penetrates the passivation layer 9 and is used to expose the second electrode 81.

[0127] In this process, a conductive layer is formed on the second electrode 81 by physical vapor deposition; then, the conductive layer is patterned to form the pixel electrode 10, see [link to documentation]. Figure 10 The pixel electrode 10 is connected to the second electrode 81 through the fourth via 104. The orthographic projection of the pixel electrode 10 on the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 21 on the substrate 1, and the orthographic projection of the pixel electrode 10 on the substrate 1 at least partially overlaps with the orthographic projection of the second electrode 81 on the substrate 1. The orthographic projection of the gate 6 on the substrate 1 completely falls into the orthographic projection of the pixel electrode 10 on the substrate 1. In this embodiment, the pixel electrode 10 extends towards the source, and the orthographic projection of the pixel electrode 10 on the substrate 1 at least partially overlaps with the orthographic projection of the source on the substrate 1. This ensures that most of the channel portion 43 of the active layer 4 is enveloped by the drain, source, and pixel electrode 10, blocking the diffusion path of external moisture into the channel of the active layer 4 and improving device reliability. It should be noted that this conductive layer can also serve as an oxide protective layer terminal of the COF bonding region, which will not be elaborated here.

[0128] In this embodiment, the resistance of the first contact portion 41 is less than the resistance of the channel portion 43, and the resistance of the second contact portion 42 is less than the resistance of the first contact portion 41. In other words, the resistance of the source contact portion is less than the resistance of the channel portion 43, and the resistance of the drain contact portion is less than the resistance of the source contact portion.

[0129] Therefore, in the display panel 1 provided in this embodiment, the source and drain are formed of different metal layers and are located on opposite sides of the active layer 4, respectively. The source is in contact with the bottom of the active layer 4, while the drain is in contact with the top of the active layer 4. The gate 6 is correspondingly disposed with the channel portion 43 of the active layer 4, and the drain extends toward the source, with its side flush with the side of the gate near the drain. Simply put, the left side of the drain is flush with the left side of the gate. During the first conductor formation, the source and drain contacts of the active layer 4 are plasma-treated using the gate 6 as a photomask. During the second conductor formation, the drain contacts of the active layer 4 are re-conducted by ion implantation based on the source pattern, thereby reducing the resistance of the drain contacts. The resistance of the source contacts is less than that of the channel 43, and the resistance of the drain contacts is less than that of the source contacts. In this way, as the driving voltage of the TFT increases, a high electric field is avoided between the gate 6 and the drain contacts of the TFT device, reducing the presence of hot carriers and thus preventing the threshold voltage (Vth) of the TFT from changing.

[0130] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0131] The above provides a detailed description of a display panel and its manufacturing method according to the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, include: substrate; A first electrode is disposed on the substrate; An active layer is disposed on the first electrode. The active layer includes a first contact portion, a second contact portion, and a channel portion. The channel portion is disposed between the first contact portion and the second contact portion. The first contact portion is connected to the first electrode. The portion of the first electrode corresponding to the channel portion serves as a light-shielding portion. The first contact portion is a drain contact portion. The second contact portion is a source contact portion. The first electrode is a drain electrode. A gate is disposed on the active layer and corresponding to the channel portion; and The second electrode is disposed on the gate and connected to the second contact portion, and the second electrode is the source electrode; Wherein, the resistance values ​​of the first contact portion and the second contact portion are both less than the resistance value of the channel portion; the resistance value of the second contact portion is less than the resistance value of the channel portion, and the resistance value of the first contact portion is less than the resistance value of the second contact portion.

2. The display panel according to claim 1, characterized in that, Also includes: A buffer layer is disposed on the first electrode and extends to the surface of the substrate, wherein the buffer layer has a first through hole for exposing the first electrode, and the first contact portion is connected to the first electrode through the first through hole; A gate insulating layer is disposed on the active layer, wherein the gate is disposed on the gate insulating layer; A dielectric layer covers the gate and extends to the surface of the buffer layer, wherein the dielectric layer has a second via for exposing the second contact portion; a second electrode is disposed on the dielectric layer and is connected to the second contact portion through the second via; A passivation layer covers the second electrode and extends to the surface of the dielectric layer; A third through-hole penetrates the passivation layer and the dielectric layer to expose the first contact portion; A pixel electrode is disposed on the second electrode and connected to the first contact portion through the third through hole.

3. The display panel according to claim 2, characterized in that, The orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the second electrode on the substrate; The second electrode extends toward the first electrode and is flush with the side of the gate near the first electrode.

4. The display panel according to claim 1, characterized in that, The first contact portion is a source contact portion, and the second contact portion is a drain contact portion; the first electrode is a source electrode, and the second electrode is a drain electrode; the resistance of the first contact portion is less than the resistance of the channel portion, and the resistance of the second contact portion is less than the resistance of the first contact portion.

5. The display panel according to claim 4, characterized in that, Also includes: A buffer layer is disposed on the first electrode and extends to the surface of the substrate, wherein the buffer layer has a first through hole for exposing the first electrode, and the first contact portion is connected to the first electrode through the first through hole; A gate insulating layer is disposed on the active layer, wherein the gate is disposed on the gate insulating layer; A dielectric layer covers the gate and extends to the surface of the buffer layer, wherein the dielectric layer has a second via for exposing the second contact portion; a second electrode is disposed on the dielectric layer and is connected to the second contact portion through the second via; A passivation layer that covers the second electrode and extends to the surface of the dielectric layer; A fourth through-hole, which penetrates the passivation layer, is used to expose the second electrode; A pixel electrode is disposed on the second electrode and connected to the second electrode through the fourth through hole.

6. The display panel according to claim 5, characterized in that, The orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the second electrode on the substrate; The second electrode extends toward the first electrode and is flush with the side of the gate near the first electrode.

7. A method for manufacturing a display panel, characterized in that, Includes the following steps: A first metal layer is deposited on a substrate, and the first metal layer is patterned to form a first electrode; An active layer thin film is deposited on the first electrode, and the active layer thin film is patterned to form an active layer; the active layer includes a first contact portion, a second contact portion, and a channel portion, the channel portion being disposed between the first contact portion and the second contact portion, wherein the first contact portion is connected to the first electrode, and the portion of the first electrode corresponding to the channel portion is a light-shielding portion. A second metal layer is deposited on the active layer, and the second metal layer is patterned to form a gate. The gate is disposed on the active layer and is disposed corresponding to the channel portion. Plasma treatment is performed on the first contact portion and the second contact portion of the active layer that are not covered by the gate to make the active layer a conductor for the first time. The first contact portion is the drain contact portion and the second contact portion is the source contact portion. A third metal layer is deposited on the gate and the third metal layer is patterned to form a second electrode. The second electrode is disposed on the gate and connected to the second contact portion. The first electrode is the drain electrode and the second electrode is the source electrode. The resistance of the source electrode contact portion is less than the resistance of the channel portion, and the resistance of the drain electrode contact portion is less than the resistance of the source electrode contact portion. Ion implantation is performed on the active layer that is not covered by the first or second electrode to achieve a second conductor formation of the active layer.

8. The method for manufacturing a display panel according to claim 7, characterized in that, In the step of achieving the second conductor formation of the active layer, the active layer not covered by the second electrode is subjected to ion implantation treatment, so that the active layer achieves the second conductor formation. The method for manufacturing the display panel further includes: A pixel electrode is deposited on the second electrode, and the pixel electrode is connected to the first contact portion; Wherein, the orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the second electrode on the substrate; The second electrode extends toward the first electrode and is flush with the side of the gate near the first electrode.

9. The method for manufacturing a display panel according to claim 7, characterized in that, The first contact portion is a source contact portion, and the second contact portion is a drain contact portion; the first electrode is a source electrode, and the second electrode is a drain electrode; the resistance of the source contact portion is less than the resistance of the channel portion, and the resistance of the drain contact portion is less than the resistance of the source contact portion; In the step of achieving the second conductor formation of the active layer, the active layer not covered by the first electrode is subjected to ion implantation treatment, so that the active layer achieves the second conductor formation. The method for manufacturing the display panel further includes: A pixel electrode is deposited on the second electrode, and the pixel electrode is connected to the second electrode; Wherein, the orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the second electrode on the substrate; The second electrode extends toward the first electrode and is flush with the side of the gate near the first electrode.

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