Super junction IGBT device and method of manufacturing the same

Abstract

The application discloses a super-junction IGBT device, and a structure in an active region comprises: a planar gate structure formed on the top of each first conductive type column, the planar gate structure is in an integral structure; a second well region composed of ion implantation regions of a second conductive type with the planar gate structure as a self-alignment condition after annealing treatment; the second well region is laterally diffused to the bottom region of the planar gate structure under the action of the annealing treatment; a channel region composed of the second well region covered by the planar gate structure, and a self-alignment structure between the second well region and the planar gate structure for improving the consistency of the device. A super-junction structure is formed in a first epitaxial layer, the second conductive type is composed of a second epitaxial layer filled in a super-junction trench, the bottom region of the first epitaxial layer has a first epitaxial sub-layer with a doping concentration greater than that of the top region, and the bottom surface of the super-junction trench is located in the first epitaxial sub-layer. The application also discloses a manufacturing method of the super-junction IGBT device. The application can improve the consistency of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a super junction IGBT device; this invention also relates to a method for manufacturing a super junction IGBT device. Background Technology

[0002] Existing superjunction devices include a current-flow region (active region), a transition region, and a termination region. A superjunction structure is formed in the current-flow region, consisting of alternating P-type and N-type pillars (PN pillars). Taking a strip-shaped PN pillar structure as an example, each N-type pillar has a planar gate structure above it, which may partially cover the surrounding P-type pillars or not. Each P-type pillar has a P-well above it, containing an N+ source region and a contact hole. The emitter metal is connected to the source region through the contact hole, and the contact hole of the emitter metal is connected to the P-region through a high-concentration P+ contact region. In the transition region, there is a P-ring covering one or more P-type pillars. The P-ring can be fabricated using the same process as the P-well, and it also contains a high-concentration P+ contact region. The formation process, concentration, and junction depth of the P+ contact region in the P-ring are the same as those in the current-flow region.

[0003] In the device structure described above, the width of the P-type well beneath the planar gate structure is actually the channel length of the device. The channel length affects the on-resistance and switching characteristics of the device. In the N-type region between the P-type wells at the bottom of the planar gate structure, N-type impurities are typically injected to reduce on-resistance and form a JFET-resistant region. The width of this JFET-resistant region directly affects the reverse transfer capacitance (Crss) of the device. Crss consists of the gate-drain capacitance (Cgd), which is also the Miller capacitance.

[0004] In existing technologies, Pwells are generally formed after or before the formation of P-type pillars. First, the formation region of the P-type ring in the transition area is defined by photolithography. The width of the P-type ring is 1 micrometer to 50 micrometers. At the same time, the formation region of the P-type well in the current flow region is defined. Then, P-type impurities, such as B or BF2, are implanted through ion implantation, thus forming the P-type well.

[0005] Then, a dielectric protection ring is formed, including: a dielectric film forming the dielectric protection ring, namely the G-field dielectric film, the G-field dielectric film is photolithographically and etched so that the G-field dielectric film only covers the surface of the transition region and the terminal region, while the G-field dielectric film on the surface of the active region is completely removed, thereby forming a dielectric protection ring surrounding the active region.

[0006] The planar gate structure is then formed, including the formation of a gate oxide film and a polysilicon gate. The gate region is defined in the active region by gate photolithography and etching, the gate vertical (Bus) is defined in the transition region, and the gate region is defined in the termination region or there is no gate region in the termination region.

[0007] After the planar gate structure is formed, the overlapping area of ​​the P-type well and the planar gate structure in the active region forms the channel region. The length of the channel region is actually affected by the size of the P-type region formed by the photolithography and etching of the P-type well, as well as the position, i.e., the photolithographic overlay accuracy. It is also affected by the size and position of the polysilicon gate in the active region formed by the photolithography and etching of the polysilicon gate. Therefore, the channel length formed by the existing method has poor consistency, and the width consistency of the anti-JFET region between the channel regions is also poor. This not only affects the consistency of the device's on-resistance and threshold voltage, but also the consistency of the device's Cgd and gate-source capacitance (Cgs). Cgd includes the capacitance formed by the planar gate structure covering the anti-JFET region between the channel regions, and Cgs includes the capacitance formed by the planar gate structure covering the channel region.

[0008] Now combined with the appendix Figure 1 The following is a description of existing superjunction IGBT devices:

[0009] like Figure 1 The diagram shown is a schematic of the structure of an existing superjunction IGBT device. Figure 1 The image only shows the cross-sectional structure of the active region. Taking the N-type superjunction IGBT device as an example, existing superjunction IGBT devices include:

[0010] A superjunction structure is formed in the semiconductor substrate. The superjunction structure is formed by alternating N-type pillars and P-type pillars 103. Each superjunction unit consists of one N-type pillar and one adjacent P-type pillar 103.

[0011] Typically, the semiconductor substrate includes a silicon substrate. Typically, an N-type epitaxial layer 102 is formed on the surface of the semiconductor substrate, and the N-type pillars are composed of the N-type epitaxial layer 102 between the P-type pillars 103.

[0012] The structures of superjunction IGBT devices located in the active region include:

[0013] A P-type well region 106 is formed on the top of the P-type pillar 103, and the P-type well region 106 extends into the N-type pillars on both sides of the P-type pillar 103. The P-type well region 106 is defined by photolithography and formed by ion implantation.

[0014] A planar gate structure is formed on the top of each of the N-type pillars, and the planar gate structure is an integral structure; the planar gate structure is formed by stacking a gate dielectric layer 104 and a gate conductive material layer 105.

[0015] Typically, the gate dielectric layer 104 includes a gate oxide layer. The gate conductive material layer 105 includes a polysilicon gate.

[0016] The planar gate structure also needs to be patterned using photolithography definition and etching processes.

[0017] N+ doped emitter regions 107 are self-aligned and formed on the surfaces of the P-type well regions 106 on both sides of the planar gate structure.

[0018] The P-type well region 106 and the planar gate structure need to overlap, and the P-type well region 106 located at the bottom of the planar gate structure forms a channel region. Figure 1 In this design, the length of the channel region, i.e., the channel length, is represented by an Lc surface. The planar gate structure is an integral structure, meaning that the planar gate structure will not split in the middle. Two channel regions will be formed on the top of the same N-type pillar, but the two channel regions share one planar gate structure. The gate conductive material layer 105 will extend from the top of one channel region to the top of the other channel region, so that the area between the channel regions is also covered by the planar gate structure.

[0019] The region between the P-type well regions 106 at the bottom of the planar gate structure is the region where the JFET effect will occur. The width of this region is Wj. Typically, N-type ion implantation is required in this region to form an anti-JFET region.

[0020] The front-side structure of the superjunction IGBT device also includes:

[0021] Interlayer film 108, through contact hole 109; at the bottom of contact hole 109 located at the top of emitter region 108, a body contact region 110 composed of P-type heavily doped regions is also formed, so that body region 104 is connected to the top contact hole 109 together with emitter region 108 through body contact region 110.

[0022] The emitter metal and gate metal are formed by patterning the front metal layer 111.

[0023] The back-side structure of the superjunction IGBT device includes:

[0024] The collector region 101 is formed by P-type backside ion implantation after the semiconductor substrate is thinned.

[0025] A collector electrode composed of a back metal layer 112 is formed on the back side of the collector region 101.

[0026] like Figure 2 The diagram shown is a flowchart of a conventional superjunction IGBT device manufacturing method. Figure 1 The existing superjunction IGBT device shown; Figure 2 The process is represented by photomask layers. Existing methods for manufacturing superjunction IGBT devices include the following steps:

[0027] Step S101, which forms the zero-layer mark, requires a combination of photolithography and etching processes. Figure 2 In this context, step S201 is also represented by Zero photo & etch.

[0028] Step S102 is performed to form the JFET-resistant region. This JFET-resistant region needs to be defined using a photolithography process. Figure 2 In this context, step S101 is represented by JFET photo & IMP.

[0029] Step S103 forms a superjunction structure, i.e., forms Figure 1 The P-type pillars 103 shown are formed using a trench etching and filling process. The N-type epitaxial layers 102 between the P-type pillars 103 form N-type pillars. Forming the superjunction structure requires a photomask that defines the trenches. Figure 2 In step S103, Trench photo & etch is used.

[0030] Step S104 is performed to form the P-type well region 106. The P-type well region 106 first requires photolithography to define the formation region, followed by ion implantation. Figure 1 In this context, step S104 is represented by Pwell photo & IMP.

[0031] Step S105 involves forming a dielectric guard ring. This requires the growth of a dielectric guard ring material layer (Gfield). Following this, a photolithography and etching process is performed to remove the material layer of the dielectric guard ring in the active region. The remaining material layer of the dielectric guard ring then forms the dielectric guard ring itself. Therefore, Figure 2 In this context, step S105 is represented by Gfield photo & etch.

[0032] Step S106 forms a planar gate structure. This planar gate structure requires first forming a superimposed structure of a gate oxide layer and a polysilicon gate, followed by photolithography and etching processes to pattern the planar gate structure. Therefore, Figure 2 In this context, step S106 is represented by poly photo & etch.

[0033] Step S107 forms the emission region 107. The emission region 107 and the planar gate structure are self-aligned in the active region. The emission region 107 is an N+ region (Nplus), and the formation process of the emission region 107 requires the use of a photomask to define the formation area of ​​the emission region 107. Figure 1 In this context, step S107 is also represented using Nplus photo & IMP.

[0034] Step S108 includes: forming an interlayer film 108 and forming a contact hole (Cont) 109 through the interlayer film 108. The formation process of the contact hole 109 requires first using photolithography to define the formation area of ​​the contact hole 109, then etching to form the opening of the contact hole 109, and finally filling the opening of the contact hole 109 with metal to form the contact hole. The formation process of the contact hole 109 requires using a photomask to define the formation area of ​​the contact hole 109, therefore... Figure 1 In this context, step S108 is also represented by Cont photo & etch.

[0035] After the opening of the contact hole 109 is opened and before the metal is filled, the step of performing P-type heavily doped ion implantation to form the bulk contact region 211 is also included.

[0036] Step S109 includes: forming a front metal layer 111 and patterning the front metal layer 111 to form emitter metal and gate metal. The formation process of the front metal layer 111 requires the use of a photomask to define the patterned area of ​​the front metal layer 111. Figure 1 In this context, step S109 is also represented by Metal photo & etch.

[0037] After the front process is completed, the back process is also required:

[0038] Backside thinning is performed, followed by backside P-type ion implantation to form a current collector region, thus forming a backside metal layer. Figure 1 and Figure 2 As shown, the P-type well region 106 needs to be implemented by photolithography and ion implantation. In the photolithography process, the thickness of the photoresist, the exposure intensity, and the development and ion implantation processes will all produce corresponding deviations, which will cause the size of the P-type well region 106 to change, that is, the photolithography and implantation processes will cause size changes. At the same time, the photolithography overlay accuracy will also cause the pattern position of the P-type well region 106 to change.

[0039] Similarly, the planar gate structure needs to be implemented using photolithography and etching. The planar gate structure will also experience dimensional changes due to changes in photolithography and etching process parameters, as well as changes in pattern position due to changes in photolithography overlay precision.

[0040] On the same semiconductor substrate, the dimensional variations of the P-type well region 106 due to photolithography and implantation processes, as well as the variations in pattern position due to photolithographic overlay accuracy parameters, and the dimensional variations of the planar gate structure due to photolithography and etching processes, as well as the variations in pattern position due to photolithographic overlay accuracy parameters, will all cause changes in the channel length Lc. The channel length Lc has a significant impact on the device's on-resistance, threshold voltage, and input capacitance (Cgs), which will affect the consistency of device performance; for example, the consistency of channel length Lc, on-resistance, threshold voltage, and Cgs will all deteriorate.

[0041] Because the JFET effect is prone to occur in the N-type region between the channel regions, JFET-resistant implantation is performed to form a JFET-resistant region. The N-type impurity concentration in the JFET-resistant region is higher than that in the N-type epitaxial layer 102, for example, by one order of magnitude or more. The width Wj of the JFET-resistant region directly affects the Cgd value of the device. The width Wj will also change, thus affecting the consistency of the Cgd of the device.

[0042] The following section uses specific parameters to illustrate the adverse effects of existing methods on device consistency:

[0043] Depend on Figure 2As can be seen, the width and position of the P-type well region 106 are determined by the photolithography process of the P-type well region 106. This is because the critical dimension (CD) after photolithography will always vary to some extent with the thickness of the photoresist, the energy of the photolithography, and the development process (e.g., within + / -0.2 micrometers, and related to the size of the photolithographic pattern, process selection, etc.). The position of the pattern will also vary within a certain range due to the overlay accuracy (e.g., 60nm-150nm). Similarly, the width of the polysilicon gate is also related to the photolithography process and etching process of the polysilicon gate, and varies within a certain range. The photolithography overlay accuracy also fluctuates within a certain range. If the photoresist thickness is approximately 1 micrometer and a 248nm lithography machine is used, the single-layer width progress may fluctuate within ±0.1 micrometers. If the overlay progress varies within ±0.06 micrometers, considering the difference between the two lithographic layers, the channel length Lc may vary within ±0.32 micrometers. For a device with a 9-micrometer step, if the polysilicon gate width is set to 7.5 micrometers (already considered in a wide direction), and the single channel length Lc is designed to be 2-3 micrometers, this ±0.32-micrometer fluctuation already has a significant impact on device consistency. If the superjunction step is further reduced, for example, to 5 micrometers, then after deducting the 0.5-micrometer contact hole width and the 0.5-micrometer distance from the contact hole to the polysilicon edge, the entire polysilicon gate width is only 3.5 micrometers. The single-sided channel length Lc will definitely be less than 1.7 micrometers. This ±0.32-micrometer variation will result in very poor consistency.

[0044] This range of variation, even if reduced through optimization of photolithography and etching processes, especially through control of process conditions, comes at the cost of higher manufacturing costs. For example, stricter control over critical dimensions and overlay precision in photolithography increases rework rates, thus raising manufacturing costs. Furthermore, this variation, or rather, this uniformity, is inevitable, and the problem becomes increasingly pronounced as the superjunction step size decreases. Summary of the Invention

[0045] The technical problem to be solved by the present invention is to provide a superjunction IGBT device that can improve device consistency. To this end, the present invention also provides a method for manufacturing a superjunction IGBT device.

[0046] To solve the above-mentioned technical problems, the superjunction IGBT device provided by the present invention includes:

[0047] A first epitaxial layer doped with a first conductivity type has a superjunction structure formed therein. The superjunction structure is formed by alternating arrangement of multiple first conductivity type pillars and second conductivity type pillars. Each superjunction unit consists of a first conductivity type pillar and an adjacent second conductivity type pillar.

[0048] The second conductivity type pillar is composed of a second epitaxial layer doped with the second conductivity type and filled in the superjunction trench, and the first conductivity type pillar is composed of the first epitaxial layer between the second conductivity type pillars.

[0049] The structures of superjunction IGBT devices located in the active region include:

[0050] A planar gate structure is formed on top of each of the first conductivity type pillars, and the planar gate structure is an integral structure; the planar gate structure is formed by stacking a gate dielectric layer and a gate conductive material layer.

[0051] The second well region is formed by annealing an ion-implanted region of the second conductivity type with the planar gate structure as the self-alignment condition; the second well region diffuses laterally to the bottom region of the planar gate structure under the action of the annealing process.

[0052] The channel region is composed of the second well region covered by the planar gate structure, and the self-alignment structure between the second well region and the planar gate structure is used to improve the consistency of the device.

[0053] The depth of each superjunction trench has a deviation caused by the etching process of the superjunction trench. The first epitaxial layer includes a first epitaxial sublayer located in the bottom region of the first epitaxial layer. The bottom surface of each superjunction trench is located in the first epitaxial sublayer. The doping concentration of the first epitaxial sublayer is greater than the doping concentration in the region located at the top of the first epitaxial sublayer in the first epitaxial layer, so as to reduce the impact of the depth deviation of the superjunction trench on the breakdown voltage and improve the breakdown voltage uniformity.

[0054] The collector region consists of a second conductivity type back ion implantation region formed in the back region of the first epitaxial sublayer.

[0055] The first epitaxial sublayer between the bottom surface of the superjunction structure and the top surface of the collector region serves simultaneously as a field cutoff layer and a barrier layer for minority carriers injected from the collector region.

[0056] A further improvement is that the superjunction trench has inclined sides and a top opening that is larger than the bottom opening.

[0057] The region of the first epitaxial layer located at the top of the first epitaxial sublayer has a doping concentration distribution that increases from bottom to top to compensate for the effect of the side-tilted superjunction trench on the charge balance of the superjunction structure.

[0058] A further improvement is that the region at the top of the first epitaxial sublayer of the first epitaxial layer includes at least a second epitaxial sublayer and a third epitaxial sublayer, the second epitaxial sublayer being superimposed on the top surface of the first epitaxial sublayer, the third epitaxial sublayer being superimposed on the top surface of the second epitaxial sublayer, and the doping concentration of the third epitaxial sublayer being greater than the doping concentration of the second epitaxial sublayer.

[0059] A further improvement is that the resistivity of the first epitaxial sublayer is at least 10% lower than that of the second epitaxial sublayer.

[0060] A further improvement is that the structure of the superjunction IGBT device located in the active region further includes:

[0061] The first well region consists of ion implantation regions of the second conductivity type formed on the top of each second conductivity type pillar, and the formation region of the first well region is defined by photolithography.

[0062] In the lateral direction, there is a gap between the first well region and the side of the planar gate structure, the first well region and the side of the planar gate structure are aligned, or the first well region extends to the bottom of the planar gate structure.

[0063] The body region is formed by the vertical stacking of the first well region and the second well region. The junction depth of the first well region is greater than that of the second well region, and the doping concentration of the first well region is less than that of the second well region, in order to reduce the leakage current of the device.

[0064] A further improvement is that a dielectric protection ring is formed on the surface of the first epitaxial layer on which the superjunction structure is formed. The dielectric protection ring covers the transition region and the terminal region and opens the active region. The area enclosed by the dielectric protection ring is the active region. The transition region surrounds the periphery of the active region, and the terminal region surrounds the periphery of the transition region.

[0065] An anti-JFET region is also formed in the active region. The anti-JFET region consists of an ion implantation region of the first conductivity type that is fully formed on the surface of the superjunction structure in the active region with the dielectric guard ring as a self-alignment condition.

[0066] The anti-JFET region is used to increase the first conductivity type doping concentration in the first conductivity type doping region to reduce the JFET effect.

[0067] The anti-JFET region is also used in the second conductivity type doping region to compensate for the second conductivity type doping impurities of the first well region in the surface region of the active region, so as to reduce the influence of the first well region on the second conductivity type doping of the surface region of the active region, and make the second conductivity type doping of the channel region determined by the second well region.

[0068] A further improvement is that a heavily doped emitter region of a first conductivity type is formed on the surface of the body region, and the emitter region and the planar gate structure are self-aligned.

[0069] A further improvement is that, in the lateral direction, the first well region at least covers the center position of the second conductive type pillar and the width of the first well region on both sides of the center position of the second conductive type pillar is more than 0.2 micrometers; or, the width of the first well region covering the second conductive type pillar is 1 micrometer to 2 micrometers or greater than 2 micrometers.

[0070] In the vertical direction, the depth of the first well region is 1 micrometer to 2 micrometers; or, the depth of the first well region is more than 2 micrometers.

[0071] A further improvement is that when the depth of the first well region is 1 micrometer to 2 micrometers, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process. The thermally oxidized layer of the dielectric protection ring causes the surface of the first epitaxial layer on which the superjunction structure is formed to be consumed. During the removal of the dielectric protection ring in the active region, the surface region of the first well region is removed. The doping concentration of the removed surface region of the first well region is higher than the doping concentration of the bottom retained region, which is used to improve the uniformity of the device.

[0072] When the depth of the first well region is 2 micrometers or more, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process, or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process, or is composed of a deposited dielectric layer formed by a deposition process. The deposited dielectric layer of the dielectric protection ring reduces the thermal process of the device, thereby reducing the specific on-resistance of the device.

[0073] A further improvement is that a second conductivity type ring is formed in the transition region, and the first well region and the second conductivity type ring have the same process structure.

[0074] A further improvement is that the superjunction IGBT device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type; or, the superjunction IGBT device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0075] To solve the above-mentioned technical problems, the manufacturing method of the superjunction IGBT device provided by the present invention includes the following steps:

[0076] Step 1: Form a first epitaxial layer doped with a first conductivity type on a semiconductor substrate. Form a plurality of superjunction trenches in a selected region of the first epitaxial layer. Fill the superjunction trenches with a second epitaxial layer doped with a second conductivity type. The second epitaxial layer filled in the superjunction trenches serves as a component of the second conductivity type pillars. The first epitaxial layers between the second conductivity type pillars form the first conductivity type pillars.

[0077] A superjunction structure is formed by alternating arrangement of multiple first-conductivity type pillars and second-conductivity type pillars. Each superjunction unit consists of one first-conductivity type pillar and one adjacent second-conductivity type pillar.

[0078] The depth of each superjunction trench has a deviation caused by the etching process of the superjunction trench. The first epitaxial layer includes a first epitaxial sublayer located in the bottom region of the first epitaxial layer. The bottom surface of each superjunction trench is located in the first epitaxial sublayer. The doping concentration of the first epitaxial sublayer is greater than the doping concentration in the region located at the top of the first epitaxial sublayer in the first epitaxial layer, so as to reduce the impact of the depth deviation of the superjunction trench on the breakdown voltage and improve the breakdown voltage uniformity.

[0079] Step 2: Define the active region on the semiconductor substrate.

[0080] Step 3: Form a planar gate structure in the active region. Each planar gate structure is formed on top of each first conductivity type pillar. The planar gate structure is an integral structure. The planar gate structure is formed by stacking a gate dielectric layer and a gate conductive material layer.

[0081] Step 4: Using the planar gate structure as the self-alignment condition, perform ion implantation of the second conductivity type to form a second well region. Then, perform annealing on the second well region. Under the action of annealing, the second well region laterally diffuses to the bottom region of the planar gate structure.

[0082] The channel region is composed of the second well region covered by the planar gate structure, and the self-alignment structure between the second well region and the planar gate structure is used to improve the consistency of the device.

[0083] Step 5: Perform back-side thinning, which completely removes the semiconductor substrate and retains a portion of the thickness of the first epitaxial sublayer.

[0084] Step 6: Perform backside ion implantation of the second conductivity type to form a collector region in the backside region of the retained first epitaxial sublayer; the first epitaxial sublayer between the bottom surface of the superjunction structure and the top surface of the collector region simultaneously serves as a field cutoff layer and a barrier layer for minority carriers implanted from the collector region.

[0085] A further improvement is that, in step one, the superjunction trench has inclined sides and the top opening is larger than the bottom opening.

[0086] The region of the first epitaxial layer located at the top of the first epitaxial sublayer has a doping concentration distribution that increases from bottom to top to compensate for the effect of the side-tilted superjunction trench on the charge balance of the superjunction structure.

[0087] A further improvement is that the region at the top of the first epitaxial sublayer of the first epitaxial layer includes at least a second epitaxial sublayer and a third epitaxial sublayer, the second epitaxial sublayer being superimposed on the top surface of the first epitaxial sublayer, the third epitaxial sublayer being superimposed on the top surface of the second epitaxial sublayer, and the doping concentration of the third epitaxial sublayer being greater than the doping concentration of the second epitaxial sublayer.

[0088] A further improvement is that the resistivity of the first epitaxial sublayer is at least 10% lower than that of the second epitaxial sublayer.

[0089] A further improvement is that, after step one is completed, the following step of forming the first well region is also included:

[0090] Photolithography defines the formation region of the first well region, which is located on top of the second conductivity type pillar in the active region.

[0091] The first well region is formed by implanting ions of the second conductivity type.

[0092] The first well region is annealed and advanced; in the lateral direction, the annealed and advanced first well region has a gap between it and the side of the planar gate structure, the first well region is aligned with the side of the planar gate structure, or the first well region extends to the bottom of the planar gate structure.

[0093] The body region is formed by the vertical stacking of the first well region and the second well region. The junction depth of the first well region is greater than that of the second well region, and the doping concentration of the first well region is less than that of the second well region, in order to reduce the leakage current of the device.

[0094] A further improvement is that step two includes the following sub-steps:

[0095] A material layer with a dielectric protective ring is formed on the surface of the first epitaxial layer on which the superjunction structure is formed.

[0096] Photolithography defines the formation region of the active region.

[0097] The dielectric protection ring is formed by etching the material layer of the dielectric protection ring. The dielectric protection ring covers the transition region and the terminal region and opens the active region. The area enclosed by the dielectric protection ring is the active region. The transition region surrounds the periphery of the active region, and the terminal region surrounds the periphery of the transition region.

[0098] A further improvement is that, after step two and before step three, the following steps are included to form the JFET-resistant region:

[0099] Using the dielectric guard ring as a self-alignment condition, first conductivity type ion implantation is performed to fully form the anti-JFET region on the surface of the active region.

[0100] The anti-JFET region is used to increase the first conductivity type doping concentration in the first conductivity type doping region to reduce the JFET effect.

[0101] The anti-JFET region is also used in the second conductivity type doping region to compensate for the second conductivity type doping impurities of the first well region in the surface region of the active region, so as to reduce the influence of the first well region on the second conductivity type doping of the surface region of the active region, and make the second conductivity type doping of the channel region determined by the second well region.

[0102] A further improvement is that, after step four, the process further includes: performing ion implantation of heavily doped ions of the first conductivity type in the active region, with the planar gate structure as the self-alignment condition, to form an emitter region.

[0103] A further improvement is that, in the lateral direction, the first well region at least covers the center position of the second conductive type pillar and the width of the first well region on both sides of the center position of the second conductive type pillar is more than 0.2 micrometers; or, the width of the first well region covering the second conductive type pillar is 1 micrometer to 2 micrometers or greater than 2 micrometers.

[0104] In the vertical direction, the depth of the first well region is 1 micrometer to 2 micrometers; or, the depth of the first well region is more than 2 micrometers.

[0105] A further improvement is that when the depth of the first well region is 1 micrometer to 2 micrometers, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process. The thermally oxidized layer of the dielectric protection ring causes the surface of the first epitaxial layer on which the superjunction structure is formed to be consumed. During the removal of the dielectric protection ring in the active region, the surface region of the first well region is removed. The doping concentration of the removed surface region of the first well region is higher than the doping concentration of the bottom retained region, which is used to improve the consistency of the device.

[0106] When the depth of the first well region is 2 micrometers or more, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process, or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process, or is composed of a deposited dielectric layer formed by a deposition process. The deposited dielectric layer of the dielectric protection ring reduces the thermal process of the device, thereby reducing the specific on-resistance of the device.

[0107] A further improvement is that a second conductivity type ring is formed in the transition region, and the first well region and the second conductivity type ring are formed simultaneously using the same process.

[0108] A further improvement is that, before step three, after the anti-JFET region is formed, the surface of the second conductivity type doped region is inverted to the first conductivity type doped.

[0109] A further improvement is that, in step five, after the back side is thinned, the thickness of the retained first epitaxial sublayer is 3 micrometers to 8 micrometers.

[0110] Unlike existing technologies where the channel region is composed of ion-implanted regions defined by a photomask, the channel region of this invention is composed of a second well region that is self-aligned with the planar gate structure. Since the second well region and the planar gate structure are self-aligned, the second well region does not need to be defined by a photomask. Therefore, the influence of photolithography on the pattern width and photolithography overlay on the pattern position can be eliminated. That is, the length of the channel region formed by the second well region will not be affected by the photolithography process and photolithography overlay accuracy corresponding to the well region. Similarly, the length of the channel region will not be affected by the photolithography and etching process and photolithography overlay accuracy of the polysilicon gate. This can improve the consistency of the channel region length, the consistency of the device on-resistance and threshold voltage, and the consistency of the gate-source capacitance (Cgs). Finally, it can greatly improve the consistency of the device.

[0111] Furthermore, if the second well region, which is self-aligned with the planar gate structure, is used alone as the entire body region, the formation process of the second well region is limited by the planar gate structure, resulting in a shallow depth of the body region formed by using only the second well region, leading to a larger leakage current in the device. To address this, the present invention can also combine the base gate of the second well region with the first well region formed by a photomask before the planar gate structure to form the body region together. This allows the second well region to be used to improve the consistency of the device, while the deeper junction depth and gradual change structure of the first well region can be used to reduce the leakage current of the device.

[0112] Furthermore, after the first well region is introduced into the body region, it extends downwards from the surface of the active region. This first well region on the surface of the active region may then become part of the channel region, affecting the channel length and ultimately the device consistency. To address this new problem, this invention adds an anti-JFET region fully implanted in the active region. Since the anti-JFET region is only located on the surface of the active region and has a first conductivity type doping opposite to that of the first well region, it compensates for the second conductivity type doping impurities on the surface region of the first well region. Typically, the doping concentration of the anti-JFET region is greater than that of the surface region of the first well region. Therefore, before the second well region is formed, the anti-JFET region causes the surface of the second conductivity type doped region in the active region to be inverted to a first conductivity type doping, resulting in the entire surface of the active region being doped with the first conductivity type. This eliminates the adverse effects of the introduction of the first well region on the channel length and doping concentration, improving the device consistency, including the consistency of channel length and threshold voltage.

[0113] The region in the anti-JFET region that actually reduces the JFET effect is the area between the channel regions covered by the planar gate structure. The width of this region is only affected by the width of the planar gate structure, which in turn is affected by the photolithography and etching process of the planar gate structure. The photolithographic overlay accuracy of the planar gate structure does not affect the width of the anti-JFET region covered by the planar gate structure between the channel regions. Therefore, the uniformity of the gate-drain capacitance (Cgd) of the device is also greatly improved.

[0114] In addition, when the junction depth is small, the first well region of the present invention can also remove the surface region with a high doping concentration by means of a thermal oxide layer, such as a thermal oxide layer forming a dielectric protection ring, thereby reducing the adverse effect of the surface region with a high doping concentration in the first well region on the channel region and further improving the consistency of the device.

[0115] When the junction depth of the first well region of the present invention is relatively deep, the doping concentration of the entire first well region is slowed down by utilizing the deeper junction depth. In this way, the doping concentration of the surface region of the first well region is also reduced, thereby reducing the adverse effects of the surface region of the first well region on the channel region and improving the consistency of the device.

[0116] This invention also employs a layered configuration for the first epitaxial layer, setting a higher doping concentration for the bottom first epitaxial sublayer. The bottom surface of the superjunction trench is required to extend into the first epitaxial sublayer. By utilizing the higher doping concentration of the first epitaxial sublayer compared to the top first epitaxial layer, the impact of superjunction trench depth deviation on breakdown voltage and improved breakdown voltage uniformity can be reduced. This is because: as the concentration of the first epitaxial sublayer increases, the breakdown voltage below the top surface of the first epitaxial sublayer is mainly determined by the first epitaxial sublayer. Therefore, the effective thickness of the superjunction structure is actually the thickness of the portion above the top surface of the first epitaxial sublayer. Thus, even if there are depth deviations in different regions of the superjunction trench, since the bottom surface of the superjunction trench is always within the first epitaxial sublayer, the longitudinal position difference of the bottom surface of the superjunction trench will not have a significant impact on the breakdown voltage. Therefore, this invention can reduce the impact of superjunction trench depth deviation on breakdown voltage and improve breakdown voltage uniformity, which also improves the consistency of the device's BVdss.

[0117] Meanwhile, the collector region is formed on the back side of the first epitaxial sublayer. In this way, the first epitaxial sublayer located between the bottom surface of the superjunction structure and the top surface of the collector region can serve as a field cutoff layer, thereby improving the electric field distribution in the drift region and increasing the breakdown voltage of the device.

[0118] Meanwhile, because the first epitaxial sublayer has a high concentration, it can also act as a barrier layer for minority carriers injected from the collector region. Taking an N-type device as an example, the minority carrier is a hole. When the device is turned on, the collector region will inject holes into the drift region. Since the first epitaxial sublayer has a high concentration, the holes injected when the device is turned off can be quickly recombinated in the first epitaxial sublayer, thus achieving a barrier effect. Therefore, it can achieve fast turn-off, thereby enabling a superjunction IGBT with fast turn-off.

[0119] The present invention can also set the doping concentration distribution of the first epitaxial layer in the top region of the first epitaxial sublayer to increase from bottom to top according to the requirement of compensating for the influence of the side-tilted superjunction trench on the charge balance of the superjunction structure. For example, the first epitaxial layer in the top region of the first epitaxial sublayer can be set as a superposition layer of the second epitaxial sublayer and the third epitaxial sublayer with a smaller doping concentration, thereby improving the charge balance at each longitudinal position of the superjunction structure and ultimately improving the device breakdown voltage. Attached Figure Description

[0120] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0121] Figure 1 This is a schematic diagram of the structure of an existing superjunction IGBT device;

[0122] Figure 2 This is a flowchart of the existing manufacturing method for superjunction IGBT devices;

[0123] Figure 3 This is a schematic diagram of the structure of a superjunction IGBT device according to an embodiment of the present invention;

[0124] Figure 4 This is a flowchart of a method for manufacturing a superjunction IGBT device according to an embodiment of the present invention;

[0125] Figures 5A-5F This is a schematic diagram of the device structure in each step of the manufacturing method of the superjunction IGBT device according to an embodiment of the present invention. Detailed Implementation

[0126] like Figure 3 The diagram shown is a structural schematic of a superjunction IGBT device according to an embodiment of the present invention; the superjunction IGBT device according to an embodiment of the present invention includes:

[0127] A first epitaxial layer 202 doped with a first conductivity type has a superjunction structure formed therein. The superjunction structure is formed by alternating arrangement of a plurality of first conductivity type pillars and second conductivity type pillars 203. Each superjunction unit consists of a first conductivity type pillar and an adjacent second conductivity type pillar 203.

[0128] The second conductivity type pillar 203 is composed of a second epitaxial layer doped with the second conductivity type and filled in the superjunction trench, and the first conductivity type pillar is composed of the first epitaxial layer 202 between the second conductivity type pillars 203.

[0129] The depth of each superjunction trench has a deviation caused by the etching process of the superjunction trench. The first epitaxial layer 202 includes a first epitaxial sublayer 2021 located in the bottom region of the first epitaxial layer 202. The bottom surface of each superjunction trench is located in the first epitaxial sublayer 2021. The doping concentration of the first epitaxial sublayer 2021 is greater than the doping concentration in the region of the first epitaxial layer 202 located at the top of the first epitaxial sublayer 2021, so as to reduce the impact of the depth deviation of the superjunction trench on the breakdown voltage and improve the breakdown voltage uniformity.

[0130] In this embodiment of the invention, the first epitaxial layer 202 is formed on the semiconductor substrate 201 (see reference). Figure 5A The surface of the semiconductor substrate 201 (shown) includes a silicon substrate.

[0131] In the back-side thinning process, the semiconductor substrate 201 is completely removed, while the first epitaxial sublayer 2021 needs to retain a portion of its thickness. Figure 1 The image shows the retained first epitaxial sublayer 2021. In some embodiments, the thickness of the retained first epitaxial sublayer 2021 is 3 micrometers to 8 micrometers.

[0132] In this embodiment of the invention, the superjunction trench has an inclined side and a top opening that is larger than the bottom opening, which is beneficial for the etching and filling of the superjunction trench.

[0133] The region of the first epitaxial layer 202 located on top of the first epitaxial sublayer 2021 has a doping concentration distribution that increases from bottom to top to compensate for the influence of the side-tilted superjunction trench on the charge balance of the superjunction structure. In some preferred embodiments, the region of the first epitaxial layer 202 located on top of the first epitaxial sublayer 2021 includes at least a second epitaxial sublayer 2022 and a third epitaxial sublayer 2023, wherein the second epitaxial sublayer 2022 is stacked on the top surface of the first epitaxial sublayer 2021, and the third epitaxial sublayer 2023 is stacked on the top surface of the second epitaxial sublayer 2022, and the doping concentration of the third epitaxial sublayer 2023 is greater than that of the second epitaxial sublayer 2022. Figure 3 The first epitaxial layer 202 is formed by stacking the first epitaxial sublayer 2021, the second epitaxial sublayer 2022, and the third epitaxial sublayer 2023.

[0134] Figure 3 The image only shows the structure of the superjunction IGBT device located in the active region. The structure of the superjunction IGBT device located in the active region includes:

[0135] A planar gate structure is formed on the top of each of the first conductivity type pillars. The planar gate structure is an integral structure, which is in contrast to the split gate structure. The two sides of the planar gate structure are respectively covered with corresponding channel regions, and the middle is connected to form an integral structure. The planar gate structure is formed by stacking a gate dielectric layer 206 and a gate conductive material layer 207.

[0136] In some preferred embodiments, the gate dielectric layer 206 includes a gate oxide layer.

[0137] The gate conductive material layer 207 includes a polysilicon gate.

[0138] The second well region 2042 is formed by annealing an ion-implanted region of the second conductivity type with the planar gate structure as the self-alignment condition; the second well region 2042 diffuses laterally to the bottom region of the planar gate structure under the action of the annealing process. The second well region 2042 also diffuses vertically downwards under the action of the annealing process.

[0139] The channel region is composed of the second well region 2042 covered by the planar gate structure, and the self-alignment structure between the second well region 2042 and the planar gate structure is used to improve the consistency of the device. Figure 3 In the diagram, the length of the channel region is represented by Lc, and the length of the channel region is also... Figure 3 The second well region 2042 is located between the two straight lines corresponding to the channel length Lc. A conductive channel is formed after the surface of the channel region is inverted.

[0140] Because the second well region 2042 is limited by self-alignment with the planar gate structure, the junction depth of the second well region 2042 is relatively shallow. If the second well region 2042 is used alone as the body region 204, a large leakage current will be generated. This situation is only applicable in situations where the leakage current requirement is not high.

[0141] A preferred option is that, in order to reduce leakage current, the structure of the superjunction IGBT device located in the active region of the present invention further includes:

[0142] The first well region 2041 is composed of ion implantation regions of the second conductivity type formed on the top of each second conductivity type pillar 203, and the formation region of the first well region 2041 is defined by photolithography.

[0143] In the lateral direction, there is a gap between the first well region 2041 and the side of the planar gate structure, the first well region 2041 and the side of the planar gate structure are aligned, or the first well region 2041 extends to the bottom of the planar gate structure. Figure 3 The image shows an overlap between the first well region 2041 and the planar gate structure.

[0144] The body region 204 is formed by vertically stacking the first well region 2041 and the second well region 2042. The junction depth of the first well region 2041 is greater than that of the second well region 2042, and the doping concentration of the first well is less than that of the second well region 2042, in order to reduce the leakage current of the device. Figure 3 In this context, the first well region 2041 is also denoted by P1 and the second well region 2042 is also denoted by P2.

[0145] In this embodiment of the invention, the first well region 2041 is formed by photolithography definition, ion implantation, and annealing. After the annealing is completed, it is ensured that: in the lateral direction, the first well region 2041 covers the center position of the second conductive type pillar 203 and the width of the first well region 2041 on both sides of the center position of the second conductive type pillar 203 is 0.2 micrometers or more; or, the width of the first well region 2041 covering the second conductive type pillar 203 is 1 micrometer to 2 micrometers or greater than 2 micrometers.

[0146] In the vertical direction, the depth of the first well region 2041 is 1 micrometer to 2 micrometers; or, the depth of the first well region 2041 is more than 2 micrometers.

[0147] A dielectric protection ring (not shown) is formed on the surface of the first epitaxial layer 202 on which the superjunction structure is formed. The dielectric protection ring covers the transition region and the terminal region and opens the active region. The area enclosed by the dielectric protection ring is the active region. The transition region surrounds the periphery of the active region, and the terminal region surrounds the periphery of the transition region.

[0148] The active region includes the superjunction structure surrounding the dielectric guard ring. Since the first well region 2041 extends downwards from the surface of the active region, a high doping concentration of the first well region 2041 on the surface of the active region may adversely affect the second well region 2042 on the surface of the active region, ultimately affecting the size and doping concentration consistency of the channel region. Therefore, in some preferred embodiments, the following may be further included:

[0149] When the depth of the first well region 2041 is 1 micrometer to 2 micrometers, the dielectric protection ring is composed of a thermal oxide layer formed by thermal oxidation process or is composed of a thermal oxide layer formed by thermal oxidation process and a deposited dielectric layer formed by deposition process. The thermal oxide layer of the dielectric protection ring causes the surface of the first epitaxial layer 202 on which the superjunction structure is formed to be consumed. During the removal of the dielectric protection ring in the active region, the surface area of ​​the first well region 2041 is removed. The doping concentration of the removed surface area of ​​the first well region 2041 is higher than the doping concentration of the bottom retained area, which is used to improve the consistency of the device.

[0150] When the depth of the first well region 2041 is 2 micrometers or more, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process, or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process, or is composed of a deposited dielectric layer formed by a deposition process. The deposited dielectric layer of the dielectric protection ring reduces the thermal process of the device, thereby reducing the specific on-resistance of the device.

[0151] An anti-JFET region 205 is also formed in the active region. The anti-JFET region 205 consists of an ion implantation region of the first conductivity type that is fully formed on the surface of the superjunction structure in the active region with the dielectric guard ring as a self-alignment condition.

[0152] The anti-JFET region 205 is used to increase the first conductivity type doping concentration in the first conductivity type doping region to reduce the JFET effect.

[0153] The anti-JFET region 205 is also used in the second conductivity type doping region to compensate for the second conductivity type doping impurities of the first well region 2041 in the surface region of the active region, so as to reduce the influence of the first well region 2041 on the second conductivity type doping of the surface region of the active region, and make the second conductivity type doping of the channel region determined by the second well region 2042.

[0154] Because the active region includes a superjunction structure, which comprises first conductivity type pillars and second conductivity type pillars 203, the superjunction structure causes the surface of the active region to have first conductivity type doped regions and second conductivity type doped regions distributed thereon. After the first well region 2041 is formed on the surface of the active region, the second conductivity type doped regions on the surface of the active region will increase. Before the second well region 2042 is formed, the anti-JFET region 205 can invert all the second conductivity type doped regions to the first conductivity type. Obviously, this can eliminate the adverse effects of the surface area of ​​the first well region 2041 on the channel region, thereby improving the consistency of the device.

[0155] A heavily doped emitter region 208 of a first conductivity type is formed on the surface of the body region 204, and the emitter region 208 and the planar gate structure are self-aligned.

[0156] A second conductivity type ring is formed in the transition region, and the first well region 2041 and the second conductivity type ring have the same process structure.

[0157] Depend on Figure 3 As shown, the front-side structure of the superjunction IGBT device also includes:

[0158] Interlayer film 209, through contact hole 210; at the bottom of contact hole 210 located at the top of emitter region 208, a body contact region 211 composed of heavily doped regions of second conductivity type is also formed, so that body region 204 is connected to the top contact hole 210 together with emitter region 208 through body contact region 211.

[0159] The emitter metal and gate metal are formed by patterning the front metal layer 212.

[0160] The back-side structure of the superjunction IGBT device includes:

[0161] The collector region 213 is composed of a second conductivity type backside ion implantation region formed in the backside region of the first epitaxial sublayer 2021. That is, after the semiconductor substrate 201 is removed and part of the thickness of the first epitaxial sublayer 2021 is removed by a backside thinning process, the collector region 213 is formed by backside ion implantation of the second conductivity type.

[0162] The first epitaxial sublayer 2021 between the bottom surface of the superjunction structure and the top surface of the collector region 213 simultaneously serves as a field cutoff layer and a barrier layer for minority carriers injected from the collector region 213.

[0163] A back metal layer 214 is formed on the back side of the current collector region 213, and the back metal layer 214 forms the current collector.

[0164] In this embodiment of the invention, the superjunction IGBT device is an N-type device, with N-type as the first conductivity type and P-type as the second conductivity type. In other embodiments, the superjunction IGBT device can also be a P-type device, with P-type as the first conductivity type and N-type as the second conductivity type.

[0165] Typically, the doping concentrations of the first epitaxial sublayer 2021, the second epitaxial sublayer 2022, and the third epitaxial sublayer 2023 can also be expressed using resistivity; a higher resistivity indicates a lower doping concentration, and vice versa. In some embodiments, the first epitaxial sublayer 2021 is a high-concentration layer, with a corresponding resistivity of, for example, 1 ohm·cm to 1.5 ohm·cm, which is at least 10% lower than the resistivity of the second epitaxial sublayer 2022. The second epitaxial sublayer 2022 is a low-concentration layer, with a corresponding resistivity of, for example, 2.5 ohm·cm to 3 ohm·cm. The resistivity of the third epitaxial sublayer 2023 is lower than that of the second epitaxial sublayer 2022, for example, 2.4 ohm·cm. The resistivity and thickness of the second epitaxial sublayer 2022 and the third epitaxial sublayer 2023 are mainly set to account for the tilt angle of the second conductive type pillar 203 in the superjunction trench, to achieve better charge balance.

[0166] In some embodiments, the process conditions for back-side ion implantation of the current collector region 213 are: B 60-100 KeV, 1-3 E13 / cm 2 That is, the injected impurity is B, the injected energy is 60keV-100keV, and the injected dose is 1-3E13 / cm. 2 The current collector region 213 is also activated by back-side laser annealing.

[0167] The configuration of the first epitaxial layer 202 formed by stacking the first epitaxial sublayer 2021, the second epitaxial sublayer 2022, and the third epitaxial sublayer 2023 has the following advantages:

[0168] 1. The concentration of the first epitaxial sublayer 2021 is increased, while ensuring that the P-type pillar, i.e. the second conductivity type pillar 203, contacts the first epitaxial sublayer 2021. Due to the high concentration of the first epitaxial sublayer 2021, the influence of the P-type pillar depth change on BVdss can be reduced, and the uniformity of BVdss can be improved.

[0169] 2. The high concentration of the first epitaxial sublayer 2021 also serves as a field cutoff layer; in addition, the high concentration of the first epitaxial sublayer 2021 makes it easy to make a fast-turn-off SJ IGBT, because the high concentration of the first epitaxial sublayer 2021 blocks the holes injected from the back side P.

[0170] Unlike existing technologies where the channel region is composed of ion-implanted regions defined by a photomask, the channel region in this embodiment of the invention is composed of a second well region 2042 that is self-aligned with the planar gate structure. Since the second well region 2042 and the planar gate structure are self-aligned, the second well region 2042 does not need to be defined by a photomask. Therefore, the influence of photolithography on the pattern width and photolithography overlay on the pattern position can be eliminated. That is, the length of the channel region formed by the second well region 2042 will not be affected by the photolithography process and photolithography overlay accuracy corresponding to the well region. Similarly, the length of the channel region will not be affected by the photolithography and etching process and photolithography overlay accuracy of the polysilicon gate. This can improve the consistency of the channel region length, the consistency of the device on-resistance and threshold voltage, and the consistency of the gate-source capacitance (Cgs). Finally, it can greatly improve the consistency of the device.

[0171] Furthermore, if the second well region 2042, which is self-aligned with the planar gate structure, is used alone as the entire body region 204, the formation process of the second well region 2042 will be limited by the planar gate structure, resulting in a shallow depth of the body region 204 formed solely by the second well region 2042, leading to a larger device leakage current. To address this, embodiments of the present invention can also combine the base gate of the second well region 2042 with a first well region 2041 formed by a photomask before the planar gate structure to form the body region 204. This allows the second well region 2042 to improve device consistency, while the deeper junction depth and gradual change structure of the first well region 2041 can be used to reduce device leakage current.

[0172] Furthermore, after the first well region 2041 is introduced into the body region 204, the first well region 2041 will extend downwards from the surface of the active region. Thus, the first well region 2041 located on the surface of the active region may become part of the channel region, affecting the length of the channel region and ultimately the device consistency. To address this new problem, this invention adds a fully implanted anti-JFET region 205 in the active region. Since the anti-JFET region 205 is only located on the surface of the active region and is doped with the first conductivity type opposite to that of the first well region 2041, it will affect the first conductivity type of the surface region of the first well region 2041. To compensate for the doping of the second conductivity type, the doping concentration of the JFET-resistant region 205 is typically greater than the doping concentration of the surface region of the first well region 2041. Therefore, before the formation of the second well region 2042, the JFET-resistant region 205 will cause the surface of the second conductivity type doped region in the active region to be inverted to the first conductivity type doped, thus making the entire surface of the active region doped with the first conductivity type. This can eliminate the adverse effects of the introduction of the first well region 2041 on the length and doping concentration of the channel region, thereby improving the consistency of the device, including the consistency of the channel length and the consistency of the threshold voltage.

[0173] The region in the anti-JFET region 205 that actually reduces the JFET effect is the area between the channel regions covered by the planar gate structure. The width of this region is only affected by the width of the planar gate structure, which in turn is affected by the photolithography and etching process of the planar gate structure. The photolithography overlay accuracy of the planar gate structure does not affect the width of the anti-JFET region 205 covered by the planar gate structure between the channel regions. Therefore, the consistency of the gate-drain capacitance (Cgd) of the device is also greatly improved.

[0174] In addition, when the junction depth of the first well region 2041 in this embodiment of the invention is small, the surface region with a high doping concentration of the first well region 2041 can be removed by a thermal oxide layer, such as a thermal oxide layer forming a dielectric protection ring, thereby reducing the adverse effect of the surface region with a high doping concentration of the first well region 2041 on the channel region and further improving the consistency of the device.

[0175] When the junction depth of the first well region 2041 in this embodiment of the invention is relatively deep, the doping concentration of the entire first well region 2041 is slowed down by utilizing the deeper junction depth. In this way, the doping concentration of the surface region of the first well region 2041 will also be reduced, thereby reducing the adverse effects of the surface region of the first well region 2041 on the channel region and improving the consistency of the device.

[0176] As can be seen from the above, in this embodiment of the invention, due to the use of self-alignment, the second well region 2042 is not affected by inconsistencies in position caused by the overlay progress, nor by differences in the width of the polysilicon gate. Therefore, the consistency of the channel length of the device is significantly improved, which improves the consistency of the threshold voltage, the consistency of the on-resistance, and the consistency of Cgs. Furthermore, the width of the N-type anti-JFET region between channels, which directly affects the size of Cgd, only varies with the width of the polysilicon gate, eliminating the influence of the overlay accuracy of the polysilicon gate lithography and the size and overlay accuracy of the Pwell, as is present in the prior art, thus significantly improving consistency.

[0177] In this embodiment of the invention, the first well region 2041 is formed before the polysilicon gate. Different depths can be obtained by adjusting the injection energy, annealing temperature, and time according to process requirements. Generally, increasing the depth can reduce the device's leakage current Ids. Simultaneously, because the impurity concentration of the first well region 2041 can be designed to be relatively low, especially by using a thermal oxide film to create a dielectric protection ring, such as a protective ring oxide film, this process adsorbs a significant amount of P-type impurities from the first well region 2041 onto the interface between the oxide film and the silicon interface. The higher concentration of surface P-type impurities is depleted, leaving only the P-type impurities pushed into deeper locations. This further improves the device's uniformity.

[0178] In this embodiment of the invention, the first epitaxial layer 202 is further layered, with a higher doping concentration in the bottom first epitaxial sublayer 2021. The bottom surface of the superjunction trench is required to extend into the first epitaxial sublayer 2021. By utilizing the higher doping concentration of the first epitaxial sublayer 2021 than that of the top first epitaxial layer 202, the impact of superjunction trench depth deviation on breakdown voltage and the uniformity of breakdown voltage can be reduced. This is because: when the concentration of the first epitaxial sublayer 2021 increases, the breakdown voltage below the top surface of the first epitaxial sublayer 2021 is mainly determined by the first epitaxial sublayer 2021. Therefore, the effective thickness of the superjunction structure is actually located at the top surface of the first epitaxial sublayer 2021. Thus, even if there are depth deviations in different regions of the superjunction trench, since the bottom surface of the superjunction trench is always within the first epitaxial sublayer 2021, the longitudinal position difference of the bottom surface of the superjunction trench will not have a significant impact on the breakdown voltage. Therefore, this invention can reduce the impact of superjunction trench depth deviation on breakdown voltage and improve the uniformity of breakdown voltage.

[0179] Meanwhile, the collector region 213 is formed on the back side of the first epitaxial sublayer 2021. Thus, the first epitaxial sublayer 2021, located between the bottom surface of the superjunction structure and the top surface of the collector region 213, can serve as a field cutoff layer, thereby improving the electric field distribution in the drift region and increasing the breakdown voltage of the device.

[0180] Meanwhile, the first epitaxial sublayer 2021 also serves as a barrier layer for injecting minority carriers in the collector region 213, thereby improving the device's turn-off speed.

[0181] In this embodiment of the invention, the doping concentration distribution of the first epitaxial layer 202 in the top region of the first epitaxial sublayer 2021 can be set to increase from bottom to top according to the requirement of compensating for the influence of the side-tilted superjunction trench on the charge balance of the superjunction structure. For example, the first epitaxial layer 202 in the top region of the first epitaxial sublayer 2021 can be set as a superposition layer of the second epitaxial sublayer 2022 and the third epitaxial sublayer 2023 with a smaller doping concentration, thereby improving the charge balance at each longitudinal position of the superjunction structure and ultimately improving the device breakdown voltage.

[0182] like Figure 4 The diagram shown is a flowchart of a method for manufacturing a superjunction IGBT device according to an embodiment of the present invention. Figure 4 The process uses photomask layers to represent each step. For example... Figures 5A to 5E The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the superjunction IGBT device according to an embodiment of the present invention. The manufacturing method of the superjunction IGBT device according to an embodiment of the present invention includes the following steps:

[0183] First, step S201 is performed. Step S201 is used to form the zero-layer mark, which requires a photolithography and etching process. Figure 4 In this context, step S201 is also represented by Zero photo & etch.

[0184] Step 1, such as Figure 5A As shown, a first epitaxial layer 202 doped with a first conductivity type is formed on a semiconductor substrate 201. A plurality of superjunction trenches are formed in a selected region of the first epitaxial layer 202. A second epitaxial layer doped with a second conductivity type is filled in the superjunction trenches. The second epitaxial layer filled in the superjunction trenches forms a second conductivity type pillar 203. The first epitaxial layer 202 between the second conductivity type pillars 203 forms a first conductivity type pillar.

[0185] A superjunction structure is formed by alternating arrangement of multiple first-conductivity type pillars and second-conductivity type pillars 203. Each superjunction unit consists of one first-conductivity type pillar and one adjacent second-conductivity type pillar 203.

[0186] The depth of each superjunction trench has a deviation caused by the etching process of the superjunction trench. The first epitaxial layer 202 includes a first epitaxial sublayer 2021 located in the bottom region of the first epitaxial layer 202. The bottom surface of each superjunction trench is located in the first epitaxial sublayer 2021. The doping concentration of the first epitaxial sublayer 2021 is greater than the doping concentration in the region of the first epitaxial layer 202 located at the top of the first epitaxial sublayer 2021, so as to reduce the impact of the depth deviation of the superjunction trench on the breakdown voltage and improve the breakdown voltage uniformity.

[0187] In the method of this embodiment of the invention, the semiconductor substrate 201 includes a silicon substrate.

[0188] The superjunction trench has inclined sides and a top opening that is larger than the bottom opening, which is beneficial for the etching and filling of the superjunction trench.

[0189] The region of the first epitaxial layer 202 located on top of the first epitaxial sublayer 2021 has a doping concentration distribution that increases from bottom to top to compensate for the influence of the side-tilted superjunction trench on the charge balance of the superjunction structure. In some preferred embodiments, the region of the first epitaxial layer 202 located on top of the first epitaxial sublayer 2021 includes at least a second epitaxial sublayer 2022 and a third epitaxial sublayer 2023, the second epitaxial sublayer 2022 being stacked on the top surface of the first epitaxial sublayer 2021, the third epitaxial sublayer 2023 being stacked on the top surface of the second epitaxial sublayer 2022, and the doping concentration of the third epitaxial sublayer 2023 being greater than that of the second epitaxial sublayer 2022. Figure 5A As shown, the first epitaxial layer 202 is formed by stacking the first epitaxial sublayer 2021, the second epitaxial sublayer 2022 and the third epitaxial sublayer 2023.

[0190] In some embodiments, the first epitaxial sublayer 2021 is a high-concentration layer with a resistivity of, for example, 1 ohm·cm to 1.5 ohm·cm, which is at least 10% lower than the resistivity of the second epitaxial sublayer 2022. The second epitaxial sublayer 2022 is a low-concentration layer with a resistivity of, for example, 2.5 ohm·cm to 3 ohm·cm. The resistivity of the third epitaxial sublayer 2023 is lower than that of the second epitaxial sublayer 2022, for example, 2.4 ohm·cm. The resistivity and thickness of the second epitaxial sublayer 2022 and the third epitaxial sublayer 2023 are mainly set to account for the tilt angle of the second conductive type pillar 203 in the superjunction trench, so as to obtain a better charge balance.

[0191] In the method of this embodiment of the invention, the second conductive type pillar 203 is formed by trench etching and trench filling process. Figure 4 Step S202 in the text corresponds to step one. Figure 4 In this context, step S202 is also represented by Trench photo & etch.

[0192] In the method of the embodiments of the present invention, such as Figure 5A As shown, after step one is completed, the following steps are also included to form the first well region 2041:

[0193] The formation region of the first well region 2041 is defined by forming a pattern of photoresist 301 using a photolithography process. The first well region 2041 is located on top of the second conductivity type pillar 203 in the active region.

[0194] The first well region 2041 is formed by implanting ions of the second conductivity type.

[0195] The first well region 2041 is annealed and advanced; in the lateral direction, after annealing and advancement, the first well region 2041 and the side of the planar gate structure are spaced apart, the first well region 2041 and the side of the planar gate structure are aligned, or the first well region 2041 extends to the bottom of the planar gate structure.

[0196] In the lateral direction, the first well region 2041 at least covers the center position of the second conductive type pillar 203 and the width of the first well region 2041 on both sides of the center position of the second conductive type pillar 203 is more than 0.2 micrometers; or, the width of the first well region 2041 covering the second conductive type pillar 203 is 1 micrometer to 2 micrometers or greater than 2 micrometers.

[0197] In the vertical direction, the depth of the first well region 2041 is 1 micrometer to 2 micrometers; or, the depth of the first well region 2041 is more than 2 micrometers.

[0198] Preferably, a second conductivity type ring is formed in the transition region, and the first well region 2041 and the second conductivity type ring are formed simultaneously using the same process. Taking an N-type device as an example, the second conductivity type ring is a P-type ring. Figure 4 Step S203 corresponds to the formation process of the P-type ring and the first well region 2041. Figure 4 In this context, step S203 is also represented by Pring photo & IMP, where IMP stands for ion implantation. In other embodiments, it can also be that the second conductivity type ring and the first well region 2041 are formed separately; or, the formation processes of the second conductivity type ring and the first well region 2041 are simultaneously cancelled; or, the formation process of the first well region 2041 is cancelled separately, while the formation process of the second conductivity type ring is retained.

[0199] Step 2: Define an active region on the semiconductor substrate 201.

[0200] In the method of this embodiment of the invention, step two includes the following sub-steps:

[0201] like Figure 5B As shown, a material layer (Gfield) 303 with a dielectric protection ring is formed on the surface of the first epitaxial layer 202 on which the superjunction structure is formed.

[0202] Photolithography defines the formation region of the active region.

[0203] like Figure 5C As shown, the dielectric protection ring is formed by etching the material layer 303 of the dielectric protection ring. The dielectric protection ring covers the transition region and the terminal region and opens the active region. The area enclosed by the dielectric protection ring is the active region. The transition region surrounds the periphery of the active region, and the terminal region surrounds the periphery of the transition region.

[0204] Figure 5A In the diagram, surface 302 represents the surface of the active region. When the depth of the first well region 2041 is 1 micrometer to 2 micrometers, the doping concentration of the first well region 2041 is relatively high near surface 302. In this case, in some preferred embodiments, the high doping concentration on the surface of the first well region 2041 is removed by means of: the dielectric guard ring is composed of a thermally oxidized layer formed by a thermal oxidation process or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process, wherein the thermally oxidized layer of the dielectric guard ring causes wear on the surface of the first epitaxial layer 202 on which the superjunction structure is formed. Figure 5B As shown, surface 304 is the bottom surface of the material layer 303 of the dielectric protection ring. Obviously, surface 304 is located below surface 302. The material of the first epitaxial layer 202, which forms the superjunction structure between surface 302 and surface 304, such as silicon, is oxidized, so that the surface region 2041a of the first well region 2041 is also oxidized.

[0205] During the removal of the dielectric protection ring in the active region, the surface region 2041a of the first well region 2041 is removed. The doping concentration of the removed surface region 2041a of the first well region 2041 is higher than that of the bottom retained region, which is used to improve the uniformity of the device. Figure 5C The image shows the surface of the active region reduced to surface 304.

[0206] In some other preferred embodiments, the depth of the first well region 2041 can be greater than 2 micrometers, after diffusion propulsion. Figure 5AIn the vicinity of surface 302, the doping concentration of the first well region 2041 becomes lighter. At this time, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process, or a combination of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process, or a deposited dielectric layer formed by a deposition process. The deposited dielectric layer of the dielectric protection ring reduces the thermal process of the device, thereby lowering the specific on-resistance. That is, in this case, the material layer 303 of the dielectric protection ring has multiple formation processes to choose from. For example, when the material layer 303 of the dielectric protection ring is entirely composed of a deposited dielectric layer, the thermal process of the device is reduced, thus lowering the specific on-resistance.

[0207] Figure 4 Step S204 corresponds to step two. Since the photomask in step two mainly involves the photolithography and etching of the material layer 303 of the dielectric protection ring, i.e., the Gfield, therefore... Figure 4 In this context, step S204 is also represented by Gfield photo & etch.

[0208] like Figure 5D As shown, in the method of this embodiment of the invention, after step two is completed and before step three is performed, the following steps are included to form the JFET-resistant region 205:

[0209] Using the dielectric guard ring as a self-alignment condition, first conductivity type ion implantation is performed to fully form the JFET-resistant region 205 on the surface of the active region.

[0210] The anti-JFET region 205 is used to increase the first conductivity type doping concentration in the first conductivity type doping region to reduce the JFET effect.

[0211] The anti-JFET region 205 is also used in the second conductivity type doping region to compensate for the second conductivity type doping impurities of the first well region 2041 on the surface region of the active region, so as to reduce the influence of the first well region 2041 on the second conductivity type doping of the surface region of the active region, and so that the second conductivity type doping of the channel region is determined by the subsequent second well region 2042.

[0212] Depend on Figure 5DAs shown, since the width of the first well region 2041 is greater than the width of the second conductivity type pillar 203, the second conductivity type doped region of the surface area of ​​the active region is the surface area of ​​the first well region 2041, and the first conductivity type doped region of the surface area of ​​the active region is the surface area of ​​the first conductivity type pillar between the first well regions 2041. After the JFET-resistant region 205 is formed, the JFET-resistant region 205 inverts the surface of the second conductivity type doped region to the first conductivity type doped region. In this way, the entire surface area of ​​the active region is doped with the first conductivity type. Taking an N-type device as an example, after the JFET-resistant region 205 is formed, the surface of the active region is N-type doped, which can prevent the P-type doping of the active region from having an adverse effect on the uniformity of the channel region.

[0213] Figure 4 Step S205 in the text corresponds to the formation step of the JFET-resistant region 205. Figure 4 In this context, step S205 is also represented using JFET IMP. Figure 2 As can be seen from the corresponding flowchart, the method of the present invention has modified the process of JFET IMP. JFET IMP no longer needs to use photomask definition, so step S205 is located outside the photomask process.

[0214] Step 3, as follows Figure 5E As shown, a planar gate structure is formed in the active region, and each planar gate structure is formed on the top of each first conductivity type pillar. The planar gate structure is an integral structure. The planar gate structure is formed by stacking a gate dielectric layer 206 and a gate conductive material layer 207.

[0215] In the method of this embodiment of the invention, the gate dielectric layer 206 includes a gate oxide layer.

[0216] The gate conductive material layer 207 includes a polysilicon gate.

[0217] Figure 4 Step S206 corresponds to step three, in which a photomask is used to define the polysilicon. Figure 4 In this context, step S206 is also represented by poly photo & etch.

[0218] Step 4, as follows Figure 5E As shown, a second well region 2042 is formed by ion implantation of the second conductivity type with the planar gate structure as the self-alignment condition. The second well region 2042 is then annealed, and under the action of the annealing process, the second well region 2042 laterally diffuses to the bottom region of the planar gate structure.

[0219] The channel region is composed of the second well region 2042 covered by the planar gate structure, and the self-alignment structure between the second well region 2042 and the planar gate structure is used to improve the consistency of the device.

[0220] The body region 204 is formed by vertically stacking the first well region 2041 and the second well region 2042. The junction depth of the first well region 2041 is greater than that of the second well region 2042, and the doping concentration of the first well is less than that of the second well region 2042, in order to reduce the leakage current of the device.

[0221] Figure 4 Step S207 in the text corresponds to step four. Figure 4 In this context, step S207 is also represented using Pwell IMP. Figure 2 As can be seen from the corresponding flowchart, the method of the present invention has modified the process of Pwell IMP. Pwell IMP no longer needs to use photomask definition, so step S207 is located outside the photomask process.

[0222] Step four also includes:

[0223] like Figure 5F As shown, ion implantation of a first conductivity type with the planar gate structure as the self-alignment condition is performed in the active region to form the emitter region 208. Taking an N-type device as an example, the emitter region 208 is an N+ region (Nplus). Figure 4 Step S208 corresponds to the formation process of the emission region 208. This formation process requires using a photomask to define the formation area of ​​the emission region 208. Figure 4 In this context, step S208 is also represented by Nplusphoto&IMP.

[0224] Next, interlayer membrane 209.

[0225] A contact hole (Cont) 210 is formed through the interlayer film 209. The formation process of the contact hole 210 requires first using a photolithography process to define the formation area of ​​the contact hole 210, then etching to form the opening of the contact hole 210, and finally filling the opening of the contact hole 210 with metal to form the contact hole. Figure 4 Step S209 corresponds to the forming process step of the contact hole 210. In the forming process step of the contact hole 210, a photomask is used to define the forming area of ​​the contact hole 210. Figure 4 In this context, step S209 is also represented by Cont photo & etch.

[0226] A body contact region 211, composed of heavily doped regions of a second conductivity type, is also formed at the bottom of the contact hole 210 located at the top of the emitter region 208, so that the body region 204 is connected to the top contact hole 210 together with the emitter region 208 through the body contact region 211. The body contact region 211 is formed by implanting heavily doped ions of the second conductivity type after the opening of the contact hole 210 is opened.

[0227] A front metal layer 212 is formed and patterned to form an emitter metal and a gate metal. Figure 4 Step S210 corresponds to the formation process of the front metal layer 212. This formation process requires using a photomask to define the patterned area of ​​the front metal layer 212. Figure 4 In this context, step S210 is also represented by Metal photo & etch.

[0228] After completing the front-side process, the following back-side process is also included:

[0229] Step 5, as follows Figure 3 As shown, back-side thinning is performed, which completely removes the semiconductor substrate 201 and retains a portion of the thickness of the first epitaxial sublayer 2021. In some embodiments, before back-side thinning, the thickness of the first epitaxial sublayer 2021 is less than 10 micrometers; after back-side thinning, the thickness of the retained first epitaxial sublayer 2021 is 3 to 8 micrometers.

[0230] In the method of this embodiment, no photomask is used in the back-side process, therefore... Figure 4 The process flow of the back-side process is not shown in the document.

[0231] Step Six, as Figure 3 As shown, a second conductivity type backside ion implantation is performed to form a collector region 213 in the backside region of the retained first epitaxial sublayer 2021; the first epitaxial sublayer 2021 between the bottom surface of the superjunction structure and the top surface of the collector region 213 simultaneously serves as a field cutoff layer and a barrier layer for implanted minority carriers of the collector region 213, thereby improving the turn-off speed of the device.

[0232] In some embodiments, the back-side ion implantation process conditions for the current collector 213 are: B60-100 KeV, 1-3 E13 / cm². 2 That is, the injected impurity is B, the injected energy is 60keV-100keV, and the injected dose is 1-3E13 / cm. 2 The current collector region 213 is also activated by back-side laser annealing.

[0233] like Figure 3 As shown, a back metal layer 214 is formed on the back side of the collector region 213, and the back metal layer 214 forms the collector electrode.

[0234] In the method of this embodiment, the superjunction IGBT device is an N-type device, with N-type as the first conductivity type and P-type as the second conductivity type. In other embodiments, the superjunction IGBT device can also be a P-type device, with P-type as the first conductivity type and N-type as the second conductivity type.

[0235] In this embodiment of the invention, the formation of the P-type channel region in the active region is self-aligned. To address the potential issue of relatively shallow P-type well depth leading to high device leakage current, a P-type ring injection process is employed. Furthermore, to mitigate the impact of inconsistent P-type ring injection positions on device consistency, full JFET injection in the active region is implemented, achieving a complete surface inversion of the active region. This improves the consistency of the chip's Cgs and Cgd.

[0236] In addition, the embodiments of the present invention specifically designed at least three layers of N epitaxy with different concentrations to improve the consistency of BVdss of the device.

[0237] This invention eliminates the impact of Pwell lithography and polysilicon lithography overlay precision on device performance, significantly improving the consistency of channel width. This improves the consistency of threshold voltage, on-resistance, and Cgs. Furthermore, the width of the N-type JFET region between channels, which directly affects Cgd size, only varies with the width of the polysilicon gate. This eliminates the influence of polysilicon gate lithography overlay precision, as well as the size and overlay precision of the Pwell, which are present in existing technologies, thus greatly improving consistency.

[0238] The method of the present invention will be further described below with reference to specific parameters:

[0239] Taking a 650V superjunction IGBT as an example, a superjunction (SJ) structure with a step size of 9 micrometers is adopted. The width of the top trench, i.e., the top width of the superjunction trench, is set to 4.5 micrometers, and the width of the top N-type epitaxial layer, i.e., the top width of the first epitaxial layer 202, is also set to 4.5 micrometers. The top width of the superjunction trench is the same as the top width of the formed second conductivity type pillar 203, and the top width of the first epitaxial layer 202 is the same as the top width of the first conductivity type pillar.

[0240] The semiconductor substrate 201 is N-type, but P-type can also be selected in other embodiments. Its resistivity is 1-10 ohm·cm, which is on the same order of magnitude as the resistivity of the first epitaxial layer 202 on it, thus avoiding the impact of impurity diffusion on chip performance.

[0241] In step one, the first epitaxial layer 202 deposited on the high-concentration semiconductor substrate 201 can be set as follows:

[0242] The total thickness of the first epitaxial layer 202 is 55 micrometers. The thicknesses of the three sub-layers of the first epitaxial layer 202 are as follows: sub-layer 2021 is 10 micrometers, sub-layer 2022 is 25 micrometers, and sub-layer 2023 is 20 micrometers.

[0243] The superjunction trench has a certain tilt angle, for example, between 89 and 89.5 degrees. Based on the center value of the tilt angle, epitaxial layers with different resistivities can be designed. The main goal is to achieve a better charge balance in both the upper and lower regions of the superjunction trench, thereby obtaining a higher BVdss or a better balance between BVdss and Rsp. One implementation involves depositing a 10-micrometer N-type epitaxial sublayer 2021 with a resistivity of 1.0 ohm·cm on a high-concentration semiconductor substrate 201, followed by a 25-micrometer N-type epitaxial sublayer 2022 with a resistivity of 2.5 ohm·cm, and then a 20-micrometer N-type epitaxial sublayer 2023 with a resistivity of 2.0 ohm·cm, maintaining the total thickness of the N-type epitaxial layer 202 at 55 micrometers.

[0244] The process of forming the superjunction structure in step one mainly involves forming P-type pillars 203, including photolithography and etching of trenches, i.e., superjunction trenches, P-type epitaxial filling and planarization in the trenches.

[0245] A dielectric film can be deposited on the N-type epitaxial layer, i.e., the first epitaxial layer 202. The dielectric film can be a single oxide film, such as an oxide film with a thickness of more than 1 micrometer. This oxide film can be used as a hard mask during trench etching. After the trench is formed, an oxide film of a certain thickness will remain, such as an oxide film with a thickness of 0.1-0.2 micrometers. During the CMP process after the epitaxial filling is completed, this oxide film serves as a protective layer for the N-type epitaxy during CMP, so that the SI at this location will not be defective due to the CMP process, causing leakage or quality problems.

[0246] The dielectric film here can also consist of an oxide film with a thickness of 0.1-0.15 micrometers, a SiN film with a thickness of 0.1-0.2 micrometers, and an oxide film with a thickness greater than 1 μm on top. This allows for better control of uniformity during fabrication: for example, after trench etching is completed, at least some SiN is left on the oxide film below it. Before epitaxial growth, the SiN is removed. This results in good uniformity of the oxide film before epitaxial growth, which also improves the uniformity of CMP.

[0247] A further improvement to the above-mentioned multilayer film structure is that the first oxide film is formed by thermal oxidation, which further improves the uniformity.

[0248] During the filling process of the P-type epitaxial layer, if the superjunction trench has a certain tilt angle, the N-type epitaxial layer lateral to the second conductivity type pillar (i.e., the P-type pillar) is composed of two resistivities, namely sublayers 2022 and 2023. Based on the requirement of optimal charge balance, the P-type impurity concentration in the trench can be divided into different segments. For example, P-type epitaxy with different resistivities or a single concentration of P-type epitaxy can be used. The goal is to obtain the optimal balance between BVdss and Rsp.

[0249] In the process steps of forming the first well region 2041 and the P-ring: the P-ring of the transition region is defined by P-ring photolithography, and the region of the first P-ring well in the active region, i.e., the region of the first well region 2041, is also defined. The P-ring surrounds the active region of the chip, and its width can range from 1 micrometer to 50 micrometers. When the gate bus is wide, the P-ring can also be widened because it does not bring additional chip area increase. When the gate bus is small or even some areas do not have a gate bus, the P-ring can also be reduced in size, and the design can be considered in terms of EAS capability requirements. The P-ring region of the active region, i.e., the first well region 2041, can have some overlap with the subsequent active region polygate, or it can be aligned with the polygate, or even have a certain distance from the polygate, as long as it is ensured that when the final process is completed, the first well region 2041 must cover the top of the P-ring pillar by 1-2 micrometers, or more, or at least cover the top of the P-ring pillar vertically by 1-2 micrometers, and laterally cover the area of ​​at least 0.2 micrometers to the left and right of the trench center.

[0250] The impurity implanted into the P-type ring can be B, BF2, or a combination thereof. The energy can be selected from 30 keV to 2 meV, depending on the required depth of the P-type column and the temperature and time of the subsequent thermal process. The dosage can be 5 E12-5 E13 atoms / cm², with one design being 60 keV to 1 E13 atoms / cm² for B.

[0251] Step two in forming the dielectric protection ring includes:

[0252] The dielectric guard ring will cover the transition region and the terminal region except for the outermost N+ region, which is not necessarily required and will be removed in the active region. In some embodiments, the material layer 303 of the dielectric guard ring is formed by thermal oxidation at a temperature of 850°C-1050°C and a thickness of 8000 angstroms to 10000 angstroms, or at least partially formed by a thermal oxide film. In this way, while pushing the P-type impurities of the previously implanted first well region 2041 into the Si depth direction, a portion of the surface Si, for example 3500 angstroms-4000 angstroms containing the implanted P-type impurities, is also oxidized.

[0253] By using dielectric protection ring photolithography and etching, the surface material layer 303 in the active region is completely removed.

[0254] In the step of forming the JFET-resistant region 205:

[0255] After the dielectric guard ring photolithography and etching are completed, the dielectric guard ring is used as a mask to perform comprehensive JFET-resistant implantation on at least the active region, forming a high-concentration N-type JFET-resistant region 205. The implanted N-type impurities can be phosphorus or arsenic. The main purpose is to create a region on the silicon wafer surface with a higher concentration of N-type epitaxial impurities than the N-type epitaxial impurities, reducing the device's Rsp. Here, this process can simultaneously compensate for the P-type impurities on the surface of the first well region 2041, making the entire surface of the active region N-type. This reduces the impact of the first well region 2041 process on the device surface, that is, it reduces the impact of the critical dimensions and overlay accuracy of the first well region 2041 photolithography on the device's threshold voltage (Vth) and other performance characteristics.

[0256] The formation process of the second well region 2042 includes the following parameters:

[0257] Ion implantation of the second well region 2042 is self-aligned with a polysilicon gate, and the impurity can be B, BF2, or a combination thereof. In the method of this embodiment, B is used; the energy and dose are set according to the threshold voltage requirements and the desired depth of the second well region 2042. For example, one ion implantation process parameter includes: implanted impurity is B, implantation energy is 120keV-150keV, and implantation dose is 1E14-2E14 / cm. 2 The obtained Vth is between 2V and 4V.

[0258] Here, the thickness of the gate oxide film, i.e., the gate dielectric layer 206, is set to 700-1000 angstroms. It is a thermal oxide film manufactured at a temperature of 850℃-1050℃.

[0259] The polysilicon gate, i.e., the gate conductive material layer 207, is an in-situ doped high-concentration N-type polysilicon with a thickness of 4000 angstroms to 8000 angstroms, such as 4000 angstroms.

[0260] Ion implantation in the second well region 2042 can be performed after the photoresist has been removed from the polycrystalline lithography, or after polycrystalline lithography etching is complete but before the photoresist has been removed. When implantation is performed while the photoresist is still attached, higher-energy P-type ion implantation can be used.

[0261] After ion implantation of the second well region 2042 is completed, the second well region 2042 is pushed to the required lateral and longitudinal positions by an annealing process at 1000℃-1150℃ for 30-180 minutes.

[0262] The process for forming the launch region 208 includes:

[0263] After the polycrystalline electrode is formed, at least the emitter region 208 of the device is formed by N+ photolithography and ion implantation. At the same time, a terminal N+ region can be formed in the outermost region of the terminal. The terminal peripheral N+ region can be used to prevent surface inversion in the terminal region, which improves the stability of the device's breakdown characteristics. The terminal peripheral N+ region can also be omitted.

[0264] The N+ injection in the emitter region 208 can generally be formed by AS or Phos injection, or a combination thereof. Injection conditions are typically 30-100 keV and 1-5 E15 / cm². 2 It can be activated through a thermal process at 9000-1050℃ after injection.

[0265] The process for forming the interlayer membrane 209 and the contact hole 210 includes:

[0266] An interlayer film 209 is deposited, which can be a combination of an undoped oxide film and a BPSG film. Then, the openings of contact holes 210 are formed through photolithography and etching. After forming the openings of contact holes 210, high-concentration P implantation is performed to form a bulk contact region 211 composed of a high-concentration P-type region, ensuring good ohmic contact between the metal and the bulk region 204. The implanted impurities in this bulk contact region 211 can be B or BF2, with the implantation energy set to 20-60 keV and the dose set to 1E13-3E15 / cm. 2 After ion implantation, activation can be achieved through a thermal process at temperatures of 690-900℃.

[0267] During the etching of the opening of the contact hole 210, silicon in the high concentration region of N+ impurities at the bottom of the interlayer film 209 can also be etched away. The etching amount can be between 2000 angstroms and 4000 angstroms, depending on the N+ implantation conditions, i.e., the implantation energy and dose. Generally, the thickness of the interlayer film is 6000-10000 angstroms.

[0268] The formation process of the interlayer film 209, contact hole 210 and front metal layer 212 includes:

[0269] An interlayer film 209 is deposited, which can be a combination of an undoped oxide film and a BPSG film. Then, the openings of contact holes 210 are formed through photolithography and etching. After forming the openings of contact holes 210, high-concentration P implantation is performed to form a bulk contact region 211 composed of a high-concentration P-type region, ensuring good ohmic contact between the metal and the bulk region 204. The implanted impurities in this bulk contact region 211 can be B or BF2, with the implantation energy set to 20-60 keV and the dose set to 1E13-3E15 / cm. 2 After ion implantation, activation can be achieved through a thermal process at temperatures of 690-900℃.

[0270] During the etching of the opening of the contact hole 210, silicon in the high concentration region of N+ impurities at the bottom of the interlayer film 209 can also be etched away. The etching amount can be between 2000 angstroms and 4000 angstroms, depending on the N+ implantation conditions, i.e., the implantation energy and dose. Generally, the thickness of the interlayer film is 6000-10000 angstroms.

[0271] The metal filling the opening of contact hole 210 can be Ti, TiN, or W, followed by etching back or CMP. Then, AlSi is deposited on the front side of the silicon wafer to form a front metal layer 212. In a preferred embodiment, the width of contact hole 210 is set to 0.5 micrometers, the thickness of interlayer film 209 is set to 8000-10000 angstroms, and the opening of contact hole 210 is formed by filling with Ti / TiN and W followed by etching back or CMP.

[0272] If the contact hole 210 is large enough, Ti, TiN, AlCu, AlSiCu, or AlSiCu deposition can be used to directly fill the opening of the contact hole 210 and form the front metal layer 212. Then, photolithography of the front metal layer 212 is performed to form the active region emitter metal and gate metal. The thickness of the barrier layer can be Ti... and TiN The thickness of AlCu or AlSiCu metal is typically 4-6 μm.

[0273] In the back-side process:

[0274] In step five, the thickness of the epitaxial sublayer 2021 left by the back-side thinning is 3-8 micrometers.

[0275] In step six, the backside ion implantation is a P-type impurity implantation, with the implantation conditions being: B 60keV-100keV, 1-3E13 / cm. 2 That is, the injected impurity is B, the injected energy is 60keV-100keV, and the injected dose is 1-3E13 / cm. 2 .

[0276] After laser annealing to activate the implanted ions, a back metal layer 214 is deposited on the back side to form a collector.

[0277] This completes the formation of a superjunction IGBT device.

[0278] In some embodiments, after the front metal layer 212 of the silicon wafer, i.e., the semiconductor substrate 201, is formed, a passivation film can be deposited, photolithographically etched, and etched, or polyimide photolithography can be added, followed by back-side thinning and deposition of the back metal layer 214, thereby further improving the reliability of the device. The passivation film thickness is generally... It can be an oxide film, SIN, SION, or a combination thereof. Polyimide is generally 5-10 micrometers thick after high-temperature baking. Both the passivation film and polyimide mainly cover the terminal area and the boundary with the front metal layer 212, generally covering 5-10 micrometers, and forming a 0-10 micrometer protection at the outermost edge of the dicing groove.

[0279] In one improved embodiment of the method, the following process parameters can be used:

[0280] In the formation process of the first well region 2041, the photoresist is used with a thickness of more than 3 micrometers, and the P-type implantation of the first well region 2041 is 1.5-2 MeV, so that the peak concentration of ion implantation is located more than 1 micrometer away from the Si surface. This ensures that the junction depth of the first well region 2041 is at least more than 2 micrometers, which can reduce the leakage current Idss of the device.

[0281] In one improved embodiment of the method, the following process parameters can be used:

[0282] After the P-type implantation of the first well region 2041 is completed and before the dielectric protection ring is formed, a high-temperature push-well process is added, such as annealing at a temperature of 1000-1150°C for 30-180 minutes, to push the depth of the first well region 2041 to a position 2 micrometers or deeper from the Si surface, and to reduce and gradually change the distribution of P-type well impurities in the first well region 2041 in the depth direction, further reducing the leakage current Ids of the device and improving the characteristics of the device body diode.

[0283] In one improved embodiment of the method, the following process parameters can be used:

[0284] After the P-type implantation of the first well region 2041 is completed and before the formation of the dielectric protection ring, a high-temperature push-well process is added, such as annealing at a temperature of 1000-1150℃ for 30-180 minutes. This pushes the depth of the first well region 2041 to a position 2 micrometers or deeper from the Si surface, and reduces and gradually modulates the distribution of P-type well impurities in the depth direction, further reducing the leakage current Ids of the device and improving the characteristics of the body diode. Simultaneously, the dielectric protection ring uses a deposited dielectric film instead of a thermally oxidized film, thus reducing the thermal processes in the manufacturing process.

[0285] In one improved embodiment of the method, the following process parameters can be used:

[0286] In the formation process of the first well region 2041, the overlap between the first well region 2041 and the polysilicon gate can be set between 0.32 and 0.5 micrometers. This ensures that under normal process control, there is an overlap of greater than or equal to 0 micrometers between the first well region 2041 and the polysilicon gate of all units, which can improve the consistency of the leakage current Idss of the device.

[0287] In one improved embodiment of the method, the following process parameters can be used:

[0288] In step four, ion implantation in the second well region 2042 can employ high-energy implantation, for example, B ion implantation with an energy higher than 1 MeV. Increasing the implantation energy increases the effective channel length of the device and reduces the leakage current Idss. In an improved embodiment, the following process parameters can be used:

[0289] The process of forming the first well region 2041 is cancelled. Figure 4 In step S203, only the second well region 2042 formed in the self-aligned process is used as the body region. At this time, the leakage current ids of the device will increase, but the consistency of switching characteristics, Vth, on-resistance (Rdson) will be further improved.

[0290] In one improved embodiment of the method, the following process parameters can be used:

[0291] The formation process of the first well region 2041 is cancelled, but the process is retained. Figure 4 In step S203, a P-type ring is formed only in the transition region. The first well region 2041 is not formed in the active region. Instead, a second well region 2042 is formed in the self-aligned process as the body region. In this case, the leakage current ids of the device will increase, but the consistency of switching characteristics, Vth, Rdson, etc. will be further improved.

[0292] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A superjunction IGBT device, characterized in that, include: A first epitaxial layer doped with a first conductivity type has a superjunction structure formed in the first epitaxial layer. The superjunction structure is formed by alternating arrangement of multiple first conductivity type pillars and second conductivity type pillars. Each superjunction unit consists of a first conductivity type pillar and an adjacent second conductivity type pillar. The second conductivity type pillar includes a second epitaxial layer doped with the second conductivity type and filled in a superjunction trench, and the first conductivity type pillar is composed of the first epitaxial layer between the second conductivity type pillars; The structures of superjunction IGBT devices located in the active region include: A planar gate structure is formed on top of each of the first conductivity type pillars, and the planar gate structure is an integral structure; the planar gate structure is composed of a gate dielectric layer and a gate conductive material layer stacked together; The second well region is formed by annealing an ion-implanted region of the second conductivity type with the planar gate structure as the self-alignment condition; the second well region diffuses laterally to the bottom region of the planar gate structure under the action of the annealing process. The channel region is composed of the second well region covered by the planar gate structure, and the self-aligned structure between the second well region and the planar gate structure is used to improve the consistency of the device. The depth of each superjunction trench has a deviation caused by the etching process of the superjunction trench. The first epitaxial layer includes a first epitaxial sublayer located in the bottom region of the first epitaxial layer. The bottom surface of each superjunction trench is located in the first epitaxial sublayer. The doping concentration of the first epitaxial sublayer is greater than the doping concentration in the region located at the top of the first epitaxial sublayer in the first epitaxial layer, so as to reduce the impact of the depth deviation of the superjunction trench on the breakdown voltage and improve the breakdown voltage uniformity. The current-collecting region is composed of a second conductivity type back ion implantation region formed in the back region of the first epitaxial sublayer; The first epitaxial sublayer between the bottom surface of the superjunction structure and the top surface of the collector region serves simultaneously as a field cutoff layer and a barrier layer for minority carriers injected from the collector region.

2. The superjunction IGBT device as described in claim 1, characterized in that: The superjunction trench has inclined sides and a top opening that is larger than the bottom opening; The region of the first epitaxial layer located at the top of the first epitaxial sublayer has a doping concentration distribution that increases from bottom to top to compensate for the effect of the side-tilted superjunction trench on the charge balance of the superjunction structure.

3. The superjunction IGBT device as described in claim 2, characterized in that: The region at the top of the first epitaxial sublayer of the first epitaxial layer includes at least a second epitaxial sublayer and a third epitaxial sublayer. The second epitaxial sublayer is superimposed on the top surface of the first epitaxial sublayer, and the third epitaxial sublayer is superimposed on the top surface of the second epitaxial sublayer. The doping concentration of the third epitaxial sublayer is greater than that of the second epitaxial sublayer.

4. The superjunction IGBT device as described in claim 3, characterized in that: The resistivity of the first epitaxial sublayer is at least 10% lower than that of the second epitaxial sublayer.

5. The superjunction IGBT device as described in claim 1, characterized in that, The structure of the superjunction IGBT device located in the active region further includes: The first well region is composed of ion implantation regions of the second conductivity type formed on the top of each second conductivity type pillar, and the formation region of the first well region is defined by photolithography. In the lateral direction, there is a gap between the first well region and the side of the planar gate structure, the first well region and the side of the planar gate structure are aligned, or the first well region extends to the bottom of the planar gate structure; The body region is formed by the vertical stacking of the first well region and the second well region. The junction depth of the first well region is greater than that of the second well region, and the doping concentration of the first well region is less than that of the second well region, in order to reduce the leakage current of the device.

6. The superjunction IGBT device as described in claim 5, characterized in that: A dielectric protection ring is formed on the surface of the first epitaxial layer on which the superjunction structure is formed. The dielectric protection ring covers the transition region and the terminal region and opens the active region. The area enclosed by the dielectric protection ring is the active region. The transition region surrounds the periphery of the active region, and the terminal region surrounds the periphery of the transition region. An anti-JFET region is also formed in the active region. The anti-JFET region consists of an ion implantation region of the first conductivity type that is fully formed on the surface of the superjunction structure in the active region with the dielectric guard ring as a self-alignment condition. The anti-JFET region is used to increase the first conductivity type doping concentration in the first conductivity type doping region in order to reduce the JFET effect. The anti-JFET region is also used in the second conductivity type doping region to compensate for the second conductivity type doping impurities of the first well region in the surface region of the active region, so as to reduce the influence of the first well region on the second conductivity type doping of the surface region of the active region, and make the second conductivity type doping of the channel region determined by the second well region.

7. The superjunction IGBT device as described in claim 5, characterized in that: A heavily doped emitter region of a first conductivity type is formed on the surface of the body region, and the emitter region and the planar gate structure are self-aligned.

8. The superjunction IGBT device as described in claim 6, characterized in that: In the lateral direction, the first well region covers at least the center of the second conductive type pillar and the width of the first well region on both sides of the center of the second conductive type pillar is more than 0.2 micrometers; or, the width of the first well region covering the second conductive type pillar is 1 micrometer to 2 micrometers or more than 2 micrometers. In the vertical direction, the depth of the first well region is 1 micrometer to 2 micrometers; or, the depth of the first well region is more than 2 micrometers.

9. The superjunction IGBT device as described in claim 8, characterized in that: When the depth of the first well region is 1 micrometer to 2 micrometers, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process. The thermally oxidized layer of the dielectric protection ring causes the surface of the first epitaxial layer on which the superjunction structure is formed to be consumed. During the removal of the dielectric protection ring in the active region, the surface region of the first well region is removed. The doping concentration of the removed surface region of the first well region is higher than the doping concentration of the bottom retained region, which is used to improve the consistency of the device. When the depth of the first well region is 2 micrometers or more, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process, or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process, or is composed of a deposited dielectric layer formed by a deposition process. The deposited dielectric layer of the dielectric protection ring reduces the thermal process of the device, thereby reducing the specific on-resistance of the device.

10. The superjunction IGBT device as described in claim 9, characterized in that: A second conductivity type ring is formed in the transition region, and the first well region and the second conductivity type ring have the same process structure.

11. The superjunction IGBT device according to any one of claims 1 to 10, characterized in that: The superjunction IGBT device is an N-type device with an N-type first conductivity type and a P-type second conductivity type; or, the superjunction IGBT device is a P-type device with a P-type first conductivity type and an N-type second conductivity type.

12. A method for manufacturing a superjunction IGBT device, characterized in that, Includes the following steps: Step 1: Form a first epitaxial layer doped with a first conductivity type on a semiconductor substrate. Form a plurality of superjunction trenches in a selected region of the first epitaxial layer. Fill the superjunction trenches with a second epitaxial layer doped with a second conductivity type. The second epitaxial layer filled in the superjunction trenches serves as a component of a second conductivity type pillar. The first epitaxial layers between the second conductivity type pillars form a first conductivity type pillar. A superjunction structure is formed by alternating arrangement of multiple first conductivity type pillars and second conductivity type pillars, and the superjunction unit consists of one first conductivity type pillar and one adjacent second conductivity type pillar; The depth of each superjunction trench has a deviation caused by the etching process of the superjunction trench. The first epitaxial layer includes a first epitaxial sublayer located in the bottom region of the first epitaxial layer. The bottom surface of each superjunction trench is located in the first epitaxial sublayer. The doping concentration of the first epitaxial sublayer is greater than the doping concentration in the region located at the top of the first epitaxial sublayer in the first epitaxial layer, so as to reduce the impact of the depth deviation of the superjunction trench on the breakdown voltage and improve the breakdown voltage uniformity. Step 2: Define the active region on the semiconductor substrate; Step 3: Form a planar gate structure in the active region. Each planar gate structure is formed on top of each first conductivity type pillar. The planar gate structure is an integral structure. The planar gate structure is formed by stacking a gate dielectric layer and a gate conductive material layer. Step 4: Using the planar gate structure as the self-alignment condition, perform ion implantation of the second conductivity type to form a second well region, and anneal the second well region. Under the action of the annealing treatment, the second well region laterally diffuses to the bottom region of the planar gate structure. The channel region is composed of the second well region covered by the planar gate structure, and the self-aligned structure between the second well region and the planar gate structure is used to improve the consistency of the device. Step 5: Perform back-side thinning, which completely removes the semiconductor substrate and retains a portion of the thickness of the first epitaxial sublayer. Step 6: Perform backside ion implantation of the second conductivity type to form a collector region in the backside region of the retained first epitaxial sublayer; the first epitaxial sublayer between the bottom surface of the superjunction structure and the top surface of the collector region simultaneously serves as a field cutoff layer and a barrier layer for minority carriers implanted from the collector region.

13. The method for manufacturing a superjunction IGBT device as described in claim 12, characterized in that: In step one, the super-junction trench has an inclined side and a top opening that is larger than the bottom opening; The region of the first epitaxial layer located at the top of the first epitaxial sublayer has a doping concentration distribution that increases from bottom to top to compensate for the effect of the side-tilted superjunction trench on the charge balance of the superjunction structure.

14. The method for manufacturing a superjunction IGBT device as described in claim 13, characterized in that: The region at the top of the first epitaxial sublayer of the first epitaxial layer includes at least a second epitaxial sublayer and a third epitaxial sublayer. The second epitaxial sublayer is superimposed on the top surface of the first epitaxial sublayer, and the third epitaxial sublayer is superimposed on the top surface of the second epitaxial sublayer. The doping concentration of the third epitaxial sublayer is greater than that of the second epitaxial sublayer.

15. The method for manufacturing a superjunction IGBT device as described in claim 14, characterized in that: The resistivity of the first epitaxial sublayer is at least 10% lower than that of the second epitaxial sublayer.

16. The method for manufacturing a superjunction IGBT device as described in claim 12, characterized in that: After step one is completed, the following steps are also included to form the first well region: Photolithography defines the formation region of the first well region, which is located on top of the second conductivity type pillar in the active region; The first well region is formed by implanting ions of the second conductivity type. The first well region is annealed and advanced; in the lateral direction, the annealed and advanced first well region has a gap between it and the side of the planar gate structure, the first well region is aligned with the side of the planar gate structure, or the first well region extends to the bottom of the planar gate structure; The body region is formed by the vertical stacking of the first well region and the second well region. The junction depth of the first well region is greater than that of the second well region, and the doping concentration of the first well region is less than that of the second well region, in order to reduce the leakage current of the device.

17. The method for manufacturing a superjunction IGBT device as described in claim 16, characterized in that: Step two includes the following sub-steps: A material layer with a dielectric protective ring is formed on the surface of the first epitaxial layer on which the superjunction structure is formed; Photolithography defines the formation region of the active region; The dielectric protection ring is formed by etching the material layer of the dielectric protection ring. The dielectric protection ring covers the transition region and the terminal region and opens the active region. The area enclosed by the dielectric protection ring is the active region. The transition region surrounds the periphery of the active region, and the terminal region surrounds the periphery of the transition region.

18. The method for manufacturing a superjunction IGBT device as described in claim 17, characterized in that: After step two is completed and before step three is performed, the following steps are included to form the JFET-resistant region: Using the dielectric guard ring as a self-alignment condition, first conductivity type ion implantation is performed to fully form the JFET-resistant region on the surface of the active region. The anti-JFET region is used to increase the first conductivity type doping concentration in the first conductivity type doping region in order to reduce the JFET effect. The anti-JFET region is also used in the second conductivity type doping region to compensate for the second conductivity type doping impurities of the first well region in the surface region of the active region, so as to reduce the influence of the first well region on the second conductivity type doping of the surface region of the active region, and make the second conductivity type doping of the channel region determined by the second well region.

19. The method for manufacturing a superjunction IGBT device as described in claim 18, characterized in that: Step four is followed by: performing ion implantation of a first conductivity type heavily doped in the active region with the planar gate structure as the self-alignment condition to form an emitter region.

20. The method for manufacturing a superjunction IGBT device as described in claim 18, characterized in that: In the lateral direction, the first well region covers at least the center of the second conductive type pillar and the width of the first well region on both sides of the center of the second conductive type pillar is more than 0.2 micrometers; or, the width of the first well region covering the second conductive type pillar is 1 micrometer to 2 micrometers or more than 2 micrometers. In the vertical direction, the depth of the first well region is 1 micrometer to 2 micrometers; or, the depth of the first well region is more than 2 micrometers.

21. The method for manufacturing a superjunction IGBT device as described in claim 20, characterized in that: When the depth of the first well region is 1 micrometer to 2 micrometers, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process. The thermally oxidized layer of the dielectric protection ring causes the surface of the first epitaxial layer on which the superjunction structure is formed to be consumed. During the removal of the dielectric protection ring in the active region, the surface region of the first well region is removed. The doping concentration of the removed surface region of the first well region is higher than the doping concentration of the bottom retained region, which is used to improve the consistency of the device. When the depth of the first well region is 2 micrometers or more, the dielectric protection ring is composed of a thermally oxidized layer formed by a thermal oxidation process, or is composed of a thermally oxidized layer formed by a thermal oxidation process and a deposited dielectric layer formed by a deposition process, or is composed of a deposited dielectric layer formed by a deposition process. The deposited dielectric layer of the dielectric protection ring reduces the thermal process of the device, thereby reducing the specific on-resistance of the device.

22. The method for manufacturing a superjunction IGBT device as described in claim 20, characterized in that: A second conductivity type ring is formed in the transition region, and the first well region and the second conductivity type ring are formed simultaneously using the same process.

23. The method for manufacturing a superjunction IGBT device as described in claim 18, characterized in that: Before step three, after the anti-JFET region is formed, the surface of the second conductivity type doped region is inverted to the first conductivity type doped.

24. The method for manufacturing a superjunction IGBT device as described in claim 12, characterized in that: In step five, after the back side is thinned, the thickness of the retained first epitaxial sublayer is 3 micrometers to 8 micrometers.

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