Locally selective passivated emitter, solar cell and method of making the same

Abstract

The application relates to a preparation method of a locally selective passivated emitter, comprising the following steps: providing an n-type silicon wafer, texturing the silicon wafer, and demarcating a metal gate line contact area on one side of the silicon wafer; providing a carrier plate with a hollow part, and placing the silicon wafer on the carrier plate; placing the carrier plate in an oxygen environment, so that the silicon wafer in the metal gate line contact area forms a first tunneling oxide layer; placing the carrier plate in an evaporation machine, and evaporating a polysilicon layer on the surface of the tunneling oxide layer; performing high-temperature boron diffusion on the silicon wafer, so that the polysilicon layer is converted into a boron-doped polysilicon layer, a boron-doped layer is formed on the surface of the silicon wafer which is not covered by the tunneling oxide layer, and a first boron-silicon glass layer is formed on the surface of the boron-doped polysilicon layer and the boron-doped layer; performing laser propulsion treatment on the first boron-silicon glass layer covering the surface of the boron-doped polysilicon layer, so that the boron-doped polysilicon layer is converted into a heavily doped polysilicon layer, and a locally selective passivated emitter is obtained. The application can form a selective emitter with a tunneling oxide layer.

Description

Technical Field

[0001] This application relates to TOPcon batteries, and more particularly to selective emitters. Background Technology

[0002] Currently, the front surface emitter of mass-produced n-type TOPCon (Tunnel Oxide Passivated Contact solar cell) solar cells is divided into two regions: one is the region in contact with the electrode paste, and the other is the illuminated region, i.e., the region without electrode paste coverage. Most mainstream TOPCon solar cells on the market use a uniformly doped emitter, meaning both the metal paste contact region and the illuminated region are uniformly doped. This doping method is simple and fast, but its performance is limited. In the next-generation concept of selectively doped TOPCon solar cells, in the metal paste contact region, increasing the doping concentration of the surface boron-doped oxide layer can reduce the metal-semiconductor contact resistance and decrease contact recombination; in the illuminated region, maintaining a low doping concentration of the surface boron-doped oxide layer can reduce surface Auger recombination, increase carrier collection efficiency, improve short-wavelength response, and enhance passivation effect—this is the so-called selective emitter.

[0003] In the metal paste contact region, a tunneling oxide layer can be formed between the boron-doped oxide layer and the silicon substrate to create a passivated contact, which is beneficial for further improving the photoelectric conversion efficiency of solar cells. However, the boron-doped oxide layer is obtained by surface treatment of the silicon substrate, and the boron-doped oxide layer is often directly and tightly bonded to the silicon substrate, making it difficult to prepare a tunneling oxide layer between the boron-doped oxide layer and the silicon substrate. Summary of the Invention

[0004] This application provides a locally selectively passivated emitter and its preparation method, as well as a solar cell and its preparation method, to solve the technical problem that it is difficult to prepare a tunneling oxide layer between a boron-doped oxide layer and a silicon substrate.

[0005] In a first aspect, embodiments of this application provide a method for preparing a locally selectively passivated emitter, the method comprising the following steps:

[0006] An n-type silicon wafer is provided, the silicon wafer is texturized, and a metal gate contact area is defined on one side of the silicon wafer;

[0007] A carrier tray with a cutout portion is provided, the shape, size and distribution of the cutout portion being exactly the same as the metal gate contact area. The silicon wafer is placed on the carrier tray so that the metal gate contact area and the cutout portion completely overlap.

[0008] The carrier disk is placed in an oxygen-rich environment, causing the silicon wafer in the metal gate contact area to be oxidized, forming a first tunneling oxide layer;

[0009] The carrier disk is placed in a vapor deposition machine, and a polycrystalline silicon layer is vapor deposited on the surface of the tunneling oxide layer.

[0010] The silicon wafer is subjected to high-temperature boron diffusion to transform the polycrystalline silicon layer into a boron-doped polycrystalline silicon layer, thereby forming a boron-doped layer on the surface of the silicon wafer not covered by the tunneling oxide layer, and forming a first borosilicate glass layer on the surface of the boron-doped polycrystalline silicon layer and the boron-doped layer.

[0011] A first borosilicate glass layer covering the surface of the boron-doped polycrystalline silicon layer is subjected to laser propulsion to transform the boron-doped polycrystalline silicon layer into a heavily doped polycrystalline silicon layer, thereby obtaining the locally selective passivated emitter.

[0012] In some embodiments of this application, the step of placing the carrier disk in an oxygen-rich environment to oxidize the silicon wafer within the metal gate contact area is also performed within the vapor deposition machine.

[0013] In some embodiments of this application, a polycrystalline silicon layer is deposited on the surface of the tunneling oxide layer, wherein the surface temperature of the tunneling oxide layer is maintained at 450–550°C, the evaporation source for the deposition is polycrystalline silicon powder, and the deposition is carried out at a temperature of 3 × 10⁻⁶ °C. -3 ~10×10 -3 Performed at Pa.

[0014] In some embodiments of this application, the high-temperature boron diffusion is carried out in a predetermined atmosphere containing at least one of BCl3 and BBr3, as well as oxygen.

[0015] In some embodiments of this application, the high-temperature boron diffusion is carried out at 1000–1100°C.

[0016] In some embodiments of this application, the thickness of the polycrystalline silicon layer is 50–200 nm.

[0017] Secondly, embodiments of this application provide a locally selectively passivated emitter, which is prepared by the method described in any embodiment of the first aspect.

[0018] Thirdly, embodiments of this application provide a solar cell, the solar cell including the locally selectively passivated emitter described in any embodiment of the second aspect.

[0019] Fourthly, embodiments of this application provide a method for preparing a solar cell, the method comprising the following steps:

[0020] Provide the selectively passivated emitter as described in the second aspect;

[0021] Remove the first borosilicate glass layer;

[0022] A second borosilicate glass layer is formed on the surface of the heavily doped polycrystalline silicon layer and the boron doped layer by high-temperature oxidation.

[0023] After removing the second borosilicate glass layer from the other side of the silicon wafer, alkaline polishing is performed to remove the boron doping layer, forming a polished surface.

[0024] A second tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are sequentially prepared on the polished surface;

[0025] Remove the second borosilicate glass layer from one side of the silicon wafer;

[0026] Passivation layers and antireflection layers are sequentially prepared on the surfaces of the heavily doped polycrystalline silicon layer and the boron doped layer, and an antireflection layer is also prepared on the surface of the phosphorus doped polycrystalline silicon layer.

[0027] Metal electrode grid lines are fabricated in the metal grid line contact area on an antireflection layer on one side of the silicon wafer.

[0028] In some embodiments of this application, the removal of the first borosilicate glass layer is performed by removing the first borosilicate glass layer with hydrofluoric acid; and / or,

[0029] The removal of the second borosilicate glass layer from the other side of the silicon wafer is performed by removing the second borosilicate glass layer with hydrofluoric acid; and / or,

[0030] The second borosilicate glass layer on one side of the silicon wafer is removed by hydrofluoric acid.

[0031] The technical solutions provided in this application have the following advantages compared with the prior art:

[0032] The method for preparing a locally selective passivated emitter provided in this application involves preparing a tunneling oxide layer separately in the metal gate contact region, then preparing a polycrystalline silicon layer on the tunneling oxide layer through a vapor deposition process, and then performing boron doping on the entire silicon wafer and laser propulsion on the polycrystalline silicon layer to prepare the vapor-deposited polycrystalline silicon layer into a heavily doped polycrystalline silicon layer, while the doping concentration of the silicon wafer is low, thereby forming a selective emitter with a tunneling oxide layer. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A schematic diagram of the structure of the product obtained in step S11 of the method for preparing a locally selectively passivated emitter provided in an embodiment of this application;

[0036] Figure 2 This is a schematic diagram of the carrier disk provided in an embodiment of this application;

[0037] Figure 3 A schematic diagram of the structure of the product obtained in step S13 of the method for preparing a locally selectively passivated emitter provided in an embodiment of this application;

[0038] Figure 4 A schematic diagram of the structure of the product obtained in step S14 of the method for preparing a locally selectively passivated emitter provided in an embodiment of this application;

[0039] Figure 5 A schematic diagram of the structure of the product obtained in step S15 of the method for preparing a locally selectively passivated emitter provided in an embodiment of this application;

[0040] Figure 6 A schematic diagram of the structure of the product obtained in step S16 of the method for preparing a locally selectively passivated emitter provided in an embodiment of this application;

[0041] Figure 7 A schematic diagram of the structure of the product obtained in step S22 of the method for preparing a solar cell according to an embodiment of this application;

[0042] Figure 8 A schematic diagram of the structure of the product obtained in step S23 of the method for preparing a solar cell according to an embodiment of this application;

[0043] Figure 9 A schematic diagram of the structure of the product obtained in step S24 of the method for preparing a solar cell according to an embodiment of this application;

[0044] Figure 10 A schematic diagram of the structure of the product obtained in step S25 of the method for preparing a solar cell according to an embodiment of this application;

[0045] Figure 11 A schematic diagram of the structure of the product obtained in step S26 of the method for preparing a solar cell according to an embodiment of this application;

[0046] Figure 12A schematic diagram of the structure of the product obtained in step S27 of the method for preparing a solar cell according to an embodiment of this application;

[0047] Figure 13 This is a schematic diagram of the structure of the product obtained in step S28 of a method for preparing a solar cell according to an embodiment of this application. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0049] Unless otherwise specified, the terminology used herein should be understood as having the meaning as commonly used in the art. Therefore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. In case of any conflict, this specification shall prevail.

[0050] Unless otherwise specified, all raw materials, reagents, instruments and equipment used in this application can be purchased from the market or prepared by existing methods.

[0051] Existing TOPcon cells face the technical challenge of fabricating a tunneling oxide layer between the boron-doped oxide layer and the silicon substrate.

[0052] The technical solution provided in this application is to solve the above-mentioned technical problems, and the general idea is as follows:

[0053] In a first aspect, embodiments of this application provide a method for preparing a locally selectively passivated emitter, the method comprising the following steps:

[0054] S11: Provide an n-type silicon wafer 1, texturing the silicon wafer 1, and marking a metal gate contact area on one side of the silicon wafer 1. The product obtained in step S1 is as follows: Figure 1 As shown;

[0055] S12: A carrier tray with a cutout portion 01 is provided. The shape, size, and distribution of the cutout portion 01 are exactly the same as the metal gate contact area. The silicon wafer 1 is placed on the carrier tray so that the metal gate contact area and the cutout portion 01 completely overlap. The structure of the carrier tray is as follows: Figure 2 As shown;

[0056] S13: Place the carrier disk in an oxygen-rich environment to oxidize the silicon wafer 1 within the metal gate contact area, forming a first tunneling oxide layer 2. The product obtained in step S3 is as follows: Figure 3 As shown;

[0057] S14: Place the carrier disk in the evaporation machine and evaporate a polycrystalline silicon layer 3 onto the surface of the tunneling oxide layer. The product obtained in step S4 is as follows: Figure 4 As shown;

[0058] S15: High-temperature boron diffusion is performed on the silicon wafer 1 to transform the polycrystalline silicon layer 3 into a boron-doped polycrystalline silicon layer 4, forming a boron-doped layer 5 on the surface of the silicon wafer 1 not covered by the tunneling oxide layer, and a first borosilicate glass layer 6 is formed on the surfaces of the boron-doped polycrystalline silicon layer 4 and the boron-doped layer 5. The product obtained in step S5 is as follows: Figure 5 As shown;

[0059] S16: The first borosilicate glass layer 6 covering the surface of the boron-doped polysilicon layer 4 is subjected to laser propulsion processing to transform the boron-doped polysilicon layer 4 into a heavily doped polysilicon layer 7, thereby obtaining the locally selective passivated emitter. The product obtained in step S6 is as follows: Figure 6 As shown.

[0060] Those skilled in the art will understand that the metal grid contact area is a predetermined area for fabricating the metal electrode.

[0061] Those skilled in the art will understand that texturing is a conventional technique in the field, which can form special morphologies on the surface of silicon wafer 1. For example, alkaline texturing can produce a pyramidal morphology, and acid texturing can produce a wormhole-like morphology. Texturing can improve the light-trapping effect of silicon wafer 1. In the field of Topcon solar cells, alkaline texturing is generally used.

[0062] It is easy to understand that when the carrier disk is placed in an oxygen-rich environment, since the metal gate contact area completely overlaps with the cutout portion 01, the silicon wafer 1 at the cutout portion 01, i.e., the silicon wafer 1 in the metal gate contact area, is directly exposed to the oxygen-rich environment. The silicon wafer 1 in the non-metal gate contact area, however, is not exposed to the oxygen-rich environment because it is in direct contact with the carrier disk. Therefore, step S3 can form the first tunneling oxide layer 2 only on the surface of the silicon wafer 1 within the metal gate contact area.

[0063] Those skilled in the art will understand that high-temperature boron diffusion is a conventional process in the field. This process can be used to dope silicon materials with boron and form borosilicate glass.

[0064] Those skilled in the art will understand that laser propulsion is a conventional technique in the field, referring to the technique of using lasers to process doped layers, causing doped atoms to diffuse into the substrate.

[0065] This application prepares a tunneling oxide layer separately in the metal gate contact area, and then prepares a polycrystalline silicon layer 3 on the tunneling oxide layer by evaporation process. Then, the silicon wafer 1 is boron doped as a whole and the polycrystalline silicon layer 3 is laser-driven to prepare the evaporated polycrystalline silicon layer 3 into a heavily doped polycrystalline silicon layer 7, while the doping concentration of the silicon wafer 1 is low, thereby forming a selective emitter with a tunneling oxide layer.

[0066] In some embodiments of this application, the step of placing the carrier disk in an oxygen-rich environment to oxidize the silicon wafer 1 within the metal gate contact area is also performed within the vapor deposition machine.

[0067] Specifically, the tunneling oxide layer can be prepared by introducing oxygen into the evaporation machine. Both the tunneling oxide layer and the polycrystalline silicon layer 3 are prepared within the evaporation machine, which simplifies the process flow.

[0068] Those skilled in the art can reasonably set the preparation conditions of the tunneling oxide layer based on common knowledge. For example, the reaction conditions can be to keep the temperature of the silicon wafer 1 at 450-550°C while introducing oxygen.

[0069] In some embodiments of this application, a polycrystalline silicon layer 3 is deposited on the surface of the tunneling oxide layer, wherein the surface temperature of the tunneling oxide layer is maintained at 450–550°C, the evaporation source for the deposition is polycrystalline silicon powder, and the deposition is carried out at a temperature of 3 × 10⁻⁶ °C. -3 ~10×10 -3 Performed at Pa.

[0070] As an example, the surface temperature of the tunneling oxide layer can be one of 450°C, 470°C, 500°C, 520°C, or 550°C.

[0071] As an example, the vapor deposition can be performed at 3×10 -3 5×10 -3 6×10 -3 8×10 -3 10×10 -3 It is carried out under a pressure of Pa.

[0072] In some embodiments of this application, the high-temperature boron diffusion is carried out in a predetermined atmosphere containing at least one of BCl3 and BBr3, as well as oxygen.

[0073] In some embodiments of this application, the high-temperature boron diffusion is carried out at 1000–1100°C.

[0074] As an example, the high-temperature boron diffusion can be carried out at one of the following temperatures: 1000°C, 1030°C, 1050°C, 1070°C, and 1100°C.

[0075] In some embodiments of this application, the thickness of the polycrystalline silicon layer 3 is 50–200 nm.

[0076] As an example, the thickness of the polycrystalline silicon can be one of 50nm, 70nm, 100nm, 130nm, 170nm, or 200nm.

[0077] Secondly, embodiments of this application provide a locally selectively passivated emitter, which is prepared by the method described in any embodiment of the first aspect. The locally selectively passivated emitter is implemented based on the preparation method described in the first aspect. Specific implementations of the locally selectively passivated emitter can refer to the embodiments of the first aspect. Since the locally selectively passivated emitter can adopt all the technical solutions of any embodiment of the first aspect, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0078] Thirdly, embodiments of this application provide a solar cell, which includes the locally selectively passivated emitter described in any embodiment of the second aspect. The solar cell is implemented based on the locally selectively passivated emitter described in the second aspect. Specific implementations of the solar cell can refer to the embodiments of the second aspect and common knowledge in the art. Since the solar cell can adopt all the technical solutions of any embodiment of the second aspect, it at least has all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0079] Fourthly, embodiments of this application provide a method for preparing a solar cell, the method comprising the following steps:

[0080] S21: Provide the selectively passivated emitter as described in the second aspect, i.e., the selectively passivated emitter obtained in step S6, such as... Figure 6 As shown;

[0081] S22: Remove the first borosilicate glass layer 6. The product obtained in step S22 is as follows: Figure 7 As shown;

[0082] S23: A second borosilicate glass layer 8 is formed on the surfaces of the heavily doped polycrystalline silicon layer 7 and the boron doped layer 5 by high-temperature oxidation. The product obtained in step S23 is as follows: Figure 8 As shown;

[0083] S24: After removing the second borosilicate glass layer 8 from the other side of the silicon wafer 1, alkaline polishing is performed to remove the boron doped layer 5, forming a polished surface. The product obtained in step S24 is as follows: Figure 9 As shown;

[0084] S25: Sequentially prepare a second tunneling oxide layer 9 and a phosphorus-doped polycrystalline silicon layer 10 on the polished surface. The product obtained in step S25 is as follows: Figure 10 As shown;

[0085] S26: Remove the second borosilicate glass layer 8 from one side of the silicon wafer 1. The product obtained in step S26 is as follows: Figure 11 As shown;

[0086] S27: A passivation layer and an anti-reflection layer are sequentially prepared on the surfaces of the heavily doped polycrystalline silicon layer 7 and the boron-doped layer 5, and an anti-reflection layer is also prepared on the surface of the phosphorus-doped polycrystalline silicon layer 10. The product obtained in step S27 is as follows: Figure 12 As shown.

[0087] S28: On the antireflection layer of one side of the silicon wafer 1, a metal electrode gate line 13 is fabricated in the metal gate line contact area. The product obtained in step S28 is as follows: Figure 13 As shown.

[0088] It is easy to understand that the solar cell obtained by the method for preparing the solar cell is a part of the embodiments of the solar cell described in the third aspect.

[0089] Those skilled in the art will understand that metal electrode grids are a conventional structure in the field. The material for metal electrode grids is generally formed using a conductive electrode paste. For example, commercially available metallized silver paste used in p-type crystalline silicon solar cells can be used, such as silver paste containing Pb-Te-O glass powder. As an exemplary fabrication method, the electrode paste can be applied to the silicon wafer 1 in a desired patterned form via screen printing. After drying, post-processing such as sintering can be performed. The conductive layer formed by the electrode paste forms an electrical contact with the silicon wafer 1, thus forming the metal electrode grids.

[0090] In some embodiments of this application, the removal of the first borosilicate glass layer 6 is performed by removing the first borosilicate glass layer 6 with hydrofluoric acid; and / or,

[0091] The removal of the second borosilicate glass layer 8 from the other side of the silicon wafer 1 is performed by removing the second borosilicate glass layer 8 with hydrofluoric acid; and / or,

[0092] The removal of the second borosilicate glass layer 8 from one side of the silicon wafer 1 is achieved by removing the second borosilicate glass layer 8 with hydrofluoric acid.

[0093] The present application is further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the application. Experimental methods in the following embodiments that do not specify specific conditions are generally determined according to industry standards. If there is no corresponding industry standard, then common international standards, conventional conditions, or conditions recommended by the manufacturer are followed.

[0094] Example

[0095] This application provides a method for preparing a solar cell, the method comprising the following steps:

[0096] Step 1: Provide an n-type silicon wafer, texturize the n-type silicon wafer, and mark a metal gate contact area on one side of the silicon wafer;

[0097] Step 2: Provide a carrier tray with a cutout portion, the shape, size and distribution of which are exactly the same as the metal gate contact area. Place the silicon wafer on the carrier tray so that the metal gate contact area and the cutout portion completely overlap.

[0098] Step 3: Place the carrier disk in the vapor deposition machine, introduce air into the vapor deposition machine, and heat the silicon wafer to 500°C to oxidize the silicon wafer in the metal gate contact area to form the first tunneling oxide layer;

[0099] Step 4: Maintain the temperature of the silicon wafer at 500°C, and evacuate the vapor deposition machine until the pressure drops to 3×10⁻⁶. -3 Pa, using polycrystalline silicon powder as the evaporation source, deposits a 50nm thick polycrystalline silicon layer on the surface of the tunneling oxide layer.

[0100] Step 5: Introduce BBr3 and oxygen into a low-pressure diffusion furnace and perform high-temperature boron diffusion on the silicon wafer at 1000-1100°C to transform the polycrystalline silicon layer into a boron-doped polycrystalline silicon layer, so that a boron-doped layer is formed on the surface of the silicon wafer not covered by the tunneling oxide layer, and a first borosilicate glass layer is formed on the surface of the boron-doped polycrystalline silicon layer and the boron-doped layer.

[0101] Step 6: Perform laser propulsion on the first borosilicate glass layer covering the surface of the boron-doped polycrystalline silicon layer to transform the boron-doped polycrystalline silicon layer into a heavily doped polycrystalline silicon layer, thereby obtaining the locally selective passivated emitter.

[0102] Step 7: Remove the first borosilicate glass layer on the locally selectively passivated emitter using hydrofluoric acid;

[0103] Step 8: A second borosilicate glass layer is formed on the surface of the heavily doped polycrystalline silicon layer and the boron doped layer by high-temperature oxidation.

[0104] Step 9: In a chain cleaning machine, after removing the second borosilicate glass layer from the other side of the silicon wafer with hydrofluoric acid, alkaline polishing is performed to remove the boron doping layer, forming a polished surface;

[0105] Step 10: Sequentially prepare a second tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer on the polished surface;

[0106] Step 11: In a chain cleaning machine, the second borosilicate glass layer on one side of the silicon wafer is removed by hydrofluoric acid;

[0107] Step 12: A passivation layer and an anti-reflection layer are sequentially prepared on the surfaces of the heavily doped polycrystalline silicon layer and the boron doped layer, and an anti-reflection layer is also prepared on the surface of the phosphorus doped polycrystalline silicon layer;

[0108] Step 13: On the antireflection layer of one side of the silicon wafer, metal electrode grid lines are fabricated in the metal grid line contact area to obtain the solar cell.

[0109] Various embodiments of this application may exist in the form of a range; it should be understood that the description in the form of a range is merely for convenience and brevity and should not be construed as a hard limitation on the scope of this application; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single numerical values ​​within that range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and single numbers within the range, such as 1, 2, 3, 4, 5, and 6, regardless of the range. Furthermore, whenever a numerical range is referred to herein, it means including any referenced number (fraction or integer) within the referred range.

[0110] In the description of this application, the terms "comprising," "including," etc., mean "including but not limited to." Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. In this document, "and / or" describes the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, or B alone. For associations involving three or more related objects described using "and / or", it indicates that any one of the three related objects can exist alone, or at least two of them can exist simultaneously. For example, for A, and / or B, and / or C, it can mean that any one of A, B, and C exists alone, or any two of them exist simultaneously, or all three of them exist simultaneously. In this document, "at least one" means one or more, and "more than one" means two or more. "At least one", "at least one of the following", or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, "at least one of a, b, or c", or "at least one of a, b, and c", can both mean: a, b, c, ab (i.e., a and b), ac, bc, or abc, where a, b, and c can each be single or multiple.

[0111] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for preparing a locally selectively passivated emitter, characterized in that, The method for preparing the locally selectively passivated emitter includes the following steps: An n-type silicon wafer is provided, the silicon wafer is texturized, and a metal gate contact area is defined on one side of the silicon wafer; A carrier tray with a cutout portion is provided, the shape, size and distribution of the cutout portion being exactly the same as the metal gate contact area. The silicon wafer is placed on the carrier tray so that the metal gate contact area and the cutout portion completely overlap. The carrier disk is placed in an oxygen-rich environment, causing the silicon wafer in the metal gate contact area to be oxidized, forming a first tunneling oxide layer; The carrier disk is placed in a vapor deposition machine, and a polycrystalline silicon layer is vapor deposited on the surface of the tunneling oxide layer. The silicon wafer is subjected to high-temperature boron diffusion to transform the polycrystalline silicon layer into a boron-doped polycrystalline silicon layer, thereby forming a boron-doped layer on the surface of the silicon wafer not covered by the tunneling oxide layer, and forming a first borosilicate glass layer on the surface of the boron-doped polycrystalline silicon layer and the boron-doped layer. A first borosilicate glass layer covering the surface of the boron-doped polycrystalline silicon layer is subjected to laser propulsion to transform the boron-doped polycrystalline silicon layer into a heavily doped polycrystalline silicon layer, thereby obtaining the locally selective passivated emitter.

2. The method for preparing a locally selectively passivated emitter according to claim 1, characterized in that, The process of placing the carrier disk in an oxygen-rich environment to oxidize the silicon wafer within the metal grid contact area is also performed within the vapor deposition machine.

3. The method for preparing a locally selectively passivated emitter according to claim 2, characterized in that, A polycrystalline silicon layer is deposited on the surface of the tunneling oxide layer, wherein the surface temperature of the tunneling oxide layer is maintained at 450–550°C, the evaporation source for the deposition is polycrystalline silicon powder, and the deposition is carried out at a temperature of 3 × 10⁻⁶ °C. -3 ~10×10 -3 Performed at Pa.

4. The method for preparing a locally selectively passivated emitter according to claim 1, characterized in that, The high-temperature boron diffusion is carried out in a predetermined atmosphere containing at least one of BCl3 and BBr3, as well as oxygen.

5. The method for preparing a locally selectively passivated emitter according to claim 1, characterized in that, The high-temperature boron diffusion is carried out at 1000–1100°C.

6. The method for preparing a locally selectively passivated emitter according to claim 1, characterized in that, The thickness of the polycrystalline silicon layer is 50–200 nm.

7. A locally selectively passivated emitter, characterized in that, The locally selectively passivated emitter is prepared by the method described in any one of claims 1 to 6.

8. A solar cell, characterized in that, The solar cell includes the locally selectively passivated emitter as described in claim 7.

9. A method for preparing a solar cell, characterized in that, The method for preparing the solar cell includes the following steps: Provides the selectively passivated emitter as described in claim 8; Remove the first borosilicate glass layer; A second borosilicate glass layer is formed on the surface of the heavily doped polycrystalline silicon layer and the boron doped layer by high-temperature oxidation. After removing the second borosilicate glass layer from the other side of the silicon wafer, alkaline polishing is performed to remove the boron doping layer, forming a polished surface. A second tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are sequentially prepared on the polished surface; Remove the second borosilicate glass layer from one side of the silicon wafer; Passivation layers and antireflection layers are sequentially prepared on the surfaces of the heavily doped polycrystalline silicon layer and the boron doped layer, and an antireflection layer is also prepared on the surface of the phosphorus doped polycrystalline silicon layer. Metal electrode grid lines are fabricated in the metal grid line contact area on an antireflection layer on one side of the silicon wafer.

10. The method for preparing a solar cell according to claim 9, characterized in that, The removal of the first borosilicate glass layer is performed by removing the first borosilicate glass layer with hydrofluoric acid; and / or, The second borosilicate glass layer is removed from the other side of the silicon wafer by using hydrofluoric acid. And / or, The second borosilicate glass layer on one side of the silicon wafer is removed by hydrofluoric acid.

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