Integrated antenna on sidewall of 3D stacked die

Abstract

This disclosure relates to an integrated antenna on the sidewall of a 3D stacked die. A semiconductor package with an integrated sidewall antenna is provided. A device includes two or more die layers bonded together, each of the two or more die layers including a top surface, a bottom surface, and one or more sidewalls. A first sidewall of the one or more sidewalls includes a first antenna array, the first antenna array including a first plurality of antenna array elements formed in at least one of the two or more die layers, wherein the first plurality of antenna array elements are at least partially exposed at the first sidewall.

Description

[0001] Copyright Notice

[0002] This patent document contains a portion of copyrighted material. The copyright holder does not object to any fax reproduction of any patent document or patent disclosure appearing in the Patent and Trademark Office's patent documents or records, but reserves all copyright rights. Technical Field

[0003] This disclosure generally relates to methods, systems, and apparatus for semiconductor packages having antennas integrated into the sidewalls. Background Technology

[0004] Sixth-generation (6G) cellular services typically utilize ultra-high frequencies (UHF) such as 300 GHz and above. Therefore, the free-space wavelength at UHF is 1 mm or less. Antenna arrays used to perform such small-wavelength beamforming are typically implemented at the wafer level rather than the package level because the spacing between antenna array elements is usually a fraction of the wavelength. However, conventional implementations of wafer-level antenna arrays can impose limitations on radiation patterns, die orientation, and semiconductor package size.

[0005] Therefore, methods, systems, and apparatus are provided for semiconductor packaging with sidewall integrated antennas. Summary of the Invention

[0006] In one aspect, this disclosure relates to an apparatus comprising: two or more die layers joined together, each of the two or more die layers including a top surface, a bottom surface, and one or more sidewalls, wherein a first sidewall of the one or more sidewalls includes a first antenna array, the first antenna array including a first plurality of antenna array elements formed in at least one of the two or more die layers, wherein the first plurality of antenna array elements are at least partially exposed at the first sidewall.

[0007] In another aspect, this disclosure relates to a semiconductor device comprising: a bottom die including an active chip; and a three-dimensional (3D) stacked die package coupled to the bottom die, wherein the 3D stacked die package includes two or more die layers bonded together, each of the two or more die layers including a top surface, a bottom surface, and one or more sidewalls, wherein a first sidewall of the one or more sidewalls includes a first antenna array, the first antenna array including a first plurality of antenna array elements formed in at least one of the two or more die layers, wherein the first plurality of antenna array elements are at least partially exposed at the first sidewall.

[0008] In a further aspect, this disclosure relates to a method comprising: stacking two or more die layers, each of the two or more die layers including at least one interconnect; bonding the two or more die layers to form a three-dimensional (3D) stacked die package, the 3D stacked die package including a top surface, a bottom surface, and one or more sidewalls; and exposing each of the at least one interconnect in the two or more die layers at at least one of the one or more sidewalls, wherein exposing each of the at least one interconnect includes making each of the at least one interconnect accessible from the outside of the 3D stacked die package; and forming one or more antenna elements of an antenna array at the at least one of the one or more sidewalls. Attached Figure Description

[0009] A further understanding of the nature and advantages of particular embodiments can be achieved by referring to the remainder of the specification and accompanying drawings, wherein similar reference numerals are used to refer to similar components. In some instances, sublabels are associated with reference numerals to indicate one of a plurality of similar components. When reference numerals are used without specifying existing sublabels, it is intended to refer to all such plurality of similar components.

[0010] Figure 1 This is a schematic diagram of a die layer according to various embodiments, the die layer being a portion of a semiconductor package having an integrated sidewall antenna;

[0011] Figure 2 This is a schematic diagram of a semiconductor package prior to exposing the integrated sidewall antenna, according to various embodiments;

[0012] Figure 3 This is a schematic diagram of a semiconductor package with an integrated sidewall antenna according to various embodiments;

[0013] Figure 4 This is a schematic diagram of a semiconductor package having an integrated sidewall antenna in a redistribution layer according to various embodiments;

[0014] Figure 5 This is a schematic diagram of a semiconductor package having integrated sidewall antennas on multiple sidewalls according to various embodiments;

[0015] Figure 6 This is a schematic diagram of a semiconductor device comprising a 3D stacked die package with an integrated sidewall antenna, according to various embodiments;

[0016] Figure 7 This is a flowchart of a method for manufacturing a 3D chip stack with integrated sidewall antennas according to various embodiments. Detailed Implementation

[0017] Various embodiments illustrate semiconductor packages with integrated sidewall antennas, and methods for manufacturing semiconductor packages with integrated sidewall antennas.

[0018] In some embodiments, a device for a semiconductor package having an integrated sidewall antenna is provided. The device includes two or more die layers bonded together, each of the two or more die layers including a top surface, a bottom surface, and one or more sidewalls. A first sidewall of the one or more sidewalls includes a first antenna array comprising a first plurality of antenna array elements formed in at least one of the two or more die layers, wherein the first plurality of antenna array elements are exposed at the first sidewall.

[0019] In other embodiments, a semiconductor device is provided with an integrated sidewall antenna. The semiconductor device includes a bottom die comprising an active chip and a three-dimensional (3D) stacked die package coupled to the bottom die. The 3D stacked die package includes two or more die layers bonded together, each of the two or more die layers including a top surface, a bottom surface, and one or more sidewalls. A first sidewall of the one or more sidewalls includes a first antenna array comprising a first plurality of antenna array elements formed in at least one of the two or more die layers, wherein the first plurality of antenna array elements are exposed at the first sidewall.

[0020] In other embodiments, a method for manufacturing a semiconductor package with integrated sidewall antennas is provided. The method includes stacking two or more die layers, each of the two or more die layers including at least one interconnect, and bonding the two or more die layers to form a three-dimensional (3D) stacked die package, the 3D stacked die package including a top surface, a bottom surface, and one or more sidewalls. The method further includes exposing each of the at least one interconnect in the two or more die layers at at least one of the one or more sidewalls, wherein exposing each of the at least one interconnect includes making each of the at least one interconnect accessible from the outside of the 3D stacked die package, and forming one or more antenna elements of an antenna array at the at least one of the one or more sidewalls.

[0021] In the following description, numerous details are set forth for purposes of explanation to provide a thorough understanding of the described embodiments. However, it will be apparent to those skilled in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, and while various features are attributed to different embodiments, it should be understood that features described with respect to one embodiment may also be incorporated into other embodiments. However, for the same reason, no single or multiple features of any described embodiment should be considered essential to every embodiment of the invention, as such features may be omitted in other embodiments of the invention.

[0022] When an element is referred to herein as “connected” or “coupled” to another element, it should be understood that the element may be directly connected to the other element, or that there may be an intermediary element between the elements. Conversely, when an element is referred to as “directly connected” or “directly coupled” to another element, it should be understood that there is no intermediary element in the “direct” connection between the elements. However, the presence of a direct connection does not preclude other connections in which intermediary elements may be present.

[0023] Similarly, when an element is referred to herein as being “joined” to another element, it should be understood that the element may be directly joined to the other element (without any intermediary element) or have an intermediary element present between the joined elements. Conversely, when an element is referred to as being “directly joined” to another element, it should be understood that there is no intermediary element in the “direct” joint between the elements. However, the presence of a direct joint does not preclude other forms of joint in which an intermediary element may be present.

[0024] Furthermore, for ease of description, the methods and processes described herein may be described in a specific order. However, it should be understood that, unless the context otherwise indicates, intermediate processes may occur before and / or after any part of the described process, and various other processes may be reordered, added, and / or omitted according to various embodiments.

[0025] Unless otherwise indicated, all figures used herein to express quantities, dimensions, etc., should be understood to be modified by the term “about” in all instances. In this application, the use of the singular includes the plural unless otherwise stated, and the use of the terms “and” and “or” means “and / or” unless otherwise indicated. Furthermore, the use of the term “comprising” and other forms such as “includes” and “included” should be considered non-exclusive. Additionally, terms such as “element” or “component” cover both elements and components comprising one unit and elements or components comprising more than one unit, unless expressly stated otherwise.

[0026] Conventional antenna arrays are typically implemented at the wafer level, utilizing very low parasitic interconnects and hybrid Cu-Cu bonding with radio frequency integrated circuits (RFICs). Antenna arrays implemented in this way are typically positioned on the top side of a die and / or on the top side of a 3D stacked die package, thereby introducing constraints on radiation patterning, orientation, and package size.

[0027] The proposed 3D stacked die package utilizes integrated sidewall antennas to provide an ultra-high frequency antenna array configured to transmit and / or receive signals at sub-THz frequencies (e.g., 300 GHz and above). By utilizing the sidewalls of the 3D stacked die package (also known as a “3D cube” or “3D die stack”), a radiation pattern laterally to the 3D die stack can be achieved. The antenna arrays on the sidewalls of the 3D die stack further exhibit improved decoupling compared to conventional arrangements. Furthermore, a single 3D stacked die package with integrated sidewall antennas can contain multiple antenna arrays. Conversely, conventional wafer / die-level antenna arrays coplanar with the die / die are confined to the top surface of the die / 3D die stack. To implement multiple antenna arrays in a conventional manner, multiple dies and / or 3D die stacks are typically used.

[0028] In this way, improved antenna array performance can be achieved by integrating sidewall antennas, and the die spacing can be used more effectively.

[0029] Figure 1 This is a schematic diagram of a die layer 100 of a semiconductor package with an integrated sidewall antenna according to various embodiments. The die layer 100 includes a die 105, which further includes a bulk silicon layer 110a and one or more back-to-office (BEOL) layers 110b. The die 105 further includes an IP core 115, interconnects 120, and through-silicon vias (TSVs) 125. It should be noted that... Figure 1 Various components of the die layer 100 are illustrated schematically, and modifications to the various components and other arrangements of the die layer 100 may be possible according to various embodiments.

[0030] In various embodiments, die layer 100 is a layer of a 3D stacked die package (e.g., a 3D die stack). Thus, die layer 100 may be a die of a stacked die package. The stacked die package itself may contain two or more die layers, such as die layer 100, which are stacked (e.g., in the vertical direction) and bonded together.

[0031] Each die 105 may be planar and further comprise six faces (e.g., outer surfaces): a bottom surface 130, a top surface 140, and four sidewalls 135a to 135d. In other embodiments, the die 105 may have different 3D shapes (e.g., polyhedral shapes and corresponding numbers of faces, or irregular shapes). Therefore, it should be understood that, for example, the shape and configuration of individual dies 105 are not limited to any particular arrangement, and in other instances, the die 105 may take the form of different shapes.

[0032] In various embodiments, die 105 may include intellectual property (IP) core 115. As used herein, IP core 115 includes (but is not limited to) discrete, reusable logic units, or circuit designs with defined input / output interfaces and behaviors. Therefore, IP core 115 can be discrete from other portions of the IC and / or semiconductor die and reused on the same and / or different die layers (e.g., die layer 100) of a 3D die stack.

[0033] In some embodiments, IP core 115 can be coupled to TSV 125 disposed along the edge of die 105 via interconnect 120. TSV 125 is a via formed into the silicon die and / or wafer, passing through bulk silicon layer 110a and / or one or more BEOL layers 110b. For example, forming TSV 125 may include (but is not limited to) drilling (e.g., laser drilling) and / or etching vias in the silicon die and / or wafer. TSV 125 may further include an internal conductive layer (e.g., a metallization layer), wherein the internal surface of TSV 125 is plated with a metal layer (e.g., copper plating or conductive material through other processes on the internal surface of the via / TSV 125). Thus, in some instances, the internal metallization layer may include a copper plating and / or copper film deposited within the via of the respective TSV 125.

[0034] In various instances, interconnect 120 includes conductive traces (e.g., metal, copper (Cu), etc.), microstrips, and / or conductive pads (e.g., copper pads). Therefore, interconnect 120 may include any structure that connects different circuit elements (in this case, elements of IP core 115 (e.g., different portions of the I / O circuitry of IP core 115)) to TSV 125. In some other instances, interconnect 120 is formed to be coplanar with die 105. Although depicted for illustrative purposes as having two TSVs 125 coupled to IP core 115 via corresponding interconnect 120, it should be understood that in other embodiments, die layer 105 may contain more than two TSVs 125 or, alternatively, fewer than two TSVs 125 (e.g., one TSV or no TSVs).

[0035] In some embodiments, interconnects 120 and TSVs 125 may be formed and / or deposited on one or more BEOL layers 110b during the BEOL manufacturing process. Therefore, one or more BEOL layers 110b refers to one or more layers and / or components formed during the BEOL phase of an IC manufacturing process. Thus, as known to those skilled in the art, the BEOL phase of a manufacturing process includes the process of forming one or more BEOL layers 110b and may refer to a stage in the IC manufacturing process where contacts, such as conductive pads, wires, vias, other interconnect structures, and dielectric structures may be formed. This contrasts with front-end operations (FEOL) processes, where active dies (e.g., transistors) and / or passive components may be formed in silicon and / or semiconductor materials (e.g., IP core 115). For example, passive components may include, for example, filters and other components (e.g., resistors, capacitors, and / or inductors).

[0036] In various instances, depending on the antenna array design, TSV 125 can be arranged and formed along sidewalls 135a to 135d at desired intervals and positions. For example, individual die layers of a 3D stacked die package (e.g., die layer 100) can be stacked at desired intervals, orientations, and / or positions to create an antenna array on the sidewalls of the 3D stacked die package. Thus, the TSV 125 of an individual die (e.g., die 105) can be arranged according to its corresponding positioning and orientation within the 3D stacked die package. According to various embodiments, one or more sidewalls 135a to 135d can be cut, diced, ground, and / or polished to expose at least a portion of the internal metallization layer of the TSV 125. For example, exposing the internal metallization of the TSV 125 can include a combination of processes, including (but not limited to) sawing, grinding, and / or chemical mechanical polishing (CMP).

[0037] In some instances, the process of exposing the internal metallization layer of TSV 125 can be performed at the individual die level (e.g., die 105) or on individual 3D stacked die packages, wherein the sidewalls of the 3D stacked die packages (and consequently the corresponding sidewalls of each of the die layers containing die layer 100) are cut, ground, and / or polished. In other instances, grinding and / or CMP can be performed on multiple 3D stacked die packages reconstructed as wafers / panels, wherein the sidewalls of interest of all 3D stacked die packages form a single process surface. In this way, the internal metallization layer of TSV 125 can be exposed at one or more sidewalls 135a to 135d. Therefore, exposing TSV 125 at the sidewalls may include at least a portion of the internal metallization layer of TSV 125 physically exposed to the external environment, or otherwise make any process physically and / or electrically accessible from the outside of die 105 and / or the 3D stacked die package via the respective sidewalls 135a to 135d.

[0038] Figure 2 This is a schematic diagram of a semiconductor package 200 before the exposure of an integrated sidewall antenna, according to various embodiments. The semiconductor package 200 includes a 3D stacked die package 205 having two or more die layers 210, said two or more die layers 210 including a first die layer 210a, a second die layer 210b, and so on, up to an nth die layer 210n. Each die layer 210a to 210n further includes a bulk silicon layer, one or more BEOL layers, and one or more adhesive layers 250 between each of the two or more die layers 210. Each die layer 210a to 210n further includes a corresponding IP core 215, interconnect 220, and TSV 225. It should be noted that the various components of the semiconductor package 200 are... Figure 2 The illustrations are schematic, and modifications to the various components and other arrangements of the semiconductor package 200 are possible according to various embodiments.

[0039] In various embodiments, semiconductor package 200 may include 3D stacked die package 205. As depicted, 3D stacked die package 205 may be formed in a cubic or cuboid shape. Thus, 3D stacked die package 205 may include six faces (e.g., outer surfaces): a bottom surface 230, a top surface 240, and four sidewalls 235a to 235d. In other instances, 3D stacked die package 205 may have different 3D shapes (e.g., polyhedral shapes and corresponding numbers of faces, or irregular shapes). Therefore, it should be understood that in various embodiments, the shape and configuration of 3D stacked die package 205 are not limited to any particular arrangement, and in other embodiments, the 3D stacked die package may have different shapes with corresponding numbers of faces and sidewalls.

[0040] The 3D stacked die package 205 includes two or more die layers 210 that have been stacked and bonded in a vertical direction. In various examples, each die layer 210a to 210n may have a planar structure, wherein each individual die layer is bonded to at least one adjacent die layer. In some examples, the two or more die layers 210 may be bonded via one or more adhesive layers 250. The one or more adhesive layers 250 may comprise (but are not limited to) epoxy resin or thermal interface materials. In still other examples, the two or more die layers 210 may be surface-bonded, for example, via oxide-oxide bonding or hybrid bonding, Cu-Cu bonding, flip-chip bonding, adhesive bonding, or other suitable bonding techniques.

[0041] In some embodiments, each individual die layer may contain an IP core 215. As previously stated relative to Figure 1As described, IP core 215 comprises discrete, reusable logic units or circuit designs with defined input / output interfaces and behaviors. Therefore, IP core 215 can be discrete from other portions of the IC and / or semiconductor die and reused on the same and / or different die layers of the 3D die stack package 205. Each IP core 215 can be further coupled via corresponding interconnects 220 to corresponding TSVs 225 arranged along the edges of the corresponding die layers 210a to 210n (and subsequently the edges of the 3D die stack 205). Interconnects 220 may include, for example, conductive traces (e.g., metal, copper (Cu), etc.), microstrips, and conductive pads (e.g., copper pads). Therefore, interconnects 220 may include any structure that connects different circuit elements (in this case, elements of IP core 215 (e.g., different portions of the I / O circuitry of IP core 215)) to TSVs 225.

[0042] As previously described, in some instances, the 3D die stack package 205 may be cuboid in shape and have a total of six rectangular (or square) faces. In a cuboid arrangement, the 3D die stack package 205 has four sidewalls 235a to 235d, a bottom surface 230, and a top surface 240. In various instances, the stacking of individual die layers 210a to 210n may be performed at the wafer level (e.g., simultaneously stacking multiple stacked 3D die packages or multiple die layers of a “cube”) and / or at the die level (e.g., stacking die layers of individually stacked 3D die packages).

[0043] In some instances, the TSV 225 is formed by exposing respective individual die layers 210a to 210n and internal metallization during grinding and / or dicing processes. In other words, the TSV 225 may be ground along plane 245 to expose the cross-section of each of two or more die layers 210a to 210n at the sidewalls (e.g., first sidewall 235a), thus exposing the internal metallization layer of each of the TSV 225. In some instances, the internal metallization layer may comprise a copper plating and / or copper film deposited within the via (e.g., the TSV 225).

[0044] In various embodiments, the TSV 225 can be arranged and spaced with desired spacing or positioning to create a desired arrangement of antenna array elements along a sidewall (e.g., first sidewall 235a). Therefore, in various embodiments, the exposed internal metallization layer can form the corresponding antenna array elements of the antenna array. As used herein, an antenna array element can refer to an individual antenna of the antenna array. In some embodiments, the TSV 225 may further include all or part of transmission lines (e.g., feed lines, etc.) coupling and / or feeding one or more antenna array elements. Therefore, in various embodiments, individual layers can be stacked with desired spacing, orientation, and / or positioning to create an antenna array of a given design, pattern, spacing, and / or orientation. The exposed internal metallization layer of the corresponding TSV 225 can thus form the corresponding antenna array element, and in some other embodiments, can form all or part of the transmission lines of the antenna array. In some instances, the antenna array element may comprise (but is not limited to) microstrip and / or patch antennas formed on sidewalls, rather than being printed and / or deposited on a corresponding die (e.g., coplanar with die layers 210a to 210n). As known to those skilled in the art, microstrip and / or patch antennas are typically planar sheets (e.g., “patches”) of conductive material (e.g., metals, such as copper) formed on a substrate. In various embodiments, the microstrip and / or patch antennas are formed on sidewalls that serve as “substrates” for the microstrip and / or patch antennas.

[0045] In various instances, the internal conductive layer (e.g., a metallization layer) of the TSV 225 may be exposed along a sidewall (e.g., a first sidewall 235a). For example, the TSV 225 may be exposed by processes such as cutting, scribing, grinding, and / or polishing, as described below relative to... Figure 3 A more detailed description will follow.

[0046] Figure 3 This is a schematic diagram of a semiconductor package 300 with integrated sidewall antennas according to various embodiments. The semiconductor package 300 includes a 3D stacked die package 305 having two or more die layers 310a to 310n. Each die layer 310a to 310n further includes a bulk silicon layer, one or more BEOL layers, and one or more adhesive layers 335 between each of the two or more die layers 310a to 310n. Each die layer 310a to 310n further includes a corresponding IP core 315, interconnect 320, TSV 325, and multiple antenna array elements 330. It should be noted that the various components of the semiconductor package 300... Figure 3 The illustrations are schematic, and modifications to the various components and other arrangements of the semiconductor package 300 are possible according to various embodiments.

[0047] As previously relative Figure 2 As described, Figure 3Depicted, for example, along the plane of each of the two or more layers of the semiconductor package 300, in each of the TSV 325 (e.g., Figure 2 The semiconductor package is formed by cutting, dicing, grinding, and / or polishing the plane 245 to expose the internal conductive layer of each of the respective TSVs 325. Thus, each of the antenna array elements 330 can form an antenna array along the sidewall of the 3D stacked die package 305.

[0048] In various instances, once the interconnects 320 and TSV 325 of two or more die layers 310a to 310n are formed, the sidewalls can be grounded to expose the TSV 325, or in some instances, the interconnects 320 can be exposed. Specifically, the interconnects 320 and TSV 325 may be formed at individual die layers extending toward the edges of the respective die layers but not yet exposed. Therefore, after stacking and bonding two or more die layers 310a to 310n, the sidewalls can be cut, ground, and / or polished. For example, exposing the interconnects 320 and / or TSV 325 may involve a combination of processes, including (but not limited to) sawing, grinding, and / or CMP. In some instances, grinding and / or CMP may utilize multiple 3D die stack packages reconstructed as wafers / panels, wherein the sidewalls of interest of all 3D die stack packages form a single process surface. Therefore, exposing interconnects 320 and / or TSVs 325 on one side may include physically exposing the internal conductive layer of the TSV 325 (or, in some instances, interconnects 320) to the external environment, or otherwise making it physically and / or electrically accessible from the external ground of the 3D stacked die package 305.

[0049] although Figure 3 Antenna array element 330 is depicted as exposed along one sidewall, but it should be understood that in other embodiments, the arrangement of the antenna array and consequently the antenna array elements (e.g., multiple antenna array elements 330) may be found on any subset or all of the sidewalls of the 3D die stack package 305. In other embodiments, the antenna array may be further formed on the sidewalls together with an antenna array formed on the top surface of the 3D stack die package 305.

[0050] Furthermore, in the depicted embodiments, each of the two or more die layers 310a to 310n contains two antenna array elements. In various instances, multiple antenna array elements 330 are arranged according to the design of the antenna array. Thus, in some instances, the antenna array elements 330, and specifically the corresponding TSVs 325, may be arranged to have specific positions and specific spacing within each layer in order to create an arrangement of antenna array elements according to the design of the antenna array.

[0051] Therefore, in various embodiments, each of the plurality of antenna array elements 330 is an internal conductive layer (e.g., a metallization layer) of a corresponding TSV 325. In various instances, the plurality of antenna array elements 330 may comprise various types of individual antennas, such as (but not limited to) microstrip antennas and / or patch antennas. In various instances, the plurality of antenna array elements 330 may together form at least a portion of an antenna array. In some instances, the internal metallization layers of two or more TSVs may be coupled together to form a corresponding antenna array element. For example, array element 340 comprises two individual TSVs, wherein the corresponding internal metallization layers are coupled together. In some instances, the internal metallization layers may be coupled, for example, via a copper plating process, wherein copper is deposited on the sidewalls to couple the individual TSVs. In other instances, conductive pads, wires, pillars, or other structures may be used for Cu-Cu bonding to the internal metallization layers of the corresponding individual TSVs to couple the individual TSVs.

[0052] In various embodiments, the antenna array is formed on the sidewalls of the 3D stacked die package 305. In some instances, the antenna array may be configured to transmit and / or receive ultra-high, sub-THz frequency signals. For example, in some embodiments, the antenna array may be configured to transmit and / or receive radio frequency (RF) signals (e.g., wireless signals) having frequencies of 300 GHz and above. In some instances, the antenna array may be configured to transmit and / or receive signals between 300 GHz and 1 THz (inclusive), or subbands of frequencies in the range of 300 GHz to 1 THz.

[0053] In other embodiments, two or more die layers 310a to 310n may contain at least a portion of a wireless transceiver circuit. In some instances, the wireless transceiver circuit may contain all or part of the receive (Rx) and / or transmit (Tx) chains of the transceiver circuit. For example, the wireless transceiver circuit may include (but is not limited to) power amplifiers and / or low-noise amplifiers (e.g., multiple antenna array elements 330) coupled to an antenna array, a mixer, a converter (e.g., a digital-to-analog converter (DAC) and / or an analog-to-digital converter (ADC)), an oscillator, or other components of an RF circuitry system. Thus, the transceiver circuitry or a portion thereof may be implemented as an RFIC. In some instances, IP core 315 of die layers 310a to 310n may contain all or part of an RFIC.

[0054] exist Figures 1 to 3In one example, multiple antenna array elements 330 are formed from exposed internal conductive layers (e.g., internal metallization layers) of corresponding TSVs 125, 225, 325. In other embodiments, the antenna array and / or antenna array elements may be formed from a redistribution layer (RDL), or more specifically, from interconnects of an RDL formed on the sidewalls of a corresponding 3D stacked die package. Figure 4 Describe an example of this type of arrangement.

[0055] Figure 4 This is a schematic diagram of a semiconductor package 400 with integrated sidewall antennas in a redistribution layer according to various embodiments. The semiconductor package 400 includes a 3D stacked die package 405, an RDL 410, and one or more antenna arrays 415 including multiple antenna array elements 420. It should be noted that the various components of the semiconductor package 400... Figure 4 The illustrations are schematic, and modifications to the various components and other arrangements of the semiconductor package 400 are possible according to various embodiments.

[0056] In various instances, with Figure 3 Similar to the 3D stacked die package 305, the 3D stacked die package 405 may contain two or more stacked die layers. Each of the two or more die layers may contain corresponding interconnects, such as copper pads, wiring, and / or traces extending toward the edge of the 3D stacked die package 405. Figure 3 Compared to a stacked die package 305, a 3D stacked die package 405 can be diced, cut, ground, and / or polished to expose corresponding interconnects of two or more die layers at the sidewalls 425 of the 3D stacked die package 405. The exposed interconnects at the sidewalls 425 can be coupled, and / or coupled via RDL 410, to form multiple antenna array elements 420 of one or more antenna arrays 415, respectively.

[0057] As used herein, an RDL refers to a metal (or other conductive material) interconnect that electrically and / or physically couples a portion of a semiconductor package to another portion (e.g., an interconnect between different components of the semiconductor package), and further provides conductive pads at other locations to allow I / O interfaces at other locations within the semiconductor package. Therefore, an RDL may include copper pads, wiring, microstrips, and traces. An RDL may further include one or more layers through which interconnects may exist. Compared to a typical RDL coplanar with the die and / or its substrate, various embodiments of the 3D stacked die package 405 provide one or more layers of RDL 410 that form (or are formed thereon) the sidewalls 425 of the 3D stacked die package 405.

[0058] In various instances, the interconnects of the RDL 410 itself may form all or part of one or more antenna arrays 415 on the sidewall 425. Specifically, in some instances, the copper pads, wiring, and / or traces of the RDL 410 may form multiple antenna array elements 420. In some instances, the interconnects of the RDL 410 may be coupled to one or more of the exposed interconnects of two or more die layers. For example, the RDL 410 may include interconnects that couple the exposed interconnects of two or more die layers to one or more other exposed interconnects of two or more die layers. In some instances, the RDL may include interconnects (e.g., pads, wiring, microstrips, or copper traces) coupled to a single exposed interconnect of two or more die layers.

[0059] In some instances, the interconnects of the RDL 410 may be bonded to exposed interconnects on two or more die layers via a copper plating process. In other instances, Cu-Cu bonding processes, such as hybrid copper bonding (HCB) and / or direct copper bonding (DCB), may be used to bond the RDL 410 to interconnects on two or more die layers. In yet another embodiment, the interconnects of the RDL may be bonded via solder bumps (e.g., microbumps, Cu bumps, etc.) formed from exposed interconnects on two or more die layers and / or by laser-assisted bonding (LAB). As used herein, bumps and / or microbumps may refer to solder microbumps. For example, a microbump may comprise a copper pillar (CuP) having a solder tip and / or solder cap. In some instances, exposed interconnects on two or more die layers may form copper pillars on which solder tips may be formed.

[0060] In various instances, RDL 410 may comprise one or more layers. Therefore, in some embodiments, one or more interconnects of one or more layers of RDL 410 are exposed at the externally facing layers of RDL 410 formed on sidewall 425. The exposed interconnects of one or more layers of RDL 410 at the externally facing layers of RDL 410 can form corresponding antenna array elements of multiple antenna array elements 420. Conventional wafer-level packaging processes can be used to form one or more layers of RDL 410. For example, in some embodiments, one or more layers of RDL 410 may be formed from multiple dielectric layers and from materials such as (but not limited to) polyimide (PI), polybenzoxazole (PBO), and / or molding compounds (e.g., epoxy resin). Therefore, using a process similar to wafer-level RDLs, a sidewall RDL can be implemented on one or more sidewalls by laterally reconstructing a 3D stacked die package 405. In other embodiments, sidewall RDLs may be formed, with or without RDLs on the top and bottom surfaces of the 3D stacked die package 405.

[0061] Although Figure 4 RDL 410 is depicted as being formed on one sidewall (e.g., sidewall 425) of the 3D stacked die package 405, but it should be understood that in other embodiments, the placement of the RDL is not limited to any particular sidewall. Furthermore, in other instances, the RDL may be formed on a subset and / or all of the sidewalls of the 3D stacked die package 405.

[0062] Figure 5 This is a schematic diagram of a semiconductor package 500 having integrated sidewall antennas on multiple sidewalls according to various embodiments. The semiconductor package 500 includes a 3D stacked die package 505 comprising a first antenna array 510 including a first plurality of antenna array elements 515a to 515n, the first antenna array 510 being formed on a first sidewall 540a and having a first radiation pattern 520. The 3D stacked die package 505 further includes a second antenna array 525 including a second plurality of antenna array elements 530a to 530n, the second antenna array 525 being formed on a second sidewall 540b and having a second radiation pattern 535. It should be noted that the various components of the semiconductor package 500 are... Figure 5 The illustrations are schematic, and modifications to the various components and other arrangements of the semiconductor package 500 are possible according to various embodiments.

[0063] In various embodiments, as previously described, either the first antenna array 510 and / or the second antenna array 525 may be formed from a TSV, wherein the respective plurality of antenna array elements 515a to 515n, 530a to 530n are formed from the exposed internal conductive layer of the respective TSV. Similarly, in some instances, either the first antenna array 510 and / or the second antenna array 525 may be formed from a respective RDL formed on the respective sidewalls 540a, 540b of the 3D stacked die package 505.

[0064] In other instances, the antenna array may be found on additional sidewalls, a subset of sidewalls, or all sidewalls of the 3D stacked die package 505. In the depicted example, antenna arrays 510 and 525 are formed on adjacent sidewalls 540a and 540b. In other instances, the antenna array may alternatively be formed on opposite sidewalls of the 3D stacked die package 505.

[0065] In some embodiments, the first antenna array 510 may have a first radiation pattern 520, and the second antenna array 525 may have a second radiation pattern 535. In some instances, antenna arrays 510 and 525 may be of the same design and include similar radiation patterns 520 and 535. In other instances, each of the first and second antenna arrays 510 and 525 has a different corresponding radiation pattern 520 and 535. In some instances, the first antenna array positioned on the first sidewall 540a may have a radiation pattern 520 that transmits a wireless signal in a first direction transverse to the 3D die stack (e.g., 3D stacked die package 505). In other words, the 3D die stack may be stacked in a vertical direction (e.g., along the z-axis). Therefore, the first antenna array 520 may be configured to transmit a wireless signal having the first radiation pattern 520 in a first direction (e.g., in a direction along the x-axis). Similarly, the second linear array 525 can be configured to transmit a wireless signal with a second radiation pattern 535 in a second direction (e.g., in the direction along the y-axis).

[0066] In the illustrated examples, for illustrative purposes, the first and second antenna arrays 510 and 525 are depicted as arrays of patch antennas and / or microstrip antennas. However, it should be understood that other antenna array designs may be utilized in other embodiments, and the antenna array design is not limited to any single design.

[0067] Figure 6 This is a schematic diagram of a semiconductor device 600 according to various embodiments, comprising a 3D stacked die package with integrated sidewall antennas bonded to an additional die. The semiconductor device 600 includes a 3D stacked die package 605, which includes an antenna array 620, a bottom die 610, and a substrate 615. It should be noted that the various components of the semiconductor device 600 are... Figure 6 The illustrations are schematic, and modifications to various components and other arrangements of the semiconductor device 600 are possible according to various embodiments.

[0068] In various embodiments, the 3D stacked die package 605 may include an antenna array 620 formed on the sidewalls of the 3D stacked die package 605, as previously described relative to... Figures 1 to 5 As described. In some instances, the 3D stacked die package 605 may be coupled to the bottom die 610 via Cu-Cu bonding (e.g., HCB and / or DCB). The bottom die 610 may contain an active die to which the 3D stacked die package 605 may be coupled.

[0069] In some instances, the bottom die 610 may contain all or part of the wireless transceiver circuitry, as previously described. Similarly, in some instances, the 3D stacked die package 605 itself may contain at least a portion of the wireless transceiver circuitry. In some instances, the wireless transceiver circuitry may contain all or part of the receive (Rx) and / or transmit (Tx) chains of the transceiver circuitry. For example, the wireless transceiver circuitry may include (but is not limited to) power amplifiers and / or low-noise amplifiers, mixers, converters (e.g., digital-to-analog converters (DACs) and / or analog-to-digital converters (ADCs)), oscillators, or other components of the RF circuitry system coupled to the antenna array 620. Thus, the transceiver circuitry or a portion thereof may be implemented as an RFIC. In some instances, the bottom die 610 is an RFIC configured to provide signals for transmission to and / or reception from the antenna array 620.

[0070] In other instances, the bottom die 610 may be coupled to a substrate 615. The substrate 615 may be configured to provide a surface for die placement. In some instances, the substrate 615 may comprise a chip carrier die, a printed circuit board (PCB), or other suitable substrate. In some instances, the substrate 615 itself may comprise two or more inner layers (e.g., wiring layers) through which component interconnects may exist. In some instances, the bottom die 610 may be coupled to the substrate 615 via a flip-chip bonding process (e.g., solder microbumps with underfill material) and / or a Cu-Cu bonding process (e.g., HCB / DCB). With the 3D stacked die package 605 bonded to the top of the bottom die 610, the functionality of the antenna array 620 can be isolated or otherwise kept unaffected by the connection between the bottom die 610 and the substrate 615.

[0071] Figure 7 This is a flowchart of a method 700 for fabricating a 3D chip stack with integrated sidewall antennas. Method 700 includes, at block 705, forming two or more die layers, each die layer containing at least one interconnect. As previously described, each die layer may contain a corresponding IP core and at least one interconnect extending outward toward the edge of the die (e.g., the die layer). The interconnect may include wires, traces, pads, and TSVs formed during the BEOL process. The interconnect may be deposited or otherwise formed as part of the die or on a die substrate. In some instances, the TSV may be formed toward the edges of the two or more die layers. For example, the TSV can be formed by forming vias in the respective die layers and plating the interior of the vias with an internal conductive layer (e.g., a metallization layer, such as copper).

[0072] At block 710, method 700 continues by stacking two or more die layers. As previously described, the two or more die layers may be stacked in a vertical direction. In some instances, the two or more die layers may be arranged with a certain spacing, orientation, and / or sequence (e.g., the design order of the two or more die layers) to produce an arrangement of antenna array elements. For example, two or more die layers may be stacked to create an antenna array with a specific design, having specific positioning, spacing, and orientation of the antenna array elements. In various instances, the stacking of two or more die layers may be performed at the wafer level (e.g., simultaneous stacking of multiple stacked 3D die packages or multiple die layers of a “cube”) and / or at the die level (e.g., stacking die layers of individually stacked 3D die packages).

[0073] At frame 715, method 700 continues by bonding a stack of two or more die layers to form a 3D stacked die package. Suitable bonding techniques may include surface bonding (e.g., oxide-oxide bonding, hybrid bonding), Cu-Cu bonding, flip-chip bonding, adhesive bonding, or other suitable bonding techniques.

[0074] Method 700 may further include, at block 720, exposing corresponding interconnects of two or more die layers at the sidewalls of the 3D stacked die package. As previously described, in some instances, the TSVs of two or more die layers may be exposed by dicing, grinding, and / or polishing processes to expose the internal conductive layers of the TSVs. In some embodiments, the TSVs may be exposed at the sidewalls by a combination of processes, including (but not limited to) sawing, grinding, and / or CMP. In some instances, grinding and / or CMP may be performed at the wafer level, where the sidewalls of interest of all 3D stacked die packages form a process surface for reconstructing the wafer / panel. In yet other embodiments, interconnects such as wires, traces, or copper pads may be exposed by similar processes. Thus, the exposure of interconnects includes processes that physically expose the interconnects to the external environment or otherwise make them physically and / or electrically accessible from the outside of the 3D stacked die package.

[0075] In some instances, method 700 continues at block 725, forming one or more layers of the RDL at the sidewalls. As previously described, the RDL may be formed at the sidewalls, thereby coupling two or more layers of the 3D stacked die package. In some instances, the RDL may comprise one or more layers formed at the sidewalls. Conventional wafer-level packaging processes can be used to form the RDL. For example, in some embodiments, one or more layers of the RDL may be formed from multiple dielectric layers and may be formed from materials such as (but not limited to) PI, PBO, and / or molding compounds. Thus, by laterally (e.g., laterally) reconfiguring the 3D stacked die package, the sidewall RDL can be implemented on all sidewalls. In other embodiments, the sidewall RDL may be formed with or without an RDL on the top and bottom surfaces of the 3D stacked die package. In some instances, interconnects (e.g., pads, wiring, traces, etc.) of the sidewall RDL may be further coupled to interconnects of two or more die layers. In some instances, the interconnects of an RDL can be coupled to interconnects of two or more die layers via solder bonding / microbumps (e.g., solder microbumps, copper pillars with solder tips, etc.), Cu-Cu bonding (including HCB and / or DCB), and / or copper plating processes.

[0076] At block 730, method 700 continues by forming one or more antenna array elements at the sidewalls. As previously described, in some instances, one or more antenna array elements may be formed from an internal conductive layer (e.g., an internal metallization layer) of the corresponding TSV already exposed at the sidewalls. In other embodiments, one or more antenna array elements may be formed via interconnects of the RDL. In some instances, one or more antenna array elements that may be formed together as an antenna array may be configured to transmit and / or receive radio frequency (RF) signals (e.g., wireless signals) having frequencies of 300 GHz and above. In some instances, the antenna array may be configured to transmit and / or receive signals between 300 GHz and 1 THz (inclusive), or subbands of frequencies in the 300 GHz to 1 THz range. The antenna array elements may include (but are not limited to) microstrip and / or patch antennas formed on the sidewalls of a 3D stacked die package.

[0077] At block 740, method 700 includes bonding a 3D stacked die package to an active die. As previously described, the 3D stacked die package may be coupled to an active die (e.g., an active die). Bonding the 3D stacked die package to the active die may involve Cu-Cu bonding processes (e.g., HCB and / or DCB). As previously described, in some instances, the active die may contain all or part of a wireless transceiver circuit, as previously described. For example, the wireless transceiver circuit may include (but is not limited to) power amplifiers and / or low-noise amplifiers, mixers, converters (e.g., digital-to-analog converters (DACs) and / or analog-to-digital converters (ADCs)), oscillators, or other components of an RF circuitry system coupled to an antenna array. In some other instances, the active die may contain an RFIC.

[0078] The techniques and processes described above with respect to various embodiments can be used to manufacture semiconductor packages 200, 300, 400, 500, semiconductor devices 600 and / or components thereof, as described herein.

[0079] While some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that many modifications are possible. For example, the methods and processes described herein can be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. Furthermore, while the various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any particular structural and / or functional architecture, but can be implemented in any suitable hardware configuration. Similarly, while some functions may be attributed to one or more system components, unless the context otherwise indicates, according to several embodiments, this functionality may be distributed across a variety of other system components.

[0080] Furthermore, although the processes of the methods and techniques described herein are presented in a specific order for ease of description, various processes may be reordered, added, and / or omitted according to various embodiments unless the context otherwise indicates. Moreover, a process described with respect to one method or process may be incorporated into other described methods or processes; similarly, system components described with respect to a particular architecture and / or system described with respect to a system may be organized in an alternative architecture and / or incorporated into other described systems. Therefore, although embodiments with or without certain features are described for ease of description and illustration of aspects of various embodiments, various components and / or features described herein with respect to a particular embodiment may be replaced, added, and / or subtracted in other described embodiments unless the context otherwise indicates. Therefore, although several embodiments have been described above, it will be understood that the invention is intended to cover all modifications and equivalents within the scope of the following claims.

Claims

1. A semiconductor device comprising: Two or more bare wafer layers bonded together, each of the two or more bare wafer layers including a top surface, a bottom surface, and one or more sidewalls. The first sidewall of one or more of the sidewalls includes a first antenna array, the first antenna array including a first plurality of antenna array elements formed in at least one of the two or more die layers, wherein the first plurality of antenna array elements are at least partially exposed at the first sidewall, and the first plurality of antenna array elements include an internal metallization layer of a through-silicon via (TSV), two or more of the internal metallization layers being coupled at the first sidewall.

2. The semiconductor device of claim 1, wherein at least a second sidewall of the one or more sidewalls comprises a second antenna array, the second antenna array comprising a second plurality of antenna array elements formed in at least one of the two or more die layers, wherein the second plurality of antenna array elements are at least partially exposed at the second sidewall.

3. The semiconductor device of claim 1, wherein at least one of the two or more die layers comprises a plurality of through-silicon vias (TSVs) forming the first plurality of antenna array elements, wherein the internal metallization layer of each of the plurality of TSVs is at least partially exposed at the first sidewall.

4. The semiconductor device of claim 3, wherein each of the plurality of TSVs forms a corresponding antenna array element in the plurality of antenna array elements.

5. The semiconductor device of claim 1, wherein the first plurality of antenna array elements comprises one or more patch antennas.

6. The semiconductor device of claim 1, wherein the first antenna array is configured to transmit wireless signals having a frequency of 300 GHz or higher.

7. The semiconductor device of claim 1, further comprising a redistribution layer RDL formed on the first sidewall, the RDL including a plurality of interconnects forming the first plurality of antenna array elements, wherein the plurality of interconnects comprises one or more of wires, traces or pads.

8. The semiconductor device of claim 1, wherein at least one of the two or more die layers comprises at least a portion of a wireless transceiver circuit, wherein the wireless transceiver circuit comprises an amplifier coupled to the first antenna array.

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