High-side NMOS drive circuit

Abstract

This invention relates to a high-side NMOS driving circuit, including a turn-on circuit. The voltage terminal of the turn-on circuit is connected to a positive voltage. The input terminal of the turn-on circuit is a control signal input terminal. The output terminal of the turn-on circuit is connected to the input terminal of a bootstrap circuit. The output terminal of the bootstrap circuit is a control signal output terminal used to output a control signal for controlling the NMOS transistor. The bootstrap circuit includes a third transistor, a second diode, and a third diode. One output terminal of the turn-on circuit is connected to the control signal output terminal via the second and third diodes, and the other output terminal is grounded via a voltage regulating circuit through the third transistor of the bootstrap circuit. The third transistor is connected to the control signal input terminal. The voltage regulating circuit includes a fourth resistor and a fifth resistor connected in series. A third capacitor is placed between the connection point of the fourth and fifth resistors and the connection point of the second and third diodes. This invention solves the problems of complex structure and high cost of high-side NMOS driving circuits.

Description

Technical Field

[0001] This invention relates to the field of driving circuits, and more specifically to a high-side NMOS driving circuit. Background Technology

[0002] With the development of the automotive industry, the power control requirements of various control boards within vehicles are increasing, and the control requirements of motor controller drive circuits that provide high-side or low-side power to these control boards are also becoming more stringent. Low-side power control of each control board is mainly achieved by controlling the on / off state of MOSFETs, while high-side power is typically implemented using high-side driver chips or PMOS transistors. Using high-side driver chips to provide high-side power is limited by the chip's performance, often resulting in a smaller output drive current. Using PMOS transistors is limited by their manufacturing process characteristics, resulting in higher on-resistance and higher heat generation. Furthermore, low-resistance PMOS transistors are often expensive, contradicting the goal of cost reduction. Therefore, using NMOS transistors in drive circuits to achieve high-side on / off control has been a long-term research focus for manufacturers.

[0003] Patent application CN116742920A discloses an NMOS power switch driving circuit and its control method. By setting up a drive enhancement module and a power selection module between the gate and signal input terminal of the NMOS transistor, the gate voltage of the NMOS transistor is increased, allowing the NMOS to quickly reach the saturation region and achieve on / off control. This solution has a complex circuit structure and functional implementation process, uses a large number of components, and is therefore too costly. Patent application CN216252682U discloses a driving circuit for using an NMOS transistor as a high-side switch. Although it uses fewer components and can reduce costs, this driving circuit can only allow the NMOS transistor to enter the linear region from the cutoff region. The NMOS transistor in the linear region has high on-resistance, resulting in insufficient circuit reliability, severe heat generation, and unsatisfactory operating conditions. Prolonged overheating can affect the device's lifespan. Furthermore, the gate voltage of the NMOS transistor is fixed and cannot be changed, resulting in insufficient flexibility and low compatibility. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by providing a high-side NMOS driving circuit that solves the problems of complex circuit structure, high cost, and low reliability in high-side NMOS driving circuit applications.

[0005] The objective of this invention is achieved through the following scheme: a high-side NMOS driving circuit, comprising a turn-on circuit, wherein the voltage terminal of the turn-on circuit is connected to a positive voltage, the input terminal of the turn-on circuit is a control signal input terminal, the output terminal of the turn-on circuit is connected to the input terminal of a bootstrap circuit, and the output terminal of the bootstrap circuit is a control signal output terminal for outputting a control signal for controlling the NMOS transistor. The bootstrap circuit includes a third transistor, a second diode, and a third diode. One output terminal of the turn-on circuit is connected to the control signal output terminal via the second and third diodes, and the other output terminal is grounded via a voltage regulating circuit through the third transistor of the bootstrap circuit. The third transistor is connected to the control signal input terminal. The voltage regulating circuit includes a fourth resistor and a fifth resistor connected in series, and a third capacitor is disposed between the connection point of the fourth and fifth resistors and the connection point of the second and third diodes.

[0006] Preferably, the drain of the NMOS transistor is connected to a positive voltage, the source of the NMOS transistor is used to connect to the load, the gate of the NMOS transistor is grounded, and the gate of the NMOS transistor is connected to the control signal output terminal; or, the drain of the NMOS transistor (M0) is used to connect to the load, the source of the NMOS transistor is connected to a positive voltage, the gate of the NMOS transistor is grounded, and the gate of the NMOS transistor is connected to the control signal output terminal.

[0007] More preferably, the gate of the NMOS transistor is grounded through a second capacitor.

[0008] Preferably, the turn-on circuit includes a first transistor and a second transistor. The base of the first transistor is connected to the control signal input terminal through a first resistor and a first diode. The emitter of the first transistor is grounded. The collector of the first transistor is connected to a positive voltage through a second resistor. The base of the second transistor is connected to the collector of the first transistor. The emitter of the second transistor is connected to a positive voltage. The collector of the second transistor is the output terminal of the turn-on circuit and is connected to a bootstrap circuit and a voltage regulation circuit, respectively.

[0009] More preferably, the switching circuit further includes a first capacitor, and the connection point between the first resistor and the first diode is grounded through the first capacitor.

[0010] More preferably, the first transistor is a type-3 transistor, and the second transistor is a type-4 transistor.

[0011] Preferably, the third transistor is a type III transistor.

[0012] Preferably, the base of the third transistor is connected to the control signal input terminal through a third resistor, the emitter is grounded, and the collector is connected to the voltage regulation circuit.

[0013] Preferably, the output voltage of the bootstrap circuit has the following relationship with the fourth resistor, the fifth resistor, the positive voltage, the second diode, and the third diode:

[0014]

[0015] In the formula, V out V is the output voltage of the bootstrap circuit. dd The voltage value of a positive voltage, V D2 V is the voltage drop across the second diode. D3 R3 is the voltage drop across the third diode, R4 is the resistance of the fourth resistor, and R5 is the resistance of the fifth resistor.

[0016] Using the above scheme, a high-side NMOS driving circuit includes a turn-on circuit. The voltage terminal of the turn-on circuit is connected to a positive voltage. The input terminal of the turn-on circuit is a control signal input terminal. The output terminal of the turn-on circuit is connected to the input terminal of a bootstrap circuit. The output terminal of the bootstrap circuit is a control signal output terminal used to output a control signal for controlling the NMOS transistor. The bootstrap circuit includes a third transistor, a second diode, and a third diode. One output terminal of the turn-on circuit is connected to the control signal output terminal via the second and third diodes. The other output terminal is grounded via a voltage regulating circuit through the third transistor of the bootstrap circuit. The third transistor is connected to the control signal input terminal. The voltage regulating circuit includes a fourth resistor and a fifth resistor connected in series. A third capacitor is disposed between the connection point of the fourth and fifth resistors and the connection point of the second and third diodes. A bootstrap circuit is used to power the control signal output, ensuring a stable voltage for the NMOS transistor and preventing interference signals from causing it to turn on falsely. The bootstrap circuit boosts the output voltage to the target voltage for the NMOS transistor, providing sufficient voltage to quickly enter saturation. This avoids high on-resistance and excessive heat, which could negatively impact operation. A second capacitor acts as an energy storage capacitor, providing voltage to the NMOS transistor and preventing it from turning off due to low voltage when the control signal is low, thus improving circuit reliability. A voltage regulator circuit adjusts the output voltage of the bootstrap circuit, allowing for a more flexible voltage output range.

[0017] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the circuit structure of the present invention;

[0019] Figure 2 This is a schematic diagram of the current flow when the control signal of the present invention is continuously low.

[0020] Figure 3 This is a schematic diagram of the current flow when the control signal of the present invention is continuously high.

[0021] Figure 4 This is a schematic diagram of the current flow when the control signal of the present invention is briefly low.

[0022] Figure 5 This is a schematic diagram illustrating the relationship between the first capacitor and the control signal in this invention;

[0023] Figure 6 This is a schematic diagram showing the relationship between the second capacitor, the third capacitor, and the control signal in this invention. Detailed Implementation

[0024] See Figures 1 to 6A high-side NMOS driving circuit includes a turn-on circuit. The voltage terminal of the turn-on circuit is connected to a positive voltage Vdd. The input terminal of the turn-on circuit is a control signal input terminal Vin. The output terminal of the turn-on circuit is connected to the input terminal of a bootstrap circuit. The output terminal of the bootstrap circuit is a control signal output terminal Vout, which is connected to the gate of NMOS transistor M0 to output a control signal for controlling NMOS transistor M0. The turn-on circuit includes a first transistor Q1 and a second transistor Q2. The base of the first transistor Q1 is connected to the control signal input terminal Vin through a first resistor R1 and a first diode D1. The emitter of the first transistor Q1 is grounded. The collector of the first transistor Q1 is connected to the positive voltage Vdd through a second resistor R2. The base of the second transistor Q2 is connected to the collector of the first transistor Q1. The emitter of the second transistor Q2 is connected to the positive voltage Vdd. The collector of the second transistor Q2 is the output terminal of the turn-on circuit, which is connected to both the bootstrap circuit and the voltage regulation circuit. The turn-on circuit also includes a first capacitor C1. The connection point between the first resistor R1 and the first diode D1 is grounded through the first capacitor C1. The first capacitor C1 stores energy when the control signal is high, and when the control signal is low, it supplies power to the first transistor Q1 and the second transistor Q2, ensuring that the first transistor Q1 and the second transistor Q2 remain continuously conducting when the control signal is low, so that the gate of the NMOS transistor M0 has sufficient turn-on voltage. The bootstrap circuit includes a third transistor Q3, a second diode D2, and a third diode D3. One output of the turn-on circuit is connected to the control signal output Vout through the second diode D2 and the third diode D3; the other output is grounded through a voltage regulator circuit via the third transistor Q3 of the bootstrap circuit. Specifically, the base of the third transistor Q3 is connected to the control signal input Vin through the third resistor R5, the emitter is grounded, and the collector is connected to the voltage regulator circuit. The voltage regulation circuit includes a fourth resistor R3 and a fifth resistor R4 connected in series. One end of the fifth resistor R4 is connected to the collector of the third transistor Q3, and the other end is connected to the output terminal of the turn-on circuit through the fourth resistor R3. A third capacitor C2 is provided between the connection point of the fourth resistor R3 and the fifth resistor R4 and the connection point of the second diode D2 and the third diode D3.

[0025] The drain of the NMOS transistor M0 is connected to a positive voltage Vdd, the source of the NMOS transistor M0 is connected to the load, and the gate of the NMOS transistor M0 is grounded and connected to the control signal output terminal Vout to control the power supply status of the load; or, the drain of the NMOS transistor M0 is connected to the load, the source of the NMOS transistor M0 is connected to a positive voltage Vdd, the gate of the NMOS transistor M0 is grounded and connected to the control signal output terminal Vout, which is used for power input protection in the circuit board to prevent damage to the subsequent circuit (load) due to reverse connection of the positive and negative terminals of the power supply.

[0026] The gate of the NMOS transistor M0 is grounded through the second capacitor C3, which acts as an energy storage capacitor to make the gate voltage of the NMOS transistor M0 more stable.

[0027] The first transistor Q1 is an NPN transistor, the second transistor Q2 is a PNP transistor, and the third transistor Q3 is an NPN transistor.

[0028] In the aforementioned turn-on circuit, when there is no signal input or the control signal is continuously low, the first transistor Q1 and the second transistor Q2 are in the off state. The gate of the NMOS transistor M0 (i.e., the control signal output terminal Vout) has insufficient voltage or no voltage, the drive circuit has no output, and the NMOS transistor remains in the off state. This turn-on circuit ensures that the NMOS transistor is in a stable operating state and prevents interference signals from causing the NMOS transistor to be falsely turned on. When a control signal is input, the first transistor Q1 and the second transistor Q2 in the turn-on circuit turn on according to the high or low state of the control signal, promptly supplying power to the bootstrap circuit. The bootstrap circuit boosts the voltage to the target voltage through the capacitor bootstrap, enabling the gate of the NMOS transistor M0 to quickly obtain the target voltage, thereby achieving the purpose of controlling the NMOS transistor M0. The voltage regulation circuit adjusts the voltage of the gate of the NMOS transistor M0 by adjusting the ratio of the parameters of the fourth resistor R3 and the fifth resistor R4, allowing the circuit to have a more flexible output range.

[0029] The current flow under various control signals of this drive circuit is described below:

[0030] like Figure 2 As shown, this is a schematic diagram of the current direction when the control signal is continuously low. The first transistor Q1 and the second transistor Q2 in the power-on circuit are in the off state, the gate voltage of the NMOS transistor M0 is 0V, the NMOS transistor is in the off state, and the current cannot pass through the first transistor Q1, the second transistor Q2, or the NMOS transistor.

[0031] like Figure 3 As shown, this is a schematic diagram of the current direction when the control signal is continuously high. The first diode D1 is turned on, the first capacitor C1 is charged, and the first transistor Q1 and the second transistor Q2 are in saturation. The current enters the bootstrap circuit from the output of the turn-on circuit. The second transistor D2 and the third transistor D3 are turned on, and the third transistor Q3 is in saturation. The current passes through the second transistor D2 and the third transistor D3 to charge the third capacitor C2 and the second capacitor C3, and reaches the gate of the NMOS transistor M0. The gate of the NMOS transistor M0 receives the target voltage.

[0032] like Figure 4The diagram illustrates the current direction during a brief low-level control signal. First diode D1 is off, first capacitor C1 discharges, first transistor Q1 and second transistor Q2 are in saturation, and third transistor Q3 is off. Second diode D2 is also off. The current from the output of the turn-on circuit flows through fourth resistor R3 to third capacitor C2, raising its voltage. This turns on third transistor D3, allowing the gate of NMOS transistor M0 to receive the target voltage and charge second capacitor C3. When the voltage in third capacitor C2 is depleted, second capacitor C3 discharges, continuing to provide voltage to the gate of NMOS transistor M0. During a brief low-level control signal, first capacitor C1 and second capacitor C3 act as energy storage capacitors, providing voltage to the turn-on circuit and the gate of NMOS transistor M0, respectively, ensuring that the NMOS transistor remains on during the brief low-level condition.

[0033] In this driving circuit, the voltage at the output of the bootstrap circuit (i.e., the gate voltage of the NMOS transistor M0) is controlled by a voltage regulation circuit. The output voltage has the following relationship with the fourth resistor R3, the fifth resistor R4, the positive voltage Vdd, the second diode D2, and the third diode D3:

[0034]

[0035] In the formula, V out V is the output voltage of the bootstrap circuit. dd The voltage value of the positive voltage Vdd, V D2 V is the voltage drop across the second diode D2. D3 R3 is the voltage drop across the third diode D3, R4 is the resistance of the fourth resistor R3, and R4 is the resistance of the fifth resistor R4.

[0036] The turn-on delay of the NMOS transistor is determined by the frequency of the control signal, the third capacitor C2, the second capacitor C3, the fourth resistor R3, and the fifth resistor R4. Among these, the third capacitor C2 is the bootstrap capacitor, and the second capacitor C3 is the energy storage capacitor. The capacitance ratio of the bootstrap capacitor to the energy storage capacitor determines the rise rate of the output voltage of the bootstrap circuit. The resistance ratio of the fourth resistor R3 and the fifth resistor R4 determines the voltage boosted by the bootstrap capacitor each time, thus affecting the final output voltage value of the bootstrap circuit.

[0037] The control signal at the control signal input terminal is a square wave signal. The frequency of this signal satisfies the following relationship with the first capacitor C1 and the first resistor R1 in the switching circuit:

[0038]

[0039] In the formula, f is the frequency of the control signal, C1 is the capacitance of the first capacitor C1, and R1 is the resistance of the first resistor R1. The frequency of the control signal satisfies the above relationship, ensuring that the output of the turn-on circuit provides sufficient voltage to the bootstrap circuit, thus ensuring stable control of the NMOS transistor.

[0040] Example 1

[0041] To ensure that the voltage at the output of the bootstrap circuit reaches the target gate voltage of the NMOS transistor, in this embodiment, the first resistor R1 has a resistance of 10kΩ, the second resistor R2 has a resistance of 10kΩ, the third resistor R5 has a resistance of 1kΩ, the fourth resistor R3 has a resistance of 1kΩ, and the fifth resistor R4 has a resistance of 100Ω; the first capacitor C1 has a capacitance of 1uF, the third capacitor C2 has a capacitance of 100nF, and the second capacitor C3 has a capacitance of 10nF; the first transistor Q1 is an NPN 2N3904, the second transistor Q2 is a PNP 2N3904, and the third transistor Q3 is an NPN 2N3904; the first diode D1, the second diode D2, and the third diode D3 are all 1N4148 (voltage drop of 0.6V), and the positive voltage Vdd is 12V.

[0042] According to the voltage V at the output terminal of the bootstrap circuit out The calculation formula,

[0043] V out =12V+10.9V-0.6V-0.6V≈21.7V.

[0044] Example 2

[0045] To ensure that the voltage at the output of the bootstrap circuit reaches the target gate voltage of the NMOS transistor, in this embodiment, the resistance of the first resistor R1 is 10kΩ, the resistance of the second resistor R2 is 10kΩ, the resistance of the third resistor R5 is 1kΩ, the resistance of the fourth resistor R3 is 1kΩ, and the resistance of the fifth resistor R4 is 1kΩ; the capacitance of the first capacitor C1 is 1uF, the capacitance of the third capacitor C2 is 100nF, and the capacitance of the second capacitor C3 is 10nF; the first transistor Q1 is an NPN 2N3904, the second transistor Q2 is a PNP 2N3904, and the third transistor Q3 is an NPN 2N3904; the first diode D1, the second diode D2, and the third diode D3 are all 1N4148 (voltage drop of 0.6V), and the positive voltage Vdd is 12V.

[0046] According to the voltage V at the output terminal of the bootstrap circuit out The calculation formula,

[0047] V out =12V+6V-0.6V-0.6V=16.8V.

[0048] According to Examples 1 and 2, by changing the resistance values ​​of the fourth resistor R3 and the fifth resistor R4, different bootstrap circuit output voltages can be obtained. By adjusting the fourth resistor R3 and the fifth resistor R4 according to the selected NMOS transistor model, the bootstrap circuit output voltage can be adjusted, making the circuit more flexible.

[0049] This invention uses a bootstrap circuit to increase the voltage at the output of the power-on circuit, thereby stabilizing the gate voltage of the NMOS transistor M0 at the target value. The circuit has high reliability, a simple structure, and uses fewer components, which helps reduce costs. At the same time, the voltage at the output of the bootstrap circuit is adjusted by a voltage regulating circuit, making the output of the bootstrap circuit more flexible and compatible. Energy storage capacitors are set in both the power-on circuit and the bootstrap circuit to further improve the reliability of the circuit.

[0050] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications made to the present invention by those skilled in the art without departing from the spirit of the present invention shall fall within the protection scope of the present invention.

Claims

1. A high-side NMOS driving circuit, comprising a turn-on circuit, wherein the voltage terminal of the turn-on circuit is connected to a positive voltage (Vdd), and the input terminal of the turn-on circuit is a control signal input terminal (Vin), characterized in that: The output terminal of the power-on circuit is connected to the input terminal of a bootstrap circuit. The output terminal of the bootstrap circuit is a control signal output terminal (Vout) used to output a control signal for controlling the NMOS transistor (M0). The bootstrap circuit includes a third transistor (Q3), a second diode (D2), and a third diode (D3). One output terminal of the power-on circuit is connected to the control signal output terminal (Vout) via the second diode (D2) and the third diode (D3). The other output terminal is connected to ground via a voltage regulating circuit through the third transistor (Q3) of the bootstrap circuit. The third transistor (Q3) is connected to the control signal input terminal (Vin). The voltage regulating circuit includes a fourth resistor (R3) and a fifth resistor (R4) connected in series. A third capacitor (C2) is provided between the connection point of the fourth resistor (R3) and the fifth resistor (R4) and the connection point of the second diode (D2) and the third diode (D3). The power-on circuit includes a first transistor (Q1) and a second transistor (Q2). The base of the first transistor (Q1) is connected to the control signal input terminal (Vin) through a first resistor (R1) and a first diode (D1). The emitter of the first transistor (Q1) is grounded. The collector of the first transistor (Q1) is connected to a positive voltage (Vdd) through a second resistor (R2). The base of the second transistor (Q2) is connected to the collector of the first transistor (Q1). The emitter of the second transistor (Q2) is connected to a positive voltage (Vdd). The collector of the second transistor (Q2) is the output terminal of the power-on circuit and is connected to a bootstrap circuit and a voltage regulation circuit, respectively. The switching circuit also includes a first capacitor (C1), and the connection point between the first resistor (R1) and the first diode (D1) is grounded through the first capacitor (C1).

2. The high-side NMOS driving circuit according to claim 1, characterized in that: The drain of the NMOS transistor (M0) is connected to a positive voltage (Vdd), the source of the NMOS transistor (M0) is used to connect to the load, the gate of the NMOS transistor (M0) is grounded, and the gate of the NMOS transistor (M0) is connected to the control signal output terminal (Vout). Alternatively, the drain of the NMOS transistor (M0) is used to connect to the load, the source of the NMOS transistor (M0) is connected to a positive voltage (Vdd), the gate of the NMOS transistor (M0) is grounded, and the gate of the NMOS transistor (M0) is connected to the control signal output terminal (Vout).

3. The high-side NMOS driving circuit according to claim 2, characterized in that: The gate of the NMOS transistor (M0) is grounded through a second capacitor (C3).

4. The high-side NMOS driving circuit according to claim 1, characterized in that: The first transistor (Q1) is an NPN transistor, and the second transistor (Q2) is a PNP transistor.

5. The high-side NMOS driving circuit according to claim 1, characterized in that: The third transistor (Q3) is an NPN transistor.

6. The high-side NMOS driving circuit according to claim 1, characterized in that: The base of the third transistor (Q3) is connected to the control signal input terminal (Vin) through the third resistor (R5), the emitter is grounded, and the collector is connected to the voltage regulation circuit.

7. The high-side NMOS driving circuit according to claim 1, characterized in that: The output voltage of the bootstrap circuit has the following relationship with the fourth resistor (R3), the fifth resistor (R4), the positive voltage (Vdd), the second diode (D2), and the third diode (D3): ， In the formula, This is the output voltage of the bootstrap circuit. The voltage value is the positive voltage (Vdd). The voltage drop across the second diode (D2) R3 is the voltage drop of the third diode (D3), R4 is the resistance of the fourth resistor (R3), and R4 is the resistance of the fifth resistor (R4).

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