A low noise amplifier integrating a switch and a non-inverting filter function filter

Abstract

The application aims to provide a low-noise amplifier integrated with a switch and a non-reflection filter, belonging to the technical field of low-noise amplifiers. The amplifier realizes high-density integration of a two-stage broadband low-noise amplifier, a non-reflection filter and a switch by reasonably designing a circuit structure, and meanwhile, a feedback network and a notch network are introduced to improve the performance of the low-noise amplifier. The amplifier has the advantages of high integration, small size, excellent performance and convenient control.

Description

Technical Field

[0001] This invention belongs to the field of low-noise amplifier technology, specifically relating to a low-noise amplifier that integrates a switch and a filter without reverse filtering function. Background Technology

[0002] The low-noise amplifier (LNO) is one of the most important active components in any radar receiver. Located as the first stage after the antenna and array switches, its noise figure is a major contributor to the overall receiver noise figure. Modern radar receivers demand wide bandwidth, low noise, and low power consumption from their LNO amplifiers. With the development of radar receiver technology, more and more radar receivers require multi-functional integration of LNO amplifiers. Multi-functional integration effectively reduces the overall size and power consumption of the receiver, while significantly simplifying the number of components. In terms of performance, multi-functional integration effectively reduces problems caused by component soldering, such as impedance mismatch, deteriorated VSWR, and low isolation.

[0003] However, current multi-functional integration of low-noise amplifiers mainly revolves around two aspects: first, integrating the low-noise amplifier with a filter; and second, integrating the low-noise amplifier with a switch. However, there are no reports of low-noise amplifiers that simultaneously integrate filters and switches.

[0004] Furthermore, the circuit following the low-noise amplifier and filter is a mixer. The mixer can only process signals of a specific frequency; any unprocessed signals will be reflected back to the antenna through the microwave link. If the isolation of the switches is insufficient, parasitic harmonics will be generated throughout the receiver link, thus degrading the receiver's sensitivity and dynamic range. One feasible solution is to replace the filter before the mixer with a non-reflective filter, but this presents problems such as the large size of non-reflective filters.

[0005] Therefore, how to design a low-noise amplifier that can integrate switching and non-reverse filtering functions has become a research focus. Summary of the Invention

[0006] To address the problems of current radar receivers, such as the inability to integrate multiple components between the antenna and mixer and the lack of reflection-free filtering functionality, the present invention aims to provide a low-noise amplifier that integrates a switch and a reflection-free filter. This amplifier achieves high-density integration of a two-stage broadband low-noise amplifier, a reflection-free filter, and a switch through a rationally designed circuit structure. Furthermore, the introduction of feedback and notch filtering networks improves the performance of the low-noise amplifier. It offers advantages such as high integration, small size, superior performance, and convenient control.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows:

[0008] A low-noise amplifier integrating a switch and a non-reflective filter includes an input matching unit, a notch network, a common-source cascode amplifier, a switch control network, a feedback network, an interstage matching unit, a parallel peaked load amplifier, an output matching unit, and a non-reflective filter network.

[0009] The input matching unit consists of three T-shaped microstrip lines. One end of the first microstrip line TL1 is connected to the input port of the low-noise amplifier. The other end of the first microstrip line TL1 is connected to one end of the second microstrip line TL2 and one end of the third microstrip line TL3. The other end of the second microstrip line TL2 is connected to the gate of the first transistor FET1 in the common-source common-gate amplifier and one end of the twelfth inductor L12 in the switch control network.

[0010] The notch filter network consists of a first inductor L1, a first capacitor C1, and a second capacitor C2; one end of the first inductor L1 is grounded, and the other end is connected to one end of the first capacitor C1 and one end of the second capacitor C2; the other end of the first capacitor C1 is connected to the drain of the first transistor FET1 in the cascode amplifier and the source of the second transistor FET2 in the cascode amplifier; the other end of the second capacitor C2 is grounded.

[0011] The common-source common-gate amplifier consists of a first transistor FET1, a second transistor FET2, a third capacitor C3, a fourth capacitor C4, and a first resistor R1. The source of the first transistor FET1 is grounded. The drain of the second transistor FET2 is connected to one end of the fourth microstrip line and one end of the sixth microstrip line in the interstage matching unit. The gate of the second transistor FET2 is connected to one end of the fourth capacitor C4 and one end of the first resistor R1. The other end of the fourth capacitor C4 is grounded. The other end of the first resistor R1 is connected to one end of the third capacitor C3 and the DC power supply VCC.

[0012] The switching control network consists of a twelfth inductor L12, a thirteenth inductor L13, a ninth microstrip line TL9, a tenth microstrip line TL10, an eleventh microstrip line TL11, a twelfth microstrip line TL12, an eleventh capacitor C11, a fourth transistor FET4, and a fifth transistor FET5. The other end of the twelfth inductor L12 is connected to one end of the ninth microstrip line TL9, and the other end of the ninth microstrip line TL9 is connected to one end of the eleventh microstrip line TL11 and the drain of the fourth transistor FET4. The gate of the fourth transistor FET4 is connected to the control voltage, and its source is grounded. The eleventh microstrip line... The other end of TL11 is connected to one end of the eleventh capacitor C11, one end of the twelfth capacitor C12, one end of the twelfth microstrip line TL12, and the control voltage; the other end of the twelfth microstrip line TL12 is connected to one end of the tenth microstrip line TL10 and the drain of the fifth transistor FET5; the source of the fifth transistor FET5 is grounded, and its gate is connected to the control voltage; the other end of the tenth microstrip line TL10 is connected to one end of the thirteenth inductor L13; the other end of the thirteenth inductor L13 is connected to the other end of the fifth microstrip line TL5 in the interstage matching unit and the gate of the third transistor FET3 in the parallel peaked load amplifier;

[0013] The feedback network consists of a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth microstrip line TL8, a first coupling line CTL1, and a fourth inductor L4. One end of the fifth capacitor C5 is grounded, and the other end is connected to the coupling end of the first coupling line CTL1. The input end of the first coupling line CTL1 is connected to one end of the eighth microstrip line TL8, the isolation end is connected to one end of the seventh capacitor C7, and the output end is connected to the drain of the second transistor FET2. The other end of the eighth microstrip line TL8 is connected to one end of the sixth capacitor C6, and the other end of the sixth capacitor C6 is connected to the DC power supply VCC and one end of the fourth inductor L4. The other end of the seventh capacitor C7 is grounded.

[0014] The interstage matching unit consists of a fourth microstrip line TL4, a fifth microstrip line TL5, a sixth microstrip line TL6, a seventh microstrip line TL7, an eighth capacitor C8, a ninth capacitor C9, and a tenth capacitor C10. The other end of the fourth microstrip line TL4 is connected to one end of the eighth capacitor C8, the other end of the eighth capacitor C8 is connected to one end of the fifth microstrip line TL5, the other end of the fifth microstrip line TL5 is connected to one end of the seventh microstrip line TL7, the other end of the thirteenth inductor L13 in the switching control network, and the gate of the third transistor FET3 in the parallel peaked load amplifier. The other end of the seventh microstrip line TL7 is connected to one end of the tenth capacitor C10, and the other end of the tenth capacitor C10 is grounded. The other end of the sixth microstrip line TL6 is connected to one end of the ninth capacitor C9, and the other end of the ninth capacitor C9 is grounded.

[0015] The parallel peaked load amplifier consists of a third transistor FET3 and a fourth inductor L4; the drain of the third transistor FET3 is connected to the other end of the fourth inductor L4 and one end of the thirteenth microstrip line TL13 in the output matching unit, and the source of the third transistor FET3 is grounded; the parallel peaked load amplifier and the feedback network share the fourth inductor L4.

[0016] The output matching unit consists of three T-shaped microstrip lines. One end of the thirteenth microstrip line TL13 is connected to the other end of the fourth inductor L4. The other end of the thirteenth microstrip line TL13 is connected to one end of the fourteenth microstrip line TL14 and one end of the fifteenth microstrip line TL15. The other end of the fourteenth microstrip line TL14 is connected to the first port of the second coupling line CTL2 in the anti-reverse filter network. The other end of the fifteenth microstrip line TL15 is open.

[0017] The reflectionless filter network consists of a second coupling line CTL2, a third coupling line CTL3, a thirteenth capacitor C13, a fourteenth capacitor C14, a second resistor R2, a third resistor R3, a sixteenth microstrip line TL16, a seventeenth microstrip line TL17, and an eighteenth microstrip line TL18. The second port of the second coupling line CTL2 is connected to one end of the second resistor R2 and one end of the thirteenth capacitor C13; the third port of the second coupling line CTL2 is connected to the first port of the third coupling line CTL3; the other end of the second resistor R2 is connected to one end of the sixteenth microstrip line TL16 and one end of the eighteenth microstrip line TL18; the third coupling line CTL2... The second port of line 3 is connected to the output port of the low-noise amplifier. The third port of the third coupling line CTL3 is connected to one end of the fourteenth capacitor C14 and one end of the third resistor R3. The fourth ports of the second coupling line CTL2 and the third coupling line CTL3 are both open. The other end of the third resistor R3 is connected to the other end of the eighteenth microstrip line TL18 and one end of the seventeenth microstrip line TL17. The other ends of the thirteenth capacitor C13, the sixteenth microstrip line TL16, the seventeenth microstrip line TL17, and the fourteenth capacitor C14 are all grounded.

[0018] Furthermore, the low-noise amplifier also includes an input DC blocking capacitor C1 and an output DC blocking capacitor C16. The input DC blocking capacitor is disposed between the input matching unit and the input terminal of the low-noise amplifier, and the output DC blocking capacitor is disposed between the output matching unit and the output terminal of the low-noise amplifier to achieve DC isolation. The capacitance value of the DC blocking capacitor is preferably 30fF.

[0019] Furthermore, broadband matching is achieved by adjusting the characteristic impedance and electrical length of the microstrip line in the input matching unit, and the bandwidth characteristics of the low-noise amplifier are enhanced by increasing the number of microstrip lines between the input capacitor and the first microstrip line TL1.

[0020] Furthermore, by adjusting the capacitance value of the second capacitor C2 in the notch filter network to adjust the resonant frequency, the resonant frequency of the notch filter network is adjusted to be outside the upper band of the low-noise amplifier, which can improve the out-of-band anti-interference capability of the low-noise amplifier and adjust the in-band ripple characteristics of the low-noise amplifier; the inductance value of the first inductor L1 and the first capacitor C1, after forming a resonant network, affect the S at the center frequency point. 21 The suppression depth also varies; the smaller the inductance value, the deeper the suppression depth.

[0021] Furthermore, the input and output terminals of the first coupling line CTL1 are cross-structured and can be converted to each other, that is, after one side of the microstrip line is used as the input port, the other side of the microstrip line is used as the output port.

[0022] Furthermore, broadband matching is achieved by adjusting the characteristic impedance and electrical length of the microstrip lines in the output matching unit, and the bandwidth characteristics of the low-noise amplifier are enhanced by increasing the number of microstrip lines between the second coupling line CTL2 and the fourteenth microstrip line TL14.

[0023] Furthermore, the switch control network has a left-right symmetrical structure, and the anti-filter network has a symmetrical bridged structure.

[0024] Furthermore, the switch control network enables the simultaneous turning on or off of the first transistor FET1 and the third transistor FET3 by regulating the control voltage.

[0025] Furthermore, the feedback network is in the form of positive feedback, and its gain is -2C. k T k , where C k T represents the coupling coefficient of the feedback network. k The coupling coefficient k of the first coupling line is smaller, resulting in a smaller gain for the feedback network, but also a larger gain fluctuation.

[0026] Furthermore, by adjusting the parameter values ​​of the thirteenth capacitor C13, the fourteenth capacitor C14, the sixteenth microstrip line TL16, the seventeenth microstrip line TL17, the second resistor R2, and the third resistor R3 in the anti-reverse filter network, S is made... 21 The return loss parameter in the band is 7-10dB.

[0027] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0028] 1. This invention integrates a switching function into a low-noise amplifier, reducing the complex impedance transformation caused by separate design of the switch and low-noise amplifier in traditional circuit structures, and reducing the system size and complexity; at the same time, it can also avoid the deterioration of the standing wave ratio caused by the mismatch between the switch and the low-noise amplifier.

[0029] 2. The present invention integrates a novel feedback network with phase-shifting function in a low-noise amplifier. By adjusting parameters such as the characteristic impedance and electrical length of the microstrip line in the input unit and output matching unit, the lower sideband roll-off factor of the low-noise amplifier can be improved and the operating bandwidth of the low-noise amplifier can be increased.

[0030] 3. This invention integrates a non-reflective filter network into a low-noise amplifier, which dissipates the reflected energy outside the mixer band through a resistor, thus preventing the reflected energy from entering the antenna through the low-noise amplifier and generating parasitic harmonics and spurious signals through intermodulation effects, thereby improving the anti-interference capability of the low-noise amplifier. Attached Figure Description

[0031] Figure 1 This is an exploded view of the integrated function of the low-noise amplifier of the present invention.

[0032] Figure 2 This is a circuit diagram of the low-noise amplifier of the present invention.

[0033] Figure 3 This is a simulation diagram of the noise figure in Embodiment 1 of the present invention.

[0034] Figure 4 This is a simulation diagram of P1dB in Embodiment 1 of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings.

[0036] A low-noise amplifier integrating a switch and a filter without inverse filtering function, its integrated functional breakdown diagram is shown below. Figure 1 As shown, it includes an input capacitor, an input matching unit, a notch filter network, a common-source cascode amplifier, a switching control network, a feedback network, an interstage matching unit, a parallel peaked load amplifier, an output matching unit, a reflection-free filter network, and an output capacitor.

[0037] The specific circuit diagram of the low-noise amplifier is as follows: Figure 2 As shown, the input matching network consists of a T-type matching network composed of three microstrip lines (TL1, TL2, TL3). The goal of the matching is to achieve conjugate matching at the minimum noise figure point of transistor FET1 in the cascode amplifier. The broadband matching of the low-noise amplifier is achieved by adjusting the characteristic impedance and electrical length of the microstrip lines. When necessary, the bandwidth characteristics can be enhanced by increasing the number of microstrip lines in the matching network.

[0038] The notch filter network consists of a parallel capacitor C2, an inductor L1, and a series capacitor C1. The parallel capacitor and the inductor, both grounded at one end, are connected in parallel and then connected in series with a fixed capacitor. By adjusting the parallel capacitor, the resonant frequency of the entire network can be changed, thus adjusting the resonant frequency of the notch filter network to the upper out-of-band of the low-noise amplifier. This can improve the out-of-band interference immunity of the low-noise amplifier and adjust its in-band ripple characteristics.

[0039] The common-source common-gate amplifier group mainly consists of a first transistor FET1 and a second transistor FET2. The first transistor FET1 has a common-source structure, and the second transistor FET2 has a common-gate structure. The two transistors together form a common-source common-gate structure. The gate of the second transistor FET2 is isolated by a resistor R1 and then connected to the DC power supply VCC. In order to increase the anti-interference characteristics of the power supply, two single-ended grounded capacitors (C3 and C4) are added on both sides of the inductor to achieve power supply filtering.

[0040] The switching control network is a symmetrical three-port network, consisting of an external voltage control port, a left control port, and a right control port. It comprises microstrip lines, transistors FET4 and FET5, an inductor, and a capacitor. Transistors FET4 and FET5 operate in common-source mode. One end of their drains is connected to the external voltage control interface via microstrip lines (TL11, TL12), while the other end is connected to the port to be controlled via microstrip lines (TL9, TL10) in series with inductors (L2, L3). Capacitors (C11, C12) are connected in parallel at the external voltage control interface for power filtering. The left control port of the switching control network is connected to the gate of transistor FET1, and the right control port is connected to the source of transistor FET3. The voltage control ports enable simultaneous on / off control of transistors FET1 and FET3.

[0041] The feedback network consists of capacitors (C5, C6, C7), microstrip line TL8, coupling line CTL1, and inductors. One end of the feedback network is connected to a DC power supply, and then connected in parallel with inductor L3, series capacitor C6, series microstrip line TL8, and series coupling line CTL1 before being connected to the drain of transistor FET2. Inductor L3 is an interoperable component, participating in both the feedback network and forming a parallel peaked load structure with transistor FET3. The input / output ports of coupling line CTL1 have a crossover structure, with one microstrip line serving as the input and the other as the output. The remaining ports are connected to ground through single-ended grounding capacitors (C5, C7).

[0042] The interstage matching unit consists of microstrip line TL4, capacitor C8, and microstrip line TL5. At the same time, microstrip lines (TL6 and TL7) and single-ended grounded capacitors (C9 and C10) are connected in parallel on both sides of the two microstrip lines (TL4 and TL5) to achieve impedance conjugate matching of the high-pass characteristics from transistor FET2 to transistor FET3.

[0043] The output matching unit consists of a T-type matching network composed of three microstrip lines (TL13, TL14, TL15). The goal of the matching is to achieve conjugate matching at the minimum noise figure point of transistor FET3. The broadband matching of the low-noise amplifier is achieved by adjusting the characteristic impedance and electrical length of the microstrip lines. When necessary, the bandwidth characteristics can be enhanced by increasing the number of microstrip lines in the matching network.

[0044] The anti-reverse filter network consists of coupled lines CTL2 and CTL3, single-ended grounded capacitors (C13, C14), resistors (R3, R4), and microstrip lines (TL16, TL17, TL18). The network comprises two branches, each consisting of a coupled line, a single-ended grounded capacitor, a resistor, and a microstrip line. The two branches are connected in series via a third microstrip line to form a symmetrical bridge structure. Coupled lines CTL2 and CTL3 are connected in series to the output port of transistor FET3 and one end of the output capacitor, respectively. The remaining ports of coupled lines CTL2 and CTL3 are connected to ground via resistors and microstrip lines, respectively. A parallel single-ended grounded capacitor (C13, C14) is added between the resistor and the coupled line to improve the filter's resonant characteristics.

[0045] Example 1

[0046] In this implementation, the low-noise amplifier is fabricated using a pHEMT MMIC process on a 0.15μm GaAs substrate. The dielectric substrate material is gallium arsenide with a dielectric constant of 12.91 and a thickness of 100μm. All circuits are etched onto the upper surface of the dielectric substrate using micro-nano fabrication, and the lower surface of the dielectric substrate is grounded through a flat metal layer.

[0047] The input and output impedances of the low-noise amplifier were calculated using an equivalent model. Optimal noise figure matching was achieved using a T-type microstrip line matching method, maximizing gain while ensuring optimal noise figure, and optimizing the matching network to exhibit bandpass filtering characteristics. To achieve DC isolation, a 30fF capacitor was connected in series between the input matching and the input terminal, and a 30fF capacitor was connected in series between the output matching and the output terminal.

[0048] Considering the relatively small Q value of the on-chip inductor, the inductance value of the notch filter network should be chosen to be as small as possible. Different inductance values ​​L1 and series capacitor C1, when forming a resonant network, will affect the S value at the center frequency. 21The suppression depth also varies: a smaller inductance value results in a deeper suppression depth. In this implementation, a 1nH inductance value is selected, and the capacitance value of the series capacitor is adjusted to achieve notch filtering at a frequency of 3.5GHz, improving the anti-interference capability of the upper sideband. The parallel capacitor C2 has a value of 100fF, and the suppression depth can be improved by adjusting the parallel capacitor. The capacitor is implemented in a MIM (metal-insulator-metal) configuration.

[0049] The first-stage amplifier circuit adopts a common-source common-gate structure and is connected to the power supply VCC through resistor R1. The capacitance values ​​of the single-ended grounding capacitors (C3 and C4) on both sides of resistor R1 are selected as 1pF and 180fF respectively, the resistor is selected as 1kΩ, and the specifications of transistors FET1 and FET2 are 2×20μm.

[0050] The interstage matching unit employs a high-pass filter to improve in-band gain flatness. Two parallel microstrip lines (TL6, TL7) are grounded via capacitors (C9, C10). In this embodiment, the capacitor value is chosen to be 150fF. The two parallel branches resonate at low frequencies, exhibiting low impedance values, which effectively suppress gain fluctuations in the preceding amplifier stage. Adjusting the values ​​of the series microstrip lines (TL4, TL5) and capacitor (C8) achieves conjugate matching from transistor FET2 to transistor FET3.

[0051] The feedback network is in the form of positive feedback, with a gain of -2C. k T k C k T represents the coupling coefficient of the feedback network. k The continuity coefficient of the feedback network is functionally related to the coupling coefficient k of the coupling line. Generally, the smaller the coupling coefficient k of the coupling line, the smaller the gain of the feedback network, but the larger the gain fluctuation. Considering the balance between gain and gain fluctuation, a coupling coefficient of 0.2 and a length of 300μm are selected for the coupling line, and other parameters are adjusted to optimize the gain fluctuation of the low-noise amplifier within the frequency band.

[0052] The switch is implemented using a common-source transistor, requiring an on-state voltage of less than -1.8V and an off-state voltage of 0V. The two transistors (FET4 and FET5) are selected as 2×10μm, and the parallel single-ended grounded capacitors (C11 and C12) are also selected as 180fF for power supply filtering. The microstrip lines (TL9, TL10, TL11, and TL12) are chosen with a characteristic impedance of 50Ω and an electrical length of 10° to minimize their impact on the interstage matching network. The inductors (L2 and L3) have a certain influence on the matching network; therefore, the inductors are adjusted to optimize the entire circuit. One end of the switching network is connected to the gate of transistor FET1, and the other end is connected to the source of transistor FET3. The switching network synchronously controls the on / off state of the two transistors.

[0053] The second-stage amplifier circuit employs a parallel peaked load structure to increase the bandwidth of the low-noise amplifier. The values ​​of inductor (L4) L, the parasitic resistance R of inductor L, and the output equivalent capacitance C of transistor FET3 are used. out The resonant structure is constructed by comprehensive consideration. By optimizing the inductance value L, the time constants C of the capacitor and resistor are optimized. out R: The time constant determined by the inductance and resistance, L / R = 2:1, achieves the effect of extending the bandwidth by 180%.

[0054] The anti-reflection-free filter network adopts a symmetrical structure based on coupled lines. Let the coupling coefficient of the entire anti-reflection-free filter network be ρ. Then, the even-mode impedance of the coupled line is... Odd-mode impedance is Adjust the values ​​of the parallel capacitors (C13, C14), the parallel microstrip lines (TL16, TL17), and the resistors (R2, R3) to make S 21 The in-band return loss is 7-10dB. Excessive return loss will reduce the gain coefficient of the low-noise amplifier, so both parameters need to be weighed.

[0055] This implementation is just an example. All values ​​of the entire low-noise amplifier can be set as variables, and the overall parameters can be optimized by using an optimization algorithm to integrate the gain, gain fluctuation, noise figure and maximum power into the optimization objective function.

[0056] Figure 3 This is a simulation diagram of the noise figure for Embodiment 1 of the present invention. As can be seen from the figure, the low-noise amplifier of this embodiment has a noise figure between 1.71 and 1.95 dB after simulation at a center frequency of 4.0-6.0 GHz, with the noise figure being better than 1.75 dB between 4.4 and 5.6 GHz. Figure 4 This is a simulation diagram of P1dB in Embodiment 1 of the present invention. P1dB fluctuates between -2.2dBm and -2.0dBm within the 4.0-6.0GHz frequency band, exhibiting good linearity. The low-noise amplifier operates over 40% of its bandwidth, demonstrating good broadband characteristics.

[0057] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A low-noise amplifier integrating a switch and a filter without reverse filtering function, characterized in that, It includes an input matching unit, a notch filter network, a cascode amplifier, a switch control network, a feedback network, an interstage matching unit, a parallel peaked load amplifier, an output matching unit, and a reflection-free filter network; The input matching unit consists of three T-shaped microstrip lines. One end of the first microstrip line TL1 is connected to the input port of the low-noise amplifier. The other end of the first microstrip line TL1 is connected to one end of the second microstrip line TL2 and one end of the third microstrip line TL3. The other end of the second microstrip line TL2 is connected to the gate of the first transistor FET1 in the common-source common-gate amplifier and one end of the twelfth inductor L12 in the switch control network. The notch filter network consists of a first inductor L1, a first capacitor C1, and a second capacitor C2; one end of the first inductor L1 is grounded, and the other end is connected to one end of the first capacitor C1 and one end of the second capacitor C2; the other end of the first capacitor C1 is connected to the drain of the first transistor FET1 in the cascode amplifier and the source of the second transistor FET2 in the cascode amplifier; the other end of the second capacitor C2 is grounded. The common-source common-gate amplifier consists of a first transistor FET1, a second transistor FET2, a third capacitor C3, a fourth capacitor C4, and a first resistor R1. The source of the first transistor FET1 is grounded. The drain of the second transistor FET2 is connected to one end of the fourth microstrip line and one end of the sixth microstrip line in the interstage matching unit. The gate of the second transistor FET2 is connected to one end of the fourth capacitor C4 and one end of the first resistor R1. The other end of the fourth capacitor C4 is grounded. The other end of the first resistor R1 is connected to one end of the third capacitor C3 and the DC power supply VCC. The other end of the third capacitor C3 is grounded. The switching control network consists of a twelfth inductor L12, a thirteenth inductor L13, a ninth microstrip line TL9, a tenth microstrip line TL10, an eleventh microstrip line TL11, a twelfth microstrip line TL12, an eleventh capacitor C11, a fourth transistor FET4, and a fifth transistor FET5. The other end of the twelfth inductor L12 is connected to one end of the ninth microstrip line TL9, and the other end of the ninth microstrip line TL9 is connected to one end of the eleventh microstrip line TL11 and the drain of the fourth transistor FET4. The gate of the fourth transistor FET4 is connected to the control voltage, and its source is grounded. The eleventh microstrip line... The other end of TL11 is connected to one end of the eleventh capacitor C11, one end of the twelfth capacitor C12, one end of the twelfth microstrip line TL12, and the control voltage; the other end of the twelfth microstrip line TL12 is connected to one end of the tenth microstrip line TL10 and the drain of the fifth transistor FET5; the source of the fifth transistor FET5 is grounded, and its gate is connected to the control voltage; the other end of the tenth microstrip line TL10 is connected to one end of the thirteenth inductor L13; the other end of the thirteenth inductor L13 is connected to the other end of the fifth microstrip line TL5 in the interstage matching unit and the gate of the third transistor FET3 in the parallel peaked load amplifier; The feedback network consists of a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth microstrip line TL8, a first coupling line CTL1, and a fourth inductor L4; one end of the fifth capacitor C5 is grounded, and the other end is connected to the coupling end of the first coupling line CTL1. The input terminal of the first coupling line CTL1 is connected to one end of the eighth microstrip line TL8, the isolation terminal is connected to one end of the seventh capacitor C7, and the output terminal is connected to the drain of the second transistor FET2; the other end of the eighth microstrip line TL8 is connected to one end of the sixth capacitor C6, the other end of the sixth capacitor C6 is connected to the DC power supply VCC and one end of the fourth inductor L4; the other end of the seventh capacitor C7 is grounded. The interstage matching unit consists of a fourth microstrip line TL4, a fifth microstrip line TL5, a sixth microstrip line TL6, a seventh microstrip line TL7, an eighth capacitor C8, a ninth capacitor C9, and a tenth capacitor C10. The other end of the fourth microstrip line TL4 is connected to one end of the eighth capacitor C8, the other end of the eighth capacitor C8 is connected to one end of the fifth microstrip line TL5, the other end of the fifth microstrip line TL5 is connected to one end of the seventh microstrip line TL7, the other end of the thirteenth inductor L13 in the switching control network, and the gate of the third transistor FET3 in the parallel peaking load amplifier. The other end of the seventh microstrip line TL7 is connected to one end of the tenth capacitor C10, and the other end of the tenth capacitor C10 is grounded. The other end of the sixth microstrip line TL6 is connected to one end of the ninth capacitor C9, and the other end of the ninth capacitor C9 is grounded. The parallel peaked load amplifier consists of a third transistor FET3 and a fourth inductor L4; the drain of the third transistor FET3 is connected to the other end of the fourth inductor L4 and one end of the thirteenth microstrip line TL13 in the output matching unit, and the source of the third transistor FET3 is grounded; the parallel peaked load amplifier and the feedback network share the fourth inductor L4. The output matching unit consists of three T-shaped microstrip lines. One end of the thirteenth microstrip line TL13 is connected to the other end of the fourth inductor L4. The other end of the thirteenth microstrip line TL13 is connected to one end of the fourteenth microstrip line TL14 and one end of the fifteenth microstrip line TL15. The other end of the fourteenth microstrip line TL14 is connected to the first port of the second coupling line CTL2 in the anti-reverse filter network. The other end of the fifteenth microstrip line TL15 is open. The reflectionless filter network consists of a second coupling line CTL2, a third coupling line CTL3, a thirteenth capacitor C13, a fourteenth capacitor C14, a second resistor R2, a third resistor R3, a sixteenth microstrip line TL16, a seventeenth microstrip line TL17, and an eighteenth microstrip line TL18. The second port of the second coupling line CTL2 is connected to one end of the second resistor R2 and one end of the thirteenth capacitor C13; the third port of the second coupling line CTL2 is connected to the first port of the third coupling line CTL3; the other end of the second resistor R2 is connected to one end of the sixteenth microstrip line TL16 and one end of the eighteenth microstrip line TL18; the second port of the third coupling line CTL3 is connected to the output port of the low-noise amplifier; and the third port of the third coupling line CTL3 is connected to one end of the fourteenth capacitor C14 and one end of the third resistor R3. The fourth port of the second coupling line CTL2 and the fourth port of the third coupling line CTL3 are both open; the other end of the third resistor R3 is connected to the other end of the eighteenth microstrip line TL18 and one end of the seventeenth microstrip line TL17; the other ends of the thirteenth capacitor C13, the sixteenth microstrip line TL16, the seventeenth microstrip line TL17 and the fourteenth capacitor C14 are all grounded.

2. The low-noise amplifier as described in claim 1, characterized in that, The low-noise amplifier also includes an input DC blocking capacitor C1 and an output DC blocking capacitor C16. The input DC blocking capacitor is disposed between the input matching unit and the input terminal of the low-noise amplifier, and the output DC blocking capacitor is disposed between the output matching unit and the output terminal of the low-noise amplifier to achieve DC isolation.

3. The low-noise amplifier as described in claim 1, characterized in that, Wideband matching is achieved by adjusting the characteristic impedance and electrical length of the microstrip line in the input matching unit, and the bandwidth characteristics of the low-noise amplifier are enhanced by increasing the number of microstrip lines between the input capacitor and the first microstrip line TL1.

4. The low-noise amplifier as described in claim 1, characterized in that, Adjusting the capacitance of the second capacitor C2 in the notch filter network to adjust the resonant frequency, thereby placing the resonant frequency of the notch filter network outside the upper band of the low-noise amplifier, can improve the out-of-band interference immunity of the low-noise amplifier and adjust its in-band ripple characteristics; the inductance value of the first inductor L1 and the first capacitor C1, after forming a resonant network, affect the S at the center frequency point. 21 The suppression depth varies; the smaller the inductance value, the deeper the suppression depth.

5. The low-noise amplifier as described in claim 1, characterized in that, The input and output terminals of the first coupling line CTL1 are cross-structured and can be converted to each other, that is, after one side of the microstrip line is used as the input port, the other side of the microstrip line is used as the output port.

6. The low-noise amplifier as described in claim 1, characterized in that, Wideband matching is achieved by adjusting the characteristic impedance and electrical length of the microstrip lines in the output matching unit, and the bandwidth characteristics of the low-noise amplifier are enhanced by increasing the number of microstrip lines between the second coupling line CTL2 and the fourteenth microstrip line TL14.

7. The low-noise amplifier as claimed in claim 1, characterized in that, The switch control network has a left-right symmetrical structure, and the anti-filter network has a symmetrical bridged structure.

8. The low-noise amplifier as described in claim 1, characterized in that, The switching control network enables the simultaneous turning on or off of the first transistor FET1 and the third transistor FET3 by regulating the control voltage.

9. The low-noise amplifier as claimed in claim 1, characterized in that, The feedback network is in the form of positive feedback, and its gain is -2C. k T k , where C k T represents the coupling coefficient of the feedback network. k The coupling coefficient k of the first coupling line is smaller, resulting in a smaller gain for the feedback network, but also a larger gain fluctuation.

10. The low-noise amplifier as claimed in claim 1, characterized in that, By adjusting the parameter values ​​of the thirteenth capacitor C13, the fourteenth capacitor C14, the sixteenth microstrip line TL16, the seventeenth microstrip line TL17, the second resistor R2, and the third resistor R3 in the anti-reverse filter network, S is made... 21 The return loss within the band is 7-10 dB.

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