Fuse trimming judgment control circuit with high interference immunity

Abstract

A fuse trimming judgment control circuit with high anti-interference capability, comprising a power voltage detection comparison module, a fuse judgment locking module TRIMMING FUSE LATCH and a circuit module to be trimmed; the power voltage detection comparison module comprises a reference current unit IBIAS, a band gap reference unit BANDGAP, a power voltage undervoltage locking unit UVLO, a power voltage detection unit VDDEN, a logic inverter, a two-input logic AND gate, a power voltage undervoltage locking delay unit UVLO DELAY, power detection voltage division resistors R1 and R2; the fuse judgment locking module TRIMMING FUSE LATCH comprises a fuse judgment unit FUSE TRIMMING and a test mode unit; the test mode unit outputs TMODE as high level when entering the test mode, and the fuse judgment unit FUSE TRIMMING judges and stores the fuse state and outputs a signal TRA <n>The application provides a fuse-burning adjustment method and a circuit module. Therefore, the application solves the problem of misjudgment of the circuit to the fuse state when the fuse is not completely burned during the fuse-burning adjustment process.< / n>

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit (IC) packaging technology and relates to a fuse adjustment judgment and control circuit with high anti-interference capability. Background Technology

[0002] In integrated circuit applications where electrical parameters are adjusted due to drift caused by integrated circuit packaging, meeting the requirements for high-precision electrical parameters is currently the industry's goal.

[0003] Please see Figure 1 and Figure 2 , Figure 1 The diagram shown is a schematic of a fuse adjustment judgment and control circuit in the prior art. Figure 2 for Figure 1 The diagram shows a schematic of the fuse trimming control circuit. As shown, this circuit includes a power supply voltage detection and comparison module, a fuse trimming latch module, and a circuit to be trimmed module. The power supply voltage detection and comparison module includes a reference current unit IBIAS, a bandgap reference unit BANDGAP, a power supply voltage undervoltage lockout unit UVLO, a power supply voltage detection unit VDDEN, and a power supply voltage undervoltage lockout delay unit UVLO DELAY. The fuse trimming latch module includes a logic inverter INV, a two-input logic AND gate AND2, and the fuse trimming latch unit.

[0004] The reference current unit IBIAS provides bias current IB to the bandgap reference unit BANDGAP, the undervoltage lockout unit UVLO, and the fuse triggering module TRIMMING FUSE LATCHFUSE Trimming. The bandgap reference module BANDGAP provides the reference voltage VREF to the undervoltage lockout unit UVLO. After the bandgap reference unit BANDGAP is working normally, its output VBGOK is at a logic high level.

[0005] Please see Figure 3 , Figure 3 The diagram shown is a timing diagram of a fuse adjustment judgment and control circuit in the prior art. Figure 3As shown, when the internal module power supply VDD is powered on, firstly, the reference current unit IBIAS works normally to generate a bias current IB, which is provided to the bandgap reference unit BANDGAP, the power supply voltage detection unit VDDEN, the power supply voltage undervoltage lockout unit UVLO, and the power supply voltage undervoltage lockout delay unit UVLO DELAY. Subsequently, the bandgap reference unit BANDGAP works normally to generate a reference voltage VREF, and after the output VBGOK signal flips to a high level, the power supply voltage detection unit VDDEN starts to work. The power supply voltage VDD continues to rise until the power supply voltage detection unit VDDEN can work normally, and the output power supply VDDEN signal flips to a high level and is output to one end of the logic AND gate AND2.

[0006] Because the voltage VS of the internal module power supply VDD, after passing through the power detection voltage divider resistors R1 and R2, is less than the reference voltage VREF, the power supply voltage undervoltage lockout unit UVLO is in an undervoltage lockout state, and the UVLO signal output is low. The power supply voltage undervoltage lockout delay unit UVLO DELAY, which receives the UVLO signal output, also has low-level delayed signals UVLOL and UVLOD. The low-level UVLOD signal is output as a high-level signal by the logic inverter to the other end of the AND gate AND2. At this time, the logic AND gate AND2 outputs a high-level enable signal ENH to the fuse determination unit FUSE TRIMMING, enabling the fuse determination unit FUSE TRIMMING to start working. By comparing the P-type transistor MP2... <n>Pull-up current and N-type transistor MN1 <n>The magnitude of the pull-down current is used to determine the fuse status.

[0007] As the power supply voltage VDD continues to rise, the UVLO and UVLOL signals remain low because the undervoltage lockout has not yet been released. The fuse status latch unit LATCH FUSE will continue to transmit the fuse status until the voltage VS of the internal module power supply VDD after passing through the power detection voltage divider resistors R1 and R2 is greater than the reference voltage VREF. At this point, the undervoltage lockout unit UVLO is released, and the UVLO signal flips to a high level.

[0008] After a delay of t1, the UVLOL signal flips to a high level. At this time, the fuse status latch unit LATCH FUSE will lock the acquired fuse status Fn signal and output TRA. <n>Upon reaching the circuit module under repair, after a delay of t2 (t2 > t1), the UVLO signal flips to a high level, at which point the enable signal ENH becomes a logic low level, and the fuse trimming unit stops working. Subsequently, the high-accuracy blocks 1 to n of the circuit module under repair receive a set of fuse trimming signals TRA output from the fuse trimming unit. <0> , ..., TRA <n>Adjust the corresponding electrical parameters.

[0009] The fuse trimming unit determines whether a fuse has blown by comparing a reference resistor R0 with the fuse resistance RF; this is equivalent to the P-type transistor MP2. <n>Pull-up current and N-type transistor MN1 <n>Pull-down current is compared; when the fuse is not blown, RF < R0, N-type transistor MN1 <n>The pull-down current of the transistor is greater than that of the P-type transistor MP2. <n>Pull-up current, output TRA <n>The voltage level is low; when the fuse needs to be blown, the external testing equipment will input a fixed voltage through the FPAD, at which point the voltage between the FPAD and the fuse resistor FU will be low. <n>Then a low-impedance path is formed on the ground terminal GND. The resulting instantaneous current will burn out the fuse. Afterward, the fuse usually exhibits a high-resistance state, i.e., RF > R0. N-type transistor MN1 <n>The pull-down current of the transistor is less than that of the P-type transistor MP2. <n>Pull-up current, output TRA <n>It is a high level.

[0010] However, during wafer fabrication, process fluctuations can affect the fuse resistance FU. <n>Inaccuracies or deviations in the testing equipment, and other such random factors, can cause the fusing current to be too low during the fuse burning process, resulting in the fuse not burning completely, i.e., the fuse resistance FU after burning out. <n>The value will exhibit randomness; when the resistance RF of the incompletely blown fuse is very close to the reference resistance R0, the P-type transistor MP2... <n>Pull-up capability and N-type transistor MN1 <n>The pull-down capability is also similar, making the P-type transistor MP2... <n>N-type transistor MN1 <n>The drain output voltage at point A is in the intermediate level, a floating state. This causes uncertainty in the fuse determination unit (FUSE TRIMMING)'s assessment of the fuse state. For example, if the P-type transistor MP2 is in this state... <n>N-type transistor MN1 <n>When the intermediate state voltage at point A, the drain output, is precisely identified as a high level, it causes the output TRA to... <n>A high level indicates that the fuse is blown, and the electrical parameters are considered to be successfully adjusted, thus the sample is judged to be a good product.

[0011] When the sample is powered on again via VDD, the P-type transistor MP2 is affected by external environmental factors such as packaging stress and temperature. <n>N-type transistor MN1 <n>The intermediate state of the drain output is identified as low, at which point the output TRA... <n>It also becomes a low level, which is considered that the fuse is not burned out at this time. The deviation of the electrical parameters cannot be adjusted, resulting in the failure of the electrical parameters test and becoming a defective product. This kind of sample will cause the fuse TRIMMING unit to misjudge the fuse state and cannot accurately screen it out during the test process, thus mixing it into the good products. Therefore, it will have a great impact on the actual yield. Summary of the Invention

[0012] To address the aforementioned technical problems, this invention proposes a fuse adjustment judgment and control circuit with high anti-interference capability, which solves the problem of misjudging the fuse status when the fuse is not completely melted during the fuse burnout adjustment process.

[0013] To achieve the above objectives, the technical solution of the present invention is as follows:

[0014] A high-accuracy fuse trimming judgment and control circuit includes a power supply voltage detection and comparison module, a fuse judgment and locking module (TRIMMING FUSE LATCH), and a high-accuracy block 1 to n of the circuit to be trimmed. The power supply voltage detection and comparison module includes a reference current unit (IBIAS), a bandgap reference unit (BANDGAP), a power supply voltage undervoltage lockout unit (UVLO), a power supply voltage detection unit (VDDEN), a logic inverter, a two-input logic AND gate, and a power supply voltage undervoltage lockout delay unit (UVLO). The system comprises three voltage divider resistors: DELAY, R1, and R2. When the external input power supply VDD is powered on, the reference current unit IBIAS generates a bias current IB, which is supplied to the bandgap reference unit BANDGAP, the power supply voltage undervoltage lockout unit UVLO, the power supply voltage detection unit VDDEN, and the power supply voltage undervoltage lockout delay unit UVLODELAY. The bandgap reference unit BANDGAP generates a reference voltage VREF and outputs a VBGOK signal to the power supply voltage detection unit VDDEN. The power supply voltage detection unit VDDEN starts working under the control of the VBGOK enable signal and continuously detects the power supply VDD voltage. It outputs a VDDEN signal to one end of the AND gate AND2. The voltage VDD is compared with the reference voltage VREF by the voltage divider resistors R1 and R2. The system determines whether the power supply VDD voltage is high or low and outputs the corresponding undervoltage lockout signal UVLO to the fuse detection lockout module TRIMMINGFUSE LATCH and the power supply voltage undervoltage lockout delay unit UVLO. DELAY; The undervoltage lockout delay unit UVLODELAY receives the UVLO signal and outputs a delayed signal UVLOD to a logic inverter, and a delayed signal UVLOL to the fuse detection and locking module TRIMMING FUSE LATCH; the UVLOD signal is inverted by the logic inverter and outputs a logic inverted signal to the other end of the AND gate AND2; the AND gate AND2 compares the states of the two input signals and outputs an enable signal ENH to the fuse detection and locking module TRIMMING FUSE LATCH to control whether the fuse detection and locking module TRIMMING FUSE LATCH works; the fuse detection and locking module TRIMMING FUSE LATCH includes a test mode unit and a fuse detection unit FUSE TRIMMING; when the test mode unit enters the test mode, it outputs TMODE as high level, and the fuse detection unit FUSE TRIMMING judges and stores the fuse state and locks it, outputting a signal TRA <n>The high-accuracy blocks 1 to n of the subsequent circuit modules to be repaired receive the output signal of the fuse TRIMMING unit to adjust the parameters to be repaired.

[0015] Furthermore, the test mode unit includes a flip-flop unit (DFFT) and an N-type transistor (M3). <n>P-type transistor M4, P-type transistor M5, P-type transistor M6, N-type transistor M7, N-type transistor M8, P-type transistor MP3 <n>Logic inverters INV3 and INV4.

[0016] Among them, the gate of N-type transistor M7, the source of N-type transistor M8, and the gate of P-type transistor M4 are connected to the ground terminal GND of the flip-flop unit DFFT; P-type transistors M4, M5, M6, and MP3 <n>The source of transistor M7 is connected to the power supply VDD; the drain of N-type transistor M7 is connected to the input V1; the drain of P-type transistor M4, the gate of P-type transistor M5, and the gate of N-type transistor M8 are connected together; the drain of P-type transistor M5, the drain of N-type transistor M8, and the drain of P-type transistor M6 are connected to the input of logic inverter INV3; the output of logic inverter INV3 is connected to the input of logic inverter INV4; the output of logic inverter INV4 is connected to the data terminal of the flip-flop unit DFFT; the CLK and SETH terminals of the flip-flop unit DFFT receive the UVLO signal; the output of the flip-flop unit DFFT is connected to N-type transistor M3. <n>The gate of the P-type transistor MP3 <n>The drain of the N-type transistor M3 <n>Source; the output terminal of the test mode unit is an N-type transistor M3. <n>Drain electrode.

[0017] Furthermore, the fuse determination unit (FUSE TRIMMING) includes a fuse state latching unit (LATCH FUSE), a P-type transistor (M0), a P-type transistor (MP0), a P-type transistor (MP1), and a P-type transistor (MP2). <n>N-type transistor M1, N-type transistor MN1 <n>P-type transistor MP1, P-type transistor MP2 <n>Logic inverter INV0, Logic inverter INV1 <n>Logic inverter INV2 <n>Resistor R0, fuse status latch unit LATCH FUSE and fuse resistor FU <n>; wherein, the source of P-type transistor M0, the source of P-type transistor MP0, the source of P-type transistor MP1, and the source of P-type transistor MP2 <n>The source of the transistor is connected to the power supply VDD; P-type transistor MP2 <n>The drain and N-type transistor MN1 <n>The drain of the N-type transistor M3 <n>The drain and logic inverter INV1 <n>The input terminals; the drain of P-type transistor M0, the drain and gate of P-type transistor MP0, the gate and pin of P-type transistor MP1, and the pin of P-type transistor MP2. <n>The gate of the N-type transistor M1 and the drain of the P-type transistor MP3 are connected. <n>The gate of N-type transistor M0, the gate of N-type transistor M1, and the input of logic inverter INV0 are connected to the ENH terminal; the output of logic inverter INV0 is connected to the gate of N-type transistor M2; the drain of N-type transistor M2 is connected to the gate and drain of N-type transistor MN0, and the input of N-type transistor MN1... <n>The gate of the P-type transistor MP1 and the drain of the P-type transistor MP1; resistor R0 is connected between the source of the N-type transistor MN0 and ground GND; fuse resistor FU <n>Connected to N-type transistor MN1 <n>Between the source and ground terminal GND, N-type transistor MN1 <n>The source receives the FPAD signal; logic inverter INV1 <n>The output terminal is connected to the logic inverter INV2. <n>The input terminal of the logic inverter INV2 <n>The output terminal outputs the Fn signal to the fuse state latching unit LATCH FUSE, and the fuse state latching unit LATCH FUSE outputs TRA in conjunction with the UVLOL signal. <n>Signal.

[0018] As can be seen from the above technical solution, the high anti-interference fuse adjustment judgment control circuit of the present invention can improve the recognition rate of the circuit in judging the fuse status, greatly reduce the probability of misjudgment when the resistance value of the fuse is close to the judgment resistor after it is burned out, ensure the consistency of the electrical parameters of the integrated circuit fuse after adjustment, and improve the yield. Attached Figure Description

[0019] Figure 1 The diagram shown is a schematic of a fuse adjustment judgment and control circuit using existing technology.

[0020] Figure 2 for Figure 1 The diagram shown illustrates the fuse trimming unit in the fuse trimming control circuit.

[0021] Figure 3 The figure shown is the timing diagram of the fuse adjustment judgment control circuit in the prior art.

[0022] Figure 4 The diagram shown is a preferred embodiment of the present invention with high anti-interference capability.

[0023] Figure 5 This is a schematic diagram of the fuse detection and locking module in an embodiment of the present invention.

[0024] Figure 6 The diagram shown is a timing diagram of the fuse adjustment judgment and control circuit in an embodiment of the present invention. Detailed Implementation

[0025] The following is in conjunction with the appendix Figure 4-6 The specific embodiments of the present invention will be further described in detail below.

[0026] Please see Figure 4 , Figure 4 The diagram shown is a preferred embodiment of a fuse adjustment judgment and control circuit with high anti-interference capability according to an embodiment of the present invention. Figure 4 As shown, the circuit includes a power supply voltage detection and comparison module, a fuse detection and locking module, a high-accuracy block 1 to n module for the circuit to be repaired, resistors and transistors, etc.

[0027] In embodiments of the present invention, the power supply voltage detection and comparison module may include a reference current unit IBIAS, a bandgap reference unit BANDGAP, a power supply voltage undervoltage lockout unit UVLO, a power supply voltage detection unit VDDEN, a logic inverter, a two-input logic AND gate and a power supply voltage undervoltage lockout delay unit UVLO DELAY, a power supply detection voltage divider resistor R1 and a power supply detection voltage divider resistor R2, etc.

[0028] The fuse detection and locking module includes a fuse detection unit (FUSE TRIMMING) and a test mode unit.

[0029] When the external input power supply VDD is powered on, the power supplies VDD of each internal module are powered on accordingly. As the power supply VDD is powered on to a certain voltage, the bias current IBIAS of the reference current unit first starts to work normally and generates bias current IB to provide to the bandgap reference unit BANDGAP, the power supply voltage undervoltage lockout unit UVLO, the power supply voltage detection unit VDDEN, and the power supply voltage undervoltage lockout delay unit UVLO DELAY.

[0030] Subsequently, the bandgap reference unit BANDGAP starts working to generate a reference voltage VREF. Once the reference voltage VREF is normal, it outputs a VBGOK signal to the power supply voltage detection unit VDDEN. The power supply voltage detection unit VDDEN is controlled by the VBGOK enable signal to start working and continuously detects the power supply voltage VDD. It outputs a VDDEN signal to one end of the AND gate AND2 via the detected signal. The power supply voltage VDD is compared with the reference voltage VREF by the voltage divider VS of the power supply detection resistors R1 and R2. The voltage value of VDD is judged to be high or low, and a corresponding undervoltage lockout signal UVLO is output to the fuse detection lockout module TRIMMING FUSE LATCH and the power supply voltage undervoltage lockout delay unit UVLO DELAY. The power supply voltage undervoltage lockout delay unit UVLO DELAY receives the UVLO signal and outputs a delayed signal UVLOD to a logic inverter, and a delayed signal UVLOL to the fuse detection lockout module TRIMMING FUSE. LATCH; The UVLOD signal is output as a logic inverter and then a logic inverted signal is sent to the other end of AND gate AND2; AND gate AND2 outputs an enable signal ENH by comparing the states of the two input signals above, which is sent to the TRIMMING FUSE LATCH module to control whether the TRIMMING FUSE LATCH module works.

[0031] When the test mode unit enters test mode, it outputs TMODE at a high level. The fuse determination unit FUSETRIMMING determines and stores the fuse status, and outputs the TRA signal. <n>The high-accuracy blocks 1 to n of the subsequent circuit modules to be repaired receive the output signal of the fuse TRIMMING unit to adjust the parameters to be repaired.

[0032] Please see Figure 5 , Figure 5 This is a schematic diagram of the fuse detection and locking module in an embodiment of the present invention. Figure 5 As shown, the fuse determination and locking module TRIMMING FUSE LATCH may include a test mode unit and a fuse determination unit FUSETRIMMING.

[0033] When the test mode unit enters test mode, it outputs TMODE at a high level. The fuse determination unit FUSETRIMMING determines and stores the fuse status, and outputs the TRA signal. <n>The high-accuracy blocks 1 to n are supplied to the subsequent high-accuracy circuit modules to be repaired. The high-accuracy blocks 1 to n receive the output signal of the test mode unit to adjust the parameters to be repaired.

[0034] like Figure 5 As shown, the test mode unit may include a flip-flop unit (DFFT) and an N-type transistor (M3). <n>P-type transistor M4, P-type transistor M5, P-type transistor M6, N-type transistor M7, N-type transistor M8, P-type transistor MP3 <n>Logic inverters INV3 and INV4.

[0035] The gate of N-type transistor M7, the source of N-type transistor M8, and the gate of P-type transistor M4 are connected to the ground terminal GND of the flip-flop unit DFFT; P-type transistors M4, M5, M6, and MP3 are connected to the ground terminal GND of the flip-flop unit DFFT. <n>The source of transistor M7 is connected to the power supply VDD; the drain of N-type transistor M7 is connected to the input V1; the drain of P-type transistor M4, the gate of P-type transistor M5, and the gate of N-type transistor M8 are connected together; the drain of P-type transistor M5, the drain of N-type transistor M8, and the drain of P-type transistor M6 are connected to the input of logic inverter INV3; the output of logic inverter INV3 is connected to the input of logic inverter INV4; the output of logic inverter INV4 is connected to the data terminal of the flip-flop unit DFFT; the CLK and SETH terminals of the flip-flop unit DFFT receive the UVLO signal; the output of the flip-flop unit DFFT is connected to N-type transistor M3. <n>The gate of the P-type transistor MP3 <n>The drain of the N-type transistor M3 <n>Source; the output terminal of the test mode unit is an N-type transistor M3. <n>Drain electrode.

[0036] The fuse determination unit (FUSE TRIMMING) may include a fuse state latching unit (LATCH FUSE), a P-type transistor M0, a P-type transistor MP0, a P-type transistor MP1, and a P-type transistor MP2. <n>N-type transistor M1, N-type transistor MN1 <n>P-type transistor MP1, P-type transistor MP2 <n>Logic inverter INV0, Logic inverter INV1 <n>Logic inverter INV2 <n>Resistor R0, fuse status latch unit LATCH FUSE and fuse resistor FU <n>.

[0037] The source of P-type transistor M0, the source of P-type transistor MP0, the source of P-type transistor MP1, and the source of P-type transistor MP2. <n>The source of the transistor is connected to the power supply VDD; P-type transistor MP2 <n>The drain and N-type transistor MN1 <n>The drain of the N-type transistor M3 <n>The drain and logic inverter INV1 <n>The input terminals; the drain of P-type transistor M0, the drain and gate of P-type transistor MP0, the gate and pin of P-type transistor MP1, and the pin of P-type transistor MP2. <n>The gate of the N-type transistor M1 and the drain of the P-type transistor MP3 are connected. <n>The gate of N-type transistor M0, the gate of N-type transistor M1, and the input of logic inverter INV0 are connected to the ENH terminal; the output of logic inverter INV0 is connected to the gate of N-type transistor M2; the drain of N-type transistor M2 is connected to the gate and drain of N-type transistor MN0, and the input of N-type transistor MN1... <n>The gate of the P-type transistor MP1 and the drain of the P-type transistor MP1; resistor R0 is connected between the source of the N-type transistor MN0 and ground GND; fuse resistor FU <n>Connected to N-type transistor MN1 <n>Between the source and ground terminal GND, N-type transistor MN1 <n>The source receives the FPAD signal; logic inverter INV1 <n>The output terminal is connected to the logic inverter INV2 <n>The input terminal of the logic inverter INV2 <n>The output terminal outputs the Fn signal to the fuse state latching unit LATCH FUSE, and the fuse state latching unit LATCH FUSE outputs TRA in conjunction with the UVLOL signal. <n>Signal.

[0038] Specifically, the power supply VDD is connected to P-type transistors M0, MP0, MP1, and MP2. <n>The source provides power; the ENH signal from the power supply voltage detection and comparison module controls the input of the logic inverter INV0 and the gates of P-type transistor M0 and N-type transistor M1; the bias current IB signal from the reference current unit IBIAS is connected to the source of N-type transistor M1, transmitting the bias current IB signal from the source to the drain, which is connected to P-type transistors MP0, MP1, and MP2. <n>The gate of each transistor provides a bias voltage to generate multiple fixed bias currents IB; the drain of P-type transistor M0 is connected to P-type transistors MP0, MP1, and MP2. <n>The gate of the N-type transistor MN0 is used to control the on / off state of the bias current IB; the gate and drain of the N-type transistor MN0 are shorted, and by receiving the current from the drain of the P-type transistor MP1, a bias voltage is generated for the N-type transistor MN1. <n>This enables the N-type transistor MN1 <n>This generates a corresponding bias current IB.

[0039] Resistor R0 serves as a comparator resistor, with one end connected to the source of N-type transistor MN0 and the other end connected to ground GND; N-type transistor M2 controls N-type transistors MN0 and MN1 by receiving the output signal from INV0. <n>The gate enables the bias current to be turned on and off; the fuse resistor FU <n>As a fuse resistor, one end is connected to an N-type transistor MN1. <n>The source terminal is connected to ground GND at one end; the circuit compares the resistor R0 and the fuse resistor FU. <n>The resistance value is used to determine the state; when the fuse has not burned out, the fuse resistance FU... <n>The resistance of the P-type transistor MP2 is less than R0. <n>The pull-up current is less than that of the N-type transistor MN1 <n>The pull-down current, A <n>The output logic is at a low level, indicating that the fuse is not broken.

[0040] When the fuse blows, the fuse resistor FU <n>The resistance of the P-type transistor MP2 is greater than the resistance R0. <n>The pull-up current is greater than that of the N-type transistor MN1 <n>The pull-down current, A <n>The output logic is high-level, indicating the fuse is open; A <n>The output signal of the point passes through INV1 <n>、INV2 <n>After buffering, the Fn signal is output to the fuse state latch unit LATCHFUSE. The fuse state latch unit LATCH FUSE receives the Fn signal, transmits it to the output terminal, and outputs the corresponding TRA. <n>The signal, the fuse status latch unit LATCH FUSE, is controlled by the UVLOL signal from the voltage detection and comparison module.

[0041] When the UVLOL signal is high, the fuse state latch unit LATCH FUSE will TRA <n>Signal state locked, at this time regardless of A <n>No matter how the signal changes, it cannot change TRA <n>The state of the signal.

[0042] Please see Figure 6 , Figure 6 The diagram shown is a timing diagram of the fuse adjustment judgment and control circuit in an embodiment of the present invention. Figure 6 As shown, the system operating timing of this circuit is basically consistent with the existing technology; however, on this basis, a test mode unit is added to the fuse judgment and locking module TRIMMING FUSE LATCH, which can multiplex the pin V1 without affecting the operation of other input pins (V1). Only a special signal needs to be provided to the pin to enter the test working mode.

[0043] In other words, when electrical parameters need to be tested, a special voltage signal of -1V is applied to the external input pin V1 to enter the test working mode.

[0044] In an embodiment of the present invention, when the internal module power supply VDD is powered on to a very low voltage, the V1 signal connects to the drain of the N-type transistor M7 to turn it on, and makes the gates of the P-type transistor M5 and the N-type transistor M8 connected to the source of the N-type transistor M7 go low, so that the drains of the P-type transistor M5 and the N-type transistor M8 output a high level, which is buffered by the logic inverters INV3 and INV4 to output a logic high level DATA signal, and the flip-flop unit DFFT is controlled by the UVLO signal.

[0045] When the undervoltage lockout is released (i.e., VS is greater than the reference voltage VREF), the enable control signal SETH and the clock control signal CLK are triggered by the UVLO high-level signal, and the flip-flop unit DFFT outputs the TMDOE logic high-level signal; P-type transistor MP3 <n>When connected to the gate of a P-type transistor such as MP0, forming a current mirror structure, it can enable the P-type transistor MP3... <n>A fixed bias current is generated, which is related to the P-type transistor M3. <n>The source terminals are connected; M3 <n>Drain A <n>Connected, P-type transistor M3 <n>The gate of the P-type transistor MP3 is connected to the TMODE signal to control the P-type transistor. <n>The bias current generated is switched on and off; since TMODE is a high-level signal at this time, it controls M3. <n>The switching transistor will switch the P-type transistor MP3. <n>The pull-up bias current of the transistor is turned off, at which point only one P-type transistor, MP2, is in operation. <n>The pull-up current and N-type transistor MN1 <n>The pull-down current is compared to determine the fuse status; after a delay of t1, the UVLOL signal flips to a high level, at which point the LATCH FUSE module will check the acquired fuse status F0. <n>The signal is locked and output as TRA. <n>The UVLO signal is transferred to the circuit module to be repaired; after a delay of t2 (t2 > t1), the UVLOD signal flips to a high level.

[0046] At this point, the enable signal ENH goes low, and the fuse trimming unit stops working. Subsequently, the high-accuracy blocks 1-n of the circuit to be trimmed receive a set of fuse trimming signals TRA output from the fuse trimming lockout module. <0> , ..., TRA <n>Adjust the corresponding electrical parameters.

[0047] The TRIMMING FUSE LATCH module determines whether a fuse has blown by comparing a reference resistor R0 with the fuse resistance RF. When the TMODE signal is high, i.e., in test mode, only the P-type transistor MP2 is active. <n>Provide pull-up current and N-type transistor MN1 <n>The pull-down current is compared; RF must be greater than R0 for A to be pulled down. <n>Point voltage pulled high level output TRA <n>High-level signal; when the TMODE signal is low, i.e., in normal operating mode, the P-type transistor MP2... <n>P-type transistor MP3 <n>Simultaneously provides pull-up current and N-type transistor MN1 <n>The pull-down current is compared; that is, only RF > 0.5 * R0 is needed to pull down A. <n>Point voltage pulled high level output TRA <n>A high-level signal; therefore, the fuse detection circuit has a stronger pull-up capability in normal working mode compared to test working mode.

[0048] Due to process fluctuations during wafer fabrication, the fuse resistance FU <n>Inaccuracies or deviations in the testing equipment, and other such random factors, can cause the fusing current to be too low during the fuse burning process, resulting in the fuse not burning completely, i.e., the fuse resistance FU after burning out. <n>The values ​​will exhibit randomness. Therefore, we put the system into test mode (TMODE is high) before testing the electrical parameters. In test mode, the P-type transistor MP2... <n>The pull-up current and N-type transistor MN1 <n>The pull-down current is compared, and when the resistance RF of the incompletely blown fuse is very close to the reference resistance R0, the P-type transistor MP2... <n>Pull-up capability and N-type transistor MN1 <n>With similar pull-down capabilities, the P-type transistor MP2 will also be affected. <n>N-type transistor MN1 <n>Drain output A <n>The point voltage is in the intermediate level, the floating state. If the P-type transistor MP2 is in this state... <n>N-type transistor MN1 <n>When the intermediate state of the drain output is identified as high, the output TRA <n>A high level indicates that the fuse is blown, and the electrical parameters are considered to be successfully adjusted. The sample will then be classified as a good product.

[0049] When the sample is powered on again in normal operating mode, i.e., when the TMODE signal is low, the P-type transistor MP2... <n>P-type transistor MP3 <n>The pull-up capability it provides is also much greater than that of the N-type transistor MN1. <n>The pull-down capability, A <n>The circuit will no longer output an intermediate state but a definite high-level state. Therefore, the fuse detection and locking module (TRIMMINGFUSE LATCH) can more accurately identify that the fuse is in a blown state and output the corresponding high-level TRA. <n>This ensures successful adjustment of electrical parameters. Even under the influence of external environmental factors such as packaging stress and temperature, this control scheme prevents the fuse status judgment circuit from reading intermediate states during normal operation, ensuring correct adjustment of the electrical parameters of the module to be adjusted, ensuring consistency of electrical parameters, preventing defective products from being mixed in, and greatly reducing the defect rate.

[0050] In summary, the high anti-interference fuse adjustment judgment and control circuit of the present invention can avoid the drift of electrical parameters caused by packaging. It is often used in integrated circuit application scenarios that require adjustment of high-precision electrical parameters. Compared with traditional fuse adjustment integrated circuits, the present invention adds a test mode unit to the fuse judgment and locking module, which can improve the circuit's recognition rate of fuse status judgment, greatly reduce the probability of misjudgment when the resistance value of the fuse is close to the judgment resistor after it is burned, ensure the consistency of electrical parameters of integrated circuit fuses after adjustment, and improve yield.

[0051] The above description is merely a preferred embodiment of the present invention. The embodiments are not intended to limit the scope of patent protection of the present invention. Therefore, any equivalent structural changes made based on the description and drawings of the present invention should also be included within the scope of protection of the present invention.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A fuse adjustment judgment and control circuit with high anti-interference capability, characterized in that, Includes a power supply voltage detection and comparison module, a fuse detection and locking module, and a high-accuracy block 1 to n for the circuit to be repaired; The power supply voltage detection and comparison module includes a reference current unit IBIAS, a bandgap reference unit BANDGAP, a power supply voltage undervoltage lockout unit UVLO, a power supply voltage detection unit VDDEN, a logic inverter, a two-input logic AND gate AND2, a power supply voltage undervoltage lockout delay unit UVLO DELAY, a power supply detection voltage divider resistor R1, and a power supply detection voltage divider resistor R2. When the external input power supply VDD is powered on, the reference current unit IBIAS generates a bias current IB, which is provided to the bandgap reference unit BANDGAP, the power supply voltage undervoltage lockout unit UVLO, the power supply voltage detection unit VDDEN, and the power supply voltage undervoltage lockout delay unit UVLO DELAY. The bandgap reference unit BANDGAP generates a reference voltage VREF and outputs a VBGOK signal to the power supply voltage detection unit VDDEN. The power supply voltage detection unit VDDEN starts working under the control of the VBGOK enable signal and continuously detects the power supply voltage VDD. It outputs a VDDEN signal to one end of the AND gate AND2. The voltage VDD is compared with the reference voltage VREF by the voltage divider VS of the power supply detection resistors R1 and R2. The system determines whether the voltage value of VDD is high or low and outputs a corresponding undervoltage lockout signal UVLO to the fuse detection lockout module TRIMMINGFUSE LATCH and the power supply voltage undervoltage lockout delay unit UVLO DELAY. The power supply voltage undervoltage lockout delay unit UVLODELAY receives the UVLO signal and outputs a delayed signal UVLOD to a logic inverter, and a delayed signal UVLOL to the fuse detection lockout module TRIMMING FUSE. LATCH; the UVLOD signal is output as a logic inverter to the other end of the AND gate AND2; the AND gate AND2 outputs an enable signal ENH to the TRIMMING FUSE LATCH module by comparing the state of the logic inverted signal and the VDDEN signal, thereby controlling whether the TRIMMING FUSE LATCH module works. The fuse detection and locking module includes a test mode unit and a fuse detection unit (FUSETRIMMING). When the test mode unit enters test mode, it outputs a high level (TMODE). The fuse detection unit (FUSETRIMMING) determines and stores the fuse status, then outputs a signal (TRA). <n> The high-accuracy blocks 1 to n of the subsequent circuit modules to be repaired receive the output signal of the fuse TRIMMING unit to adjust the parameters to be repaired.< / n> 2. The high anti-interference fuse adjustment judgment and control circuit according to claim 1, characterized in that, The test mode unit includes a flip-flop unit DFFT and an N-type transistor M3. <n>P-type transistor M4, P-type transistor M5, P-type transistor M6, N-type transistor M7, N-type transistor M8, P-type transistor MP3 <n> Logic inverters INV3 and INV4;< / n> < / n> Among them, the gate of N-type transistor M7, the source of N-type transistor M8, and the gate of P-type transistor M4 are connected to the ground terminal GND of the flip-flop unit DFFT; P-type transistors M4, M5, M6, and MP3 <n>The source of transistor M7 is connected to the power supply VDD; the drain of N-type transistor M7 is connected to the input V1; the drain of P-type transistor M4, the gate of P-type transistor M5, and the gate of N-type transistor M8 are connected together; the drain of P-type transistor M5, the drain of N-type transistor M8, and the drain of P-type transistor M6 are connected to the input of logic inverter INV3; the output of logic inverter INV3 is connected to the input of logic inverter INV4; the output of logic inverter INV4 is connected to the data terminal of the flip-flop unit DFFT; the CLK and SETH terminals of the flip-flop unit DFFT receive the UVLO signal; the output of the flip-flop unit DFFT is connected to N-type transistor M3. <n>The gate of the P-type transistor MP3 <n>The drain of the N-type transistor M3 <n>Source; the output terminal of the test mode unit is an N-type transistor M3. <n> Drain electrode.< / n> < / n> < / n> < / n> < / n> 3. The high anti-interference fuse adjustment judgment and control circuit according to claim 2, characterized in that, The fuse determination unit (FUSE TRIMMING) includes a fuse state latching unit (LATCH FUSE), P-type transistor M0, P-type transistor MP0, P-type transistor MP1, and P-type transistor MP2. <n>N-type transistor M1, N-type transistor M2, N-type transistor MN1 <n>N-type transistor MN0, logic inverter INV0, logic inverter INV1 <n>Logic inverter INV2 <n>Resistor R0, fuse status latch unit LATCH FUSE and fuse resistor FU <n> ;in,< / n> < / n> < / n> < / n> < / n> The source of P-type transistor M0, the source of P-type transistor MP0, the source of P-type transistor MP1, and the source of P-type transistor MP2. <n>The source of the transistor is connected to the power supply VDD; P-type transistor MP2 <n>The drain and N-type transistor MN1 <n>The drain of the N-type transistor M3 <n>The drain and logic inverter INV1 <n>The input terminals; the drain of P-type transistor M0, the drain and gate of P-type transistor MP0, the gate of P-type transistor MP1, and P-type transistor MP2. <n>The gate of the N-type transistor M1 and the drain of the P-type transistor MP3 are connected. <n>The gate of the P-type transistor M0, the gate of the N-type transistor M1, and the input of the logic inverter INV0 are connected to the ENH terminal; the output of the logic inverter INV0 is connected to the gate of the N-type transistor M2; the drain of the N-type transistor M2 is connected to the gate and drain of the N-type transistor MN0, and the N-type transistor MN1... <n>The gate of the P-type transistor MP1 and the drain of the P-type transistor MP1; resistor R0 is connected between the source of the N-type transistor MN0 and ground GND; fuse resistor FU <n>Connected to N-type transistor MN1 <n>Between the source and ground terminal GND, N-type transistor MN1 <n>The source receives the FPAD signal; logic inverter INV1 <n>The output terminal is connected to the logic inverter INV2. <n>The input terminal of the logic inverter INV2 <n>The output terminal outputs the Fn signal to the fuse state latching unit LATCH FUSE, and the fuse state latching unit LATCH FUSE outputs TRA in conjunction with the UVLOL signal. <n> Signal.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Images