A logic gate circuit, chip and control method based on memristor

Abstract

The application relates to the field of digital integrated circuits, in particular to a logic gate circuit based on a memristor, a chip and a control method. The logic gate circuit comprises a nonvolatile first memristor and a nonvolatile second memristor, the resistance values of the first memristor and the second memristor are programmed before logic operation; when the logic operation is performed, control signals are input to a first input end and a second input end of the logic gate circuit, different resistance states of the first memristor and the second memristor and the combination of different control signals of the first input end and the second input end are used, so that the logic gate circuit has different resistance states; when the input end of the logic gate circuit inputs a working voltage, a corresponding logic operation result is output from an information output end of the logic gate circuit, various logic operation results of OR, AND and tri-state logic are simultaneously realized in the same logic gate circuit, the reliability and flexibility of an electronic device are improved, and the unification of information storage and processing is realized.

Description

Technical Field

[0001] This invention relates to the field of digital integrated circuits, and in particular to a logic gate circuit, chip, and control method based on memristors. Background Technology

[0002] Logic gates are fundamental components in digital integrated circuits. Currently, widely used logic integrated circuits are still interconnected using MOS transistor devices based on CMOS technology. In the pursuit of higher performance computing systems in the future, the limitations of the traditional von Neumann computing architecture and the failure of Moore's Law have created an urgent need to explore new logic gate circuit designs.

[0003] Memristors are simple in structure and compatible with CMOS technology. By combining logic design with the non-volatile characteristics of memristors, memristor-based logic gates offer an opportunity to break Moore's Law in next-generation computers. This design system integrates memory and logic modules into a single unit, solving the "memory wall" and "power wall" problems caused by the physical separation between processing units and memory, and enabling in-memory computing technology for future high-performance systems. Currently, memristor-based logic gates suffer from complex circuit design and high power consumption. Therefore, it is necessary to simplify the design of memristor-based logic gates to achieve high integration, reduced power consumption, and the ability for a single logic gate to support multiple logic operations. Summary of the Invention

[0004] To achieve the above objectives, the present invention provides a logic gate circuit based on a memristor, comprising:

[0005] A first basic component and a second basic component are connected in parallel. The first parallel terminal of the first basic component and the first parallel terminal of the second basic component serve as the information input terminal of the logic gate circuit, and the second parallel terminal of the first basic component and the second parallel terminal of the second basic component serve as the information output terminal of the logic gate circuit.

[0006] The first basic component includes a first memristor and a first transistor, the first memristor and the first transistor are connected in series, and the gate of the first transistor serves as the first input terminal of the logic gate circuit.

[0007] The second basic component includes a second memristor and a second transistor, the second memristor and the second transistor are connected in series, and the gate of the second transistor serves as the second input terminal of the logic gate circuit;

[0008] The first memristor and the second memristor are non-volatile memristors. Before the logic gate circuit performs logic operations, the resistance values ​​of the first memristor and the second memristor are programmed to make the first memristor and the second memristor be in corresponding resistive states. The corresponding resistive states of the first memristor and the second memristor include low-resistance state and high-resistance state.

[0009] When the logic gate circuit performs a logic operation, the first input terminal and the second input terminal of the logic gate circuit receive control signals, and the information output terminal of the logic gate circuit outputs the corresponding logic operation result.

[0010] Optionally, the first memristor is the same as the second memristor, and the first transistor is the same as the second transistor.

[0011] Optionally, the OR logic operation can be implemented when both the first memristor and the second memristor are in a low-resistance state.

[0012] Optionally, when both the first memristor and the second memristor are in a high-impedance state, the AND logic operation can be implemented.

[0013] Optionally, when the first memristor is programmed to be in a high-resistance state and the second memristor is in a low-resistance state, a three-state logic operation can be implemented.

[0014] The present invention also provides a logic gate circuit chip based on memristors, including any of the logic gate circuits described above.

[0015] The present invention also provides a logic gate circuit control method based on memristors, which applies a logic gate circuit based on memristors as described in any one of the above claims, including:

[0016] Program the resistance values ​​of the first and second memristors;

[0017] Input the operating voltage to the information input terminal of the logic gate circuit;

[0018] Input control signals to the first and second input terminals of the logic gate circuit;

[0019] The information output terminal of the logic gate circuit outputs the corresponding logic operation result.

[0020] This invention also provides a logic gate control method based on memristors, which implements OR logic using a logic gate based on memristors as described in any one of the above-mentioned methods, including:

[0021] The first memristor and the second memristor are programmed to be in a low-resistance state;

[0022] Input the operating voltage to the information input terminal of the logic gate circuit;

[0023] A control signal is input to the first input terminal and the second input terminal of the logic gate circuit to control the switching state of the first input terminal and the second input terminal of the logic gate circuit;

[0024] The information output terminal of the logic gate circuit outputs the corresponding logic operation result.

[0025] This invention also provides a logic gate control method based on memristors, which implements AND logic using a logic gate based on memristors as described in any one of the above claims, including:

[0026] The first memristor and the second memristor are programmed to be in a high-resistance state;

[0027] Input the operating voltage to the information input terminal of the logic gate circuit;

[0028] A control signal is input to the first input terminal and the second input terminal of the logic gate circuit to control the switching state of the first input terminal and the second input terminal of the logic gate circuit;

[0029] The information output terminal of the logic gate circuit outputs the corresponding logic operation result.

[0030] This invention also provides a logic gate control method based on memristors, which implements three-state logic using a logic gate based on memristors as described in any one of the above-mentioned methods, including:

[0031] The first memristor is programmed to be in a high-resistance state and the second memristor to be in a low-resistance state;

[0032] Input the operating voltage to the information input terminal of the logic gate circuit;

[0033] A control signal is input to the first input terminal and the second input terminal of the logic gate circuit to control the switching state of the first input terminal and the second input terminal of the logic gate circuit;

[0034] The information output terminal of the logic gate circuit outputs the corresponding logic operation result.

[0035] In summary, the advantages and beneficial effects of the present invention are as follows:

[0036] The first and second memristors are non-volatile memristors. Before the logic gate circuit performs logic operations, the resistance values ​​of the first and second memristors are programmed to make them corresponding low-resistance or high-resistance states. When the logic gate circuit performs logic operations, control signals are input to the first and second input terminals of the logic gate circuit. Through the combination of different resistance states of the first and second memristors and different control signals at the first and second input terminals, the logic gate circuit has different resistance states. When the operating voltage is input to the input terminal of the logic gate circuit, the information output terminal of the logic gate circuit outputs the corresponding logic operation result according to the different resistance states of the logic gate circuit. Multiple logic operation results of OR, AND, and tri-state logic can be realized simultaneously in the same logic gate circuit. Furthermore, the memristor-based logic gate circuit can not only realize the logic processing function of existing gate circuits, but also improve the reliability and flexibility of electronic devices and realize the unification of information storage and processing.

[0037] Meanwhile, the input terminal of the logic gate circuit is a voltage, and the output terminal of the logic gate circuit is also a voltage as the result of the logic operation. There is no time difference in the process of storing and reading information and exchanging data, and there is no signal delay problem. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of a logic gate circuit based on a memristor in this embodiment;

[0039] Figure 2 This is a schematic diagram of a logic gate control method based on memristors according to this embodiment;

[0040] Figure 3 This embodiment implements the truth table for OR logic using a logic gate control method based on memristors.

[0041] Figure 4 This embodiment implements the truth table of AND logic using a logic gate control method based on memristors.

[0042] Figure 5 This embodiment provides a truth table for implementing three-state logic using a logic gate control method based on memristors. Detailed Implementation

[0043] To facilitate understanding by those skilled in the art, the present invention will be further described in detail below with reference to specific embodiments.

[0044] This invention provides a logic gate circuit based on memristors, such as... Figure 1 As shown, it includes:

[0045] A first basic component and a second basic component are connected in parallel. The first parallel terminal of the first basic component and the first parallel terminal of the second basic component serve as the information input terminal S of the logic gate circuit. The second parallel terminal of the first basic component and the second parallel terminal of the second basic component serve as the information output terminal Y of the logic gate circuit.

[0046] The first basic component includes a first memristor R1 and a first transistor B. The first memristor R1 and the first transistor B are connected in series, and the gate of the first transistor B serves as the first input terminal of the logic gate circuit.

[0047] The second basic component includes a second memristor R2 and a second transistor A. The second memristor R2 and the second transistor A are connected in series, and the gate of the second transistor A serves as the second input terminal of the logic gate circuit.

[0048] The first memristor R1 and the second memristor R2 are non-volatile memristors. Before the logic gate circuit performs logic operations, the resistance values ​​of the first memristor R1 and the second memristor R2 are programmed to make the first memristor R1 and the second memristor R2 be in corresponding resistance states. The corresponding resistance states of the first memristor R1 and the second memristor R2 include low resistance state and high resistance state.

[0049] When the logic gate circuit performs a logic operation, the first input terminal and the second input terminal of the logic gate circuit receive control signals, and the information output terminal of the logic gate circuit outputs the corresponding logic operation result.

[0050] Specifically, in this embodiment of the invention, when the first memristor R1 and the second memristor R2 are both programmed to be in a low-resistance state (LRS), the OR logic operation is implemented.

[0051] In this embodiment of the invention, when the first memristor R1 and the second memristor R2 are both programmed to be in a high-resistance state HRS, the AND logic operation is implemented.

[0052] In this embodiment of the invention, when the first memristor R1 is programmed to be in a high-resistance state and the second memristor R2 is in a low-resistance state, a three-state logic operation is achieved.

[0053] Before performing logic operations, the first memristor R1 and the second memristor R2 are programmed to have low or high resistance states. Subsequently, when the logic gate circuit performs logic operations, the different resistance states of the first memristor R1 and the second memristor R2 are combined with the different conduction states of the first transistor B and the second transistor A, so that the logic gate circuit has different resistance states. When the input terminal S of the logic gate circuit is high, the output terminal Y of the logic gate circuit outputs a high-level logic signal or a low-level logic signal according to the resistance state change.

[0054] In this embodiment of the invention, the steps for programming the high and low configurations of the first memristor R1 and the second memristor R2 are as follows: turn on the first transistor B and the second transistor A, and apply voltage to the input terminal S and the output terminal Y of the logic gate circuit, thereby programming the first memristor R1 and the second memristor R2.

[0055] In other embodiments, the steps for programming the high and low configurations of the first memristor and the second memristor are as follows: an external circuit is used to apply voltages to the two ends of the first memristor and the second memristor respectively to program the first memristor and the second memristor.

[0056] This invention also provides a logic gate circuit chip based on memristors, including the above-mentioned logic gate circuit based on memristors.

[0057] This invention also provides a logic gate circuit control method based on memristors, which applies the above-mentioned logic gate circuit based on memristors, such as... Figure 2 As shown, it includes:

[0058] Step S10: Program the resistance values ​​of the first memristor and the second memristor;

[0059] Step S20: Input the operating voltage to the information input terminal of the logic gate circuit;

[0060] Step S30: Input control signals to the first input terminal and the second input terminal of the logic gate circuit;

[0061] In step S40, the information output terminal of the logic gate circuit outputs the corresponding logic operation result.

[0062] Specifically, in step S10, the resistance values ​​of the first memristor R1 and the second memristor R2 are programmed.

[0063] In this embodiment of the invention, the first memristor R1 and the second memristor R2 are non-volatile memristors. Before the logic gate circuit performs logic operations, the resistance values ​​of the first memristor R1 and the second memristor R2 are programmed to make the first memristor R1 and the second memristor R2 be in the corresponding resistive state.

[0064] Execute step S20, input the operating voltage to the information input terminal S of the logic gate circuit.

[0065] In this embodiment of the invention, a high voltage is input to the information input terminal S of the logic gate circuit as the operating voltage.

[0066] Step S30 is executed, and control signals are input to the first input terminal and the second input terminal of the logic gate circuit.

[0067] In this embodiment of the invention, the threshold switching characteristics of the first transistor B and the second transistor A are utilized to set the on or off state of the first transistor B and the second transistor A as a control signal for the memristor-based logic gate circuit.

[0068] In step S40, the information output terminal Y of the logic gate circuit outputs the corresponding logic operation result.

[0069] By combining the different resistance states of the first memristor R1 and the second memristor R2 with the different control signals of the first input terminal and the second input terminal, the logic gate circuit has different resistance states. When the input terminal S of the logic gate circuit is input with a working voltage, the information output terminal Y of the logic gate circuit outputs the corresponding logic operation result according to the different resistance states of the logic gate circuit. At the same time, the input terminal S of the logic gate circuit is a voltage, and the output terminal Y of the logic gate circuit also outputs a voltage as the logic operation result. There is no time difference in the process of storing and reading information and exchanging data, and there is no signal delay problem.

[0070] The logic gate circuit provided by this invention enables the implementation of multiple logic operations such as OR, AND, and tri-state logic within the same logic gate circuit. Furthermore, the memristor-based logic gate circuit not only realizes the logic processing functions of existing gate circuits but also improves the reliability and flexibility of electronic devices, achieving the unification of information storage and processing.

[0071] Example 1:

[0072] This embodiment provides a logic gate control method based on memristors, which implements OR logic using any of the above-described logic gates based on memristors, such as... Figure 3 As shown, it includes:

[0073] Step S11: Program the first memristor R1 and the second memristor R2 to both be in a low-resistance state (LRS).

[0074] Step S21, input a high level to the information input terminal S of the logic gate circuit [1];

[0075] Step S31: Input control signals to the second transistor A and the first transistor B of the logic gate circuit to control the second transistor A and the first transistor B of the logic gate circuit to be turned on [0] or turned off [1].

[0076] In step S41, the information output terminal Y of the logic gate circuit outputs the corresponding logic operation result, that is, outputs a high-level logic signal [1] or a low-level logic signal [0].

[0077] When the second transistor A is turned on [0] and the first transistor B is turned on [0], the logic gate circuit has a low resistance value, and at this time the information output terminal Y of the logic gate circuit outputs a high-level logic signal [1].

[0078] When the second transistor A is turned on [0] and the first transistor B is turned off [1], the logic gate circuit has a high resistance value, and at this time the information output terminal Y of the logic gate circuit outputs a low-level logic signal [0].

[0079] When the second transistor A is off [1] and the first transistor B is on [0], the logic gate circuit has a high resistance value, and at this time the information output terminal Y of the logic gate circuit outputs a low-level logic signal [0].

[0080] When the second transistor A is off[1] and the first transistor B is off[1], the logic gate circuit has a high resistance value, and at this time the information output terminal Y of the logic gate circuit outputs a low-level logic signal[0].

[0081] Example 2:

[0082] This embodiment provides a logic gate control method based on memristors, which implements AND logic using any of the above-described logic gates based on memristors, such as... Figure 4 As shown, it includes:

[0083] Step S12: Program the first memristor R1 and the second memristor R2 to both be in a high-resistivity state (HRS).

[0084] Step S22, input a high level to the information input terminal S of the logic gate circuit [1];

[0085] Step S32: Input control signals to the second transistor A and the first transistor B of the logic gate circuit to control the second transistor A and the first transistor B of the logic gate circuit to be turned on [0] or turned off [1];

[0086] In step S42, the information output terminal Y of the logic gate circuit outputs the corresponding logic operation result, namely a high-level logic signal [1] or a low-level logic signal [0].

[0087] When the second transistor A is off [1] and the first transistor B is off [1], the logic gate circuit has a high resistance value, and at this time the information output terminal Y of the logic gate circuit outputs a low-level logic signal [0].

[0088] When the second transistor A is off[1] and the first transistor B is on[0], the logic gate circuit has a low resistance value, and at this time the information output terminal Y of the logic gate circuit outputs a high-level logic signal[1].

[0089] When the second transistor A is turned on [0] and the first transistor B is turned off [1], the logic gate circuit has a low resistance value, and at this time the information output terminal Y of the logic gate circuit outputs a high-level logic signal [1].

[0090] When the second transistor A is turned on [0] and the first transistor B is turned on [0], the logic gate circuit has a low resistance value, and at this time, the information output terminal Y of the logic gate circuit outputs a high-level logic signal [1].

[0091] Example 3:

[0092] This embodiment provides a logic gate control method based on memristors, which implements three-state logic using any of the aforementioned logic gates based on memristors, such as... Figure 5 As shown, it includes:

[0093] Step S13: Program the first memristor to a high-resistance state HRS and the second memristor to a low-resistance state LRS;

[0094] Step S23, input a high level to the information input terminal S of the logic gate circuit [1];

[0095] Step S33: Input a control signal to the second transistor A and the first transistor B of the logic gate circuit to control the second transistor A and the first transistor B of the logic gate circuit to be turned on [0] or turned off [1];

[0096] In step S43, the information output terminal Y of the logic gate circuit outputs the corresponding logic operation result, namely a high-level logic signal [1] or a low-level logic signal [0].

[0097] When the second transistor A is off [1] and the first transistor B is off [1], the logic gate circuit has a high resistance value, and at this time the information output terminal Y of the logic gate circuit outputs a low-level logic signal [0].

[0098] When the second transistor A is off[1] and the first transistor B is on[0], the logic gate circuit has a high resistance value, and at this time the information output terminal Y of the logic gate circuit outputs a low-level logic signal[1].

[0099] When the second transistor A is turned on [0] and the first transistor B is turned off [1], the logic gate circuit has a low resistance value, and at this time the information output terminal Y of the logic gate circuit outputs a high-level logic signal [1].

[0100] When the second transistor A is turned on [0] and the first transistor B is turned on [0], the logic gate circuit has a low resistance value, and at this time, the information output terminal Y of the logic gate circuit outputs a high-level logic signal [1].

[0101] Finally, it should be noted that any modification or equivalent substitution of some or all of the technical features based on the device structure and the technical solutions of the embodiments of the present invention, without departing from the corresponding technical solutions of the present invention, shall fall within the patent scope of the device structure and the embodiments of the present invention.

Claims

1. A logic gate circuit based on memristors, characterized in that, include: A first basic component and a second basic component are connected in parallel. The first parallel terminal of the first basic component and the first parallel terminal of the second basic component serve as the information input terminal of the logic gate circuit, and the second parallel terminal of the first basic component and the second parallel terminal of the second basic component serve as the information output terminal of the logic gate circuit. The first basic component includes a first memristor and a first transistor, the first memristor and the first transistor are connected in series, and the gate of the first transistor serves as the first input terminal of the logic gate circuit. The second basic component includes a second memristor and a second transistor, the second memristor and the second transistor are connected in series, and the gate of the second transistor serves as the second input terminal of the logic gate circuit; The first memristor and the second memristor are non-volatile memristors. Before the logic gate circuit performs logic operations, the resistance values ​​of the first memristor and the second memristor are programmed to make the first memristor and the second memristor be in corresponding resistive states. The corresponding resistive states of the first memristor and the second memristor include low-resistance state and high-resistance state. The steps for programming the high and low resistance states of the first memristor and the second memristor are as follows: turn on the first transistor and the second transistor, apply voltage to the input and output terminals of the logic gate circuit, or use an external circuit to apply voltage to the two ends of the first memristor and the second memristor respectively to realize the programming of the first memristor and the second memristor. When the logic gate circuit performs a logic operation, the first input terminal and the second input terminal of the logic gate circuit receive control signals, and the information output terminal of the logic gate circuit outputs the corresponding logic operation result.

2. The logic gate circuit based on memristors as described in claim 1, characterized in that, When both the first and second memristors are in a low-resistance state, implement the OR logic operation.

3. A logic gate circuit based on a memristor as described in claim 1, characterized in that, When both the first memristor and the second memristor are in a high-impedance state, implement the AND logic operation.

4. A logic gate circuit based on a memristor as described in claim 1, characterized in that, The program implements three-state logic operations when the first memristor is in a high-resistance state and the second memristor is in a low-resistance state.

5. A logic gate chip based on memristors, characterized in that, The present invention includes a logic gate circuit based on a memristor as described in any one of claims 1 to 4.

6. A logic gate control method based on memristors, characterized in that, A logic gate circuit based on a memristor according to any one of claims 1 to 4, comprising: Program the resistance values ​​of the first and second memristors; Input the operating voltage to the information input terminal of the logic gate circuit; Input control signals to the first and second input terminals of the logic gate circuit; The information output terminal of the logic gate circuit outputs the corresponding logic operation result.

7. A logic gate control method based on memristors, characterized in that, Implementing OR logic using a memristor-based logic gate circuit as described in any one of claims 1 to 4, comprising: The first memristor and the second memristor are programmed to be in a low-resistance state; Input the operating voltage to the information input terminal of the logic gate circuit; A control signal is input to the first input terminal and the second input terminal of the logic gate circuit to control the switching state of the first input terminal and the second input terminal of the logic gate circuit; The information output terminal of the logic gate circuit outputs the corresponding logic operation result.

8. A logic gate control method based on memristors, characterized in that, Implementing AND logic using a memristor-based logic gate circuit according to any one of claims 1 to 4, comprising: The first memristor and the second memristor are programmed to be in a high-resistance state; Input the operating voltage to the information input terminal of the logic gate circuit; A control signal is input to the first input terminal and the second input terminal of the logic gate circuit to control the switching state of the first input terminal and the second input terminal of the logic gate circuit; The information output terminal of the logic gate circuit outputs the corresponding logic operation result.

9. A logic gate circuit control method based on memristors, characterized in that, Implementing tri-state logic using a memristor-based logic gate circuit according to any one of claims 1 to 4, comprising: The first memristor is programmed to be in a high-resistance state and the second memristor to be in a low-resistance state; Input the operating voltage to the information input terminal of the logic gate circuit; A control signal is input to the first input terminal and the second input terminal of the logic gate circuit to control the switching state of the first input terminal and the second input terminal of the logic gate circuit; The information output terminal of the logic gate circuit outputs the corresponding logic operation result.

Images