A method for decoding IRIG-B(AC) code

Abstract

The application discloses a demodulation method of IRIG-B(AC) code and relates to the technical field of time unification. The digital demodulation circuit of the IRIG-B(AC) code adopted by the method comprises an IRIG-B(AC) input interface, a front-stage filter circuit, a high-speed ADC sampling chip and a DSP processor which are sequentially connected. The high-speed ADC sampling chip and the DSP processor both support parallel data communication. The application directly demodulates the IRIG-B(AC) signal in the mode of DSP+ADC, and does not need the step of converting the IRIG-B(AC) alternating current signal into an IRIG-B(DC) direct current signal. Through the mode, the error and the jitter caused in the signal conversion process can be removed, and the demodulation precision of the IRIG-B(AC) alternating current signal can be improved to the nanosecond level.

Description

Technical Field

[0001] This invention relates to the field of time unification technology, and in particular to a demodulation method for IRIG-B(AC) codes. Background Technology

[0002] Traditional IRIG-B (AC) demodulation methods primarily involve FPGA + ARM + filtering circuits + zero-crossing detection circuits to convert the input IRIG-B (AC) signal into an IRIG-B (DC) signal before decoding. This method results in significant jitter in the output IRIG-B (DC) signal, leading to substantial errors in the subsequent demodulation of the 1PPS and time code signals (PPS jitter is on the microsecond level). With technological advancements, higher demodulation accuracy is now required for IRIG-B (AC), and the traditional method of converting AC signals to DC signals is no longer sufficient. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a demodulation method for IRIG-B(AC) code to improve the demodulation accuracy of IRIG-B(AC) AC signals.

[0004] The objective of this invention is achieved through the following technical solution: An IRIG-B(AC) code demodulation method is provided, wherein the IRIG-B(AC) code digital demodulation circuit includes an IRIG-B(AC) input interface, a pre-stage filter circuit, a high-speed ADC sampling chip, and a DSP processor connected in sequence; the high-speed ADC sampling chip and the DSP processor both support parallel data communication. The specific steps of the demodulation method are as follows: S1: Use the pre-stage filter circuit to filter out glitches or abnormal signals from the raw signal of the IRIG-B(AC) input interface; S2: Initialize the DSP processor's timers TIMER1 and TIMER2 and serial port UART1, and initialize the parallel data bus between the high-speed ADC sampling chip and the DSP processor; S3: The high-speed ADC sampling chip is used to sample the IRIG-B(AC) signal, and the DSP processor analyzes it to obtain the symbol information and the TIMER1 timestamp of the symbol start time; S4: Demodulate the TOD time information and second header information according to the IRIG-B code protocol; S5: Use serial port UART1 to output the parsed TOD time information; configure the PWM value according to the TIMER1 timestamp in the second header information, and output 1PPS.

[0005] Furthermore, the DSP processor's chip model is TMS320C6748, and it uses an externally stable 10MHz clock as the system clock.

[0006] Furthermore, the timer TIMER1 is configured with a 100MHz operating clock and also has PWM functionality.

[0007] Furthermore, the timer TIMER2 is configured with a 50MHz operating clock to generate an overflow interrupt every 1µs, triggering the DSP processor to read the sampling data from the high-speed ADC sampling chip.

[0008] Furthermore, the specific process of step S3 is as follows: S31: Continuous analog signals are input to the high-speed ADC sampling chip for sampling, and the sampled values ​​of the high-speed ADC sampling chip are sent to the DSP processor in real time. S32: When an overflow interrupt of TIMER2 is detected, the DSP processor triggers the reading of a sine wave of the current ADC sampling signal to obtain a complete sine wave sampling data; S33: Obtain the TIMER1 timestamp of the positive zero-crossing point of a complete sine wave, and calculate the amplitude of the sine wave based on the subsequent 500 ADC sampling data based on this timestamp. S34: Determine whether it is a large wave or a small wave by the magnitude of the amplitude and record the data to obtain discrete digital information; S35: Use a linked list with an internal window of 15 to store the key data of the sampled wave, and use a sliding window with a window of 10 to distinguish the data as 0, 1 and P symbols, and at the same time record the TIMER1 timestamp of the start time of the current symbol.

[0009] Furthermore, the specific process of obtaining the TIMER1 timestamp of the positive zero-crossing point of a complete sine wave in step S33 is as follows: find the two timestamps before and after the positive zero-crossing point, denoted as t1 and t2; calculate the theoretical zero-crossing point timestamp value y1: y1=(t1+t2) / 2.

[0010] Furthermore, the TIMER1 timestamp of the current symbol start time mentioned in step S35 is then calculated using the following formula: in y i (i=0~9) represents the zero-crossing timestamps of the 10 sine waves in a symbol.

[0011] Further, the specific process of step S4 is as follows: by analyzing the code data linked list, find two consecutive P codes, and the connection position of the two P codes is the 1PPS second position to obtain the second header information; then parse the 99 code elements after the second header to obtain the TOD time information.

[0012] Furthermore, the process of configuring the PWM value based on the TIMER1 timestamp in the second header information and outputting 1PPS in step S5 is as follows: write the start timestamp Y of the second P code among the two consecutive P codes found into the CCRx register of TIMER1 to obtain an accurate 1PPS output signal.

[0013] The beneficial effects of this invention are: This invention uses a DSP+ADC approach to directly demodulate IRIG-B (AC) signals, eliminating the need to convert the IRIG-B (AC) AC signal to an IRIG-B (DC) DC signal. This method removes errors and jitter introduced during signal conversion, improving the demodulation accuracy of IRIG-B (AC) AC signals to the nanosecond level. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the IRIG-B(AC) code digital demodulation circuit used in this invention; Figure 2 A flowchart illustrating the steps of a demodulation method for an IRIG-B(AC) code as provided in one embodiment; Figure 3 A schematic diagram of the IRIG-B(AC) signal's three code elements: 0, 1, and P; Figure 4 This is a flowchart illustrating the amplitude acquisition process of a sinusoidal signal according to the present invention. Figure 5 A schematic diagram showing the positions of two timestamps before and after the positive zero-crossing point of a sine wave; Figure 6 This is a diagram illustrating the position of the code element start timestamp Y within a P code element. Figure 7 The position is 1PPS. Detailed Implementation

[0015] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] See Figures 1-7 The present invention provides a technical solution: A demodulation method for IRIG-B(AC) code employs an IRIG-B(AC) code digital demodulation circuit comprising an IRIG-B(AC) input interface, a pre-stage filter circuit, a high-speed ADC sampling chip, and a DSP processor connected in sequence; both the high-speed ADC sampling chip and the DSP processor support parallel data communication; a schematic diagram of the IRIG-B(AC) code digital demodulation circuit is shown below. Figure 1 As shown.

[0017] like Figure 2 The specific steps of the demodulation method are as follows: S1: The pre-stage filter circuit filters the raw signal of the IRIG-B(AC) input interface to remove glitches or abnormal signals; the filter circuit can protect the downstream modules by filtering the signal to remove glitches or abnormal signals.

[0018] S2: Initialize the DSP processor's timers TIMER1 and TIMER2 and serial port UART1, and initialize the parallel data bus between the high-speed ADC sampling chip and the DSP processor. In this embodiment, the high-speed ADC chip is model AD7641, which supports a sampling rate of 2Msps, a sampling voltage within ±2*Vref, 18-bit high-precision sampling, and parallel data communication. The parallel data bus transmission method can improve data read / write capabilities and reduce data read / write time.

[0019] In this embodiment, the DSP processor chip model is TMS320C6748, which uses an external stable 10MHz as the system clock, providing a precise time base for DSP operation; the DSP runs at a clock rate of 200MHz and supports the parallel data acquisition interface EMIFA.

[0020] The timer TIMER1 is configured with a 100MHz operating clock and PWM functionality. The timer TIMER1 configuration is shown in Table 1 below.

[0021] Timer TIMER2 is configured to operate at a 50MHz clock speed, generating an overflow interrupt every 1µs to trigger the DSP processor to read the sampled data from the high-speed ADC sampling chip, as shown in Table 2 below. Internally, each Cnt count in TIMER2 represents 10ns, providing a precise timestamp for data sampling. Simultaneously, the timer's PWM function outputs a demodulated 1PPS signal.

[0022] The main function of the UART1 serial port is to output the TOD time information after demodulation. Its configuration information is shown in Table 3 below.

[0023] S3: The high-speed ADC sampling chip is used to sample the IRIG-B(AC) signal, and the DSP processor analyzes it to obtain the symbol information and the TIMER1 timestamp of the symbol start time; A complete IRIG-B(AC) consists of 100 symbols, including three types: 0, 1, and P. Each symbol comprises ten sine waves. IRIG-B(AC) symbol 0 contains two large waves and eight small waves, which translates to the digital signal "1100000000". IRIG-B(AC) symbol 1 contains five large waves and five small waves, which translates to the digital signal "1111100000". IRIG-B(AC) symbol P contains eight large waves and two small waves, which translates to the digital signal "1111111100". A schematic diagram of the three symbols is shown below. Figure 3 .

[0024] Furthermore, the specific process of step S3 is as follows: S31: Continuous analog signals are input to the high-speed ADC sampling chip for sampling, and the sampled values ​​of the high-speed ADC sampling chip are sent to the DSP processor in real time. S32: When an overflow interrupt of TIMER2 is detected, the DSP processor triggers the reading of a sine wave of the current ADC sampling signal to obtain a complete sine wave sampling data; S33: Obtain the TIMER1 timestamp of the positive zero-crossing point of a complete sine wave, and calculate the amplitude of the sine wave based on the subsequent 500 ADC sampling data based on this timestamp. S34: Determine whether it is a large wave or a small wave by the magnitude of the amplitude and record the data to obtain discrete digital information; S35: Use a linked list with an internal window of 15 to store the key data of the sampled wave, and use a sliding window with a window of 10 to distinguish the data as 0, 1 and P symbols, and at the same time record the TIMER1 timestamp of the start time of the current symbol.

[0025] Each symbol consists of 10 sine waves. By acquiring the amplitude of a single sine wave, it can be determined whether it is a large wave or a small wave. The acquisition process is as follows: Figure 4 As shown.

[0026] The specific process for obtaining the TIMER1 timestamp of a complete sine wave's positive zero-crossing point as described in step S33 involves finding the two timestamps before and after the positive zero-crossing point, denoted as t1 and t2, as follows: Figure 5As shown; calculate the theoretical zero-crossing timestamp value y1: y1=(t1+t2) / 2. The time difference between t1 and t2 is 1us. By calculating the theoretical zero-crossing timestamp value y1, the theoretical timestamp y1 can be estimated to the middle position, thus reducing the error from 1us to 0.5us.

[0027] If the TIMER1 timestamp of the current symbol start time mentioned in step S35 is valid, then the symbol start timestamp is calculated using the following formula: in y i (i=0~9) represents the zero-crossing timestamps of 10 sine waves in a symbol. By calculating the timestamps of the positive zero-crossings of 10 sine waves in a symbol, the timestamp accuracy can be improved to 50ns. The position of the symbol start timestamp Y in a P symbol is as follows: Figure 6 As shown.

[0028] S4: Demodulate the TOD time information and second header information according to the IRIG-B code protocol; The specific process of step S4 is as follows: Find two consecutive P codes by analyzing the code data linked list, such as... Figure 7 The connection point of the two P codes is the 1PPS second position, from which the second header information is obtained; then the 99 code elements after the second header are analyzed to obtain the TOD time information.

[0029] S5: Use serial port UART1 to output the parsed TOD time information; configure the PWM value according to the TIMER1 timestamp in the second header information, and output 1PPS.

[0030] The process of configuring the PWM value based on the TIMER1 timestamp in the second header information and outputting 1PPS in step S5 is as follows: write the start timestamp Y of the second P code among the two consecutive P codes found into the CCRx register of TIMER1 to obtain an accurate 1PPS output signal.

[0031] Since the operating clock of TIMER1 is 100MHz, each Cnt count is 10ns. A PWM wave with a period of 1 second is required. The reload value needs to be configured as 100000000 (1 second), and its compare register value needs to be configured as 0. When the Cnt count is 0, an interrupt is sent, the output level is high, and the value of the compare register is changed to 100000. When the Cnt count is 100000, an interrupt occurs, the output level is low, and the value of the compare register is configured as 0. Repeating this process will produce a PPS pulse signal with a pulse width of 1 millisecond.

[0032] This invention uses a DSP+ADC approach to directly demodulate IRIG-B (AC) signals, eliminating the need to convert the IRIG-B (AC) AC signal to an IRIG-B (DC) DC signal. This method removes errors and jitter introduced during signal conversion, improving the demodulation accuracy of IRIG-B (AC) AC signals to the nanosecond level.

[0033] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A demodulation method for IRIG-B (AC) codes, characterized in that: The IRIG used The B(AC) code digital demodulation circuit includes an IRIG-B(AC) input interface, a pre-stage filter circuit, a high-speed ADC sampling chip, and a DSP processor connected in sequence; both the high-speed ADC sampling chip and the DSP processor support parallel data communication. The specific steps of the demodulation method are as follows: S1: Use the pre-stage filter circuit to filter out glitches or abnormal signals from the raw signal of the IRIG-B(AC) input interface; S2: Initialize the DSP processor's timers TIMER1 and TIMER2 and serial port UART1, and initialize the parallel data bus between the high-speed ADC sampling chip and the DSP processor; S3: The high-speed ADC sampling chip is used to sample the IRIG-B(AC) signal, and the DSP processor analyzes it to obtain the symbol information and the TIMER1 timestamp of the symbol start time; S4: Demodulate the TOD time information and second header information according to the IRIG-B code protocol; S5: Use serial port UART1 to output the parsed TOD time information; configure the PWM value according to the TIMER1 timestamp in the second header information, and output 1PPS; The specific process of step S3 is as follows: S31: Continuous analog signals are input to the high-speed ADC sampling chip for sampling, and the sampled values ​​of the high-speed ADC sampling chip are sent to the DSP processor in real time. S32: When an overflow interrupt of TIMER2 is detected, the DSP processor triggers the reading of a sine wave of the current ADC sampling signal to obtain a complete sine wave sampling data; S33: Obtain the TIMER1 timestamp of the positive zero-crossing point of a complete sine wave, and calculate the amplitude of the sine wave based on the subsequent 500 ADC sampling data based on this timestamp. S34: Determine whether it is a large wave or a small wave by the magnitude of the amplitude and record the data to obtain discrete digital information; S35: Use a linked list with an internal window of 15 to store the key data of the sampled wave, and use a sliding window with a window of 10 to distinguish the data as 0\1\P symbols, and at the same time record the TIMER1 timestamp of the start time of the current symbol. The specific process of obtaining the TIMER1 timestamp of the positive zero-crossing point of a complete sine wave as described in step S33 is as follows: find the two timestamps before and after the positive zero-crossing point of the sine wave, denoted as t1 and t2; calculate the theoretical zero-crossing point timestamp value y1 of the sine wave: y1=(t1+t2) / 2; If the TIMER1 timestamp of the current symbol start time mentioned in step S35 is valid, then the symbol start timestamp is calculated using the following formula: ； Where y i (i=0~9) represents the zero-crossing timestamps of the 10 sine waves in a symbol.

2. The demodulation method for an IRIG-B (AC) code according to claim 1, characterized in that: The DSP processor is a TMS320C6748 chip, which uses an externally stable 10MHz clock as the system clock.

3. The demodulation method for an IRIG-B (AC) code according to claim 1, characterized in that: The timer TIMER1 is configured to operate at a 100MHz clock speed and also has PWM functionality.

4. The demodulation method for an IRIG-B(AC) code according to claim 1, characterized in that: The timer TIMER2 is configured to operate at a 50MHz clock speed and is used to generate an overflow interrupt every 1µs to trigger the DSP processor to read the sampling data from the high-speed ADC sampling chip.

5. The demodulation method for an IRIG-B(AC) code according to claim 1, characterized in that: The specific process of step S4 is as follows: by analyzing the code data linked list, find two consecutive P codes, and the connection position of the two P codes is the 1PPS second position to obtain the second header information; then parse the 99 code elements after the second header to obtain the TOD time information.

6. The demodulation method for an IRIG-B(AC) code according to claim 5, characterized in that: The process of configuring the PWM value based on the TIMER1 timestamp in the second header information and outputting 1PPS in step S5 is as follows: write the start timestamp Y of the second P code among the two consecutive P codes found into the CCRx register of TIMER1 to obtain an accurate 1PPS output signal.

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