Dual-coupled polar codes
Patent Information
- Application Number
- CN202311493522.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-09
- Publication Date
- 2026-09-01
- Estimated Expiration
- 2043-11-09
AI Technical Summary
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Figure CN117478152B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to channel coding technology, and more particularly to polar codes, specifically a dual-coupled polar code that can optimize the error correction performance of CA-SCL under high signal-to-noise ratio. Background Technology
[0002] Channel coding is a crucial component of modern communication systems. It enhances system reliability by adding redundant bits to resist interference in the transmission channel. Polar codes have been chosen as one of the channel coding methods for 5G systems due to their superior decoding performance and lower decoding complexity. While polar codes can reach the Shannon limit with infinitely increasing code length, the code length cannot be increased indefinitely in real-world transmission systems. Therefore, when polar codes have a medium to short code length, their decoding performance is inferior to channel coding methods such as LDPC codes.
[0003] While Serial Cancellation (SC) decoding has relatively low decoding complexity, its error correction performance is poor. To improve the decoding performance of SC decoding, Serial Cancellation List (SCL) decoding was proposed. This method reduces the probability of the correct path being eliminated by retaining both 0 and 1 information bits. CA-SCL decoding improves the performance of traditional SCL decoding by adding a CRC check bit to the end of the information bit sequence and selecting the optimal path information.
[0004] To further improve decoding performance, an inter-frame polar code encoding / decoding algorithm was proposed. This algorithm corrects frames that fail the CRC test on the first decoding attempt and then re-decodes them, thereby further enhancing decoding performance. In each frame's coupled coding block, which is retransmitted in the next frame, the coupled coding block of the correctly decoded frame can be used to correct the coupled coding block of the erroneous frame. The corrected coupled coding block is then treated as a frozen bit and re-decoded using CA-SCL, increasing the probability that the erroneous frame will pass the CRC test on the second decoding attempt. Therefore, the decoding performance of the polar code is significantly improved. However, if consecutive frames fail to decode, re-decoding is not possible.
[0005] To further improve decoding performance, this invention proposes a novel coupled polar code structure, which differs from inter-frame polar codes in three ways. First, inter-frame polar codes have two coupled coding blocks per frame, while this invention proposes multiple coupled coding blocks per frame. Second, inter-frame polar codes have only one coupling process, while this invention performs two coupling processes. Third, inter-frame polar codes perform one error correction decoding, while the algorithm proposed in this invention involves multiple attempts at error correction decoding. Summary of the Invention
[0006] The main objective of this invention is to improve the performance of CA-SCL decoding. This invention proposes a dual-coupled polar code structure and a corresponding decoding algorithm. Frames are correlated through coupled coding blocks, and frames that fail the first CA-SCL decoding undergo cyclic error correction and re-decoding. First, a cyclic error correction step is performed, traversing all coupled decoding blocks that failed to correct errors, and attempting to correct each uncorrected coupled coding block twice. After one traversal, if there are still coupled decoding blocks that can be corrected, the traversal is repeated; otherwise, the decoding process continues. Coupled coding blocks containing successfully corrected errors are used as dynamically frozen bits for re-CA-SCL decoding. If all erroneous frames fail CRC checks or all erroneous frames pass CRC checks, decoding is terminated; otherwise, cyclic error correction and re-decoding are repeated. By continuously performing cyclic error correction and re-decoding on erroneous frames, the decoding performance of the polar code is improved.
[0007] To achieve the above objectives, the present invention is mainly divided into the following four parts:
[0008] 1. Sub-channels are divided into good channels and bad channels according to reliability from high to low. Bad channels are used to transmit frozen bits. Good channels are further divided into two parts: high-reliability sub-channels and relatively reliable sub-channels. The information bits in a frame are divided into two parts: one part is transmitted through the high-reliability sub-channel and does not participate in coupling coding; the other part is coupled and then transmitted through the relatively reliable sub-channel. A total of F frames of polar codes need to be transmitted. Each frame of polar code has M coupled coding blocks, and each coupled coding block contains I bits. This represents the i-th bit in the m-th coupled coded block of the f-th frame.
[0009] 2. Perform two coupled encodings on each frame using parity check codes:
[0010] The first coupling coding determines the bits in the first M-1 coupled coding blocks of frame F by the parity sum of the corresponding bits in the corresponding coupled coding blocks of the first F-1 frames, using the following formula:
[0011]
[0012] The second coupling coding is determined by the parity check sum of the corresponding bits in the Mth coupled coding block from the first frame to the Fth frame, based on the parity check sum of the Mith coupled coding block (i = 1, 2, L, M-1) of the ith frame. The specific formula is as follows:
[0013]
[0014] The reason for ((F-M+f+l-1)modF)+1 is that each F frame constitutes a cyclic frame group. For example, the M-1 frames before the first frame are the F frame, the F-1 frame, L, and the F-M+1 frame. That is, the bits in the Mth coupled coded block of the first frame are determined by the parity sum of the corresponding bits of the (M-1)th coupled coded block of the F frame, the (M-2)th coupled coded block of the F-1 frame, L, and the first coupled coded block of the F-M+1 frame.
[0015] 3. After each frame of the coupled coding is polar-coded and BPSK modulated, the uncoupled information bits of each frame are transmitted through a high-reliability sub-channel, and the coupled information bits of each frame are transmitted through a relatively reliable sub-channel of the polar code. After transmission through the channels, the frames reach the receiving end, which demodulates them and then begins decoding frame by frame. If each frame passes the CRC check, the decoding is successful and ends. If one or more frames fail the CRC check, the frames that fail the decoding are continuously cyclically corrected and re-decoded until all failed frames are successfully decoded or the frames that fail the decoding cannot be successfully decoded again.
[0016] 4. The single-cycle error correction and decoding process mainly includes two steps: a cycle error correction step for coupled decoded blocks that failed to be corrected, and a second CA-SCL decoding step for frames containing corrected coupled decoded blocks. First, the cycle error correction step iterates through each coupled decoded block that failed to be corrected and attempts to correct it twice. If the coupled decoded block is successfully corrected, it is considered a successfully corrected coupled decoded block and participates in the error correction of other coupled decoded blocks. After one iteration, it is determined whether there are other coupled decoded blocks that failed to be corrected. If so, the cycle error correction step is performed again; otherwise, the decoding step is repeated. The two attempts at error correction are as follows:
[0017] First error correction attempt: If a coupled decoded block in a frame fails to correct an error, but the corresponding coupled decoded blocks in other frames succeed in correction, then the error correction of that coupled decoded block is successful. Specifically, if the j-th coupled decoded block in the i-th frame fails to correct an error, but the j-th coupled decoded block in another frame succeeds in correction, then the j-th coupled decoded block in the i-th frame can be successfully corrected. The specific formula is:
[0018]
[0019] Second error correction attempt: If a coupled decoded block in a certain frame fails to correct an error, but the corresponding coupled decoded blocks in the adjacent M frames succeed in correction, then the coupled decoded block fails to correct an error. Specifically, if the j-th coupled decoded block in the i-th frame fails to correct an error, but all l coupled decoded blocks in the mod(F-j+i+l-1,F)+1-th frame succeed in correction, where l = 1, 2, Lj-1, j+1, LM, then the j-th coupled decoded block in the i-th frame can be successfully corrected. The specific formula is:
[0020]
[0021] Bits from successfully corrected coupled decoded blocks are used as dynamically frozen bits, and CA-SCL decoding is performed on erroneous frames containing successfully corrected coupled decoded blocks. Decoding stops if all erroneous frames pass CRC check or all erroneous frames fail CRC check. Otherwise, the correction and decoding process is repeated.
[0022] By continuously attempting to correct the error in the coupled decoding block, and then using the bits in the corrected coupled decoding block as dynamic frozen bits, the CA-SCL decoding of the erroneous frame is attempted again, thereby improving the decoding performance of traditional CA-SCL decoding. Attached Figure Description
[0023] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the following figures are provided for illustration:
[0024] Figure 1 The flowchart below shows the encoding and decoding process of the dual-coupled polar code proposed in this invention.
[0025] Figure 2 This is a schematic diagram of the single-pass error correction process proposed in this invention.
[0026] Figure 3 This is a schematic diagram of the first coupling coding diagram proposed in this invention.
[0027] Figure 4 This is a schematic diagram of the second coupling coding diagram proposed in this invention. Detailed Implementation
[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. The specific implementation steps of the encoding and decoding method of the dual-coupled polar code will be given below. The polar code length N is 1024, the code rate R is 0.5, the list length L is 16, and the CRC check bit length is 8 bits. In each frame, the number of coupled decoding blocks M is 4, the number of coupled frames F is 8, and the number of bits I in each coupled decoding block is 8 bits. The modulation method is BPSK, and transmission is performed through an AWGN channel.
[0029] The first step is to sort the sub-channels of the polar code in ascending order based on channel reliability, dividing them into two parts. The "good channel" consists of the last K' = N×R + I + I×(M-1) / F = 1024×1 / 2 + 4 + 4×8 / 8 = 520 highly reliable channels, while the ring channel consists of the first N-K' = 1024-520 = 504 low-reliability channels. The "good channel" is further divided into two parts: one part consists of the first M×I = 4×8 = 32 relatively reliable sub-channels, and the other part consists of K'-M×I = 520-32 = 498 highly reliable sub-channels. Similarly, the information bits are also divided into two parts: one part consists of information bits directly from the highly reliable channels that do not require coupling, and the other part consists of information bits transmitted through the more reliable channels that require coupling and coding.
[0030] The second step involves performing two coupling codes on the M=4 coupled coding blocks of frame F=8: The first coupling code determines the bits of the first M-1=3 coupled coding blocks of frame F=8 by the parity sum of the corresponding bits of the corresponding coding blocks in the first F-1=7 frames. The bits of the first coupled coding block of frame 8 are determined by the parity sum of the corresponding bits of the first coupled coding blocks from frame 1 to frame 8, and the bits of the second coupled coding block of frame 8 are determined by the parity sum of the corresponding bits of the second coupled coding blocks from frame 1 to frame 8, until the bits of the third coupled coding block of frame 8 are calculated. The second coupling code performs coupling coding on the bits of the last coding block of each frame. The M=4th coupled coding block of each frame is determined by the parity check sum of the previous 3 frames. For example, the bits of the 4th coupled coding block of the 1st frame are obtained by parity check of the corresponding bits of the 3rd coupled coding block of the 8th frame, the 2nd coupled coding block of the 7th frame, and the 1st coupled coding block of the 6th frame, and so on, until the bits of the 4th coupled coding block of the 8th frame are calculated.
[0031] The third step is to add a CRC to each frame and then perform polar coding. The polar coding method can be represented as follows: in, It is a generating matrix of dimension N. This is a generator matrix with a code length of N=2. The generated information bit sequence is modulated using BPSK to obtain the information sequence to be transmitted, and then sent into the AWGN channel for transmission.
[0032] The fourth step, at the receiving end, involves demodulating each received frame before it enters the decoding module. The decoding module first performs CA-SCL decoding on the received frames. If each frame passes the CRC check, the decoding is successful, and the decoding process ends. If one or more frames fail the CRC check, these failed frames undergo multiple rounds of error correction and re-decoding until all decoding is successful or it becomes impossible to successfully decode the failed frames again.
[0033] Step 5: If one or more frames fail the CRC check, multiple cyclic error correction and re-decoding steps are performed. Each cyclic error correction process includes two steps: cyclic error correction and re-decoding. First, the coupled decoded blocks that failed to be corrected are traversed, and two error correction attempts are made. If the correction is successful, it is treated as a successfully corrected coupled decoded block and used in other failed coupled decoded blocks. When all failed coupled decoded blocks have been traversed, if there are still correctable coupled decoded blocks, the traversal of failed coupled decoded blocks is repeated; otherwise, it means that all correctable coupled decoded blocks have been corrected, and the re-decoding step begins. For each frame containing a successfully corrected coupled decoded block, CA-SCL decoding is performed again until all decoding is successful or the failed frames cannot be successfully decoded again.
[0034] For example, if decoding of the first and second frames fails, firstly, the coupled decoded blocks of the first and second frames are traversed: the first coupled decoded block of the first frame does not satisfy the two-error-correction-attempt formula, therefore its error correction fails. Similarly, the fourth coupled decoded block of the first frame satisfies the second error-correction-attempt formula, therefore its error correction is successful, and it is used as a successfully corrected coupled decoded block in the other coupled decoded blocks. Then, the first coupled decoded block of the second frame satisfies the second error-correction-attempt formula, therefore its error correction is successful, and so on. The fourth coupled decoded block of the second frame satisfies the first error-correction-attempt formula, therefore its error correction is successful. After one traversal, it is necessary to determine if there are other coupled decoded blocks that can be successfully corrected: some coupled decoded blocks that failed to correct can be corrected by successfully corrected coupled decoded blocks, therefore, a second traversal of the coupled decoded blocks is performed. This process continues until all coupled decoded blocks that failed to correct are successfully corrected.
[0035] First, the bits in the successfully error-corrected coupled decoding block are used as dynamic freeze bits. Then, CA-SCL decoding is performed on the failed frame containing the successfully error-corrected coupled decoding block: the bits in the successfully error-corrected coupled decoding blocks of the first and second frames are used as dynamic freeze bits, and CA-SCL decoding is performed again on the first and second frames. If both the first and second frames fail to decode, decoding ends and is declared a failure; if both the first and second frames succeed, decoding ends and is declared a success. If the first or second frame passes the CRC check, but the other frame fails the CRC check, then another cyclic error correction and decoding step is performed.
[0036] If the first frame passes the CRC check but the second frame fails, the following steps are taken: First, the coupled decoding blocks of the second frame are traversed. The first coupled decoding block of the second frame satisfies the first error correction attempt formula, therefore the first coupled decoding block of the first frame has successfully corrected the error. Similarly, the fourth coupled decoding block of the second frame satisfies the first error correction attempt formula, therefore the fourth coupled decoding block of the second frame has successfully corrected the error. Since all coupled decoding blocks have successfully corrected the error, the bits in the successfully corrected coupled decoding blocks of the second frame are used as dynamically frozen bits for another CA-SCL decoding of the second frame. If the second frame decoding is successful, the decoding ends, and the decoding is declared successful. If the second frame fails the CRC check, the decoding ends, and the decoding is declared failed.
Claims
1. Double coupled polar code, characterized in that, For a set of F frames, two parity checks are used for two encodings. After the F-th frame is coupled and checked to the previous F-1 frames, it is coupled and coded to the adjacent frames. Finally, during decoding, the successfully decoded frames and the parity check codes are used to perform cyclic error correction and decoding again on the undecoded frames to improve decoding performance. The detailed steps are as follows: Step 1: Based on channel reliability, the sub-channels of the polar code are arranged in ascending order and divided into good channels and bad channels. Bad channels are used to transmit frozen bits, and good channels are further divided into high-reliability sub-channels and relatively reliable sub-channels. Furthermore, the information bits of each frame are divided into two parts: the first part is transmitted through the high-reliability sub-channel and does not participate in coupling coding. The second part is transmitted through a more reliable sub-channel after being coupled and encoded; then the information bits that need to be coupled and transmitted in the second part are divided into M coupled coding blocks, each block containing I bits; Step 2: Perform two coupling codes on the M coupled coding blocks of frame F using parity check codes: The first coupling code determines the bits of the first M-1 coupled coding blocks of frame F by the parity check sum of the corresponding bits of the corresponding coding blocks of the first F-1 frames, using the following formula: wherein u j (i,f) denotes the jth bit of the ith coupled coding block of the fth frame; The second coupling coding is performed on frames 1 to F. The bits in the Mth coupled coding block of each frame are determined by the parity check sum of the preceding M-1 frames, and the specific formula is as follows: The reason for ((F-M+f+l-1)modF)+1 is that: every M frames constitute a set of cyclic frames; the m-th coupled coding block of the f-th frame is composed of the first coupled coding block of the ((F-M+f)modF)+1-th frame, the second coupled coding block of the ((F-M+f+1)modF)+1-th frame, ..., the M-th coupled coding block of the ((F+f+1)modF)+1-th frame; specifically, if 8 frames are transmitted, and the number of coupled coding blocks in each frame is 4, then the bits of the fourth coupled coding block of the first frame are determined by the parity check sum of the bits corresponding to the bits of the first coupled coding block of the sixth frame, the second coupled coding block of the seventh frame, and the third coupled coding block of the eighth frame. Step 3: After adding CRC check code, polar coding and modulation to each frame after coupling coding, transmit the uncoupled encoded information bits of each frame through a high-reliability sub-channel, and transmit the coupled encoded information bits of each frame through a more reliable sub-channel of polar coding; after transmission through the channel, the information reaches the receiving end, and the receiving end demodulates and begins decoding frame by frame. Step four: The decoding module performs CA-SCL decoding on the received frames. If each frame passes the CRC check, the decoding is successful and the decoding ends. If one or more frames fail the CRC check, the decoding module performs cyclic error correction and decodes the failed frames again.
2. The dual-coupled polar code of claim 1, wherein, The specific steps for performing multiple cyclic error corrections and re-decodings on frames that fail to be decoded are as follows: The first step is to perform two error correction attempts on each coupled decoded block of all failed decoding frames according to the parity check formula of the two coupled codes. If the error correction is successful, it is used as a successfully corrected coupled decoded block to participate in the error correction of other failed coupled decoded blocks. If no coupled decoded block error correction attempt is successful or every coupled decoded block of all failed decoding frames is successfully corrected, then exit this step; otherwise, continue to execute this step in a loop. The second step is to perform CA-SCL decoding on frames containing successfully coupled decoding blocks that attempted error correction in the first step. The third step is to exit the loop error correction and decoding if all failed frames pass the CRC check or if no frame passes the CRC check in the second step, and end the decoding process. Otherwise, the first and second steps are executed in a loop.
Citation Information
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