A phase detection compensation method based on FPGA control in an optical fiber phase-stable transmission system

Abstract

The application discloses a phase detection compensation method based on FPGA control in an optical fiber phase-stable transmission system, which adopts a phase detection compensation module to receive a clock signal of a basic atomic clock and an electrical signal obtained after PD frequency mixing from a link of external devices; based on a local signal, two-way digital signals containing complete phase information obtained through ADC sampling are subjected to frequency reduction mixing; phase noise introduced in the link of external devices is compensated, and a frequency signal phase-locked to a signal at the end is recovered. The application processes near-end and far-end digital signals obtained through ADC sampling in an FPGA and synthesizes phase errors, so that the difference between the synthesized time delay fluctuation and the original time delay fluctuation is about 2 orders of magnitude lower than the original fluctuation value. Based on the detected synthesized time delay (phase) fluctuation, a pre-compensation amount of a phase-stable module is obtained through PID calculation, and when the system is continuously stabilized, the phase-stable precision and the compensation precision will be continuously improved.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing technology, and specifically relates to a phase detection and compensation method based on FPGA control in an optical fiber phase-stable transmission system. Background Technology

[0002] Digital signal processing boasts numerous advantages, including low cost, high transmission speed, flexible and accurate data conversion, small device size, and strong anti-interference capabilities. FPGA (FPGA Programmable Array) is a programmable logic array whose basic structure includes programmable input / output units, configurable logic blocks, a digital clock management module, embedded block RAM, routing resources, embedded dedicated hard cores, and low-level embedded functional units. Due to its abundant routing resources, reprogrammability, high integration, and relatively low investment, FPGA has been widely used in digital circuit design. FPGA can achieve highly efficient logic operations. Furthermore, FPGA typically possesses parallel computing capabilities, enabling the processing of large amounts of data.

[0003] Phase-stable transmission technology is a technique used to transmit highly stable signals, widely applied in scientific research, communications, measurement, and precision positioning. Its background can be traced back to the ever-increasing demand for high-precision frequency and phase transmission. In traditional communications, signal transmission based on cables and microwaves suffers from stability and noise issues. With the development of modern scientific research, wireless communication, and precision measurement, the requirements for frequency and phase transmission have become more stringent. Against this backdrop, phase-stable transmission technology emerged.

[0004] Fiber optic phase-stabilized transmission technology has a wide range of applications, including communications, precision measurement, positioning and navigation, laser interferometers, and atomic clocks. In communications, it provides high-speed, high-quality signal transmission and supports high-capacity data communication and network connectivity. In precision positioning and navigation systems, it provides highly stable clock and reference signals for high-precision position measurement and navigation. Currently, most phase-stabilization schemes are based on analog signal processing, and there is no mature FPGA-based digital signal processing solution to improve phase-stabilization accuracy and transmission stability. Therefore, developing an FPGA-controlled digital signal processing phase detection and compensation method is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The technical problem this invention aims to solve is to address the shortcomings of the existing technology by providing a phase detection and compensation method based on FPGA control in a fiber optic phase-stabilized transmission system. This method processes the near-end and far-end digital signals obtained through ADC sampling within the FPGA and integrates them with the phase error. The integrated delay fluctuation and its difference from the original delay fluctuation are approximately two orders of magnitude lower than the original fluctuation value. Based on the detected and integrated delay (phase) fluctuation, the pre-compensation amount for the phase-stabilized module is calculated using PID control. As the system gradually stabilizes, the phase stabilization accuracy and compensation accuracy will continuously improve.

[0006] To achieve the above-mentioned technical objectives, the technical solution adopted by the present invention is as follows:

[0007] A phase detection and compensation method based on FPGA control is proposed in a fiber optic phase-stable transmission system. The method uses a phase detection and compensation module to receive, down-mix, and compensate the signal from external devices, and then apply the compensation to the external devices to achieve phase detection and compensation.

[0008] The phase detection and compensation module includes a signal receiving module, a down-converting and mixing module, and a phase compensation module connected in sequence based on an FPGA. The signal input terminal of the signal receiving module includes a radio frequency interface and two ADC inputs. The radio frequency interface is connected to a basic atomic clock to receive the clock signal from the basic atomic clock. The two ADC inputs are connected to the output terminal of the external device link to receive the electrical signal obtained from the external device link after being beat by a PD. The down-converting and mixing module performs digital mixing, down-converting, filtering, downsampling / averaging noise reduction, amplitude detection and normalization, and mixing / low-pass processing on two digital signals containing complete phase information obtained by ADC sampling based on the local oscillator signal. The phase compensation module receives the two output signals from the down-converting and mixing module and compensates for the phase noise introduced in the external device link through the FPGA algorithm, recovering the frequency signal whose phase is locked to the local signal and transmitting it to the input terminal of the external device link through a DAC.

[0009] To optimize the above technical solution, the specific measures also include:

[0010] The external devices on the aforementioned external device link include a local temperature-controlled voltage-controlled crystal oscillator (OCXO), a combiner, an optical radio frequency (RF) transmitter module, a fiber optic coupler, a circulator, an optical fiber transmission remote module, and two photodetectors (PDs). The OCXO receives the signal transmitted from the DAC and finely controls it to obtain an RF signal with phase pre-compensation. The combiner sends the original RF signal from the atomic clock and the RF signal with phase pre-compensation obtained after fine control by the OCXO together to the optical radio frequency transmitter module. Then, through the fiber optic coupler, one branch of the optical signal is sent to one PD, and the other branch is sent to port 1 of the circulator and transmitted to the optical fiber transmission remote module via port 2 through a long-distance fiber optic link. After that, the optical fiber transmission remote module returns part of the optical signal to the circulator through the long-distance fiber optic link. The optical signal returned by the optical fiber transmission remote module is sent to another PD through port 3 of the circulator. The electrical signals obtained by the two PDs at their respective beat frequencies are amplified and filtered, and then sampled by an ADC into a digital signal with a frequency of 100MHz containing complete phase information, which is then sent to the phase detection and compensation module.

[0011] The aforementioned signal receiving module includes a code conversion submodule, a data buffer submodule, and a DDS local oscillator signal submodule. The two code conversion submodules and the two data buffer submodules perform code conversion processing and data buffering on the two digital signals from the ADC. At the same time, the DDS local oscillator signal submodule receives the clock signal generated by the basic atomic clock after passing through the phase-locked loop, uses it as the reference clock and system clock for the internal signal processing of the FPGA, and generates a local oscillator signal for digital down-conversion, digital mixing, and phase detection.

[0012] The aforementioned code conversion submodule is used to descramble the ADC output signal based on the low-bit code stream, and at the same time complete the conversion from offset encoding to binary two's complement encoding to obtain signed numbers for digital signal processing.

[0013] The aforementioned data buffer submodule sends the sampled signal after code transformation into a high-speed data buffer to obtain multiple sets of parallel sampled data. At the same time, the local oscillator signal generated by the DDS local oscillator signal submodule is also sent into a buffer module of the same depth.

[0014] The aforementioned down-conversion mixing module includes a digital mixing / down-conversion submodule, an FIR low-pass filter submodule, a downsampling / averaging noise reduction submodule, an amplitude detection and normalization submodule, and a mixing / low-pass filter submodule. The digital mixing / down-conversion submodule mixes the two signals processed by the signal receiving module with the local oscillator signal from the DSS local oscillator signal module, and then processes them through the FIR low-pass filter submodule, the downsampling / averaging noise reduction submodule, and the amplitude detection and normalization submodule to obtain the two down-conversion signals. The mixing / low-pass filter submodule mixes the two down-conversion signals with the local oscillator signal generated by the DDS local oscillator signal module, and after low-pass filtering, detects the local phase difference and far-end phase difference of the RF signal.

[0015] The aforementioned FIR low-pass filter submodule uses a 16th-order FIR digital low-pass Equiripple filter design to filter the mixing signal.

[0016] The downsampling / averaging noise reduction submodule described above performs sample averaging on the high-speed sampled signal to achieve downsampling.

[0017] The aforementioned phase compensation module includes a phase error calculation submodule and a phase compensation synthesis submodule. The phase error calculation submodule obtains the phase difference between the local and remote ends through table lookup transformation, and the sum / difference can be synthesized to obtain the system phase difference. In the phase compensation synthesis submodule, the control compensation signal is obtained through PID algorithm and output to the DAC to be converted into an analog signal. The resulting RF signal with phase pre-compensation is obtained after fine control of the OCXO.

[0018] The present invention has the following beneficial effects:

[0019] This invention's phase detection and compensation method is based on FPGA control and processing. The digital signals from the near and far ends, sampled by an ADC, are processed and their phase errors are synthesized within the FPGA. This results in a time delay fluctuation that is approximately two orders of magnitude lower than the original fluctuation. Based on the detected and synthesized time delay (phase) fluctuation, a pre-compensation amount for the phase stabilization module is calculated using PID control. This pre-compensation amount is applied to the external DAC, which converts the signal into an analog signal. Fine control of the OCXO yields a radio frequency signal with phase pre-compensation, which is injected into the optical fiber and sent to the far-end module for phase compensation. As the system stabilizes, the phase stabilization and compensation accuracy continuously improve. Simultaneously, frequency synthesis reduces the signal frequency entering the FPGA to 10MHz, meeting the FPGA's processing requirements. The FPGA's digital processing avoids phase lock-up caused by phase jumps exceeding one cycle during active compensation. After long-term testing, the frequency stability of the optical fiber phase-stabilized transmission device can reach 10... -17 / 10 4 s. Attached Figure Description

[0020] Figure 1 This is a schematic diagram illustrating the principle of the phase detection and compensation method based on FPGA control in the optical fiber phase-stable transmission device of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0022] Although the steps in this invention are arranged by reference numerals, this is not intended to limit the order of the steps. Unless the order of the steps is explicitly stated or the execution of a step requires other steps as a basis, the relative order of the steps can be adjusted. It is understood that the term "and / or" as used herein refers to and covers any and all possible combinations of one or more of the associated listed items.

[0023] like Figure 1 As shown, this invention discloses a phase detection and compensation method based on FPGA control in a fiber optic phase-stable transmission system. The method employs a phase detection and compensation module to receive, down-mix, and compensate signals from external devices, then applies the compensation to the external devices to achieve phase detection and compensation. The phase detection and compensation module includes a signal receiving module, a down-mixing module, and a phase compensation module connected sequentially based on an FPGA. The signal input of the signal receiving module includes a radio frequency (RF) interface and two ADC inputs. The RF interface is connected to a basic atomic clock to receive its clock signal, and the two ADC inputs are connected to the output of the external device link to receive digital signals containing complete phase information from the external device link. The down-mixing module simultaneously performs digital mixing, down-mixing, filtering, downsampling / averaging noise reduction, amplitude detection and normalization, and mixing / low-pass processing on the two digital signals input from the two ADC inputs based on the local oscillator signal. The phase compensation module receives the two output signals from the down-mixing module and compensates for phase noise introduced into the external device link using an FPGA algorithm, recovering a frequency signal whose phase is locked to the local signal and transmitting it to the input of the external device link via a DAC.

[0024] In this embodiment, signal reception processing, down-conversion mixing, and phase compensation are performed on the signal input from external devices. This process is then applied to the external devices to achieve phase detection and compensation functions. The signal reception module, down-conversion mixing module, and phase compensation module are all implemented within the FPGA. The signal to be processed is input via an RF interface and an ADC. The signal processed by this method is connected to external devices such as a DAC and an OCXO. Furthermore, it is connected via optical fiber to an optical fiber coupler, a circulator, and a remote optical fiber transmission module. The signal reception module receives signals returned from the optical fiber coupler and the remote optical fiber transmission module, performs frequency beat at a PD, and then samples them via the ADC. The system receives a 100MHz digital signal containing complete phase information and a 100MHz clock signal from a basic atomic clock to generate a local oscillator signal for digital down-conversion, digital mixing, and phase detection. The down-conversion and mixing module simultaneously performs digital mixing down-conversion, filtering, downsampling, amplitude detection and normalization, and mixing / low-pass processing on both signals. The phase compensation module uses FPGA algorithms to compensate for the phase noise introduced into the optical fiber transmission system, recovering the frequency signal whose phase is locked to the local signal and transmitting it to the DAC to be converted into an analog signal. Fine control of the OCXO can obtain an RF signal with phase pre-compensation, which is injected into the optical fiber and sent to the remote module.

[0025] In the embodiment, the phase detection and compensation function is realized by signal input and output based on external devices. The external devices on the external device link mainly include local temperature-controlled voltage-controlled crystal oscillator (OCXO), combiner, optical radio frequency transmission module, fiber optic coupler, circulator, fiber optic transmission remote module, two photodetectors (PDs), etc. The OCXO receives and finely controls the signal transmitted from the DAC to obtain a radio frequency (RF) signal with phase pre-compensation. The combiner sends the original RF signal from the atomic clock and the RF signal with phase pre-compensation obtained after fine control by the OCXO together into the optical radio frequency transmission module. Then, through the fiber optic coupler, one branch of the optical signal is sent to a PD, and the other branch is sent to port 1 of the circulator and transmitted to the fiber optic transmission remote module via port 2 through a long-distance fiber optic link. After that, the fiber optic transmission remote module will send part of the optical signal back to the circulator through the long-distance fiber optic link. The optical signal returned by the fiber optic transmission remote module is sent to another PD through port 3 of the circulator. The electrical signals obtained by the two PDs at their respective beat frequencies are amplified, filtered, and then sampled by the ADC into a digital signal with a frequency of 100MHz containing complete phase information, which is then sent to the phase detection and compensation module (FPGA) for processing and phase compensation synthesis.

[0026] This invention uses FPGA and digital signal processing methods to control phase detection compensation. The near-end and far-end digital signals obtained by ADC sampling are processed and phase error synthesized in the FPGA. The difference between the synthesized experimental fluctuation and the element delay fluctuation is about two orders of magnitude lower than the original fluctuation value.

[0027] The following is a detailed explanation of the implementation principle of this invention, wherein the reference frequency signal generated by the local atomic clock is denoted as...

[0028]

[0029] Where A, ω0 and These are the amplitude, angular frequency, and initial phase of the signal, respectively.

[0030] Since this invention focuses only on phase changes, the signal amplitude is temporarily ignored in the analysis. Transmitted signal This is the radio frequency (RF) signal that the fiber optic phase-stabilized system ultimately aims to reproduce at the remote module of the fiber optic transmission. A local temperature-controlled crystal oscillator (OCXO) generates a signal V2 to assist in detecting fluctuations and performs phase compensation adjustments. Together with V1, this signal can be used to obtain the phase change introduced into the RF signal during long-distance fiber optic link transmission. The RF signal generated based on the OCXO is represented as... For ease of subsequent calculations, its angular frequency ω2 is set to a fixed value ω. r During phase compensation, the OCXO's adjustment of the frequency signal is mainly reflected in the phase Φ, and satisfies:

[0031]

[0032] Where ξ is the initial phase difference between the two radio frequency signals, at this time

[0033]

[0034]

[0035] The two radio frequency signals V1 and V2 are modulated by the optical radio frequency transmitter module and then transmitted in the optical fiber.

[0036] To further compensate for the phase noise introduced by the delay of external devices (such as the single transmission path between the laser and the fiber coupler) in the photonic loading and transmission link of the RF signal, let the delay time caused by this part be τ1. After passing through the fiber coupler, one branch is directly sent to a PD. At this time, the transmitted signal is... The auxiliary detection compensation signal is

[0037] The intermediate frequency signal obtained after bandpass filtering and demodulation of the two signals at this PD can be expressed as:

[0038]

[0039] The other branch reaches the remote optical transmission module and returns a portion of the optical signal. Assuming the accumulated delay of the round-trip transmission over the long-distance optical fiber link is 2τ², and considering the previous link delay τ¹, the returned signal is...

[0040] After entering the circulator, the intermediate frequency signal obtained by passing through port 3 and then through the PD beat frequency bandpass filter for demodulation can be expressed as:

[0041]

[0042] Its angular frequency is ω0, and its phase delay is ξ+Φ. V7 and V8 are sampled by two ADCs and enter the phase detection and compensation module.

[0043] The other signal from V3 and V4 is transmitted via a long-distance fiber optic link. V can be obtained by beat frequency analysis of the PD in the fiber optic transmission remote module. 12 =cos(ω0t-ω0(τ1+τ2)+ξ+Φ).

[0044] For V7 and V8 entering the phase detection and compensation module, the frequency synchronized with V0 is (ω0-ω) m The frequency-synthesized signal V9 undergoes digital mixing / down-frequency processing to reduce signal processing speed and improve processing accuracy. The down-frequency signal can be represented as V... 10 =cos[ω m t-ω0τ1+ξ+Φ] and V 11 =cos(ω m t-ω0(τ1+2τ2)+ξ+Φ).

[0045] V 10 V 11 After mixing, the signal to be compensated, cos(-ω0(τ1+τ2)+ξ+Φ), is obtained. This signal beats with the signal obtained by the fiber optic transmission remote module to obtain V. 12 Consistency refers to the deviation between the remote signal and the reference frequency. By using FPGA algorithms to compensate for the phase noise introduced into the fiber optic transmission system, the frequency signal with phase locked to the local signal is recovered and transmitted to the DAC to be converted into an analog signal. After fine control of the OCXO, an RF signal with phase pre-compensation can be obtained, which is injected into the fiber optic cable and sent to the remote module to complete the phase compensation for system delay fluctuations.

[0046] In this embodiment, the signal receiving module includes a code conversion submodule, a data buffer submodule, and a DDS local oscillator signal submodule;

[0047] Two code conversion submodules and two data buffer submodules perform code conversion processing and data buffering on two digital signals from the ADC. At the same time, the DDS local oscillator signal submodule receives the clock signal after passing through a phase-locked loop from a 100MHz clock generated by a basic atomic clock. It uses this clock signal as the reference clock and system clock for the internal signal processing of the FPGA and generates 90MHz and 10MHz local oscillator signals for digital down-conversion, digital mixing and phase detection.

[0048] To minimize interference from digital signals to the system, the signal receiving module uses low-bit scrambling to descramble the sampled digital signal at the low end of the ADC output signal, employing offset binary encoding. Therefore, the code conversion submodule within the signal receiving module descrambles the ADC output signal based on low-bit code streams and simultaneously converts the offset encoding to two's complement encoding to obtain signed numbers for digital signal processing.

[0049] The data buffer submodule in the signal receiving module sends the sampled signal after code transformation into a high-speed data buffer to obtain multiple sets of parallel sampled data. Simultaneously, the 90MHz local oscillator signal generated by the DDS local oscillator signal submodule is also sent to a buffer module of the same depth. Since the ADC has a high sampling rate, directly processing the data serially according to the sampling rate places very high demands on the FPGA hardware; therefore, buffering is necessary first.

[0050] In this embodiment, the down-conversion mixing module includes a digital mixing / down-conversion submodule, an FIR low-pass filter submodule, an downsampling / averaging noise reduction submodule, an amplitude detection and normalization submodule, and a mixing / low-pass filter submodule.

[0051] The digital mixing / downsampling submodule mixes the two 100MHz signals processed by the signal receiving module with the 90MHz local oscillator signal from the DSS local oscillator signal module. After processing by the FIR low-pass filter submodule, downsampling / averaging noise reduction submodule, amplitude detection and normalization submodule, two down-frequency 10MHz signals are obtained. The mixing / low-pass filter submodule mixes the two down-frequency signals with the 10MHz local oscillator signal generated by the DDS local oscillator signal module. After low-pass filtering, the local phase difference and far-end phase difference of the RF signal can be detected.

[0052] The FIR low-pass filter submodule in the down-conversion mixing module uses a 16th-order FIR digital low-pass Equiripple filter design to filter the mixing signal. Based on the frequency of the mixing input signal and the characteristics of the output target signal, the 3dB bandwidth of the filter is designed to be 16MHz. The response at the output target frequency of 10MHz is about 0dB, and the amplitude response near 90M, 100M, and 190M reaches -100dB. It can effectively and fully filter out the high-frequency components generated by digital mixing and the residual frequency components of the original input. The use of FIR filtering ensures good phase linearity in signal processing, while the 16th order introduces a small processing delay and high real-time performance.

[0053] The downsampling / averaging noise reduction submodule in the down-conversion mixing module performs sample averaging on the high-speed sampled signal to achieve downsampling and effective noise reduction. After downsampling, it is processed at a sampling rate of 50MHz, which is convenient for serial digital signal processing. Furthermore, the signal after digital down-conversion processing in the down-conversion mixing module carries phase information at a center frequency of 10MHz AC, rather than a near-DC signal that directly reflects phase fluctuations. This facilitates real-time normalization processing of the signal in the amplitude detection and normalization submodule. The two down-converted 10MHz signals are mixed with the 10MHz local oscillator signal generated by the DDS local oscillator signal submodule. After low-pass filtering, the local and far-end phase differences of the RF signal can be detected.

[0054] In this embodiment, the local phase difference and far-end phase difference signals obtained after mixing in the phase compensation module are the cosine values ​​of the actual phase difference. The actual phase difference can be easily obtained through digital calculation using digital signal processing methods. To prevent frequent jumps across the π phase during the calculation process, the absolute values ​​of the obtained local phase difference and far-end phase difference signals are monitored after mixing. The initial phase of the local oscillator signal is adjusted based on the monitored values. This ensures that the absolute value of the phase error measurement is far away from the π phase jump point during the compensation process and after the system stabilizes, thereby improving the stability of the system.

[0055] The phase compensation module includes a phase error calculation submodule and a phase compensation synthesis submodule. The phase error calculation in the phase compensation module employs a lookup table method, utilizing the FPGA's internal SRAM as ROM to store cosine and inverse cosine function table values. This method is convenient, fast, and highly accurate. The phase error calculation submodule obtains the local and remote phase differences through table lookup transformation. After sum / difference synthesis, the system phase difference (link delay fluctuation) is obtained. In the phase compensation synthesis submodule, a PID algorithm is used to obtain a control compensation signal, which is then output to the DAC to be converted into an analog signal. This signal, after fine control of the OCXO, results in a pre-compensated RF signal.

[0056] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0057] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A phase detection and compensation method based on FPGA control in a fiber optic phase-stable transmission system, characterized in that, The method employs a phase detection and compensation module to receive, down-convert, and phase-compensate signals from external devices, and then applies these signals to the external devices to achieve phase detection and compensation. The phase detection and compensation module includes a signal receiving module, a down-converting and mixing module, and a phase compensation module connected in sequence based on an FPGA. The signal input terminal of the signal receiving module includes a radio frequency interface and two ADC inputs. The radio frequency interface is connected to a basic atomic clock to receive the clock signal from the basic atomic clock. The two ADC inputs are connected to the output terminal of the external device link to receive the analog signal obtained by PD beat frequency from the external device link. The down-conversion mixing module performs digital mixing down-conversion, filtering, downsampling / averaging noise reduction, amplitude detection and normalization, and mixing / low-pass processing on the two digital signals output by the two ADCs based on the local oscillator signal. The phase compensation module receives the two output signals from the down-conversion mixing module and compensates for the phase noise introduced in the external device link through the FPGA algorithm, recovers the frequency signal whose phase is locked to the local signal, and transmits it to the input of the external device link through the DAC. The external devices on the module external device link include a local temperature-controlled voltage-controlled crystal oscillator (OCXO), a combiner, an optical radio frequency (RF) transmitter module, an optical fiber coupler, a circulator, an optical fiber transmission remote module, and two photodetectors (PDs). The OCXO receives the signal transmitted from the DAC and finely controls it to obtain an RF signal with phase pre-compensation. The combiner sends the original RF signal from the atomic clock and the RF signal with phase pre-compensation obtained after fine control by the OCXO together to the optical radio frequency transmitter module. Then, through the optical fiber coupler, one branch of the optical signal is sent to one PD, and the other branch is sent to port 1 of the circulator and transmitted to the optical fiber transmission remote module via port 2 through a long-distance optical fiber link. The optical fiber transmission remote module returns part of the optical signal to the circulator through the long-distance optical fiber link. Through port 3 of the circulator, the optical signal returned by the optical fiber transmission remote module is sent to another PD. The electrical signals obtained by the two PDs at their respective beat frequencies are amplified and filtered, and then sampled by an ADC into a digital signal with a frequency of 100MHz containing complete phase information, which is then sent to the phase detection and compensation module.

2. The phase detection and compensation method based on FPGA control in a fiber optic phase-stable transmission system according to claim 1, characterized in that, The signal receiving module includes a code conversion submodule, a data buffer submodule, and a DDS local oscillator signal submodule. The two code conversion submodules and the two data buffer submodules perform code conversion processing and data buffering on the two digital signals from the ADC. At the same time, the DDS local oscillator signal submodule receives the clock signal generated by the basic atomic clock after passing through the phase-locked loop, uses it as the reference clock and system clock for the internal signal processing of the FPGA, and generates a local oscillator signal for digital down-conversion, digital mixing, and phase detection.

3. The phase detection and compensation method based on FPGA control in a fiber optic phase-stable transmission system according to claim 2, characterized in that, The code conversion submodule is used to descramble the ADC output signal based on the low-bit code stream, and at the same time complete the conversion from offset encoding to binary two's complement encoding to obtain signed numbers for digital signal processing.

4. The phase detection and compensation method based on FPGA control in a fiber optic phase-stable transmission system according to claim 2, characterized in that, The data buffer submodule sends the sampled signal after code transformation into a high-speed data buffer to obtain multiple sets of parallel sampled data. At the same time, the local oscillator signal generated by the DDS local oscillator signal submodule is also sent into a buffer module of the same depth.

5. The phase detection and compensation method based on FPGA control in a fiber optic phase-stable transmission system according to claim 1, characterized in that, The down-conversion mixing module includes a digital mixing / down-conversion submodule, an FIR low-pass filter submodule, an downsampling / averaging noise reduction submodule, an amplitude detection and normalization submodule, and a mixing / low-pass filter submodule. The digital mixing / down-frequency submodule mixes the two signals processed by the signal receiving module with the local oscillator signal from the DSS local oscillator signal module. Then, after processing by the FIR low-pass filter submodule, downsampling / averaging noise reduction submodule, amplitude detection and normalization submodule, the two down-frequency signals are obtained. The mixing / low-pass filter submodule mixes the two down-frequency signals with the local oscillator signal generated by the DDS local oscillator signal submodule. After low-pass filtering, the local phase difference and far-end phase difference of the RF signal are detected.

6. The phase detection and compensation method based on FPGA control in a fiber optic phase-stable transmission system according to claim 5, characterized in that, The FIR low-pass filter submodule uses a 16th-order FIR digital low-pass Equiripple filter to filter the mixing signal.

7. The phase detection and compensation method based on FPGA control in a fiber optic phase-stable transmission system according to claim 5, characterized in that, The downsampling / averaging noise reduction submodule performs sample averaging on the high-speed sampled signal to achieve downsampling.

8. The phase detection and compensation method based on FPGA control in a fiber optic phase-stable transmission system according to claim 1, characterized in that, The phase compensation module includes a phase error calculation submodule and a phase compensation synthesis submodule; The phase error calculation submodule obtains the phase difference between the local and remote ends through table lookup transformation, and obtains the system phase difference after sum / difference synthesis. In the phase compensation synthesis submodule, the control compensation signal is obtained through PID algorithm and output to DAC to be converted into an analog signal. The resulting RF signal with phase pre-compensation is obtained after fine control of OCXO.

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