A storage structure, electronic device

Abstract

A storage structure and an electronic device, the storage structure comprising a substrate and a plurality of groups of storage units arranged at intervals on the substrate, each group of storage units comprising a plurality of storage units arranged at intervals; wherein each storage unit comprises two transistors arranged in sequence in a direction perpendicular to the substrate, and the connecting line of the geometric centers of the orthographic projections of some or all of the groups of storage units is a hexagon.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of storage technology, specifically to a storage structure and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared with static memory, DRAM has the advantages of simpler structure, lower manufacturing cost, and higher capacity density. With the development of technology, the application of DRAM is becoming increasingly widespread.

[0003] Higher integration levels are an important development direction for memory to meet consumer demands for superior performance and low prices. For memory, integration level is a significant factor determining product price, thus increasing integration is particularly desirable. For two-dimensional or planar memory devices, since their integration level is primarily determined by the area occupied by the memory structure, it is greatly influenced by the level of fine patterning technology. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of this disclosure provide a storage structure, including a substrate and a group of storage cells disposed on the substrate at intervals from each other, the group of storage cells including a plurality of storage cells disposed at intervals from each other; wherein, each storage cell includes two transistors stacked sequentially in a direction perpendicular to the substrate, and the connecting line of some or all of the storage cells in the group of storage cells at the geometric center of the orthographic projection of the substrate is hexagonal.

[0006] In an exemplary embodiment, the two transistors stacked sequentially in the memory cell include a first transistor and a second transistor. The first transistor and the second transistor have an overlapping region in their orthogonal projections onto the substrate. The second transistor is located on the side of the first transistor away from the substrate. Both the first transistor and the second transistor are vertical transistors.

[0007] In an exemplary embodiment, the first transistor includes:

[0008] A first gate is located on the substrate, and the first gate is columnar.

[0009] The first semiconductor layer is located outside the first gate and is insulated from the first gate;

[0010] The first electrode is located on the side of the first gate near the substrate, and the first electrode is connected to the first semiconductor layer;

[0011] The second electrode is located on the side of the first electrode away from the substrate and is connected to the first semiconductor layer;

[0012] The second transistor includes:

[0013] The second gate is located on the side of the first gate away from the substrate, and the second gate is columnar.

[0014] The second semiconductor layer is located outside the second gate and is insulated from the second gate;

[0015] The third electrode is located on the side of the second gate near the substrate, and the third electrode is connected to the second semiconductor layer;

[0016] The fourth electrode is located on the side of the third electrode away from the substrate and is connected to the second semiconductor layer.

[0017] In an exemplary embodiment, it further includes a first word line, a first bit line, a second word line, and a second bit line. The first word line is connected to the first gate, the first bit line is connected to the second electrode, the second word line is connected to the second gate, and the second bit line is connected to the fourth electrode. The first word line, the first bit line, the second word line, and the second bit line extend in at least three directions, and the three extension directions intersect each other.

[0018] In an exemplary embodiment, two of the first word line, the first bit line, the second word line, and the second bit line extend in the same direction.

[0019] In an exemplary embodiment, the first word line, the first bit line, the second word line, and the second bit line are four signal lines, and the first word line, the first bit line, the second word line, and the second bit line are located in different signal line layers, and the two signal lines located in adjacent signal line layers have different extension directions.

[0020] In an exemplary embodiment, the extension direction of the first word line intersects the extension direction of the first bit line, the extension direction of the second word line intersects the extension direction of the second bit line, and the extension direction of one of the first word line and the first bit line is the same as the extension direction of one of the second word line and the second bit line.

[0021] In an exemplary embodiment, one of the first word line and the first bit line partially overlaps with the orthographic projection of one of the second word line and the second bit line onto the substrate, and partially does not overlap.

[0022] In an exemplary embodiment, the extension direction of one of the first word line and the first bit line intersects the extension direction of the other of the second word line and the second bit line.

[0023] In an exemplary embodiment, the third electrode is in contact with the first gate.

[0024] In an exemplary embodiment, the device further includes a first electrode plate, a second electrode plate, and an insulating layer disposed between the first electrode plate and the second electrode plate. The first electrode plate is connected to the first gate, and the second electrode plate is connected to the third electrode. The first electrode plate and the second electrode plate form a storage capacitor.

[0025] In an exemplary embodiment, the storage cell group includes a first storage cell, a second storage cell, a third storage cell, a fourth storage cell, a fifth storage cell, a sixth storage cell, and a seventh storage cell. The second storage cell, the third storage cell, the fourth storage cell, the fifth storage cell, the sixth storage cell, and the seventh storage cell are arranged around the first storage cell. The line connecting the geometric centers of the second storage cell, the third storage cell, the fourth storage cell, the fifth storage cell, the sixth storage cell, and the seventh storage cell on the orthographic projection of the substrate is hexagonal.

[0026] In an exemplary embodiment, the hexagon is a regular hexagon.

[0027] In an exemplary embodiment, the channels of the first transistor and the second transistor in the memory cell are both full-around channels.

[0028] Secondly, embodiments of this disclosure also provide an electronic device, including the aforementioned storage structure.

[0029] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0030] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0031] Figure 1 This is an equivalent circuit diagram of the storage structure in an embodiment of this application;

[0032] Figure 2 This is a top view of a group of storage cells in the storage structure of an embodiment of this application;

[0033] Figure 3 A cross-sectional view of a storage cell in the storage structure of an embodiment of this application. Figure 1 ;

[0034] Figure 4 This is a perspective view of the storage structure according to an embodiment of this application;

[0035] Figure 5 This is a side view of the storage structure according to an embodiment of this application;

[0036] Figure 6 This is a top view of the storage structure according to an embodiment of this application;

[0037] Figure 7a This is a schematic diagram of the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of this application embodiment. Figure 1 ;

[0038] Figure 7b This is a schematic diagram of the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of this application embodiment. Figure 2 ;

[0039] Figure 7c This is a schematic diagram of the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of this application embodiment. Figure 3 ;

[0040] Figure 7d This is a schematic diagram of the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of this application embodiment. Figure 4 ;

[0041] Figure 7e This is a schematic diagram of the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of this application embodiment. Figure 5 ;

[0042] Figure 7f This is a schematic diagram of the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of this application embodiment. Figure 6 ;

[0043] Figure 7g This is a schematic diagram (7) showing the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of this application embodiment;

[0044] Figure 7h This is a schematic diagram (8) showing the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of this application embodiment;

[0045] Figure 8a This is a schematic diagram showing the formation of the first word line during the storage structure fabrication process of an embodiment of this application;

[0046] Figure 8b This is a schematic diagram showing the first bit line formed during the fabrication process of the storage structure in this embodiment of the application.

[0047] Figure 8c This is a schematic diagram showing the formation of the first semiconductor layer during the fabrication of the storage structure according to an embodiment of this application;

[0048] Figure 8d This is a schematic diagram showing the formation of the first gate during the fabrication process of the memory structure according to an embodiment of this application;

[0049] Figure 8e This is a schematic diagram showing the second bit line formed during the fabrication of the storage structure in an embodiment of this application;

[0050] Figure 8f This is a schematic diagram showing the formation of the second semiconductor layer during the fabrication of the storage structure according to an embodiment of this application;

[0051] Figure 9 A cross-sectional view of a storage cell in the storage structure of an embodiment of this application. Figure 2 . Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0053] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0054] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0055] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0056] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0057] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (also called the drain terminal, drain region, or drain electrode) and the source electrode (also called the source terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0058] In this specification, the first electrode mentioned below can be the drain electrode and the second electrode can be the source electrode, or both can be either the source electrode or the drain electrode. In practical applications, which electrode is the source and which is the drain depends on the direction of current flow; generally, current flows from the source to the drain. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0059] In this specification, "electrical connection" includes situations where components are connected together by elements that have some electrical function, such as physical connections or signal connections. There are no particular limitations on the "elements that have some electrical function," as long as they enable the transmission and reception of electrical signals between the connected components. Examples of "elements that have some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0060] In this specification, the terms "parallel" and "perpendicular" as used below refer to approximately parallel and approximately perpendicular lines within the tolerance range. "Parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes angles greater than -5° and less than 5°. Similarly, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes angles greater than 85° and less than 95°.

[0061] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0062] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0063] In related technologies, Dynamic Random Access Memory (DRAM) typically employs multiple transistors connected in planar channels on the same plane. For example, a 2T0C or 2T1C DRAM structure generally uses two planar channel transistors connected in the same plane, with no overlap in the direction perpendicular to the substrate. This results in a larger area occupied, which is not conducive to improving integration density. The planar channel refers to the channel of the planar transistors, as opposed to vertical transistors. Furthermore, the arrangement of memory cells in the memory array presents an array distribution with multiple rows and columns, and the memory cells are located at the intersections of rows and columns, indicating that storage density still needs to be improved.

[0064] This application provides a storage structure, including a substrate and a group of storage cells spaced apart on the substrate. The storage cell group includes a plurality of storage cells spaced apart. Each storage cell includes two transistors stacked sequentially in a direction perpendicular to the substrate. The connecting line between the geometric centers of some or all of the storage cells in the storage cell group when projected onto the substrate is hexagonal.

[0065] Figure 1 This is an equivalent circuit diagram of the storage structure in an embodiment of this application. Taking a 2TOC storage structure as an example, in an exemplary embodiment, as... Figure 1As shown, the memory structure in this embodiment includes a first transistor and a second transistor stacked sequentially on a substrate. The first transistor can serve as a read transistor, and the second transistor can serve as a write transistor. The gate of the first transistor is connected to the drain of the second transistor. The gate of the first transistor can be connected to a first word line, which can serve as a read word line (RWL) in the read transistor; the source electrode of the first transistor can be connected to a first bit line, which can serve as a read bit line (RBL) in the read transistor. The gate of the second transistor can be connected to a second word line, which can serve as a write word line (WWL) in the write transistor; the source electrode of the second transistor can be connected to a second bit line, which can serve as a write bit line (WBL) in the write transistor.

[0066] The storage structure in this application changes the charge in the gate electrode of the read transistor by writing the transistor, thereby affecting the resistance state between the source and drain of the read transistor, thus achieving the distinction between "0" and "1". The specific principle is as follows.

[0067] During the writing "1" process, a positive voltage (greater than the threshold voltage Vth) is applied to the write word line (WWL) of the write transistor to turn it on, and a positive voltage is applied to the write bit line (WBL) of the write transistor to inject charge into the first gate of the read transistor. After charge injection, the voltages on the write word line (WWL) and write bit line (WBL) of the write transistor are removed, and the "1" state is preserved.

[0068] In the process of reading "1", a reading voltage is applied to the drain electrode of the reading tube. Since there is a certain charge in the first gate of the reading tube, the reading tube is in a low resistance state and obtains a large current. The reading "1" process is then completed after being amplified and identified by the external circuit.

[0069] During the writing "0" process, a positive voltage (greater than the threshold voltage Vth) is applied to the write word line (WWL) of the write transistor to turn it on, and a negative voltage is applied to the write bit line (WBL) of the write transistor to draw charge from the first gate of the read transistor. After the charge is drawn, the voltages on the write word line (WWL) and the write bit line (WBL) of the write transistor are removed, and the "0" state is preserved.

[0070] In the process of reading "0", a reading voltage is applied to the drain electrode of the read transistor. Since there is no charge in the first gate of the read transistor, the read transistor is in a high resistance state and obtains a small current. This current is then amplified and identified by the external circuit to complete the process of reading "0".

[0071] Figure 2 This is a top view of a group of storage cells in the storage structure of an embodiment of this application. In an exemplary embodiment, as shown... Figure 2As shown, the storage structure in this embodiment includes a substrate and a group of storage cells spaced apart on the substrate. Each storage cell group includes multiple spaced-apart storage cells, and each storage cell includes two transistors stacked sequentially in a direction perpendicular to the substrate. For example, a storage cell may include a first transistor and a second transistor stacked sequentially on the substrate. The first transistor can serve as a read transistor, and the second transistor can serve as a write transistor. The connecting line between the geometric centers of the orthographic projections of some or all of the storage cells in the storage cell group onto the substrate is hexagonal.

[0072] In an exemplary embodiment, the hexagon formed by the connecting lines of the geometric centers of the orthographic projections of some or all of the memory cells in the memory cell group onto the substrate can be a regular hexagon, for example, a regular hexagon. At least six memory cells are located near the vertices of the hexagon. Memory cells can also be disposed within the region of the hexagon.

[0073] The storage structure of this application embodiment uses a hexagonal line connecting the geometric centers of multiple storage cells (all or part of the storage cells in the storage cell group) projected onto the substrate. The multiple storage cells are arranged in a hexagonal pattern. Compared with multiple storage cells arranged in a rectangle, the storage structure of this application embodiment can increase storage density and significantly increase the area ratio of storage cells in the storage structure, thereby greatly improving the area utilization rate of the storage structure.

[0074] In an exemplary embodiment, the orthographic projection of the memory cell onto the substrate can include various shapes. For example, the orthographic projection of the memory cell onto the substrate can include regular or irregular shapes such as circles, rectangles, rhombuses, pentagons, and hexagons. Generally, the outline of the memory cell is mainly determined by the gate. If the gate is columnar and has a circular or elliptical cross-section, then the orthographic projection (i.e., the outer outline) of the memory cell onto the substrate is a circle or an ellipse.

[0075] In an exemplary embodiment, such as Figure 2 As shown, the storage cell group includes a first storage cell 41, a second storage cell 42, a third storage cell 43, a fourth storage cell 44, a fifth storage cell 45, a sixth storage cell 46, and a seventh storage cell 47. The second storage cell 42, the third storage cell 43, the fourth storage cell 44, the fifth storage cell 45, the sixth storage cell 46, and the seventh storage cell 47 are arranged around the first storage cell 41. The connecting lines of the geometric centers of the second storage cell 42, the third storage cell 43, the fourth storage cell 44, the fifth storage cell 45, the sixth storage cell 46, and the seventh storage cell 47 on the orthographic projection of the substrate form a hexagon.

[0076] In an exemplary embodiment, such as Figure 2As shown, the distances from the center of the first storage unit 41 to the centers of the second storage unit 42, the third storage unit 43, the fourth storage unit 44, the fifth storage unit 45, the sixth storage unit 46, and the seventh storage unit 47 are all the same.

[0077] Figure 3 A cross-sectional view of a storage cell in the storage structure of an embodiment of this application. Figure 1 .in, Figure 3 This illustrates a storage structure employing a 2TOC architecture. In an exemplary embodiment, as shown... Figure 3 As shown in the embodiment of this application, the two transistors stacked sequentially in a memory cell include a first transistor 100 and a second transistor 200 stacked sequentially on a substrate 300. The second transistor 200 is located on the side of the first transistor 100 away from the substrate 300, and the first transistor 100 and the second transistor 200 are electrically connected. The orthographic projections of the first transistor 100 and the second transistor 200 onto the substrate 300 overlap. For example, the orthographic projections of the first transistor 100 and the second transistor 200 onto the substrate 300 completely overlap. In this embodiment, the first transistor 100 and the second transistor 200 of the memory cell are stacked along a direction perpendicular to the substrate 300 (direction Z), thereby reducing the occupied area of ​​the memory cell and increasing the integration density of the memory cell. The first transistor 100 can serve as a read transistor, and the second transistor 200 can serve as a write transistor.

[0078] In an exemplary embodiment, such as Figure 3 As shown, both the first transistor 100 and the second transistor 200 are vertical transistors. For example, the first transistor 100 and the second transistor 200 are VCAA (vertical channel allaround) transistors.

[0079] In an exemplary embodiment, such as Figure 3 As shown, the first transistor 100 includes a first electrode 1a, a second electrode 2a, a first gate 8, a first semiconductor layer 6, and a first gate insulating layer 10. The first electrode 1a can serve as the drain electrode of the first transistor 100, and the second electrode 2a can serve as the source electrode of the first transistor 100.

[0080] In an exemplary embodiment, such as Figure 3 As shown, the first gate 8 is located on the substrate 300. The first gate 8 extends along a direction perpendicular to the substrate 300 (direction Z). The first gate 8 is columnar, and the vertical cross-section of the first gate 8 can be T-shaped.

[0081] In an exemplary embodiment, such as Figure 3As shown, the first semiconductor layer 6 is located outside the first gate 8 and is insulated from the first gate 8, forming the channel of the first transistor 100. For example, the first gate 8 includes sidewalls and a bottom wall, and the first semiconductor layer 6 is located outside the sidewalls and bottom wall of the first gate 8 and is insulated from the sidewalls and bottom wall of the first gate 8.

[0082] In an exemplary embodiment, such as Figure 3 As shown, the first gate insulating layer 10 is located between the first semiconductor layer 6 and the first gate 8, separating the first semiconductor layer 6 from the first gate 8. For example, the first gate 8 includes a sidewall and a bottom wall, and the first gate insulating layer 10 is located outside the sidewall and bottom wall of the first gate 8, separating the sidewall and bottom wall of the first gate 8 from the first semiconductor layer 6.

[0083] In an exemplary embodiment, such as Figure 3 As shown, the first electrode 1a is located on the side of the first gate 8 near the substrate 300 and is insulated from the first gate 8. The first electrode 1a and the first gate 8 overlap in their orthographic projections onto the substrate 300. For example, the first gate 8 includes a sidewall and a bottom wall, and the orthographic projection of the bottom wall of the first gate 8 onto the substrate 300 lies within the orthographic projection of the first electrode 1a onto the substrate 300. A first gate insulating layer 10 and a first semiconductor layer 6 are disposed between the first electrode 1a and the first gate 8. The first electrode 1a is connected to the first semiconductor layer 6, and the first electrode 1a is insulated from the first gate 8 through the first gate insulating layer 10.

[0084] In an exemplary embodiment, such as Figure 3 As shown, the second electrode 2a is located on the side of the first electrode 1a away from the substrate 300. The second electrode 2a is located outside the first gate 8 and is insulated from the first gate 8. The orthographic projections of the second electrode 2a and the first electrode 1a onto the substrate 300 overlap; for example, the orthographic projections of the second electrode 2a and the first electrode 1a onto the substrate 300 completely overlap. A first gate insulating layer 10 and a first semiconductor layer 6 are disposed between the second electrode 2a and the first gate 8. The second electrode 2a is connected to the first semiconductor layer 6, and the second electrode 2a is insulated from the first gate 8 through the first gate insulating layer 10.

[0085] In an exemplary embodiment, such as Figure 3 As shown, the second transistor 200 includes a third electrode 3, a fourth electrode 4a, a second gate 9, a second semiconductor layer 7, and a second gate insulating layer 11. The third electrode 3 can serve as the drain electrode of the second transistor 200, and the fourth electrode 4a can serve as the source electrode of the second transistor 200.

[0086] In an exemplary embodiment, such as Figure 3As shown, the second gate 9 is located on the side of the first gate 8 away from the substrate 300. The second gate 9 extends along a direction perpendicular to the substrate 300 (direction Z). The second gate 9 is columnar, and its vertical cross-section can be T-shaped. The orthographic projections of the second gate 9 and the first gate 8 onto the substrate 300 overlap; for example, the orthographic projections of the second gate 9 and the first gate 8 onto the substrate 300 completely overlap.

[0087] In an exemplary embodiment, such as Figure 3 As shown, the second semiconductor layer 7 is located outside the second gate 9 and is insulated from the second gate 9, forming the channel of the second transistor 200. For example, the second gate 9 includes sidewalls and a bottom wall, and the second semiconductor layer 7 is located outside the sidewalls and bottom wall of the second gate 9 and is insulated from the sidewalls and bottom wall of the second gate 9.

[0088] In an exemplary embodiment, such as Figure 3 As shown, the second gate insulating layer 11 is located between the second semiconductor layer 7 and the second gate 9, separating the second semiconductor layer 7 from the second gate 9. For example, the second gate 9 includes sidewalls and a bottom wall, and the second gate insulating layer 11 is located outside the sidewalls and bottom wall of the second gate 9, separating the sidewalls and bottom wall of the second gate 9 from the second semiconductor layer 7.

[0089] In an exemplary embodiment, such as Figure 3 As shown, the third electrode 3 is located on the side of the second gate 9 closest to the substrate 300 and is insulated from the second gate 9. The third electrode 3 is in contact with the side of the first gate 8 furthest from the substrate 300. The orthographic projections of the third electrode 3 and the second gate 9 onto the substrate 300 overlap. For example, the second gate 9 includes a sidewall and a bottom wall, and the orthographic projection of the bottom wall of the second gate 9 onto the substrate 300 lies within the orthographic projection of the third electrode 3 onto the substrate 300. A second gate insulating layer 11 and a second semiconductor layer 7 are disposed between the third electrode 3 and the second gate 9. The third electrode 3 is connected to the second semiconductor layer 7, and the third electrode 3 is insulated from the second gate 9 through the second gate insulating layer 11.

[0090] In an exemplary embodiment, such as Figure 3 As shown, the fourth electrode 4a is located on the side of the third electrode 3 away from the substrate 300. The fourth electrode 4a is located outside the second gate 9 and is insulated from the second gate 9. The orthographic projections of the fourth electrode 4a and the third electrode 3 onto the substrate 300 overlap; for example, the orthographic projections of the fourth electrode 4a and the third electrode 3 onto the substrate 300 completely overlap. A second gate insulating layer 11 and a second semiconductor layer 7 are disposed between the fourth electrode 4a and the second gate 9. The fourth electrode 4a is connected to the second semiconductor layer 7, and the fourth electrode 4a is insulated from the second gate 9 through the second gate insulating layer 11.

[0091] In an exemplary embodiment, the channels of the first transistor and the second transistor in the memory cell are both all-around channels, that is, the first semiconductor layer in the first transistor is ring-shaped and surrounds the first gate. The second semiconductor layer in the second transistor is ring-shaped and surrounds the second gate.

[0092] In an exemplary embodiment, both the first semiconductor layer 6 and the second semiconductor layer 7 can be made of oxide semiconductor materials, for example, both the first semiconductor layer 6 and the second semiconductor layer 7 can be made of indium gallium zinc oxide (IGZO). Because indium gallium zinc oxide thin-film transistors have very low off-state leakage current, the information in the storage node can be retained for a relatively long time.

[0093] In an exemplary embodiment, the first gate insulating layer 10 and the second gate insulating layer 11 serve as insulation between the gate and the semiconductor layer. Preferably, they are made of materials with a wide bandgap and high dielectric constant, or materials suitable for fabricating extremely small devices, such as hafnium dioxide (HfO2). Both the first and second gate insulating layers can be made of a single-layer dielectric material, such as an oxide or nitride; or, both can be made of a multilayer dielectric material, such as a combination of oxides and nitrides.

[0094] Figure 4 This is a perspective view of the storage structure according to an embodiment of this application; Figure 5 This is a side view of the storage structure according to an embodiment of this application. Figure 6 This is a top view of the storage structure according to an embodiment of this application. In an exemplary embodiment, as shown... Figure 4 , Figure 5 and Figure 6 As shown, the storage structure in this embodiment further includes a first word line 1, a first bit line 2, a second word line 5, and a second bit line 4. The first word line 1 is connected to the first gate of the first transistor, and the first bit line 2 is connected to the second electrode 2a of the first transistor; the second word line 5 is connected to the second gate of the second transistor, and the second bit line 4 is connected to the fourth electrode 4a of the second transistor. The first word line 1, the first bit line 2, the second word line 5, and the second bit line 4 extend in at least three directions, and these three directions intersect each other.

[0095] In an exemplary embodiment, two of the first character line 1, the first digit line 2, the second character line 5, and the second digit line 4 extend in the same direction. For example, the extension direction of the first character line 1 is the same as the extension direction of the second character line 5; or, the extension direction of the first character line 1 is the same as the extension direction of the second digit line 4; or, the extension direction of the first digit line 2 is the same as the extension direction of the second character line 5; or, the extension direction of the first digit line 2 is the same as the extension direction of the second digit line 4.

[0096] In an exemplary embodiment, the first word line 1, the first bit line 2, the second word line 5, and the second bit line 4 are four signal lines, and they are located in different signal line layers, i.e., they are all located in different film layers. The two signal lines located in adjacent signal line layers have different extension directions. For example, the first word line 1, the first bit line 2, the second bit line 4, and the second word line 5 are sequentially spaced along a direction perpendicular to the substrate (direction Z). The first word line 1 and the first bit line 2 have different extension directions, the first bit line 2 and the second bit line 4 have different extension directions, and the second bit line 4 and the second word line 5 have different extension directions.

[0097] In an exemplary embodiment, the extension direction of the first word line 1 in the storage structure of this application embodiment intersects the extension direction of the first bit line 2. A certain angle is formed between the orthographic projection of the first word line 1 onto the substrate and the orthographic projection of the first bit line 2 onto the substrate. For example, the angle formed between the orthographic projection of the first word line 1 onto the substrate and the orthographic projection of the first bit line 2 onto the substrate is 60 degrees. The extension direction of the second word line 5 intersects the extension direction of the second bit line 4. A certain angle is formed between the orthographic projection of the second word line 5 onto the substrate and the orthographic projection of the second bit line 4 onto the substrate. For example, the angle formed between the orthographic projection of the second word line 5 onto the substrate and the orthographic projection of the second bit line 4 onto the substrate is 60 degrees.

[0098] In an exemplary embodiment, the extension direction of one of the first character line 1 and the first bit line 2 is the same as the extension direction of one of the second character line 5 and the second bit line 4. For example, the extension direction of the first character line 1 is the same as the extension direction of the second character line 5; or, the extension direction of the first character line 1 is the same as the extension direction of the second bit line 4; or, the extension direction of the first bit line 2 is the same as the extension direction of the second character line 5; or, the extension direction of the first bit line 2 is the same as the extension direction of the second bit line 4.

[0099] In an exemplary embodiment, the extension direction of one of the first character line 1 and the first digit line 2 is the same as the extension direction of one of the second character line 5 and the second digit line 4, and the orthographic projection of one of the first character line 1 and the first digit line 2 onto the substrate partially overlaps and partially does not overlap. For example, the extension direction of the first character line 1 is the same as the extension direction of the second character line 5, and the orthographic projections of the first character line 1 and the second character line 5 onto the substrate partially overlap and partially do not overlap.

[0100] In an exemplary embodiment, the extension direction of one of the first character line 1 and the first position line 2 is the same as the extension direction of one of the second character line 5 and the second position line 4, and the extension direction of the other of the first character line 1 and the first position line 2 intersects the extension direction of the other of the second character line 5 and the second position line 4.

[0101] The arrangement of the first word line 1, the first bit line 2, the second word line 5, and the second bit line 4 in the storage structure of this application embodiment enables multiple storage cells to share the first word line 1, the first bit line 2, the second word line 5, and the second bit line 4, thereby increasing the density of storage cells in the storage structure and thus improving the utilization rate of the storage structure area.

[0102] Figure 7a This is a schematic diagram of the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of this application embodiment. Figure 1 In an exemplary embodiment, such as Figure 7a As shown, the first character line 1 and the second character line 4 both extend along direction X, which is horizontal. The extension direction of the first character line 1 is the same as that of the second character line 4, and the orthographic projections of the first character line 1 and the second character line 4 on the base partially overlap and partially do not overlap. The first character line 2 extends along direction Y1, and its extension direction intersects the extension directions of the first character line 1 and the second character line 4. The first character line 2 forms a certain angle with the first character line 1; for example, the angle between the first character line 2 and the first character line 1 can be 60 degrees. The second character line 5 extends along direction Y2, and its extension direction intersects the extension directions of the first character line 2, the first character line 1, and the second character line 4. The second character line 5 forms a certain angle with the first character line 1; for example, the angle between the second character line 5 and the first character line 1 can be 60 degrees. The second character line 5 forms a certain angle with the first character line 2; for example, the angle between the second character line 5 and the first character line 2 can be 60 degrees. The first word line 1, the second bit line 4, the first bit line 2, and the second word line 5 are arranged in a staggered, rotating pattern along the circumference of the memory cell, with the geometric center of the memory cell as the center.

[0103] Figure 7b This is a schematic diagram of the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of this application embodiment. Figure 2 In an exemplary embodiment, such as Figure 7bAs shown, the first character line 1 and the second character line 4 both extend along direction X, which is horizontal. The extension direction of the first character line 1 is the same as that of the second character line 4, and the orthographic projections of the first character line 1 and the second character line 4 on the base partially overlap and partially do not overlap. The second character line 5 extends along direction Y1, and its extension direction intersects the extension directions of both the first character line 1 and the second character line 4. The second character line 5 forms a certain angle with the first character line 1; for example, the angle between the second character line 5 and the first character line 1 can be 60 degrees. The first character line 2 extends along direction Y2, and its extension direction intersects the extension directions of the second character line 5, the first character line 1, and the second character line 4. The first character line 2 forms a certain angle with the first character line 1; for example, the angle between the first character line 2 and the first character line 1 can be 60 degrees. The second character line 5 forms a certain angle with the first character line 2; for example, the angle between the second character line 5 and the first character line 2 can be 60 degrees. The first word line 1, the second bit line 4, the second word line 5, and the first bit line 2 are arranged in a staggered, rotating arrangement along the circumference of the memory cell with the geometric center of the memory cell as the center.

[0104] Figure 7c This is a schematic diagram of the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of this application embodiment. Figure 3 In an exemplary embodiment, such as Figure 7c As shown, the first character line 2 and the second character line 4 both extend along direction X, which is horizontal. The extension direction of the first character line 2 is the same as that of the second character line 4, and the orthographic projections of the first character line 2 and the second character line 4 on the base partially overlap and partially do not overlap. The first character line 1 extends along direction Y1, and its extension direction intersects the extension directions of the first character line 2 and the second character line 4. The first character line 1 and the first character line 2 form a certain angle; for example, the angle between the first character line 1 and the first character line 2 can be 60 degrees. The second character line 5 extends along direction Y2, and its extension direction intersects the extension directions of the first character line 1, the first character line 2, and the second character line 4. The second character line 5 and the first character line 2 form a certain angle; for example, the angle between the second character line 5 and the first character line 2 can be 60 degrees. The second character line 5 and the first character line 1 form a certain angle; for example, the angle between the second character line 5 and the first character line 1 can be 60 degrees. The first bit line 2, the second bit line 4, the first word line 1, and the second word line 5 are arranged in a staggered, rotating arrangement along the circumference of the storage cell with the geometric center of the storage cell as the center.

[0105] Figure 7d This is a schematic diagram of the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of this application embodiment. Figure 4In an exemplary embodiment, such as Figure 7d As shown, the first character line 2 and the second character line 4 both extend along direction X, which is horizontal. The extension direction of the first character line 2 is the same as that of the second character line 4, and the orthographic projections of the first character line 2 and the second character line 4 on the base partially overlap and partially do not overlap. The second character line 5 extends along direction Y1, and its extension direction intersects the extension directions of the first character line 2 and the second character line 4. The second character line 5 forms a certain angle with the first character line 2; for example, the angle between the second character line 5 and the first character line 2 can be 60 degrees. The first character line 1 extends along direction Y2, and its extension direction intersects the extension directions of the second character line 5, the first character line 2, and the second character line 4. The first character line 1 forms a certain angle with the first character line 2; for example, the angle between the first character line 1 and the first character line 2 can be 60 degrees. The second character line 5 forms a certain angle with the first character line 1; for example, the angle between the second character line 5 and the first character line 1 can be 60 degrees. The first bit line 2, the second bit line 4, the second word line 5, and the first word line 1 are arranged in a staggered, rotating arrangement along the circumference of the storage cell with the geometric center of the storage cell as the center.

[0106] Figure 7e This is a schematic diagram of the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of this application embodiment. Figure 5 In an exemplary embodiment, such as Figure 7e As shown, both the first character line 1 and the second character line 5 extend along direction X, which is horizontal. The extension direction of the first character line 1 is the same as that of the second character line 5, and the orthographic projections of the first character line 1 and the second character line 5 on the base partially overlap and partially do not overlap. The first character line 2 extends along direction Y1, and its extension direction intersects the extension directions of both the first character line 1 and the second character line 5. The first character line 2 forms a certain angle with the first character line 1; for example, the angle between the first character line 2 and the first character line 1 can be 60 degrees. The second character line 4 extends along direction Y2, and its extension direction intersects the extension directions of the first character line 2, the first character line 1, and the second character line 5. The second character line 4 forms a certain angle with the first character line 1; for example, the angle between the second character line 4 and the first character line 1 can be 60 degrees. The second character line 4 forms a certain angle with the first character line 2; for example, the angle between the second character line 4 and the first character line 2 can be 60 degrees. The first word line 1, the second word line 5, the first bit line 2, and the second bit line 4 are arranged in a staggered, rotating arrangement along the circumference of the memory cell with the geometric center of the memory cell as the center.

[0107] Figure 7fThis is a schematic diagram of the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of this application embodiment. Figure 6 In an exemplary embodiment, such as Figure 7e As shown, both the first character line 1 and the second character line 5 extend along direction X, which is horizontal. The extension direction of the first character line 1 is the same as that of the second character line 5, and the orthographic projections of the first character line 1 and the second character line 5 on the base partially overlap and partially do not overlap. The second character line 4 extends along direction Y1, and its extension direction intersects the extension directions of both the first character line 1 and the second character line 5. The second character line 4 forms a certain angle with the first character line 1; for example, the angle between the second character line 4 and the first character line 1 can be 60 degrees. The first character line 2 extends along direction Y2, and its extension direction intersects the extension directions of the second character line 4, the first character line 1, and the second character line 5. The first character line 2 forms a certain angle with the first character line 1; for example, the angle between the first character line 2 and the first character line 1 can be 60 degrees. The first character line 2 forms a certain angle with the second character line 4; for example, the angle between the first character line 2 and the second character line 4 can be 60 degrees. The first word line 1, the second word line 5, the second bit line 4, and the first bit line 2 are arranged in a staggered, rotating arrangement along the circumference of the storage cell with the geometric center of the storage cell as the center.

[0108] Figure 7g This is a schematic diagram (seven) illustrating the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of an embodiment of this application. In an exemplary embodiment, as shown... Figure 7g As shown, the first character line 2 and the second character line 5 both extend along direction X, which is horizontal. The extension direction of the first character line 2 is the same as that of the second character line 5, and the orthographic projection of the first character line 2 onto the base partially overlaps with the orthographic projection of the second character line 5 onto the base, and partially does not overlap. The first character line 1 extends along direction Y1, and its extension direction intersects the extension directions of the first character line 2 and the second character line 5. The first character line 1 and the first character line 2 form a certain angle; for example, the angle between the first character line 1 and the first character line 2 can be 60 degrees. The second character line 4 extends along direction Y2, and its extension direction intersects the extension directions of the first character line 1, the first character line 2, and the second character line 5. The second character line 4 and the first character line 1 form a certain angle; for example, the angle between the second character line 4 and the first character line 1 can be 60 degrees. The first bit line 2, the second word line 5, the first word line 1, and the second bit line 4 are arranged in a staggered manner, rotating around the geometric center of the storage cell along the circumference of the storage cell.

[0109] Figure 7h This is a schematic diagram (eight) illustrating the arrangement of the first word line, the first bit line, the second word line, and the second bit line in the storage structure of an embodiment of this application. In an exemplary embodiment, as shown... Figure 7h As shown, the first line 2 and the second character line 5 both extend along direction X, which is horizontal. The extension direction of the first line 2 is the same as that of the second character line 5, and the orthographic projection of the first line 2 onto the base partially overlaps and partially does not overlap with the orthographic projection of the second character line 5 onto the base. The second line 4 extends along direction Y1, and its extension direction intersects the extension directions of the first line 2 and the second character line 5. The second line 4 forms a certain angle with the first line 2; for example, the angle between the second line 4 and the first line 2 can be 60 degrees. The first character line 1 extends along direction Y2, and its extension direction intersects the extension directions of the second line 4, the first line 2, and the second character line 5. The first character line 1 forms a certain angle with the first line 2; for example, the angle between the first character line 1 and the first line 2 can be 60 degrees. The first character line 1 forms a certain angle with the second line 4; for example, the angle between the first character line 1 and the second line 4 can be 60 degrees. The first bit line 2, the second word line 5, the second bit line 4, and the first word line 1 are arranged in a staggered, rotating arrangement along the circumference of the storage cell with the geometric center of the storage cell as the center.

[0110] In an exemplary embodiment, such as Figure 6 As shown, the storage structure in this embodiment further includes a first peripheral signal line 21, a second peripheral signal line 22, a third peripheral signal line 23, and a fourth peripheral signal line 24. The first peripheral signal line 21 is connected to the end of the first word line 1 and is used to provide a signal to the first word line 1; the second peripheral signal line 22 is connected to the end of the first bit line 2 and is used to provide a signal to the first bit line 2; the third peripheral signal line 23 is connected to the end of the second bit line 4 and is used to provide a signal to the second bit line 4; the fourth peripheral signal line 24 is connected to the end of the second word line 5 and is used to provide a signal to the second word line 5.

[0111] In an exemplary embodiment, such as Figure 6 As shown, the first peripheral signal line 21, the second peripheral signal line 22, the third peripheral signal line 23, and the fourth peripheral signal line 24 are all disposed on the same layer as the second word line 5. Specifically, the storage structure of this embodiment further includes a connecting electrode 31. The end of the first word line 1 is connected to the connecting electrode 31 through a first via, and the connecting electrode 31 is connected to the first peripheral signal line 21 through a second via. The end of the first bit line 2 is connected to the connecting electrode 31 through a third via, and the connecting electrode 31 is connected to the second peripheral signal line 22 through a fourth via. The third peripheral signal line 23 is connected to the end of the second bit line 4 through a fifth via. The fourth peripheral signal line 24 is connected to the second word line 5.

[0112] Figure 9 A cross-sectional view of a storage cell in the storage structure of an embodiment of this application. Figure 2 .in, Figure 9 This illustrates a storage structure employing a 2T1C architecture. In an exemplary embodiment, as shown... Figure 9 As shown, the storage structure in this embodiment further includes a first electrode plate 71, a second electrode plate 72, and an insulating layer 73 disposed between the first electrode plate 71 and the second electrode plate 72. The first electrode plate 71 is connected to the first gate of the first transistor 100, and the second electrode plate 72 is connected to the third electrode of the second transistor 200; alternatively, the first electrode plate 71 can be part of the first gate, and the second electrode plate 72 can be part of the third electrode. The first electrode plate 71 and the second electrode plate 72 form a storage capacitor 500, which is used to store charge to affect the resistance state between the source and drain of the read transistor.

[0113] The following reference Figures 8a to 8f The fabrication process of the storage structure is illustrated by example.

[0114] The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0115] In an exemplary embodiment, the fabrication process of the storage structure may include:

[0116] (1) Provide a base.

[0117] In an exemplary embodiment, the substrate can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator, etc., with the corresponding top semiconductor material being silicon, germanium, silicon germanium, or gallium arsenide, etc. Meanwhile, the semiconductor layer on the substrate has a doping type determined according to the device type to form a P-well (for nMOSFETs) or an n-well (for pMOSFETs).

[0118] (2) Form the first character line.

[0119] In an exemplary embodiment, forming the first word lines includes: sequentially depositing a first insulating film and a first conductive film on the substrate; patterning the first insulating film and the first conductive film using a patterning process; forming a first barrier layer disposed on the substrate using the first insulating film; and forming a plurality of first word lines 1 disposed on the first barrier layer using the first conductive film. The plurality of first word lines 1 all extend along the X direction, and are spaced apart from each other, such as... Figure 8a As shown.

[0120] (3) Form the first line.

[0121] In an exemplary embodiment, forming the first first line includes: sequentially depositing a second insulating film, a second conductive film, and a third insulating film on a substrate on which the aforementioned pattern is formed; patterning the second insulating film, the second conductive film, and the third insulating film using a patterning process; forming a second barrier layer covering a plurality of first first lines 1 on the second insulating film; forming a plurality of first first lines 2 on the second barrier layer on the second conductive film; and forming a third barrier layer covering the plurality of first first lines 2 on the third insulating film. The plurality of first first lines 2 all extend along the direction Y1, and are spaced apart from each other, such as... Figure 8b As shown.

[0122] (4) Form the first semiconductor layer.

[0123] In an exemplary embodiment, forming the first semiconductor layer includes forming a plurality of first receiving holes 51, a plurality of first vias 52 and a plurality of third vias 53 in a third barrier layer on a substrate on which the aforementioned pattern is formed.

[0124] The first receiving hole 51 is located at the intersection of the first character line 1 and the first character line 2. The orthographic projection of the first receiving hole 51 onto the substrate is located within the orthographic projections of the first character line 1 and the first character line 2 onto the substrate. The first receiving hole 51 passes through the third barrier layer, the first character line 2, and the second barrier layer in sequence.

[0125] A first semiconductor thin film (e.g., IGZO material, IZO material, etc.) and a first dielectric thin film (e.g., silicon oxide, iron oxide, zirconium oxide, etc.) are sequentially deposited on the inner wall of the first receiving hole 51, so that the first semiconductor thin film forms the first semiconductor layer and the first dielectric thin film forms the first gate insulating layer.

[0126] The orthographic projection of the first via 52 onto the substrate lies within the orthographic projection of the first character line 1 onto the substrate, and the orthographic projections of the first via 52 and the first character line 2 onto the substrate do not overlap. The first via 52 passes sequentially through the third barrier layer and the second barrier layer to the surface of the first character line 1, exposing the first character line 1.

[0127] The orthographic projection of the third via 53 onto the substrate lies within the orthographic projection of the first line 2 onto the substrate. The third via 53 does not overlap with the orthographic projection of the first line 1 onto the substrate. The third via 53 passes through the third barrier layer to the surface of the first line 2, exposing the first line 2. Figure 8c As shown.

[0128] (5) Form the first gate.

[0129] In an exemplary embodiment, forming the first gate includes: depositing a fourth conductor film in a plurality of first receiving holes 51 on a substrate on which the aforementioned pattern is formed; patterning the fourth conductor film using a patterning process to form a first gate 8 disposed in the plurality of first receiving holes 51 and a plurality of connection electrodes 31 disposed on a third barrier layer. A portion of the first gate 8 is disposed in the first receiving hole and is located on the side of the first semiconductor layer away from the inner wall of the first receiving hole; the first gate is insulated from the first semiconductor layer by a first gate insulating layer.

[0130] The orthographic projection of the connecting electrode 31 onto the substrate overlaps with the orthographic projections of the first via 52 and the third via 53 onto the substrate. The orthographic projections of the first via 52 and the third via 53 onto the substrate are located within the orthographic projection of the connecting electrode 31 onto the substrate. The connecting electrode 31 is connected to the first word line 1 through the first via 52, and the connecting electrode 31 is connected to the first word line 2 through the third via 53, as shown below. Figure 8d As shown.

[0131] (6) Form the second position line.

[0132] In an exemplary embodiment, forming the second bit lines includes: sequentially depositing a fourth insulating film, a fifth conductor film, and a fifth insulating film on a substrate on which the aforementioned pattern is formed; patterning the fourth insulating film, the fifth conductor film, and the fifth insulating film using a patterning process; forming a fourth barrier layer covering the first gate and the connecting electrode on the fourth insulating film; forming a plurality of second bit lines 4 disposed on the fourth barrier layer on the fifth conductor film; and forming a fifth barrier layer covering the plurality of second bit lines 4 on the fifth insulating film. The plurality of second bit lines 4 all extend along the direction X, and the extension direction of the second bit lines 4 is the same as the extension direction of the first word line 1, such as... Figure 8e As shown.

[0133] (6) Forming a second semiconductor layer.

[0134] In an exemplary embodiment, forming the second semiconductor layer includes forming a plurality of second receiving holes 61, a plurality of second vias 62, a plurality of fourth vias 63, and a plurality of fifth vias 64 in a fifth insulating film on a substrate on which the aforementioned pattern is formed.

[0135] The second receiving hole 61 is located at the intersection of the second bit line 4 and the first gate 8. The orthographic projection of the second receiving hole 61 onto the substrate is always within the orthographic projection of the second bit line 4 onto the substrate. The second receiving hole 61 passes sequentially through the fifth barrier layer, the second bit line 4, and the fourth barrier layer to the surface of the first gate 8.

[0136] A second semiconductor thin film (e.g., IGZO material, IZO material, etc.) and a second dielectric thin film (e.g., silicon oxide, iron oxide, zirconium oxide, etc.) are sequentially deposited on the inner wall of the second receiving hole 61, so that the second semiconductor thin film forms the second semiconductor layer and the second dielectric thin film forms the second gate insulating layer.

[0137] The second via 62 overlaps with the first via 52 on the substrate. The second via 62 passes through the fifth barrier layer and the fourth barrier layer in sequence to the surface of the connecting electrode 31, exposing the connecting electrode 31.

[0138] The fourth via 63 and the third via 53 overlap in their orthographic projections on the substrate. The fourth via 63 passes through the fifth barrier layer and the fourth barrier layer in sequence to the surface of the connecting electrode 31, exposing the connecting electrode 31.

[0139] The fifth via 64 passes through the fifth barrier layer to the surface of the end of the second bit line 4, exposing the end of the second bit line 4, as shown. Figure 8f As shown.

[0140] (7) Form the second character line.

[0141] In an exemplary embodiment, forming the second word line includes: depositing a sixth conductor film on a substrate on which the aforementioned pattern is formed, and patterning the sixth conductor film using a patterning process to form a plurality of second word lines 5 disposed on a fifth barrier layer, a second gate located in a second receiving hole 61, a plurality of first peripheral signal lines 21, a plurality of second peripheral signal lines 22, a plurality of third peripheral signal lines 23, and a plurality of fourth peripheral signal lines 24. The second word lines 5 extend along the direction Y2.

[0142] The first peripheral signal line 21 is connected to the connecting electrode 31 through the second via 62, and the connecting electrode 31 is connected to the end of the first word line 1 through the first via 52; the second peripheral signal line 22 is connected to the connecting electrode 31 through the fourth via 63, and the connecting electrode 31 is connected to the end of the first bit line 2 through the third via 53; the third peripheral signal line 23 is connected to the end of the second bit line 4 through the fifth via 64. The fourth peripheral signal line 24 is connected to the first sub-second gate 5, as shown below. Figure 6 As shown.

[0143] The method for fabricating the storage structure in this application embodiment allows multiple storage cells to share at least one of the first word line, the first bit line, the third source / drain electrode, and the second bit line, thereby increasing the density of storage cells in the storage structure and thus improving the utilization rate of the storage structure area.

[0144] This application also provides an electronic device including any of the storage structures described above. This application does not impose any special limitations on the specific form of the aforementioned storage device.

[0145] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure, i.e., features within the embodiments, can be combined with each other to obtain new embodiments.

[0146] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A storage structure, characterized in that, The device includes a substrate and a group of memory cells spaced apart on the substrate. The group of memory cells includes a plurality of memory cells spaced apart. Each memory cell includes two transistors stacked sequentially in a direction perpendicular to the substrate. The connecting line between the geometric centers of some or all of the memory cells in the group when projected onto the substrate is hexagonal. The two transistors stacked sequentially in the memory cell include a first transistor and a second transistor; The first transistor includes a first gate, a first electrode, and a second electrode; The second transistor includes a second gate, a third electrode, and a fourth electrode; It also includes a first word line, a first bit line, a second word line, and a second bit line. The first word line is connected to the first electrode, the first bit line is connected to the second electrode, the second word line is connected to the second gate, and the second bit line is connected to the fourth electrode. The first word line, the first bit line, the second word line, and the second bit line extend in at least three directions, the three extension directions intersect each other, and all three extension directions are horizontal.

2. The storage structure according to claim 1, characterized in that, The first transistor and the second transistor have an overlapping region in their orthogonal projections onto the substrate, the second transistor is located on the side of the first transistor away from the substrate, and both the first transistor and the second transistor are vertical transistors.

3. The storage structure according to claim 2, characterized in that, The first gate is located on the substrate and is columnar; the first electrode is located on the side of the first gate closer to the substrate, and the second electrode is located on the side of the first electrode away from the substrate. The first transistor further includes: The first semiconductor layer is located outside the first gate and is insulated from the first gate; The first electrode is connected to the first semiconductor layer; the second electrode is connected to the first semiconductor layer; The second gate is located on the side of the first gate away from the substrate, and the second gate is columnar; the third electrode is located on the side of the second gate close to the substrate, and the fourth electrode is located on the side of the third electrode away from the substrate; The second transistor also includes: The second semiconductor layer is located outside the second gate and is insulated from the second gate; The third electrode is connected to the second semiconductor layer; the fourth electrode is connected to the second semiconductor layer.

4. The storage structure according to claim 1, characterized in that, Two of the first character line, the first position line, the second character line, and the second position line extend in the same direction.

5. The storage structure according to claim 4, characterized in that, The first word line, the first bit line, the second word line, and the second bit line are four signal lines, and the first word line, the first bit line, the second word line, and the second bit line are located in different signal line layers. The two signal lines located in adjacent signal line layers have different extension directions.

6. The storage structure according to claim 5, characterized in that, The extension direction of the first character line intersects the extension direction of the first bit line, the extension direction of the second character line intersects the extension direction of the second bit line, and the extension direction of one of the first character line and the first bit line is the same as the extension direction of one of the second character line and the second bit line.

7. The storage structure according to claim 6, characterized in that, One of the first word line and the first bit line partially overlaps with the orthographic projection of one of the second word line and the second bit line onto the substrate, and partially does not overlap.

8. The storage structure according to claim 6, characterized in that, The extension direction of one of the first word line and the first bit line intersects the extension direction of the other of the second word line and the second bit line.

9. The storage structure according to claim 3, characterized in that, The third electrode is in contact with the first gate.

10. The storage structure according to claim 3, characterized in that, It also includes a first electrode plate, a second electrode plate, and an insulating layer disposed between the first electrode plate and the second electrode plate. The first electrode plate is connected to the first gate, and the second electrode plate is connected to the third electrode. The first electrode plate and the second electrode plate form a storage capacitor.

11. The storage structure according to any one of claims 1 to 10, characterized in that, The storage unit group includes a first storage unit, a second storage unit, a third storage unit, a fourth storage unit, a fifth storage unit, a sixth storage unit, and a seventh storage unit. The second storage unit, the third storage unit, the fourth storage unit, the fifth storage unit, the sixth storage unit, and the seventh storage unit are arranged around the first storage unit. The line connecting the geometric centers of the second storage unit, the third storage unit, the fourth storage unit, the fifth storage unit, the sixth storage unit, and the seventh storage unit on the orthographic projection of the substrate is hexagonal.

12. The storage structure according to claim 11, characterized in that, The hexagon is a regular hexagon.

13. The storage structure according to any one of claims 1 to 10, characterized in that, The channels of the first transistor and the second transistor in the memory cell are both full-around channels.

14. An electronic device, characterized in that, Includes the storage structure described in any one of claims 1 to 13.

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