Display panel and display terminal

Abstract

The application relates to a display panel and a display terminal, wherein the display panel comprises: a pixel driving circuit layer comprising a plurality of pixel driving circuits; a wiring layer comprising a first VSS wiring and a touch wiring, the touch wiring being electrically connected to a corresponding touch electrode; and a light emitting device layer comprising a plurality of light emitting devices electrically connected to the plurality of pixel driving circuits, each light emitting device comprising an anode, a cathode and a light emitting part electrically connected between the anode and the cathode, the cathode being electrically connected to the first VSS wiring; the display panel further comprises a second VSS wiring, the second VSS wiring being electrically connected to the first VSS wiring and being arranged in a layer different from the first VSS wiring and the touch wiring. By electrically connecting the second VSS wiring to the first VSS wiring and arranging the second VSS wiring in a layer different from the first VSS wiring and the touch wiring, the application can avoid the VSS signal and the touch signal being accessed in the same layer, reduce the short circuit risk, achieve the design requirement of a narrow frame, be compatible with the existing display panel design, and have high flexibility.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display terminal. Background Technology

[0002] In related technologies, Active-Matrix Organic Light-Emitting Diode (AMOLED) display panels are mainly divided into light-emitting components and touch components. The light-emitting components typically use metal bonding from the side of the screen to input VSS signals, while the touch components are routed above the encapsulation layer using either On-Cell or external bonding modes. If the light-emitting components use an in-plane bonding (VSS in AA) scheme and the touch components use an in-cell touch (In-Cell Touch) scheme, the touch traces and VSS signal lines may be on the same layer. Due to the structural limitations of narrow bezel designs, it is almost impossible to design the touch traces and VSS signal lines on the same layer. This poses a short-circuit risk between different signal lines and affects the design requirements of narrow bezels, resulting in poor compatibility of the display panel design. Summary of the Invention

[0003] In view of this, this application proposes a display panel and display terminal that can access the VSS signal through a second VSS trace on a different layer than the first VSS trace. This avoids the VSS signal and touch signal being accessed on the same layer, reducing the risk of short circuits between the VSS trace and the touch trace. Furthermore, since the VSS signal can be accessed through the second VSS trace instead of from the sides of the panel, the bezel size of the display panel can be reduced, achieving the design requirement of a narrow bezel. In addition, since there is ample implementation space and high flexibility in setting the second VSS trace on a different layer from both the first VSS trace and the touch trace, it can be implemented through various schemes without affecting the pixel driving circuit or the touch component, and is compatible with existing display panel structural designs.

[0004] According to one aspect of this application, a display panel is provided, the display panel comprising: a pixel driving circuit layer including a plurality of pixel driving circuits; a wiring layer located on the pixel driving circuit layer, including a first VSS wiring and a touch wiring, the touch wiring being electrically connected to a corresponding touch electrode; and a light-emitting device layer located on the wiring layer, including a plurality of light-emitting devices electrically connected to the plurality of pixel driving circuits, each of the light-emitting devices including an anode, a cathode, and a light-emitting portion electrically connected between the anode and the cathode, the cathode being electrically connected to the first VSS wiring; wherein, the display panel further includes a second VSS wiring, the second VSS wiring being electrically connected to the first VSS wiring and disposed on a different layer from both the first VSS wiring and the touch wiring.

[0005] Furthermore, the pixel driving circuit layer includes a semiconductor layer, which includes active patterns of transistors of the pixel driving circuit and the second VSS trace.

[0006] Furthermore, the resistivity of the second VSS trace is less than the resistivity of the channel region of the active pattern.

[0007] Furthermore, the pixel driving circuit layer also includes a conductive layer, which includes the source pattern, drain pattern, and connection portion of the transistor, and the connection portion is electrically connected between the first VSS trace and the second VSS trace.

[0008] Furthermore, the conductive layer also includes a first VDD trace and a second VDD trace, which are arranged crosswise and electrically connected to each other.

[0009] Furthermore, the light-emitting device layer includes an anode layer, which includes the anode and the touch electrode.

[0010] Furthermore, the first VSS trace and the second VSS trace are arranged to cross each other, and the second VSS trace and the touch trace are arranged to cross each other.

[0011] Furthermore, the pixel driving circuit layer includes data lines electrically connected to the pixel driving circuit, the touch traces are parallel to the data lines, and the number of touch traces is less than or equal to the number of data lines.

[0012] Furthermore, the routing layer also includes a reset signal line electrically connected to the pixel driving circuit, the reset signal line being parallel to the first VSS routing line.

[0013] According to another aspect of this application, a display terminal is provided, the display terminal including a terminal body and a display panel, the terminal body being connected to the display panel.

[0014] By electrically connecting the second VSS trace to the first VSS trace and setting it to a different layer from both the first VSS trace and the touch trace, according to various aspects of this application, the VSS signal can be accessed through the second VSS trace, which is on a different layer from the first VSS trace. This avoids the VSS signal and the touch signal being accessed on the same layer, reducing the risk of short circuits between the VSS trace and the touch trace. Furthermore, since the VSS signal can be accessed through the second VSS trace instead of from the sides of the panel, the bezel size of the display panel can be reduced, achieving the design requirement of a narrow bezel. In addition, since setting the second VSS trace to a different layer from both the first VSS trace and the touch trace provides ample implementation space and high flexibility, it can be implemented through various schemes without affecting the pixel driving circuit or the touch section, and is compatible with existing display panel structural designs. Attached Figure Description

[0015] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0016] Figure 1 This is a schematic diagram of a first structure of a display panel according to an embodiment of this application.

[0017] Figure 2 This is a schematic diagram of a second structure of a display panel according to an embodiment of this application.

[0018] Figure 3 A wiring diagram of a display panel according to an embodiment of this application is shown. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0020] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0022] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials. In some instances, methods, means, elements, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of this application.

[0023] This application primarily provides a display panel, which can be an Organic Light-Emitting Diode (OLED) display panel. Preferably, since Active-Matrix Organic Light-Emitting Diodes (AMOLEDs) are driven in an active manner, the power line arrangement is complex. To adapt to the design requirements of narrow bezels and improve the compatibility of panel designs, this application is particularly suitable for AMOLED display panels. The following description will use an OLED display panel as an example, but those skilled in the art should understand that the applicability of this application is not limited to this.

[0024] Specifically, the display panel of this application may include a pixel driving circuit layer, a wiring layer, and a light-emitting device layer. The wiring layer is located on the pixel driving circuit layer, and the light-emitting device layer is located on the wiring layer. That is, the pixel driving circuit layer, the wiring layer, and the light-emitting device layer may be stacked sequentially.

[0025] The pixel driving circuit layer may include multiple pixel driving circuits, which may have structures such as 2T1C or 3T1C. Taking a 2T1C circuit as an example, the pixel driving circuit may include a switching transistor, a driving transistor, and a capacitor. The gate of the switching transistor is electrically connected to the scan line, the source of the switching transistor is electrically connected to the data line, and the gate of the driving transistor is electrically connected to the drain of the switching transistor. The drain of the driving transistor is electrically connected to a preset power supply, and the source of the driving transistor is electrically connected to the light-emitting device in the light-emitting device layer to drive the light-emitting device to emit light. One end of the capacitor is electrically connected to the gate of the driving transistor. When the scan line is high, the switching transistor is in the conducting state. At this time, the data signal on the data line is transmitted to the gate of the driving transistor, thereby controlling the driving transistor to conduct, so that the light-emitting device emits light. When the driving transistor is continuously switching on and off, the capacitor can store electrical charge, allowing the light-emitting device to emit light continuously.

[0026] Furthermore, the routing layer may include a first VSS trace and a touch trace, the touch trace being electrically connected to a corresponding touch electrode. The first VSS trace can be used to transmit the VSS signal on the cathode. In practical applications, the first VSS trace may be a low power supply voltage trace, the VSS voltage on which can be 0V, or a low power supply voltage close to 0V, such as 0.5V.

[0027] In one embodiment, the touch trace can be used to transmit touch signals. The touch trace can be electrically connected to the touch electrodes of the display panel, and the touch electrodes are coupled to corresponding electrodes in the display panel. The coupling method can be self-capacitance or mutual capacitance. For example, when a finger presses on the screen of the display panel, the touch signal on the touch trace changes, thereby locating the position of the finger touch based on the change in the touch signal, thus realizing the touch function. It should be understood that the touch function of the display panel can be implemented in various possible ways, and this application does not limit how the touch function of the display panel is specifically implemented.

[0028] Furthermore, the light-emitting device layer includes multiple light-emitting devices electrically connected to multiple pixel driving circuits, each light-emitting device including an anode, a cathode, and a light-emitting portion electrically connected between the anode and the cathode. The light-emitting device can emit light of colors such as red, green, or blue. In this application, the pixel driving circuit can drive at least one of the light-emitting devices. The number of light-emitting devices driven by the pixel driving circuit can be set as needed, and this application is not limited in this regard. For example, each pixel driving circuit drives one light-emitting device.

[0029] In one embodiment, the wiring layer further includes a first anode wiring, the anode being electrically connected to the first anode wiring, the first anode wiring being electrically connected to the source or drain of the driving transistor, and the cathode being electrically connected to the first VSS wiring. Multiple first VSS wirings are parallel to each other.

[0030] To more clearly illustrate the relationship between the various traces in the display panel, the following will combine... Figure 1 Let's take an example to illustrate. Figure 1 This diagram illustrates a first structural design of a display panel according to an embodiment of this application. See also... Figure 1 The display panel may include a substrate 1, a buffer layer 2, a gate insulating layer 3, an inner matrix layer 4, an interlayer insulating layer 5, a first planarization layer 6, a second planarization layer 7, and a pixel definition layer 8, which are stacked sequentially. The second planarization layer 7 and the pixel definition layer 8 are both patterned. The pixel driving circuit layer, the wiring layer, and the light-emitting device layer may be stacked on the aforementioned layers of the display panel as needed.

[0031] The light-emitting device layer includes an anode layer, which comprises the anode and the touch electrode. See also... Figure 1The anode 81 is electrically connected to the first anode trace 72 through a connection hole 810. The anode can be patterned, and anodes 82 and 81 can be components of the anode pattern. Anode 82 can be electrically connected to anode 81. The touch electrode 83 is electrically connected to the touch trace 73 through a connection hole 830. Anodes 81, 82, and 83 are arranged at intervals in the same layer. For example, anodes 81, 82, and 83 can be disposed on the second planarization layer 7.

[0032] Furthermore, the display panel also includes a second VSS trace 31, which is electrically connected to the first VSS trace 71 and is disposed on a different layer from both the first VSS trace 71 and the touch trace 73. By electrically connecting the second VSS trace to the first VSS trace and disposing it on a different layer from both the first VSS trace and the touch trace, this embodiment of the application can access the VSS signal through the second VSS trace, which is on a different layer from the first VSS trace. This avoids the VSS signal and the touch signal being accessed on the same layer, reducing the risk of short circuit between the VSS trace and the touch trace. At the same time, since the VSS signal can be accessed through the second VSS trace instead of from the sides of the panel, the bezel size of the display panel can be reduced, achieving the design requirement of a narrow bezel. In addition, since there is ample room for implementation in disposing the second VSS trace on a different layer from both the first VSS trace and the touch trace, it is highly flexible and can be implemented through various schemes. Moreover, it does not affect the pixel driving circuit or the touch part, and can be well compatible with the existing display panel structural design.

[0033] Furthermore, the pixel driving circuit layer includes a semiconductor layer, which includes an active pattern of transistors for the pixel driving circuit and the second VSS trace. The second VSS trace is disposed on the same layer as the active pattern. For example, in Figure 1 In this embodiment, both the second VSS trace 31 and the active pattern 34 are disposed on the buffer layer 2. The second VSS trace 31 can be made of the same material as the active pattern 34, such as polycrystalline silicon. By disposing the second VSS trace and the active pattern on the same layer, this embodiment can reuse existing array processes while achieving a narrow bezel design, thereby reducing the process flow for manufacturing the display panel and improving the compatibility of display panel production.

[0034] In one embodiment, the resistivity of the second VSS trace is less than the resistivity of the channel region of the active pattern. In this embodiment, to enable a more stable electrical connection between the second VSS trace and the first VSS trace, when the second VSS trace uses the same semiconductor material as the active pattern, the doping concentration of the second VSS trace is higher than the doping concentration of the channel region of the active pattern, thereby making the resistivity of the second VSS trace less than the resistivity of the channel region of the active pattern, thus improving the conductivity of the second VSS trace.

[0035] In one embodiment, the pixel driving circuit layer further includes a conductive layer, the conductive layer including the source pattern, drain pattern, and connection portion of the transistor, the connection portion being electrically connected between the first VSS trace and the second VSS trace. Figure 1 For example, the conductive layer may include the source pattern 62, the drain pattern 63, and the connection portion 61 of the transistor. The source pattern 62, the drain pattern 63, and the connection portion 61 are disposed in the same layer and are all located on the interlayer insulating layer.

[0036] The positions of the source pattern 62 and the drain pattern 63 can be interchanged, depending on whether the transistor is actually N-type or P-type. Therefore, in other embodiments... Figure 1 62 can also be a drain pattern, and 63 can also be a source pattern. It should be understood that the positional arrangement of the source pattern 62 and the drain pattern 63 is exemplary.

[0037] The connection portion 61 is electrically connected between the first VSS trace 71 and the second VSS trace 31. The connection portion 61 can be electrically connected to the first VSS trace 71 through a connection hole 710, which is an inverted trapezoidal structure and penetrates the first planarization layer 6. The connection portion 61 can also be electrically connected to the second VSS trace 31 through the connection hole 610, which is also an inverted trapezoidal structure and sequentially penetrates the gate insulating layer 3, the inner matrix layer 4, and the interlayer insulating layer 5. In other words, the connection portion 61 acts as a connection intermediary between the first VSS trace 71 and the second VSS trace 31. Compared to directly connecting the first VSS trace 71 and the second VSS trace 31, this makes the connection between the first VSS trace 71 and the second VSS trace 31 more stable and reduces the risk of connection interruption.

[0038] In one embodiment, such as Figure 1As shown, the orthographic projection of the connecting portion 61 on the substrate 1 completely overlaps with the orthographic projection of the second trace 31 on the substrate 1. The size of the connecting portion 61 is the same as the size of the second VSS trace 31. The size of the second VSS trace 31 can be manufactured according to the size of the source pattern 62 or the drain pattern 63. This allows for the mass production of the connecting portion 61 and the second VSS trace 31 based on existing processes, improving the manufacturing efficiency of the display panel. Furthermore, the orthographic projection of the first VSS trace 71 on the substrate 1 can partially overlap with the orthographic projection of the connecting portion 61 on the substrate 1. The size of the first VSS trace 71 is larger than the size of the connecting portion 61 to increase the width of the first VSS trace, improve its anti-interference capability, and make the VSS signal on the first VSS trace more stable.

[0039] In one embodiment, the source pattern is electrically connected to the source electrode portion of the transistor, and the drain pattern is electrically connected to the drain electrode portion of the transistor. For example, in Figure 1 In this configuration, the source pattern 62 is electrically connected to the source electrode portion 32 of the transistor via a connection hole 620, and the drain pattern 63 is electrically connected to the drain electrode portion 33 of the transistor via a connection hole 630. The active pattern 34 is located between the source electrode portion 32 and the drain electrode portion 33. The source electrode portion 32, the drain electrode portion 33, the active pattern 34, and the second VSS trace 31 are all disposed on the same layer.

[0040] In one embodiment, the conductive layer further includes a first VDD trace and a second VDD trace, which are intersected and electrically connected to each other to form a mesh structure. For example, the first VDD trace 64 may be disposed to the left of the drain pattern 63 and disposed on the same layer as the drain pattern. The first VDD trace 64 and the second VDD trace ( Figure 1 (Not shown) can all be high power supply voltage traces used to transmit high power supply voltage signals from the pixel driving circuit, such as 1.8V, 3.3V, etc. Crossing the first VDD trace and electrically connecting them to each other helps to organize the high power supply voltage signal traces, quickly deliver the high power supply voltage signals to different pixel driving circuits, and reduce the signal delay caused by excessively long power supply traces.

[0041] In one embodiment, the first VSS trace and the second VSS trace are arranged to cross each other, and the second VSS trace and the touch trace are also arranged to cross each other. The first VSS trace and the touch trace are arranged parallel to each other. By arranging the first VSS trace and the second VSS trace to cross each other, and the second VSS trace and the touch trace to cross each other, crosstalk between the first VSS trace and the second VSS trace can be further reduced, while crosstalk between the second VSS trace and the touch trace can be reduced, thereby improving the stability of the display panel operation.

[0042] In one embodiment, reference Figure 1 The pixel driving circuit layer may further include a gate layer and a data signal layer. The gate layer includes a gate trace 41, which is used to transmit a scan signal, which may be a row scan signal. The data signal layer includes a data signal trace 51, which is used to transmit a data signal to drive the corresponding light-emitting device to emit light.

[0043] Furthermore, such as Figure 1 As shown, the routing layer also includes a reset signal line 74 electrically connected to the pixel driving circuit, and the reset signal line 74 is parallel to the first VSS routing line 71. For example, the reset signal line 74 can be electrically connected to the anode via a switch to reset the pixel driving circuit in case of an abnormality.

[0044] Figure 2 A second structural schematic diagram of a display panel according to an embodiment of this application is shown. For example... Figure 2 As shown, in another embodiment, Figure 1 The second VSS trace 31 can be replaced with a third VSS trace 21. The third VSS trace is electrically connected to the first VSS trace and is disposed on a different layer from both the first VSS trace and the touch trace. Figure 1 The difference is that the third VSS trace 21 is located on the substrate 1.

[0045] In one example, the third VSS trace can be used with a light-shielding layer (BSM). Figure 2The third VSS trace (not shown) is made of the same material as the first VSS trace and is disposed in the same layer as the light-shielding layer. The third VSS trace can be appropriately extended downward with reference to the first VSS trace, and other settings of the third VSS trace can be adaptively adjusted with reference to the first VSS trace. In another example, if other transistors are disposed below the driving transistor layer, the third VSS trace can also be appropriately adjusted downward with reference to the other transistors, and the same material as the channel layer of the active pattern of the other transistors is used. It should be noted that since the source electrode portion 32 and the drain electrode portion 33 of the driving transistor layer are disposed on the buffer layer, in order to avoid the third VSS trace interfering with the traces above the source electrode portion 32 and the drain electrode portion 33 of the driving transistor layer, the third VSS trace is extended downward with reference to the first VSS trace as much as possible, rather than shortened upward. It is understood that in practical applications, other modifications may exist in the above embodiments, and this application does not limit the specific location of the third VSS trace.

[0046] Figure 3 This diagram illustrates the wiring of a display panel according to an embodiment of this application. Please refer to... Figure 3 Viewed from above, the display panel comprises an array of pixel units arranged in rows and columns. Each pixel unit includes a red sub-pixel unit R, a green sub-pixel unit G, and a blue sub-pixel unit B. The four red sub-pixel units R are located at the vertices of a square grid, the green sub-pixel units G are located at the midpoints of each side of the square grid, and the blue sub-pixel units B are located at the intersection of the diagonals of the square grid. Each sub-pixel unit is equipped with a light-emitting component.

[0047] Combination Figure 1 and Figure 3 The first VSS trace 71 can be arranged vertically. The first VSS trace 71, the first VDD trace 64, the reset signal line 74, and the data signal trace 51 are parallel to each other. The first VSS trace 71, the first VDD trace 64, the reset signal line 74, and the data signal trace 51 are all connected to the sub-pixel units in the corresponding columns of the pixel unit array. The touch trace 73 is arranged parallel to the first VSS trace 71 and is disposed between two adjacent columns of sub-pixel units.

[0048] See also Figure 1 and Figure 3The second VSS trace 31 can be arranged horizontally, and the second VSS trace 31, the gate trace 41, and the second VDD trace 65 are parallel to each other. The second VSS trace 31, the gate trace 41, and the second VDD trace 65 are all connected to the sub-pixel units in the corresponding rows of the pixel unit array. The second VSS trace 31 is disposed between every two adjacent rows of sub-pixel units. The second VSS trace 31 intersects with the first VSS trace 71 and is electrically connected through a CNT hole 30. The CNT hole can be a collective term for the connection hole 710, the connection portion 61, and the connection hole 610.

[0049] In one embodiment, the pixel driving circuit layer includes data lines electrically connected to the pixel driving circuit, the touch traces are parallel to the data lines, and the number of touch traces is less than or equal to the number of data lines. For example, see... Figure 3 Each pair of adjacent touch traces 73 is spaced by three columns of sub-pixel units, with one touch trace positioned every three columns of sub-pixel units; each column of sub-pixel units corresponds to one data line. Therefore, the number of touch traces is less than or equal to the number of data lines, which reduces the number of touch traces and the bezel of the display panel, thus meeting the design requirements for narrow bezels of the display panel.

[0050] In summary, this application, by electrically connecting the second VSS trace to the first VSS trace and setting it to a different layer from both the first VSS trace and the touch trace, enables the VSS signal to be accessed through the second VSS trace, which is on a different layer from the first VSS trace. This avoids the VSS signal and touch signal being accessed on the same layer, reducing the risk of short circuits between the VSS trace and the touch trace. Furthermore, since the VSS signal can be accessed through the second VSS trace instead of from the sides of the panel, the bezel size of the display panel can be reduced, achieving the design requirement of a narrow bezel. In addition, since the second VSS trace is set to a different layer from both the first VSS trace and the touch trace, there is ample room for implementation, high flexibility, and multiple solutions can be used. It also has no impact on the pixel driving circuit and the touch section, and is compatible with existing display panel structural designs.

[0051] Furthermore, this application also provides a display terminal, which includes a terminal body and a display panel, wherein the terminal body is connected to the display panel. It is understood that this application does not limit the specific application scenarios of the display terminal.

[0052] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0053] The display panel and display terminal provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, The display panel includes: The pixel driving circuit layer includes multiple pixel driving circuits; A routing layer, located on the pixel driving circuit layer, includes a first VSS routing line and a touch routing line arranged parallel to each other, wherein the touch routing line is electrically connected to a corresponding touch electrode; and The light-emitting device layer, located on the wiring layer, includes multiple light-emitting devices electrically connected to multiple pixel driving circuits. Each light-emitting device includes an anode, a cathode, and a light-emitting part electrically connected between the anode and the cathode. The cathode is electrically connected to the first VSS wiring. The display panel further includes multiple sub-pixel units and a second VSS trace. Each sub-pixel unit is provided with a light-emitting part. The touch trace is disposed between two adjacent columns of sub-pixel units. The second VSS trace is disposed between two adjacent rows of sub-pixel units. The second VSS trace is electrically connected to the first VSS trace and is disposed on a different layer from both the first VSS trace and the touch trace.

2. The display panel according to claim 1, characterized in that, The pixel driving circuit layer includes a semiconductor layer, which includes active patterns of transistors of the pixel driving circuit and the second VSS trace.

3. The display panel according to claim 2, characterized in that, The resistivity of the second VSS trace is less than the resistivity of the channel region of the active pattern.

4. The display panel according to claim 2, characterized in that, The pixel driving circuit layer further includes a conductive layer, which includes the source pattern, drain pattern, and connection portion of the transistor. The connection portion is electrically connected between the first VSS trace and the second VSS trace.

5. The display panel according to claim 4, characterized in that, The conductive layer also includes a first VDD trace and a second VDD trace, which are arranged crosswise and electrically connected to each other.

6. The display panel according to claim 1, characterized in that, The light-emitting device layer includes an anode layer, which includes the anode and the touch electrode.

7. The display panel according to claim 1, characterized in that, The first VSS trace and the second VSS trace are arranged to cross each other, and the second VSS trace and the touch trace are arranged to cross each other.

8. The display panel according to claim 7, characterized in that, The pixel driving circuit layer includes data lines electrically connected to the pixel driving circuit, the touch traces are parallel to the data lines, and the number of touch traces is less than or equal to the number of data lines.

9. The display panel according to claim 1, characterized in that, The routing layer also includes a reset signal line electrically connected to the pixel driving circuit, and the reset signal line is parallel to the first VSS routing line.

10. A display terminal, characterized in that, The display terminal includes a terminal body and a display panel as described in any one of claims 1 to 9, wherein the terminal body is connected to the display panel.

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