Power amplifier and high frequency module

Abstract

A power amplifier of the present disclosure is provided with: an input terminal which is inputted with a high frequency signal from the outside; an MMIC which is inputted with the high frequency signal via the input terminal and amplifies the high frequency signal; an input matching circuit; a transistor which is inputted with the high frequency signal amplified by the MMIC via the input matching circuit and amplifies the high frequency signal; an output matching circuit; an output terminal which is inputted with a drain voltage of the transistor from the outside, is inputted with the high frequency signal amplified by the transistor via the output matching circuit, and outputs the high frequency signal to the outside; and a drain bias circuit substrate which connects a drain of the transistor and a drain of the MMIC, the transistor and the MMIC being conjugately matched with an impedance of less than 50 Ω.

Description

Technical Field

[0001] This disclosure relates to power amplifiers and high-frequency modules. Background Technology

[0002] Non-patent document 1 discloses a GaN-based MMIC (Monolithic Microwave Integrated Circuit). This MMIC achieves a high output of 50W in the Ku-band.

[0003] Non-Patent Literature 1: QORVO, TGA2239-CP, 13.4-15.5GHz, 50Watt, GaN Power Amplifier, Product Data Sheet, Rev. B, February 2021, <URL: https: / / www.qorvo.com / products / p / TGA2239-CP>

[0004] In high-frequency modules used in small ground stations for satellite communications, typically in the 14GHz band, semiconductor power amplifiers are commonly employed for miniaturization. These high-frequency modules typically have a high output of 40–100W. Therefore, the semiconductor power amplifier in the final stage of the high-frequency module's transmitting circuit primarily uses an internally matched FET (Field Effect Transistor). In the driver stage, either an internally matched FET or a MMIC is typically used.

[0005] For example, in the case of a high-frequency module with an output of 70W, a 70W-level internally matched FET is used in the final stage. Such a high-frequency module may also include, for example, a 50W-level internally matched FET driving the 70W-level internally matched FET, and a 30W-level internally matched FET located before the 50W-level internally matched FET. There are also cases where the 30W-level amplifier uses an MMIC.

[0006] Typically, internally matched FETs are matched to 50Ω on both the input and output sides. Therefore, inter-stage matching circuits are not required. However, peripheral circuits such as bias circuits for RF (Radio Frequency) / DC (Direct Current) separation circuits or coupling capacitors to separate the bias circuits of preceding and following stages from the DC circuit are considered necessary. This could potentially increase the overall size of the high-frequency module. In particular, internally matched FETs are single-stage amplifiers with a gain of around 10dB. Therefore, multi-stage high-frequency modules could potentially lead to a significant increase in size.

[0007] Furthermore, with the increasing output of MMICs, as shown in Non-Patent Document 1, high-output MMICs exceeding 50W have been achieved in the Ku band. MMICs can be constructed from multi-stage amplifiers; that is, the final stage and driver stage can be integrated into a single MMIC. Therefore, miniaturization of high-frequency modules is possible. However, the SiC substrates used in GaN-MMICs are typically very expensive, potentially increasing manufacturing costs.

[0008] Alternatively, consider combining a mid-output MMIC with a high-output internally matched FET and integrating them into a single package. In this case, the package size may also increase due to the matching circuitry between the MMIC and the internally matched FET. Summary of the Invention

[0009] The purpose of this disclosure is to obtain power amplifiers and high-frequency modules that can be miniaturized.

[0010] The power amplifier disclosed herein comprises: an input terminal for receiving a high-frequency signal from the outside; a microcontroller (MMIC) for receiving the high-frequency signal via the input terminal and amplifying the high-frequency signal; an input matching circuit; a transistor for receiving the amplified high-frequency signal from the MMIC via the input matching circuit and amplifying the high-frequency signal; an output matching circuit; an output terminal for receiving the drain voltage of the transistor from the outside, receiving the amplified high-frequency signal from the transistor via the output matching circuit, and outputting the high-frequency signal to the outside; and a drain bias circuit board for connecting the drain of the transistor to the drain of the MMIC, wherein the transistor and the MMIC are conjugate matched with an impedance of less than 50Ω.

[0011] In the power amplifier disclosed herein, the transistor and MMIC are conjugate matched with an impedance of less than 50Ω. This enables the miniaturization of the power amplifier. Attached Figure Description

[0012] Figure 1 This is a diagram illustrating the structure of the high-frequency module in Embodiment 1.

[0013] Figure 2 This is a top view of the power amplifier in Implementation Method 1.

[0014] Figure 3 This is a top view illustrating the detailed structure of the power amplifier in Embodiment 1.

[0015] Figure 4 This is the equivalent circuit diagram of the MMIC in Implementation Method 1.

[0016] Figure 5 This is a diagram showing the structure of the gate bias circuit and the drain bias circuit in Embodiment 1.

[0017] Figure 6 This is a diagram showing the structure of the drain bias circuit board of a modified embodiment 1.

[0018] Figure 7 This is a diagram showing the stabilization circuit of Implementation Method 1.

[0019] Figure 8 This is a diagram illustrating the structure of the high-frequency module in the comparative example of Embodiment 1.

[0020] Figure 9 This is a top view of the power amplifier in Embodiment 2.

[0021] Figure 10 This is a diagram showing the structure of the drain bias circuit in Embodiment 2.

[0022] Figure 11 This is the equivalent circuit diagram of the voltage divider circuit in Implementation Method 3.

[0023] Figure 12 This is a top view of the power amplifier in embodiment 4.

[0024] Figure 13 This is a top view of the power amplifier in embodiment 5.

[0025] Figure 14 This is a top view of the power amplifier of a modified embodiment 5. Detailed Implementation

[0026] Referring to the accompanying drawings, the power amplifiers and high-frequency modules of each embodiment will be described. There are instances where the same or corresponding components are labeled with the same reference numerals, and repeated descriptions are omitted.

[0027] Implementation method 1.

[0028] Figure 1 This is a diagram illustrating the structure of the high-frequency module 100 according to Embodiment 1. The high-frequency module 100 includes a power amplifier 10, a gate bias circuit 80 that supplies a gate voltage to the power amplifier 10, and a drain bias circuit 90 that supplies a drain voltage to the power amplifier 10. The power amplifier 10, for example, has a Ku-band frequency and an output in the 70W range.

[0029] Figure 2 This is a top view of the power amplifier 10 according to Embodiment 1. The power amplifier 10 has only an input terminal 11 and an output terminal 12 as terminals. A high-frequency signal is input to the input terminal 11 from the outside via a gate bias circuit 80. In addition, the gate voltage of the MMIC 20 is input to the input terminal 11 from the gate bias circuit 80.

[0030] The MMIC 20 receives a high-frequency signal via input terminal 11 and amplifies the high-frequency signal. The power amplifier 10, serving as the MMIC 20, includes MMIC 20a and MMIC 20b. An input matching circuit 30 is connected to the output of the MMIC 20. The power amplifier 10, serving as the input matching circuit 30, includes an input matching circuit 30a connected to MMIC 20a and an input matching circuit 30b connected to MMIC 20b.

[0031] A transistor 40 is connected to the output of the input matching circuit 30. The transistor 40 receives and amplifies the high-frequency signal amplified by the MMIC 20 via the input matching circuit 30. The power amplifier 10, acting as transistor 40, includes transistor 40a connected to the input matching circuit 30a and transistor 40b connected to the input matching circuit 30b. Transistor 40a amplifies the high-frequency signal amplified by the MMIC 20a. Transistor 40b amplifies the high-frequency signal amplified by the MMIC 20b. Transistors 40a and 40b are each transistor chips. An output matching circuit 50 is connected to the output of transistor 40.

[0032] The high-frequency signal amplified by the input transistor 40 is received at output terminal 12 via output matching circuit 50, and then output to the outside via drain bias circuit 90. Additionally, the drain voltage of transistor 40 is input to output terminal 12 from drain bias circuit 90.

[0033] The drain bias circuit board 60 connects the drain of transistor 40 to the drain of MMIC 20. The power amplifier 10, as the drain bias circuit board 60, includes drain bias circuit boards 60a and 60b. Drain bias circuit board 60a connects the drain of transistor 40a to the drain of MMIC 20a. Drain bias circuit board 60b connects the drain of transistor 40b to the drain of MMIC 20b. The drain bias circuit boards 60a and 60b are disposed outside the region where transistors 40a and 40b are disposed.

[0034] Hereinafter, the path from input terminal 11 through MMIC 20a and transistor 40a to output terminal 12 is referred to as the first path 10a. The path from input terminal 11 through MMIC 20b and transistor 40b to output terminal 12 is referred to as the second path 10b.

[0035] Figure 3 This is a top view illustrating the detailed structure of the power amplifier 10 according to Embodiment 1. The power amplifier 10 is a three-stage amplifier. Specifically, the power amplifier 10 is composed of an MMIC 20 consisting of a two-stage amplifier and a first-stage transistor 40.

[0036] The power amplifier 10 includes an output matching circuit 50a connected to transistor 40a and an output matching circuit 50b connected to transistor 40b, which serve as the output matching circuit 50. The output matching circuit 50a comprises two matching circuit substrates 51a and 55a. Similarly, the output matching circuit 50b comprises two matching circuit substrates 51b and 55b. The output matching circuits 50a and 50b combine signals input from the plurality of transistor units 42 and output them to the output terminal 12 via wire 13.

[0037] Matching circuit substrates 51a and 51b each have a substrate 52 and a pattern 53 formed on the substrate 52. In the matching circuit substrates 51a and 51b connected to the transistor 40, a titanium oxide substrate with a dielectric constant of approximately 40 is used as the substrate 52. Typically, a low-impedance line is required in the matching circuit immediately following the transistor. Therefore, a low-impedance line is achieved using a titanium oxide substrate with a relatively high dielectric constant. Furthermore, using a high-dielectric-constant substrate with a relative dielectric constant of approximately 40 allows for a narrower line width. This enables miniaturization of the circuit size.

[0038] Matching circuit substrates 55a and 55b each have a substrate 56 and a pattern 57 formed on the substrate 56. The substrate 56 is, for example, an alumina substrate with a dielectric constant of about 10.

[0039] In each transistor 40a and 40b, a plurality of transistor units 42 are formed on a substrate 41. The substrate 41 is, for example, a SiC substrate. The transistor units 42 are, for example, formed of GaN-based compound semiconductors. A pre-matching circuit 43 is formed on the gate side of each transistor unit 42. The pre-matching circuit also serves as a high-order harmonic processing circuit and a stabilization circuit. This improves the efficiency of the transistor 40 and stabilizes its operation.

[0040] Input matching circuits 30a and 30b each have a substrate 31 and a pattern 32 formed on the substrate 31. In input matching circuit 30, signals from the outputs of MMIC 20 are distributed to three transistor units 42. Input matching circuits 30a and 30b match MMIC 20a and 20b with transistors 40a and 40b at an impedance of 24Ω. Typically, in input matching circuits, conjugate matching is performed at 50Ω. In contrast, in this embodiment, matching is performed at approximately half of that impedance. Alternatively, a circuit with the same characteristics as input matching circuit 30 can be formed on transistor 40 or MMIC 20. In this case, input matching circuit 30 can be omitted.

[0041] The MMIC20 has a substrate 28 and a two-stage amplifier formed on the substrate 28. The substrate 28 is, for example, a SiC substrate. Figure 4This is an equivalent circuit diagram of MMIC 20 according to Embodiment 1. MMIC 20a and 20b are each a chip. MMIC 20 is composed of output-side circuit 26, second-stage transistors Tr22a to Tr22d, inter-stage circuit 25, first-stage transistors Tr21a and Tr21b, and input-side circuit 24. Tr21a to Tr21b and Tr22a to Tr22d are, for example, formed of GaN-based compound semiconductors. Furthermore, in Figure 4 The distributed constant circuit, matching circuit, stabilization circuit, etc. are omitted.

[0042] The output-side circuit 26 consists of a main line, a quarter-wavelength line 27 serving as a short stub, a capacitor C21, a coupling capacitor C22, and bonding pads. Capacitor C21 is a MIM (Metal-Insulator-Metal) capacitor. The quarter-wavelength line 27 electrically connects the main line to the ground terminal via capacitor C21. The bonding pads include an output pad 23 and a drain pad 22. In this embodiment, the impedance at the output pad 23 is 24Ω. The impedance of the input matching circuit 30 is also 24Ω, therefore the MMIC 20 is matched to the input matching circuit 30.

[0043] Interstage circuit 25 performs conjugate matching between the second-stage transistors Tr22a-Tr22d and the first-stage transistors Tr21a and Tr21b. The matching method is a bandpass filter type. Input-side circuit 24 converts the input impedance of the first-stage transistors Tr21a and Tr21b to 100Ω. The two MMICs 20a and 20b are connected to the input terminal 11 of the package 15 via wire 13, thereby making the input impedance of the power amplifier 10 50Ω. Input terminal 11 is also referred to as the feed-through.

[0044] Next, the drain bias circuit 90 will be explained. Figure 5 This diagram illustrates the structure of the gate bias circuit 80 and drain bias circuit 90 in Embodiment 1. In the power amplifier 10, the DC and RF signals of the output terminal 12 of the package 15 are not separated. Therefore, the drain voltage is supplied from the output terminal 12. The drain bias circuit 90 has a drain bias supply point Vdd that supplies the drain voltage to the output terminal 12. The drain voltage is supplied to the output terminal 12 from the drain bias supply point Vdd provided on the module substrate via quarter-wavelength lines 91b, 91d, and quarter-wavelength open-circuit stubs 91a, 91c. Figure 3 As shown, the drain voltage supplied to the output terminal 12 supplies power to the drain of the transistor 40 via the output matching circuit 50.

[0045] Furthermore, the drain bias circuit 90 observed from the main line becomes a high impedance through the 1 / 4 wavelength open-circuit stub 91a and the 1 / 4 wavelength line 91b. Therefore, the influence of the drain bias circuit 90 on the main line can be suppressed. Additionally, the 1 / 4 wavelength open-circuit stub 91c and the 1 / 4 wavelength line 91d are configured to further increase the impedance observed from the main line on the power supply side.

[0046] Next, the method of supplying drain voltage to MMIC20 will be explained. For example... Figure 3 As shown, the output matching circuit 50 and the drain bias circuit board 60 are connected by wire 13. Additionally, the drain bias circuit board 60 and the drain pad 22 of the MMIC 20 are connected by wire 13. Figure 4 As shown, the drains of the second-stage and first-stage transistors Tr21a, Tr21b, and Tr22a to Tr22d are connected to the drain pad 22 via a quarter-wavelength line 27 and a capacitor C21. The capacitor C21 is also referred to as the bypass capacitor. Thus, the drains of all stages are common.

[0047] In addition, capacitor C21 is configured to suppress the influence of drain bias circuit 90 on the main circuits of the first and second stages. Capacitor C21 also suppresses the influence of drain bias circuit 90 on the main circuit of transistor 40. Alternatively, multiple bypass capacitors can be added to the drain bias circuit substrate 60. This suppresses the influence on the main circuit and improves stability at low frequencies.

[0048] Figure 6 This diagram illustrates the structure of the drain bias circuit board 60 according to a modified embodiment 1. In the drain bias circuit board 60, a choke inductor L61 may be provided on the line 62 connecting the drain of transistor 40 and the drain of MMIC 20. This can interrupt the loop with the drain bias circuit 90. Furthermore, in the drain bias circuit board 60, it is sufficient that at least the line 62 connecting the drain of transistor 40 and the drain of MMIC 20 is provided on the board 61.

[0049] The substrate 61 of the drain bias circuit substrate 60 can also be a low-cost resin substrate. Alternatively, the drain bias circuit substrate 60 can also be an IPD (Integrated Passive Device) formed on substrates such as Si, GaAs, or glass.

[0050] Next, the gate bias circuit 80 will be described. The structure of the gate bias circuit 80 is the same as that of the drain bias circuit 90. For example... Figure 5As shown, the gate voltage is supplied from the gate bias supply point Vgg located on the module substrate to the input terminal 11 of the package 15 via quarter-wavelength lines 81b, 81d and quarter-wavelength open-circuit stubs 81a, 81c. The input terminal 11 is connected to the input pad 21 of the MMIC 20 via wire 13.

[0051] No coupling capacitor is provided in the input-side circuit 24 of MMIC20. Therefore, the gate voltage input to the input pad 21 supplies power to the gates of the first-stage transistors Tr21a and Tr21b. In the second-stage transistors Tr22a to Tr22d, the gate voltage is supplied via the choke inductors L21 and L22 formed on MMIC20. In transistor 40, the gate voltage is supplied to the gate of transistor cell 42 via the choke inductors L21 and L23, the output pad 23, the wire 13, the input matching circuit 30, and the pre-matching circuit 43.

[0052] In addition, bypass capacitors for suppressing oscillations can also be set in choke inductors L21, L22, and L23. Figure 7 It means in Figure 4 The diagram of the stabilization circuit 29 in Embodiment 1 is omitted. The stabilization circuit 29 also serves as a matching circuit. The stabilization circuit 29 includes, for example, a matching line 29a, a resistor R29, and a bypass capacitor C29. The choke inductors L21 and L22 may not be located on the main line, but rather... Figure 7 The image shows the bypass capacitor C29 of the stabilization circuit 29.

[0053] Figure 8 This diagram illustrates the structure of the high-frequency module 800 of the comparative example of Embodiment 1. The output of the high-frequency module 800 is 70W. In the high-frequency module 800, the final stage uses a 70W-level internally matched FET 810c. In addition, to drive the internally matched FET 810c, a 50W-level internally matched FET 810b and a 30W-level internally matched FET 810a are provided.

[0054] The input and output sides of the internally matched FETs 810a to 810c are each matched to 50Ω. Therefore, no inter-stage matching circuitry is required. However, this structure necessitates gate biasing circuitry, drain biasing circuitry, etc., at each stage, potentially leading to a larger high-frequency module 800. In particular, internally matched FETs are typically single-stage amplifiers with a gain of around 10dB. Therefore, using internally matched FETs in a multi-stage configuration could significantly increase the size of the high-frequency module 800.

[0055] In contrast, in this embodiment, a multi-stage amplifier can be constructed using a package 15 with only two terminals, similar to that of an internally matched FET. In this embodiment, for example, a gain of approximately 30 dB is achieved, enabling the output of power in the 70W range. Therefore, a high-frequency module 100 can be constructed using a single power amplifier 10. Consequently, the high-frequency module 100 can be miniaturized. Furthermore, the high-frequency module 100 can be manufactured at low cost.

[0056] Furthermore, in power amplifier 10, the multi-stage amplifier is housed within a single package. Therefore, as in... Figure 8 Compared to using multiple internally matched FETs, this method can improve the gain.

[0057] Furthermore, in this embodiment, two terminal packages can be used, thus simplifying the redesign of conventional high-frequency modules. Additionally, the package 15 can be of the same type as conventionally used product groups. Moreover, the inspection and evaluation fixtures used in conventional products can be used. Therefore, initial costs such as procurement costs and operating costs can be reduced.

[0058] Furthermore, in this embodiment, a small, low-output GaN-MMIC 20 is combined with a high-output transistor 40 constructed with the minimum necessary circuitry to form the power amplifier 10. Therefore, compared to the case where all circuitry of the entire stage is constructed using a GaN-MMIC, manufacturing costs can be suppressed. That is, the use of the expensive SiC substrate required for GaN-HEMTs can be minimized. Additionally, MMICs typically employ multi-pin packages. In contrast, in this embodiment, as described above, a two-terminal package can be used.

[0059] Furthermore, in this embodiment, the interstage matching is not 50Ω. The output impedance of MMIC20 becomes low in the Ku band. Therefore, the input matching circuit 30 is matched with 24Ω, which is close to the output impedance of MMIC20, thus making matching easy. Also, by not matching with 50Ω, the input matching circuit 30 can be miniaturized. Therefore, the power amplifier 10 and the high-frequency module 100 can be miniaturized. Furthermore, the input matching circuit 30 can be simplified, thus increasing gain through reduced matching circuit losses. Furthermore, the power amplifier 10 can be made wider band. Additionally, the reduced losses in the input matching circuit 30 reduce the output of MMIC20. Therefore, low distortion characteristics can be obtained.

[0060] In this embodiment, as an example, transistor 40 and MMIC20 are conjugate matched with an impedance of 24Ω. However, this is not a limitation; transistor 40 and MMIC20 can be conjugate matched with an impedance of less than 50Ω.

[0061] Furthermore, in this embodiment, drain bias circuit substrates 60a and 60b are disposed on both sides of the package 15. In this structure, the drain current of the MMIC 20 is distributed across the two drain bias circuit substrates 60a and 60b. Therefore, the wiring width of the drain bias circuit substrates 60a and 60b can be reduced. Therefore, a high-impedance line 62 can be achieved, thereby improving the insulation between the drain of the transistor 40 and the drain of the MMIC 20. Therefore, stability can be improved, thereby suppressing unwanted oscillations.

[0062] exist Figure 3 In this configuration, signals from the left and right output matching circuits 50a and 50b are combined at the output terminal 12 via wire 13. As a variation, such as... Figure 2 As shown, the signals from the first path 10a and the second path 10b can also be combined on an output matching circuit 50. In this case, since the combination can be performed without passing through the wire 13, which is prone to length deviation, manufacturing deviations can be suppressed.

[0063] As an example, transistor 40 in this embodiment is a GaN transistor formed on a SiC substrate. However, it is not limited to this; transistor 40 can also be a GaAs transistor. Alternatively, transistor 40 can also be formed on a Si substrate, a GaN substrate, or a diamond substrate. Furthermore, power amplifier 10 can also be a Doherty amplifier.

[0064] The above-described modifications can be appropriately applied to the power amplifier and high-frequency module of the following embodiments. Furthermore, since the power amplifier and high-frequency module of the following embodiments share many similarities with Embodiment 1, the description will focus on their differences from Embodiment 1.

[0065] Implementation method 2.

[0066] Figure 9 This is a top view of the power amplifier 210 according to Embodiment 2. In this embodiment, the path connecting the drain of transistor 40 to the drain of MMIC 20 via drain bias circuit board 60 is connected to a ground terminal by capacitors C71 and C72. Capacitors C71 and C72 have a capacitance of 50Ω or less relative to the difference frequency of the high-frequency signal amplified by transistor 40, as observed from transistor 40.

[0067] Additionally, short-circuit stubs 258a and 258b are provided on the path connecting the drain of transistor 40 to the drain of MMIC 20 via drain bias circuit board 60. Short-circuit stubs 258a and 258b are provided on board 56 and have a line length of 1 / 4 wavelength of the high-frequency signal amplified by transistor 40. Short-circuit stub 258a is connected between capacitor C71 and pattern 57, and is connected to the ground terminal via capacitor C71. Short-circuit stub 258b is connected between capacitor C72 and pattern 57, and is connected to the ground terminal via capacitor C72. Furthermore, line 62 of drain bias circuit board 60 has a line length of 1 / 4 wavelength of the high-frequency signal amplified by transistor 40. The other structures are the same as those of power amplifier 10.

[0068] Short-circuited stubs 258a and 258b, along with capacitors C71 and C72, constitute a difference frequency short-circuit circuit. The difference frequency is explained below. If the fundamental signals of two waves with frequencies f1 and f2 are input to the transistor, distortion components are generated at the difference frequencies |f2-f1| and |f1-f2|. Through the mixing of these distortion components with the fundamental signals, distortion components of 2f2-f1 and 2f1-f2 are generated near the frequencies f1 and f2 of the fundamental signals. This is called IMD3 (3rd Intermodulation Distortion).

[0069] The frequency of IMD3 is close to that of the fundamental frequency signal, so a large IMD3 can significantly degrade communication quality. Therefore, power amplifiers typically aim to minimize IMD3. For example, in the case of a power amplifier for satellite communication, if the fundamental frequency is set to f1 = 14.00 GHz and f2 = 14.01 GHz, the difference frequency is Δf = 10 MHz. In this case, the IMD3 relative to the fundamental frequency signal should be, for example, below -25 dBc. Furthermore, in recent years, multi-carrier communication has become popular to expand communication capacity. In this case, there are situations where a wide-band difference frequency characteristic of several MHz to approximately 400 MHz is required.

[0070] The difference frequency short-circuit circuit is configured to suppress IMD3. In this embodiment, the difference frequency short-circuit circuit is constructed by attaching capacitors C71 and C72, which are chip capacitors, to the front ends of short-circuit stubs 258a and 258b, which have an electrical length of 1 / 4 wavelength relative to the fundamental frequency, which is the main signal. To suppress the difference frequency, the impedance relative to the difference frequency can also be short-circuited at the drain terminal of transistor 40. Therefore, capacitors C71 and C72 are used with higher resonant frequencies to ensure they are short-circuited relative to the difference frequency.

[0071] Furthermore, the difference frequency short-circuit circuit is intended not to affect the RF characteristics of the fundamental frequency. In this embodiment, the impedance of the short-circuit stubs 258a and 258b is open relative to the fundamental frequency. Therefore, the influence of the short-circuit stubs 258a and 258b on the fundamental frequency characteristics can be suppressed.

[0072] Furthermore, when suppressing the difference frequency over a wide frequency band, it is effective to use multiple capacitors such that the impedance observed from the drain terminal of transistor 40 is either short-circuited or low (less than 50Ω) relative to the desired difference frequency. For example, it has been found that when short-circuiting the difference frequency in the range of 1MHz to 375MHz, three sets of capacitors and short-circuit stubs can be provided in the output side circuit of transistor 40. For example, three chip capacitors can be selected such that the impedance is less than 50Ω in 157MHz, 27MHz, and 5MHz. Thus, impedance relative to the difference frequency can be reduced across a wide frequency band.

[0073] In this embodiment, the power amplifier 210 is provided with two sets of short-circuit stubs 258a and 258b, and capacitors C71 and C72. Additionally, in... Figure 9 Two capacitors C72 are connected in a short-circuit stub 258a, but both capacitors C72 are used for the purpose of short-circuiting at the same frequency, so they are referred to as one. Figure 10 As shown, the third group of differential frequency short-circuit circuits is set in the drain bias circuit 90.

[0074] Figure 10 This diagram illustrates the structure of the drain bias circuit 90 in Embodiment 2. In the drain bias circuit 90, a short-circuit stub 91 and a capacitor C91 connected to the front end of the short-circuit stub 91 are provided as a third set of difference frequency short-circuit circuits. The short-circuit stub 91 has a line length of 1 / 4 wavelength of the high-frequency signal amplified by the transistor 40. The path connecting the drain bias supply point Vdd to the output terminal 12 is connected to a ground terminal by the capacitor C91. The capacitor C91 has an impedance of 50Ω or less as observed from the transistor 40 relative to the difference frequency of the high-frequency signal amplified by the transistor 40.

[0075] Accordingly, in this embodiment, the difference frequency can be suppressed over a wide band by using three sets of difference frequency short-circuit circuits. Furthermore, the short-circuit stubs 258a, 258b, and 91 become quarter-wavelength lines in the Ku band. Therefore, the impact of the difference frequency short-circuit circuit on the main circuit of the final stage can be suppressed in the Ku band. Additionally, capacitor C71 is used for 157MHz, capacitor C72 for 27MHz, and capacitor C91 for 5MHz.

[0076] In this embodiment, a third differential frequency short-circuit circuit is disposed on the module substrate in order to be housed in the existing package 15. Furthermore, the differential frequency short-circuit circuit for 5MHz also functions as a drain bias circuit.

[0077] In this context, GaN-based amplifiers typically exhibit less favorable distortion characteristics compared to GaAs-based amplifiers. Therefore, in multi-stage amplifiers constructed with GaN transistors, distortion generated in the driver stage is often unavoidable. Furthermore, suppressing the IMD3 of the driver stage can reduce the overall IMD3 of the amplifier. Therefore, even in the driver stage, a difference frequency short-circuit circuit can be incorporated.

[0078] That is, even with respect to the first and second stage transistors Tr21a, Tr21b, Tr22a to Tr22d, it is preferable to use a capacitor to short-circuit the difference frequency. For example, a short-circuit stub connected to the capacitor at the front end can also be provided on the MMIC20. This difference frequency short-circuit circuit is connected to the drain of transistors Tr21a, Tr21b, Tr22a to Tr22d. As the difference frequency short-circuit circuit, for example, a quarter-wavelength line 27 and a capacitor C21 can be used.

[0079] Furthermore, the drains of transistors Tr21a, Tr21b, and Tr22a to Tr22d are located on the outside of the MMIC chip and are connected to capacitors C71, C72, and C91 via the drain bias circuit board 60. In this embodiment, the line length of the drain bias circuit board 60 is 1 / 4 wavelength. Therefore, relative to the fundamental frequency, the impedance on the outside increases from the drain pad 22, which can suppress the influence of the drain bias circuit board 60 on the RF characteristics of the driver stage. In this way, the drain bias circuit board 60 can be used as a difference frequency short-circuit circuit for the driver stage.

[0080] In addition, if the power amplifier 210 has the loop gain characteristic of a multi-stage amplifier, a choke inductor may be provided on the wiring terminal of the drain bias circuit board 60 on the side opposite to the capacitor C72.

[0081] In this embodiment, not only in the final stage but also in the transistors of the driver stage, the difference frequency can be short-circuited over a wide band. Therefore, low distortion characteristics can be achieved throughout the power amplifier 210.

[0082] In passing Figure 8In the case of differential frequency short-circuiting in the three-stage amplifier shown, three sets of short-circuit stubs are used for each stage. Therefore, nine sets of short-circuit stubs are required in a three-stage amplifier, which may increase the circuit size. In addition, if a multi-stage amplifier is constructed using a single package 15 as in this embodiment, ensuring sufficient space for the differential frequency short-circuit circuit for the driver stage becomes difficult. Furthermore, when the differential frequency short-circuit circuit for the driver stage is placed outside the package 15, the drain terminal of the driver stage needs to be placed separately within the package 15. Therefore, the number of terminals may increase. In addition, the circuit size of the module substrate may increase due to the need to install the differential frequency short-circuit circuit.

[0083] In contrast, in this embodiment, by utilizing the drain bias circuit board 60, the area of ​​the differential frequency short-circuit circuit can be suppressed. Furthermore, since it is not necessary to separately house the differential frequency short-circuit circuit for the driver stage on the module board, the circuit size of the module board can be reduced. Additionally, the increase in the number of terminals of the package 15 can be suppressed.

[0084] Furthermore, in this embodiment, drain bias circuit boards 60a and 60b are disposed on both sides of the package 15. This allows for easy placement of short-circuit stubs 258a and 258b.

[0085] In this embodiment, a short-circuit stub for a lower frequency of 5MHz is provided on the module substrate to meet circuit size requirements. However, this is not a limitation; all differential frequency short-circuit circuits may also be configured within the power amplifier 210.

[0086] Implementation method 3.

[0087] Figure 11 This is an equivalent circuit diagram of the voltage divider circuit 325 in Embodiment 3. The MMIC 20 includes a voltage divider circuit 325 that divides the gate voltage input from the outside via the input terminal 11. A voltage divided by the voltage divider circuit 325 is supplied to the gates of transistors Tr21a, Tr21b, Tr22a to Tr22d (which function as amplifiers) within the MMIC 20, or to the gate of transistor 40. Furthermore, in Figure 11 For simplicity, the MMIC20 and transistor 40 are shown in the diagram. Figure 11 In the diagram, transistor Tr21 is equivalent to transistors Tr21a and Tr21b, and transistor Tr22 is equivalent to transistors Tr22a to Tr22d.

[0088] The voltage divider circuit 325 has resistors R21 to R26. The gate voltage supplied to each stage of the transistor is determined by the resistance values ​​of R21 to R26. Therefore, different gate voltages can be applied to each stage. For example, the voltages supplied from the voltage divider circuit 325 to the gates of transistors Tr21 and Tr22 in the MMIC 20 can be different from the voltage supplied from the voltage divider circuit 325 to the gate of transistor 40. In this configuration, different types of transistors can be used in the power amplifier 10.

[0089] For example, transistors Tr21 and Tr22 in MMIC20 can be formed on a Si substrate, while transistor 40 can be formed on a SiC substrate. Specifically, the final stage uses GaN transistors formed on a SiC substrate that can achieve good RF characteristics, while the driver stage uses inexpensive GaN transistors formed on a Si substrate to reduce costs. This ensures RF characteristics and suppresses costs. To improve distortion characteristics or reliability, there are cases where the epitaxial structures of transistors on the SiC substrate and transistors on the Si substrate differ, resulting in different optimal gate voltages. According to this embodiment, optimal gate bias can be supplied to transistors formed on different substrates. Furthermore, there are cases where the optimal drain voltages of transistors Tr21 and Tr22 on the Si substrate differ from those of transistor 40 on the SiC substrate. In this case, it is also possible to... Figure 6 The inductor L61 can be replaced with a resistor. Alternatively, a resistor can be added in series with the inductor L61 on line 62. As a result, the voltage drop across the resistor on the drain bias circuit board 60 allows for the supply of optimal drain voltage to Tr21 and Tr22.

[0090] Furthermore, in the relationship between gain and input power, it was found that whether gain compression or gain amplification occurs depends on the third derivative of the drain current based on the gate voltage, i.e., gm3. This relationship between gain and input power is known as the AM-AM characteristic, which significantly affects IMD3. Here, gain compression means a decrease in gain relative to input power, while gain amplification means an increase in gain relative to input power. Gain amplification occurs when gm3 > 0, and gain compression occurs when gm3 < 0. gm3 depends on the gate voltage. Therefore, by controlling the gate voltage, it is possible to control whether gain amplification or gain compression occurs.

[0091] In this embodiment, one of the transistors Tr21 and Tr22 in the MMIC20 and the transistor 40 may be supplied with a voltage whose gain is reduced relative to the input power from the voltage divider circuit 325, while the other may be supplied with a voltage whose gain is increased relative to the input power from the voltage divider circuit 325. For example, a gate voltage that amplifies the gain may be supplied to the transistor 40, while a gate voltage that compresses the gain may be supplied to the transistors Tr21 and Tr22. In this case, the AM-AM characteristics in the MMIC20 and the transistor 40 become inverse characteristics. That is, AM-AM is canceled out in the power amplifier 10 as a whole. This improves IMD3. In this case, the transistors are based on the premise of using transistors of the same process throughout the entire stage.

[0092] Alternatively, resistors R21 to R26 can be preset to values ​​lower than the target value. Therefore, even with significant characteristic deviations in each manufacturing batch, laser trimming of resistors R21 to R26 can improve RF characteristics. Furthermore, the power amplifier 10 can be manufactured with a high yield. Additionally, the voltage divider circuit 325 can be located outside the MMIC 20 in the power amplifier 10. The voltage divider circuit 325 can also be a single chip.

[0093] Implementation method 4.

[0094] Figure 12 This is a top view of the power amplifier 410 according to Embodiment 4. In this embodiment, the drain bias circuit board 60 is disposed between the first path 10a and the second path 10b. In this embodiment, a drain bias circuit board 60 common to both the first path 10a and the second path 10b is used. Furthermore, for the capacitor used for difference frequency short-circuiting, a capacitor C70 common to both the first path 10a and the second path 10b can also be disposed between the first path 10a and the second path 10b. This reduces the number of components, material costs, and assembly costs.

[0095] Implementation method 5.

[0096] Figure 13 This is a top view of the power amplifier 510 according to Embodiment 5. The power amplifier 510 includes a diode linearizer 75 disposed between the first path 10a and the second path 10b. In the diode linearizer 75, the anode of diode D11 is connected to a ground terminal via resistor R11. Furthermore, in... Figure 13 The drain bias circuit board 60 is omitted in the text.

[0097] Therefore, the diode linearizer 75 can be configured without making the package 15 large. This significantly improves distortion characteristics. Since the anode of diode D11 is grounded, the bias terminal of the diode linearizer 75 becomes useless. Therefore, the number of terminals in the package 15 can be maintained at two.

[0098] Diode D11 can also be connected in parallel to the front stage of the first stage of MMIC20. When diode D11 is connected in the rear stage of transistor 40 after the power has been amplified, a diode D11 with a high power tolerance is required.

[0099] Figure 14 This is a top view of the power amplifier 610, a variation of embodiment 5. Resistor R11 can also be placed in MMIC20.

[0100] The technical features described in each embodiment can also be used in appropriate combinations.

[0101] Explanation of reference numerals in the attached figures

[0102] 10…Power Amplifier; 10a…First Path; 10b…Second Path; 11…Input Terminal; 12…Output Terminal; 13…Wire; 15…Package; 20, 20a, 20b…MMIC; 21…Input Pad; 22…Drain Pad; 23…Output Pad; 24…Input Side Circuit; 25…Interstage Circuit; 26…Output Side Circuit; 27…1 / 4 Wavelength Circuit; 28…Substrate; 29…Stabilization Circuit; 29a…Matching Circuit; 30, 30a, 30b…Input Matching Circuit; 31…Base Board; 32… Pattern; 40, 40a, 40b… Transistors; 41… Substrate; 42… Transistor Unit; 43… Pre-matching Circuit; 50, 50a, 50b… Output Matching Circuit; 51a, 51b… Matching Circuit Substrate; 52… Substrate; 53… Pattern; 55a, 55b… Matching Circuit Substrate; 56… Substrate; 57… Pattern; 60, 60a, 60b… Drain Bias Circuit Substrate; 61… Substrate; 62… Line; 75… Diode Linearizer; 80… Gate Bias Circuit; 81a, 81c… 1 / 4 wavelength open-circuit stub; 81b, 81d… 1 / 4 wavelength lines; 90… drain bias circuit; 91… short-circuit stub; 91a… 1 / 4 wavelength open-circuit stub; 91b… 1 / 4 wavelength lines; 91c… 1 / 4 wavelength open-circuit stub; 91d… 1 / 4 wavelength lines; 100… high-frequency module; 210… power amplifier; 258a, 258b… short-circuit stub; 325… voltage divider circuit; 410, 510, 610… power amplifier; 800… high-frequency module; 810a~810c …Internal matching FET; C21, C22…capacitor; C29…bypass capacitor; C70, C71, C72, C91…condenser; D11…diode; L21~L23, L61…choke inductor; R11, R21~R26, R29…resistor; Tr21, Tr21a, Tr22b, Tr22, Tr22a~Tr22d…transistor; Vdd…drain bias supply point; Vgg…gate bias supply point.

Claims

1. A power amplifier, characterized in that, have: The input terminal allows high-frequency signals to be input from the outside. The MMIC receives the high-frequency signal via the input terminal and amplifies the high-frequency signal. Input matching circuit; A transistor, which is input to the high-frequency signal amplified by the MMIC via the input matching circuit, and amplifies the high-frequency signal; Output matching circuit; The output terminal receives the drain voltage of the transistor from the outside, and the high-frequency signal amplified by the transistor is input through the output matching circuit, and the high-frequency signal is output to the outside. as well as A drain bias circuit board that connects the drain of the transistor to the drain of the MMIC. The transistor and the MMIC are conjugate matched with an impedance of less than 50Ω.

2. The power amplifier according to claim 1, characterized in that, The gate voltage of the MMIC is input from the outside to the input terminal.

3. The power amplifier according to claim 1 or 2, characterized in that, The power amplifier has only two terminals for external connection: the input terminal and the output terminal.

4. The power amplifier according to claim 1 or 2, characterized in that, In the drain bias circuit board, a choke inductor is provided on the line connecting the drain of the transistor to the drain of the MMIC.

5. The power amplifier according to claim 1 or 2, characterized in that, The path connecting the drain of the transistor to the drain of the MMIC via the drain bias circuit board is connected to a ground terminal by a first capacitor.

6. The power amplifier according to claim 5, characterized in that, The first capacitor has an impedance of less than 50Ω as observed from the transistor relative to the difference frequency of the high-frequency signal.

7. The power amplifier according to claim 5, characterized in that, It has a short-circuit stub, which is disposed on the path and has a line length of 1 / 4 wavelength of the high-frequency signal.

8. The power amplifier according to claim 5, characterized in that, The drain bias circuit board has a line length of 1 / 4 wavelength of the high-frequency signal.

9. The power amplifier according to any one of claims 1, 2, 6 to 8, characterized in that, It includes a voltage divider circuit that divides the gate voltage input from the outside via the input terminal. A voltage, which is a voltage divided by the voltage divider circuit, is supplied to the gate of the amplifier or the gate of the transistor within the MMIC.

10. The power amplifier according to claim 9, characterized in that, The voltage supplied from the voltage divider circuit to the gate of the amplifier is different from the voltage supplied from the voltage divider circuit to the gate of the transistor.

11. The power amplifier according to claim 10, characterized in that, The amplifier is formed on a Si substrate. The transistor is formed on a SiC substrate.

12. The power amplifier according to claim 9, characterized in that, One of the amplifier and the transistor is supplied with a voltage whose gain is reduced relative to the input power from the voltage divider circuit. The amplifier and the transistor are supplied with a voltage from the voltage divider circuit that increases the gain relative to the input power.

13. The power amplifier according to any one of claims 1, 2, 6-8, 10-12, characterized in that, have: The MMIC described in the first paragraph; The second type of MMIC; The first transistor amplifies the high-frequency signal amplified by the first MMIC; The second transistor amplifies the high-frequency signal amplified by the second MMIC; The first drain bias circuit board connects the drain of the first transistor to the drain of the first MMIC. as well as The second drain bias circuit board connects the drain of the second transistor to the drain of the second MMIC. The first drain bias circuit board and the second drain bias circuit board are disposed outside the region where the first MMIC, the second MMIC, the first transistor and the second transistor are disposed.

14. The power amplifier according to any one of claims 1, 2, 6-8, 10-12, characterized in that, have: The MMIC described in the first paragraph; The second type of MMIC; The first transistor amplifies the high-frequency signal amplified by the first MMIC; and The second transistor amplifies the high-frequency signal amplified by the second MMIC. The drain bias circuit board is disposed between a first path from the input terminal through the first MMIC and the first transistor to the output terminal, and a second path from the input terminal through the second MMIC and the second transistor to the output terminal.

15. The power amplifier according to any one of claims 1, 2, 6-8, 10-12, characterized in that, have: The MMIC described in the first paragraph; The second MMIC; The first transistor amplifies the high-frequency signal amplified by the first MMIC; The second transistor amplifies the high-frequency signal amplified by the second MMIC; as well as A diode linearizer is configured between a first path from the input terminal through a first MMIC and a first transistor to the output terminal, and a second path from the input terminal through a second MMIC and a second transistor to the output terminal.

16. A high-frequency module, characterized in that, The power amplifier is provided according to any one of claims 1 to 15.

17. The high-frequency module according to claim 16, characterized in that, It has a drain bias supply point that supplies the drain voltage to the output terminal. The path connecting the drain of the transistor to the drain of the MMIC via the drain bias circuit board is connected to a ground terminal by a first capacitor. The path connecting the drain bias supply point to the output terminal is connected to the ground terminal by a second capacitor.

18. The high-frequency module according to claim 17, characterized in that, The second capacitor has an impedance of less than 50Ω as observed from the transistor relative to the difference frequency of the high-frequency signal.

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