A vehicle wheel speed signal acquisition circuit and method for a domain controller

Abstract

The application provides a vehicle wheel speed signal acquisition circuit and method of a domain controller, which comprises a first limiting circuit, an amplitude gating circuit, a signal conditioning circuit, a signal amplification circuit, a second limiting circuit and a signal reloading circuit; a vehicle wheel speed signal is input from an input end of the first limiting circuit; output ends of the first limiting circuit are respectively connected with an input end of the amplitude gating circuit and a first input end of the signal conditioning circuit; an output end of the amplitude gating circuit is connected with an input end of the signal amplification circuit; an output end of the signal amplification circuit is connected with an input end of the second limiting circuit; an output end of the second limiting circuit is connected with an input end of the signal reloading circuit; and an output end of the signal reloading circuit is connected with a second input end of the signal conditioning circuit. The application can process high-amplitude signals without distortion, has simple circuit structure, low design cost and strong practicability, and can realize acquisition of vehicle wheel speed signals with large amplitude variation range.

Description

Technical Field

[0001] This invention relates to the technical field of vehicle signal acquisition, and in particular to a vehicle wheel speed signal acquisition circuit and method for a domain controller. Background Technology

[0002] Sensor signals are the information source for automotive electronic control systems, and accurate acquisition of sensor signals is a crucial aspect of these systems. Especially with the continuous improvement of automotive intelligence, domain controllers need to acquire various types of vehicle signals, such as the output signals from wheel speed sensors. The amplitude and frequency of these output signals increase with vehicle speed and decrease with vehicle speed, and the amplitude can vary between 0.3V and 15V. Circuits that only acquire frequency signals cannot measure low-amplitude, low-frequency wheel speed signals, resulting in the loss of wheel speed signals at low speeds. Therefore, to effectively measure wheel speed signals across the entire range, it is necessary to process low-amplitude wheel speed signals.

[0003] Currently, a common approach to processing low-amplitude wheel speed signals is to amplify the signal and then use a comparator or Schmitt trigger for signal conditioning to convert the sinusoidal signal into a square wave signal. For example, existing patent literature discloses a vehicle brake-by-wire wheel speed acquisition circuit, including a filtering circuit, an amplification circuit, a comparator circuit, and a shaping circuit. The current signal output by the wheel speed sensor is filtered to remove interference signals, then transmitted to the amplification circuit for amplification, then to the comparator circuit, and finally to the shaping circuit for shaping into a pulse signal. The pulse signal is then sent to the MCU. The comparator circuit typically includes a comparison... Using an op-amp or Schmitt trigger presents two problems. First, there's the issue of amplification factor. Because the amplitude of the input signal varies widely, when the circuit meets the amplification factor for low-amplitude signals, high-amplitude signals will face the same amplification factor. At this point, the signal amplification exceeds the power supply range of the op-amp, causing signal distortion even with rail-to-rail op-amps. Second, while designing the amplifier circuit to adjust the amplification factor according to the amplitude to adapt to changes in the input signal amplitude is an option, adjusting the amplification factor requires additional circuit components, resulting in high design costs and low practicality. Summary of the Invention

[0004] To address the problems of distortion when processing high-amplitude signals, high design costs, and low practicality in existing vehicle wheel speed acquisition circuits, this invention proposes a vehicle wheel speed signal acquisition circuit and method for a domain controller. This circuit processes high-amplitude signals without distortion, has a simple circuit structure, low design costs, and high practicality, and can acquire vehicle wheel speed signals with a wide amplitude variation range.

[0005] To achieve the above-mentioned technical effects, the technical solution of the present invention is as follows:

[0006] A vehicle wheel speed signal acquisition circuit for a domain controller includes: a first limiting circuit, an amplitude gating circuit, a signal conditioning circuit, a signal amplification circuit, a second limiting circuit, and a signal reload circuit;

[0007] The vehicle wheel speed signal is input from the input terminal of the first limiting circuit. The output terminal of the first limiting circuit is connected to the input terminal of the amplitude gating circuit and the first input terminal of the signal conditioning circuit. The output terminal of the amplitude gating circuit is connected to the input terminal of the signal amplification circuit. The output terminal of the signal amplification circuit is connected to the input terminal of the second limiting circuit. The output terminal of the second limiting circuit is connected to the input terminal of the signal reload circuit. The output terminal of the signal reload circuit is connected to the second input terminal of the signal conditioning circuit.

[0008] In this technical solution, the first limiting circuit is used to limit the vehicle wheel speed signal, the amplitude gating circuit is used to select low amplitude signal input, the signal amplification circuit is used to amplify the low amplitude signal, and the second limiting circuit is used to limit the amplified signal to obtain the second limiting signal. This avoids the problem of signal distortion caused by indiscriminately amplifying high amplitude signals. Then, the second limiting signal is reloaded and optimized using a signal reloading circuit without the need to add additional comparators or Schmitt triggers for signal shaping, reducing circuit hardware resource overhead and making it practical. Furthermore, the high amplitude signal or reloaded signal is converted into a square wave signal output using a signal conditioning circuit, which facilitates signal acquisition by the domain controller.

[0009] Preferably, the first limiting circuit includes a first capacitor C1 and a first Zener diode D1. One end of the first capacitor C1 is connected to the input terminal of the first limiting circuit, and the other end of the first capacitor C1 is grounded. The cathode of the first Zener diode D1 is connected to the input terminal of the first limiting circuit, the input terminal of the amplitude gating circuit, and the first input terminal of the signal conditioning circuit, respectively. The anode of the first Zener diode D1 is grounded. The first limiting circuit limits the vehicle wheel speed signal whose amplitude is higher than the voltage value that the signal conditioning circuit can withstand.

[0010] Preferably, the amplitude selection circuit includes a first resistor R1, a first comparator U1-A, a second resistor R2, and an NMOS transistor Q1. One end of the first resistor R1 is connected to the negative terminal of the first Zener diode D1, and the other end of the first resistor R1 is connected to the negative input terminal of the first comparator U1-A. The positive input terminal of the first comparator U1-A is connected to the input terminal of the reference voltage Vref. The power input terminal of the first comparator U1-A is connected to the input terminal of the first supply voltage VCC1. The power output terminal of the first comparator U1-A is grounded. The signal output terminal of the first comparator U1-A is connected to one end of the second resistor R2 and the gate of the NMOS transistor Q1. The other end of the second resistor R2 is connected to the input terminal of the second supply voltage VCC2. The source of the NMOS transistor Q1 is connected to the input terminal of the signal amplification circuit, and the drain of the NMOS transistor Q1 is connected to the negative terminal of the first Zener diode D1.

[0011] Preferably, the signal conditioning circuit includes a third resistor R3, a second comparator U1-B, and a fourth resistor R4. One end of the third resistor R3 is connected to the negative terminal of the first Zener diode D1, and the other end of the third resistor R3 is connected to the positive input terminal of the second comparator U1-B. The negative input terminal of the second comparator U1-B is connected to the input terminal of the reference voltage Vref. The power input terminal of the second comparator U1-B is connected to the input terminal of the third power supply voltage VCC3. The power output terminal of the second comparator U1-B is grounded. The signal output terminal of the second comparator U1-B is connected to one end of the fourth resistor R4 and the vehicle wheel speed signal output terminal, respectively. The other end of the fourth resistor R4 is connected to the input terminal of the fourth power supply voltage VCC4.

[0012] Preferably, the signal amplification circuit includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and an amplifier U2. The source of the NMOS transistor Q1 is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6, respectively. The other end of the sixth resistor R6 is connected to the positive input terminal of the amplifier U2. The other end of the fifth resistor R5 and one end of the seventh resistor R7 are grounded together. The other end of the seventh resistor R7 is connected to the negative input terminal of the amplifier U2 and one end of the eighth resistor R8, respectively. The other end of the eighth resistor R8 is connected to the second limiting circuit and the signal output terminal of the amplifier U2, respectively. The power input terminal of the amplifier U2 is connected to the fifth power supply voltage VPP input terminal, and the power output terminal of the amplifier U2 is grounded.

[0013] Preferably, the second limiting circuit includes a ninth resistor R9 and a second Zener diode D2. The positive terminal of the second Zener diode D2 is grounded, and the negative terminal of the second Zener diode D2 is connected to the signal reload circuit and one end of the ninth resistor R9. The other end of the ninth resistor R9 is connected to the signal output terminal of the amplifier U2.

[0014] Preferably, the signal reload circuit includes a first unidirectional diode E1, the cathode of the first unidirectional diode E1 is connected to one end of the third resistor R3, the anode of the first unidirectional diode E1 is connected to the output terminal of the second limiting circuit, and a second unidirectional diode E2 is also provided on the connection line between the cathode of the first Zener diode D1 and one end of the third resistor R3, wherein the anode of the second unidirectional diode E2 is connected to the cathode of the first Zener diode D1, and the cathode of the second unidirectional diode E2 is connected to one end of the third resistor R3.

[0015] This invention also proposes a method for acquiring vehicle wheel speed signals from a domain controller, characterized by comprising the following steps:

[0016] S1. Input the vehicle wheel speed signal into the first limiting circuit. The first limiting circuit limits the vehicle wheel speed signal to obtain a first limiting signal. The first limiting signal includes a high amplitude signal and a low amplitude signal.

[0017] S2. The low-amplitude signal is selected by using an amplitude gating circuit, and the high-amplitude signal is selected by using a signal conditioning circuit;

[0018] S3. The amplitude gating circuit amplifies the selected low-amplitude signal input signal into the signal amplification circuit to obtain an amplified signal;

[0019] S4. The amplified signal is transmitted to the second limiting circuit for limiting to obtain the second limiting signal;

[0020] S5. Input the second limiting signal to the signal reload circuit for reload optimization processing to obtain the reload signal;

[0021] S6. The high-amplitude signal or the heavy-load signal is converted into a square wave signal and output to the domain controller using the signal conditioning circuit.

[0022] Preferably, if the amplitude of the first limiting signal is not lower than the reference voltage Vref, then the first limiting signal is recorded as a high amplitude signal; otherwise, if the amplitude of the first limiting signal is lower than the reference voltage Vref, then the first limiting signal is recorded as a low amplitude signal.

[0023] The present invention also proposes a vehicle, including the vehicle wheel speed signal acquisition circuit of the domain controller.

[0024] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0025] This invention proposes a vehicle wheel speed signal acquisition circuit and method for a domain controller. The circuit includes a first limiting circuit, an amplitude gating circuit, a signal conditioning circuit, a signal amplification circuit, a second limiting circuit, and a signal reloading circuit. The first limiting circuit limits the vehicle wheel speed signal, the amplitude gating circuit selects low-amplitude signals for input, the signal amplification circuit amplifies the low-amplitude signals, and the second limiting circuit limits the amplified signals to obtain a second-limited signal. This avoids the problem of signal distortion caused by indiscriminately amplifying high-amplitude signals. The signal reloading circuit then optimizes the second-limited signal by reloading it, eliminating the need for additional comparators or Schmitt triggers for signal shaping, thus reducing hardware resource overhead and making it practical. Furthermore, the signal conditioning circuit converts the high-amplitude or reloaded signal into a square wave signal for output, facilitating signal acquisition by the domain controller. This invention processes high-amplitude signals without distortion, has a simple circuit structure, low design cost, and strong practicality, enabling the acquisition of vehicle wheel speed signals with a wide amplitude variation range. Attached Figure Description

[0026] Figure 1 This diagram illustrates the structure of a vehicle wheel speed signal acquisition circuit for a domain controller according to an embodiment of the present invention.

[0027] Figure 2 This diagram illustrates the schematic of a vehicle wheel speed signal acquisition circuit for a domain controller proposed in an embodiment of the present invention.

[0028] Figure 3 This diagram illustrates the waveform processing of the vehicle wheel speed signal as presented in this embodiment of the invention.

[0029] Figure 4 This is a flowchart illustrating a method for acquiring vehicle wheel speed signals for a domain controller according to an embodiment of the present invention. 1. First limiting circuit; 2. Amplitude gating circuit; 3. Signal conditioning circuit; 4. Signal amplification circuit; 5. Second limiting circuit; 6. Signal reload circuit. Detailed Implementation

[0030] The accompanying drawings are for illustrative purposes only and should not be construed as limiting the scope of this patent.

[0031] To better illustrate this embodiment, some parts of the accompanying drawings may be omitted, enlarged, or reduced, and do not represent actual dimensions. The descriptions of directions such as "up" and "down" are not intended to limit this patent. It should be understood that although the terms "first," "second," "third," etc., may be used to describe various information in this invention, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this invention, a first input terminal may also be referred to as a second input terminal, and similarly, a second input terminal may also be referred to as a first input terminal.

[0032] It is understandable to those skilled in the art that some well-known details may be omitted from the accompanying drawings;

[0033] The terms used to describe positional relationships in the accompanying drawings are for illustrative purposes only and should not be construed as limiting this patent.

[0034] First, the relevant explanations of the English words and abbreviations mentioned in this embodiment are as follows:

[0035] MCU, Microcontroller Unit;

[0036] Vref, Voltage reference, refers to the voltage value used as a reference point when measuring voltage values;

[0037] VCC, Voltage Current Condenser, is the power supply voltage of the circuit.

[0038] NMOS, N-Metal-Oxide-Semiconductor;

[0039] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0040] Example 1

[0041] like Figure 1 As shown, this embodiment proposes a vehicle wheel speed signal acquisition circuit for a domain controller, including: a first limiting circuit 1, an amplitude gating circuit 2, a signal conditioning circuit 3, a signal amplification circuit 4, a second limiting circuit 5, and a signal reload circuit 6;

[0042] The vehicle wheel speed signal is input from the input terminal of the first limiting circuit 1. The output terminal of the first limiting circuit 1 is connected to the input terminal of the amplitude gating circuit 2 and the first input terminal of the signal conditioning circuit 3. The output terminal of the amplitude gating circuit 2 is connected to the input terminal of the signal amplification circuit 4. The output terminal of the signal amplification circuit 4 is connected to the input terminal of the second limiting circuit 5. The output terminal of the second limiting circuit 5 is connected to the input terminal of the signal reload circuit 6. The output terminal of the signal reload circuit 6 is connected to the second input terminal of the signal conditioning circuit 3.

[0043] Here, the vehicle wheel speed signal is first input to the first limiting circuit 1. The first limiting circuit 1 limits the vehicle wheel speed signal to obtain a first limiting signal. The first limiting signal includes a high amplitude signal and a low amplitude signal. The low amplitude signal is selected for input by the amplitude gating circuit 2, and the high amplitude signal is selected for input by the signal conditioning circuit 3. The amplitude gating circuit 2 amplifies the selected low amplitude signal into the signal amplification circuit 4 to obtain an amplified signal. The amplified signal is transmitted to the second limiting circuit 5 for limiting to obtain a second limiting signal. The second limiting signal is input to the signal reload circuit 6 for reload optimization processing to obtain a reload signal. The signal conditioning circuit 3 converts the high amplitude signal or the reload signal into a square wave signal and outputs it to the microcontroller unit (MCU) of the domain controller.

[0044] When the vehicle wheel speed signal is input to the first limiting circuit 1, it needs to pass through the first limiting circuit 1 because the amplitude of the vehicle wheel speed signal varies greatly. The first limiting circuit 1 limits the amplitude of the vehicle wheel speed signal that is higher than the voltage value that the signal conditioning circuit 3 can withstand, and obtains the first limiting signal. After passing through the first limiting circuit 1, the vehicle wheel speed signal enters the amplitude selection circuit 2 and the signal conditioning circuit 3 through two channels respectively. The channel entering the amplitude selection circuit 2 is for high amplitude signals with an amplitude not lower than the reference voltage Vref to be signal conditioned, and the channel entering the signal conditioning circuit 3 is for low amplitude signals with an amplitude lower than the reference voltage Vref to be signal processed. The amplitude selection circuit 2 is used to distinguish low amplitude signals and perform subsequent amplification signal processing on low amplitude signals with an amplitude lower than the reference voltage Vref, while high amplitude signals are adjusted by the signal conditioning circuit 3 without signal amplification, so that the high amplitude signals are not distorted and the vehicle wheel speed signal of the full range can be collected.

[0045] See Figure 2 The first limiting circuit 1 includes a first capacitor C1 and a first Zener diode D1. One end of the first capacitor C1 is connected to the input terminal of the first limiting circuit 1, and the other end of the first capacitor C1 is grounded. The cathode of the first Zener diode D1 is connected to the input terminal of the first limiting circuit 1, the input terminal of the amplitude gating circuit 2, and the first input terminal of the signal conditioning circuit 3, respectively. The anode of the first Zener diode D1 is grounded. The first limiting circuit 1 limits the vehicle wheel speed signal whose amplitude is higher than the voltage value that the signal conditioning circuit 3 can withstand.

[0046] In the first limiting circuit 1, see Figure 3 The vehicle wheel speed signal is first input from the input terminal, passes through the first capacitor C1 to filter out high-frequency interference signals, and then passes through the first Zener diode D1. The first Zener diode D1 limits the amplitude of the vehicle wheel speed signal that is higher than the voltage value that the signal conditioning circuit 3 can withstand. The resulting signal is as follows: Figure 3The waveform of the clipped signal obtained in the middle region;

[0047] The amplitude selection circuit 2 includes a first resistor R1, a first comparator U1-A, a second resistor R2, and an NMOS transistor Q1. One end of the first resistor R1 is connected to the cathode of the first Zener diode D1, and the other end of the first resistor R1 is connected to the negative input terminal of the first comparator U1-A. The positive input terminal of the first comparator U1-A is connected to the input terminal of the reference voltage Vref. The power input terminal of the first comparator U1-A is connected to the input terminal of the first supply voltage VCC1. The power output terminal of the first comparator U1-A is grounded. The signal output terminal of the first comparator U1-A is connected to one end of the second resistor R2 and the NMOS transistor Q1. The gate of the OS transistor Q1 is connected to the input terminal of the second power supply voltage VCC2, the other end of the second resistor R2 is connected to the input terminal of the signal amplifier circuit 4, and the drain of the NMOS transistor Q1 is connected to the negative terminal of the first Zener diode D1. Among them, the first resistor R1 is a current limiting resistor, the second resistor R2 is a pull-up resistor, and the amplitude selection circuit 2 selectively sends low amplitude signals below the reference voltage Vref into the subsequent signal amplifier circuit 4. Thus, the amplitude variation range of the low amplitude signal entering the signal amplifier circuit 4 is from the minimum amplitude of the low amplitude signal to the reference voltage Vref.

[0048] The signal conditioning circuit 3 includes a third resistor R3, a second comparator U1-B, and a fourth resistor R4. One end of the third resistor R3 is connected to the cathode of the first Zener diode D1, and the other end of the third resistor R3 is connected to the positive input terminal of the second comparator U1-B. The negative input terminal of the second comparator U1-B is connected to the input terminal of the reference voltage Vref. The power input terminal of the second comparator U1-B is connected to the input terminal of the third supply voltage VCC3. The power output terminal of the second comparator U1-B is grounded. The signal output terminal of the second comparator U1-B is connected to the fourth resistor R4. One end of resistor 4 is connected to the vehicle wheel speed signal output terminal, and the other end of resistor R4 is connected to the fourth power supply voltage VCC4 input terminal; wherein, resistor R3 is a current limiting resistor, resistor R4 is a pull-up resistor, and the high amplitude or heavy load signal entering signal conditioning circuit 3 is a sine wave signal. The function of signal conditioning circuit 3 is to convert the sine wave signal into a square wave signal, that is, to convert the high amplitude or heavy load signal into a square wave signal. The function of signal conditioning circuit is to convert the sine wave signal into a square wave signal of a certain frequency so that the microcontroller unit (MCU) of the domain controller can perform signal acquisition;

[0049] After the vehicle wheel speed signal is limited, one path goes to the negative input of the first comparator U1-A, and the other path goes to the positive input of the second comparator U1-B. The first limited signal entering the negative input of the first comparator U1-A is compared with the reference voltage Vref. If the amplitude of the first limited signal is not lower than the reference voltage Vref, then the first limited signal is a high-amplitude signal, the signal output of the first comparator U1-A is low, and the gate of the NMOS transistor Q1 controlled by the first comparator U1-A is also low. At this time, the NMOS transistor Q1 is in the closed state and no current path is formed. If the amplitude of the first limited signal is lower than the reference voltage Vref, then the first limited signal is a low-amplitude signal, and the first comparator U1-B... When the signal output terminal of A is high, the gate of NMOS transistor Q1 controlled by the first comparator U1-A is also high, and NMOS transistor Q1 is in the on-state, forming a current path. After NMOS transistor Q1 is turned on, although the low-amplitude signal cannot be conditioned in the second comparator U1-B, it can enter the signal amplification circuit 4 through the NMOS transistor Q1 of the amplitude selection circuit 2 for amplitude amplification. The first limiting signal entering the positive input terminal of the second comparator U1-B is compared with the reference voltage Vref. If the amplitude of the first limiting signal is not lower than the reference voltage Vref, then the first limiting signal is a high-amplitude signal, and the circuit of the second comparator U1-B is turned on, converting the current high-amplitude signal into a high-amplitude signal. Figure 3 The lower region is a square wave signal; otherwise, the circuit of the second comparator U1-B is turned off, and the second comparator U1-B does not work; the voltage values ​​of the first supply voltage VCC1, the second supply voltage VCC2, the third supply voltage VCC3, and the fourth supply voltage VCC4 are the same, and the voltage values ​​are consistent with the port supply voltage of the microcontroller unit MCU of the domain controller; the reference voltage Vref input terminal is connected to the positive input terminal of the first comparator U1-A and the negative input terminal of the second comparator U1-B respectively;

[0050] The signal amplification circuit 4 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and an amplifier U2. The source of the NMOS transistor Q1 is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to the positive input terminal of the amplifier U2. The other end of the fifth resistor R5 and one end of the seventh resistor R7 are grounded together. The other end of the seventh resistor R7 is connected to the negative input terminal of the amplifier U2 and one end of the eighth resistor R8. The other end of the eighth resistor R8 is connected to the second limiting circuit 5 and the signal output terminal of the amplifier U2. The power input terminal of the amplifier U2 is connected to the fifth power supply voltage VPP input terminal, and the power output terminal of the amplifier U2 is grounded.

[0051] In signal amplification circuit 4, the fifth resistor R5 is a grounding resistor, the sixth resistor R6 is an input resistor, and the combination of the seventh resistor R7 and the eighth resistor R8 provides the amplification factor. The amplification factor of the entire operational amplifier circuit is (1 + R8 / R7). Signal amplification circuit 4 only needs to amplify the gating signal of amplitude gating circuit 2, that is, the low amplitude signal selected by amplitude gating circuit 2. The operational amplifier in signal amplification circuit 4 needs to be powered by the fifth supply voltage VPP. The voltage of the fifth supply voltage VPP is higher than the amplification factor multiplied by the reference voltage Vref. In signal amplification circuit 4, the voltage of the fifth supply voltage VPP is 24V, which ensures that the amplified signal is not distorted within 24V. It should be noted that the fifth supply voltage VPP is not limited to the above 24V in actual use. It can also be set to 28V or other voltage values. The above 24V fifth supply voltage VPP is only used to understand this embodiment and does not represent the only voltage value of the fifth supply voltage VPP.

[0052] The second limiting circuit 5 includes a ninth resistor R9 and a second Zener diode D2. The anode of the second Zener diode D2 is grounded, and the cathode of the second Zener diode D2 is connected to the signal reload circuit 6 and one end of the ninth resistor R9. The other end of the ninth resistor R9 is connected to the signal output terminal of the amplifier U2. When a low-amplitude signal is amplified by the signal amplification circuit 4, the maximum amplitude of the amplified signal exceeds the maximum voltage that the signal conditioning circuit 3 can withstand. Therefore, the amplified signal needs to be limited to obtain a second limiting signal. The second limiting signal is a sinusoidal signal, which needs to be shaped to facilitate the microcontroller operation of the domain controller. The MCU performs signal acquisition. From a design perspective, the conventional approach is to process the limited signal using a Schmitt or comparator circuit to obtain a standard square wave. However, this conventional approach requires at least one Schmitt or comparator, as well as an I / O port of the domain controller's microcontroller unit (MCU), increasing the circuit hardware overhead and design cost. Therefore, a signal reload circuit 6 is needed to reload the second limited signal to the second input of the signal conditioning circuit 3 without adding an extra Schmitt or comparator. This achieves the signal conditioning function while reducing the high design cost.

[0053] A low-amplitude signal is input from the positive terminal of amplifier U2, amplified to obtain an amplified signal, and then passes through the ninth resistor R9. The amplified signal is then processed by the second limiting circuit 5, composed of the second Zener diode D2, to obtain a second limited signal. This second limited signal reaches the signal reload circuit 6, which includes a first unidirectional diode E1. The cathode of the first unidirectional diode E1 is connected to one end of the third resistor R3, and the anode of the first unidirectional diode E1 is connected to the output terminal of the second limiting circuit 5. A second unidirectional diode E2 is also provided on the connection line between the cathode of the first Zener diode D1 and one end of the third resistor R3, with the anode of the second unidirectional diode E2 connected to the cathode of the first Zener diode D1. Connect one end of the third resistor R3 to the cathode of diode E2. In the signal reload circuit 6, the high-amplitude signal enters the signal conditioning circuit 3 from the second unidirectional diode E2, and the low-amplitude signal sequentially passes through the amplitude gating circuit 2, the signal amplification circuit 4, the second limiting circuit 5, and the first unidirectional diode E1 of the signal reload circuit 6 before entering the signal conditioning circuit 3. Since the low-amplitude signal is lower than the reference voltage Vref, the high-amplitude signal input from the second unidirectional diode E2 cannot affect the reloaded signal entering the signal conditioning circuit 3 from the first unidirectional diode E1 after amplification, thus completing the reload processing of the low-amplitude signal. The square wave signal output by the signal conditioning circuit 3 after conditioning is connected to the acquisition pin of the microcontroller unit (MCU) of the domain controller.

[0054] Thus, the frequency value f of the square wave signal of the microcontroller unit (MCU) of the input domain controller is obtained, and the frequency value f has the following relationship with the wheel speed:

[0055] n = K * f / Z

[0056] Where n represents wheel speed, K is a proportionality coefficient that can be calibrated by software, and Z represents the number of teeth; the wheel speed of the vehicle is calculated based on the above formula.

[0057] In this embodiment, the circuit includes a first limiting circuit, an amplitude gating circuit, a signal conditioning circuit, a signal amplification circuit, a second limiting circuit, and a signal reload circuit. The first limiting circuit limits the vehicle wheel speed signal, the amplitude gating circuit selects a low-amplitude signal for input, the signal amplification circuit amplifies the low-amplitude signal, and the second limiting circuit limits the amplified signal to obtain a second limited signal. This avoids the problem of signal distortion caused by indiscriminately amplifying high-amplitude signals. The signal reload circuit then optimizes the second limited signal by reloading it without the need for additional comparators or Schmitt triggers for signal shaping, reducing hardware resource overhead and making it practical. Furthermore, the signal conditioning circuit converts the high-amplitude signal or the reloaded signal into a square wave signal for output, facilitating signal acquisition by the domain controller's microcontroller unit (MCU). This invention processes high-amplitude signals without distortion, has a simple circuit structure, low design cost, and strong practicality, enabling the acquisition of vehicle wheel speed signals with a wide amplitude variation range.

[0058] Example 2

[0059] See Figure 4 This embodiment proposes a method for acquiring vehicle wheel speed signals in a domain controller, characterized by the following steps:

[0060] S1. Input the vehicle wheel speed signal into the first limiting circuit 1. The first limiting circuit 1 limits the vehicle wheel speed signal to obtain a first limiting signal. The first limiting signal includes a high amplitude signal and a low amplitude signal.

[0061] In step S1, if the amplitude of the first limiting signal is not lower than the reference voltage Vref, then the first limiting signal is recorded as a high amplitude signal; otherwise, if the amplitude of the first limiting signal is lower than the reference voltage Vref, then the first limiting signal is recorded as a low amplitude signal.

[0062] S2. The low-amplitude signal is selected by the amplitude gating circuit 2, and the high-amplitude signal is selected by the signal conditioning circuit 3;

[0063] S3. The amplitude selection circuit 2 amplifies the selected low amplitude signal input signal amplifier circuit 4 to obtain an amplified signal;

[0064] S4. The amplified signal is transmitted to the second limiting circuit 5 for limiting to obtain the second limiting signal;

[0065] S5. The second limiting signal is input to the signal reload circuit 6 for reload optimization processing to obtain the reload signal;

[0066] S6. The high-amplitude signal or the heavy-load signal is converted into a square wave signal and output to the domain controller using the signal conditioning circuit 3.

[0067] In step S6, the domain controller is equipped with a microcontroller unit (MCU), which acquires the square wave signal.

[0068] In this embodiment, a first limiting circuit limits the vehicle wheel speed signal, an amplitude selection circuit selects a low-amplitude signal for input, a signal amplification circuit amplifies the low-amplitude signal, and a second limiting circuit limits the amplified signal to obtain a second limited signal. This avoids the problem of signal distortion caused by indiscriminately amplifying high-amplitude signals. A signal reloading circuit then optimizes the second limited signal without requiring additional comparators or Schmitt triggers for signal shaping, reducing hardware resource overhead and demonstrating practicality. Furthermore, a signal conditioning circuit converts the high-amplitude or reloaded signal into a square wave output, facilitating signal acquisition by the domain controller's microcontroller unit (MCU). This invention processes high-amplitude signals without distortion, has a simple circuit structure, low design cost, and strong practicality, enabling the acquisition of vehicle wheel speed signals with a wide amplitude variation range.

[0069] Example 3

[0070] This embodiment proposes a vehicle including the vehicle wheel speed signal acquisition circuit of the domain controller described in Embodiment 1 above. The acquisition circuit includes: a first limiting circuit 1, an amplitude gating circuit 2, a signal conditioning circuit 3, a signal amplification circuit 4, a second limiting circuit 5, and a signal reload circuit 6.

[0071] The vehicle wheel speed signal is input from the input terminal of the first limiting circuit 1. The output terminal of the first limiting circuit 1 is connected to the input terminal of the amplitude gating circuit 2 and the first input terminal of the signal conditioning circuit 3. The output terminal of the amplitude gating circuit 2 is connected to the input terminal of the signal amplification circuit 4. The output terminal of the signal amplification circuit 4 is connected to the input terminal of the second limiting circuit 5. The output terminal of the second limiting circuit 5 is connected to the input terminal of the signal reload circuit 6. The output terminal of the signal reload circuit 6 is connected to the second input terminal of the signal conditioning circuit 3.

[0072] The vehicle wheel speed signal is input to the first limiting circuit 1, which limits the vehicle wheel speed signal to obtain a first limiting signal. The first limiting signal includes a high amplitude signal and a low amplitude signal. The low amplitude signal is selected for input by the amplitude gating circuit 2, and the high amplitude signal is selected for input by the signal conditioning circuit 3. The amplitude gating circuit 2 amplifies the selected low amplitude signal into the signal amplification circuit 4 to obtain an amplified signal. The amplified signal is transmitted to the second limiting circuit 5 for limiting to obtain a second limiting signal. The second limiting signal is input to the signal reload circuit 6 for reload optimization processing to obtain a reloaded signal. The signal conditioning circuit 3 converts the high amplitude signal or the reloaded signal into a square wave signal and outputs it to the microcontroller unit (MCU) of the domain controller.

[0073] In this embodiment, a first limiting circuit limits the vehicle wheel speed signal, an amplitude selection circuit selects a low-amplitude signal for input, a signal amplification circuit amplifies the low-amplitude signal, and a second limiting circuit limits the amplified signal to obtain a second limited signal. This avoids the problem of signal distortion caused by indiscriminately amplifying high-amplitude signals. A signal reloading circuit then optimizes the second limited signal without requiring additional comparators or Schmitt triggers for signal shaping, reducing hardware resource overhead and demonstrating practicality. Furthermore, a signal conditioning circuit converts the high-amplitude or reloaded signal into a square wave output, facilitating signal acquisition by the domain controller's microcontroller unit (MCU). This invention processes high-amplitude signals without distortion, has a simple circuit structure, low design cost, and strong practicality, enabling the acquisition of vehicle wheel speed signals with a wide amplitude variation range.

[0074] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A vehicle wheel speed signal acquisition circuit for a domain controller, characterized in that, include: The circuit consists of a first limiting circuit (1), an amplitude gating circuit (2), a signal conditioning circuit (3), a signal amplification circuit (4), a second limiting circuit (5), and a signal reload circuit (6). The vehicle wheel speed signal is input from the input terminal of the first limiting circuit (1). The output terminal of the first limiting circuit (1) is connected to the input terminal of the amplitude gating circuit (2) and the first input terminal of the signal conditioning circuit (3). The output terminal of the amplitude gating circuit (2) is connected to the input terminal of the signal amplification circuit (4). The output terminal of the signal amplification circuit (4) is connected to the input terminal of the second limiting circuit (5). The output terminal of the second limiting circuit (5) is connected to the input terminal of the signal reload circuit (6). The output terminal of the signal reload circuit (6) is connected to the second input terminal of the signal conditioning circuit (3). The amplitude selection circuit (2) is used to compare the amplitude of the vehicle wheel speed signal with the reference voltage Vref. When the amplitude is lower than the reference voltage Vref, the vehicle wheel speed signal is selected to the signal amplification circuit (4). The signal reload circuit (6) is used to load the amplified and second-limited signal to the second input terminal of the signal conditioning circuit (3); The signal conditioning circuit (3) is used to convert a high-amplitude signal from its first input terminal or a heavy-load signal from its second input terminal into a square wave signal output.

2. The vehicle wheel speed signal acquisition circuit of the domain controller according to claim 1, characterized in that, The first limiting circuit (1) includes a first capacitor C1 and a first Zener diode D1. One end of the first capacitor C1 is connected to the input terminal of the first limiting circuit (1), and the other end of the first capacitor C1 is grounded. The negative terminal of the first Zener diode D1 is connected to the input terminal of the first limiting circuit (1), the input terminal of the amplitude gating circuit (2), and the first input terminal of the signal conditioning circuit (3), respectively. The positive terminal of the first Zener diode D1 is grounded. The first limiting circuit (1) limits the vehicle wheel speed signal whose amplitude is higher than the voltage value of the signal conditioning circuit (3).

3. The vehicle wheel speed signal acquisition circuit of the domain controller according to claim 2, characterized in that, The amplitude selection circuit (2) includes a first resistor R1, a first comparator U1-A, and a second resistor. With NMOS transistor Q1, one end of the first resistor R1 is connected to the cathode of the first Zener diode D1, and the other end of the first resistor R1 is connected to the negative input terminal of the first comparator U1-A. The positive input terminal of the first comparator U1-A is connected to the reference voltage Vref input terminal, the power input terminal of the first comparator U1-A is connected to the first supply voltage VCC1 input terminal, the power output terminal of the first comparator U1-A is grounded, and the signal output terminals of the first comparator U1-A are respectively connected to the second resistor. One end is connected to the gate of NMOS transistor Q1, and the second resistor The other end is connected to the input terminal of the second power supply voltage VCC2. The source of NMOS transistor Q1 is connected to the input terminal of the signal amplifier circuit (4). The drain of NMOS transistor Q1 is connected to the negative terminal of the first Zener diode D1.

4. The vehicle wheel speed signal acquisition circuit of the domain controller according to claim 3, characterized in that, The signal conditioning circuit (3) includes a third resistor R3, a second comparator U1-B and a fourth resistor R4. One end of the third resistor R3 is connected to the negative terminal of the first Zener diode D1, and the other end of the third resistor R3 is connected to the positive input terminal of the second comparator U1-B. The negative input terminal of the second comparator U1-B is connected to the input terminal of the reference voltage Vref. The power input terminal of the second comparator U1-B is connected to the input terminal of the third power supply voltage VCC3. The power output terminal of the second comparator U1-B is grounded. The signal output terminal of the second comparator U1-B is connected to one end of the fourth resistor R4 and the vehicle wheel speed signal output terminal, respectively. The other end of the fourth resistor R4 is connected to the input terminal of the fourth power supply voltage VCC4.

5. The vehicle wheel speed signal acquisition circuit of the domain controller according to claim 4, characterized in that, The signal amplification circuit (4) includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and an amplifier U2. The source of the NMOS transistor Q1 is connected to one end of the fifth resistor R5 and the sixth resistor R6, respectively. The other end of the sixth resistor R6 is connected to the positive input terminal of the amplifier U2. The other end of the fifth resistor R5 and one end of the seventh resistor R7 are grounded together. The other end of the seventh resistor R7 is connected to the negative input terminal of the amplifier U2 and one end of the eighth resistor R8, respectively. The other end of the eighth resistor R8 is connected to the second limiting circuit (5) and the signal output terminal of the amplifier U2, respectively. The power input terminal of the amplifier U2 is connected to the fifth power supply voltage VPP input terminal, and the power output terminal of the amplifier U2 is grounded.

6. The vehicle wheel speed signal acquisition circuit of the domain controller according to claim 5, characterized in that, The second limiting circuit (5) includes a ninth resistor R9 and a second Zener diode D2. The positive terminal of the second Zener diode D2 is grounded, and the negative terminal of the second Zener diode D2 is connected to the signal reload circuit (6) and one end of the ninth resistor R9. The other end of the ninth resistor R9 is connected to the signal output terminal of the amplifier U2.

7. The vehicle wheel speed signal acquisition circuit of the domain controller according to claim 6, characterized in that, The signal reload circuit (6) includes a first unidirectional diode E1, the negative terminal of the first unidirectional diode E1 is connected to one end of the third resistor R3, the positive terminal of the first unidirectional diode E1 is connected to the output terminal of the second limiting circuit (5), and a second unidirectional diode E2 is also provided on the connection line between the negative terminal of the first Zener diode D1 and one end of the third resistor R3, wherein the positive terminal of the second unidirectional diode E2 is connected to the negative terminal of the first Zener diode D1, and the negative terminal of the second unidirectional diode E2 is connected to one end of the third resistor R3.

8. A method for acquiring vehicle wheel speed signals of a domain controller, implemented using the vehicle wheel speed signal acquisition circuit of the domain controller as described in any one of claims 1-7, characterized in that, Includes the following steps: S1. Input the vehicle wheel speed signal into the first limiting circuit (1). The first limiting circuit (1) limits the vehicle wheel speed signal to obtain a first limiting signal. The first limiting signal includes a high amplitude signal and a low amplitude signal. S2. The low amplitude signal is selected by using the amplitude gating circuit (2), and the high amplitude signal is selected by using the signal conditioning circuit (3); S3. The amplitude selection circuit (2) amplifies the selected low amplitude signal input signal amplification circuit (4) to obtain an amplified signal; S4. The amplified signal is transmitted to the second limiting circuit (5) for limiting to obtain the second limiting signal; S5. Input the second limiting signal to the signal reload circuit (6) for reload optimization processing to obtain the reload signal; S6. The high-amplitude signal or the heavy-load signal is converted into a square wave signal and output to the domain controller using the signal conditioning circuit (3).

9. The vehicle wheel speed signal acquisition method for a domain controller according to claim 8, characterized in that, If the amplitude of the first limiting signal is not lower than the reference voltage Vref, then the first limiting signal is recorded as a high amplitude signal; otherwise, if the amplitude of the first limiting signal is lower than the reference voltage Vref, then the first limiting signal is recorded as a low amplitude signal.

10. A vehicle, characterized in that, The vehicle wheel speed signal acquisition circuit includes the domain controller as described in any one of claims 1-7.

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