Firmware chip data pin identification method and device

Abstract

Embodiments of the present disclosure provide a firmware chip data pin identification method and device; applied to the field of computer application technology. The method comprises collecting the time sequence when reading data of the to-be-tested firmware chip, and marking the clock signal and each to-be-identified pin signal; measuring and recording the signal delay value of each to-be-identified pin signal in all clock cycles respectively; calculating the average signal delay value of each to-be-identified pin signal respectively, if the average signal delay value is within the preset signal delay value change range M of the known firmware chip of the same type as the to-be-tested firmware chip, the to-be-identified pin corresponding to the average signal delay value is a data pin. In this way, the data pin of the firmware chip can be correctly identified.

Description

Technical Field

[0001] This disclosure relates to the field of computer application technology, and in particular to a method and apparatus for identifying firmware chip data pins. Background Technology

[0002] Firmware chips store firmware systems and related data, which can be retrieved using correct read / write commands. However, some firmware chips have their surface markings erased, resulting in unclear pin signals and making it difficult to correctly extract the firmware system and related data. Therefore, researching methods for identifying data pins on firmware chips with erased surface markings is crucial, as mastering such methods can support the extraction of firmware systems and related data from these chips. Summary of the Invention

[0003] This disclosure provides a method, apparatus, device, and storage medium for identifying firmware chip data pins.

[0004] According to a first aspect of this disclosure, a method for identifying firmware chip data pins is provided. The method includes:

[0005] The timing sequence of the firmware chip under test when reading data is acquired, and the clock signal and the signals of each pin to be identified are marked.

[0006] Measure and record the signal delay value of each pin to be identified in all clock cycles;

[0007] Calculate the average signal delay value of each pin to be identified. If the average signal delay value is within the preset signal delay value variation range M of a known firmware chip of the same type as the firmware chip under test, then the pin to be identified corresponding to the average signal delay value is a data pin.

[0008] In some possible implementations of the first aspect, acquiring the timing sequence of data read from the firmware chip under test includes acquiring the timing sequence of data read from the firmware chip under test via a logic analyzer.

[0009] In some possible implementations of the first aspect, the signal delay value is the difference between the time when the clock signal triggers the falling edge and the time when the corresponding transition of the pin signal to be identified occurs within one clock cycle.

[0010] In some possible implementations of the first aspect, calculating the average signal delay value of each pin signal to be identified includes:

[0011] Calculate the ratio of the sum of the signal delay values ​​of each pin to be identified over all clock cycles to the sum of the number of times the pin to be identified and the clock signal trigger each other over all clock cycles.

[0012] In some possible implementations of the first aspect, the preset signal delay value variation range M of a known firmware chip of the same type as the firmware chip under test is set by the following methods:

[0013] Timing data is acquired from multiple known firmware chips of different types during data reading. The signal delay values ​​of each data signal in each type of firmware chip are measured and recorded over all clock cycles. The average signal delay value D of the data signals of each type of firmware chip is obtained. A delay deviation percentage T is set to obtain the range M of signal delay value variation for each type of firmware chip.

[0014] M = [D*(1-T), D*(1+T)]; 0 <T<=1。

[0015] In some possible implementations of the first aspect, the type of firmware chip includes at least one of the following:

[0016] EPROM chips, SRAM chips, DRAM chips, NAND chips, and NOR chips.

[0017] In some possible implementations of the first aspect, obtaining the average signal delay value D of the data signals of various types of firmware chips includes:

[0018] Based on the signal delay values ​​of each data signal in all clock cycles in each type of firmware chip, the average signal delay value of each data signal in each type of firmware chip is calculated. The average signal delay values ​​of each data signal obtained in each type of firmware chip are summed to obtain the total signal delay value of the data signals of each type of firmware chip. The total signal delay value is then compared with the total number of data pins of the corresponding type of firmware chip to obtain the average signal delay value D of the data signals of each type of firmware chip.

[0019] According to a second aspect of this disclosure, a firmware chip data pin identification device is provided. The device includes:

[0020] The timing acquisition module under test is used to acquire the timing of the firmware chip under test when reading data, and to mark the clock signal and the signals of each pin to be identified.

[0021] The data pin identification module is used to measure and record the signal delay value of each pin to be identified in all clock cycles.

[0022] Calculate the average signal delay value of each pin to be identified. If the average signal delay value is within the preset signal delay value variation range M of a known firmware chip of the same type as the firmware chip under test, then the pin to be identified corresponding to the average signal delay value is a data pin.

[0023] According to a third aspect of this disclosure, an electronic device is provided. The electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method described above.

[0024] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions for causing a computer to perform the methods described above.

[0025] According to a fifth aspect of this disclosure, embodiments of this disclosure provide a computer program product comprising a computer program that, when executed by a processor, implements the methods described above.

[0026] In this disclosure, the timing sequence of the firmware chip under test (DUT) reading data is collected to mark the clock signal and each pin signal to be identified; the signal delay value of each pin signal to be identified is measured and recorded over all clock cycles; the average signal delay value of each pin signal to be identified is calculated, and it is determined whether the average signal delay value of the pin signal to be identified is within the preset signal delay value variation range of a known firmware chip of the same type as the DUT. If it is within this variation range, the pin to be identified is a data pin. In this way, the data pins of the firmware chip can be correctly identified.

[0027] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0028] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of this disclosure. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0029] Figure 1 A flowchart of a firmware chip data pin identification method provided in an embodiment of this disclosure is shown;

[0030] Figure 2 This diagram illustrates the triggering relationship between the data signal and the clock signal provided in an embodiment of the present disclosure.

[0031] Figure 3 A schematic diagram of the trigger delay of the data signal and clock signal provided in an embodiment of this disclosure is shown;

[0032] Figure 4A structural diagram of a firmware chip data pin identification device provided in an embodiment of this disclosure is shown.

[0033] Figure 5 A structural diagram of an exemplary electronic device capable of implementing embodiments of the present disclosure is shown. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0035] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0036] To address the problems in the background art, this disclosure provides a method and apparatus for identifying data pins of a firmware chip. Specifically, by acquiring the timing sequence of the firmware chip under test reading data, the clock signal and each pin signal to be identified are marked; the signal delay value of each pin signal to be identified is measured and recorded over all clock cycles; the average signal delay value of each pin signal to be identified is calculated; and it is determined whether the average signal delay value of the pin signal to be identified is within a preset range of signal delay values ​​for known firmware chips of the same type as the firmware chip under test. If it is within this range, the pin to be identified is a data pin. In this way, the data pins of the firmware chip can be correctly identified.

[0037] The firmware chip data pin identification method and apparatus provided in this disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] Figure 1 A flowchart of a firmware chip data pin identification method provided in this disclosure embodiment is shown. Method 100 includes the following steps:

[0039] S110 acquires the timing data of the firmware chip under test when it reads data, and marks the clock signal and the signals of each pin to be identified.

[0040] In some embodiments, the timing sequence for acquiring data read from the firmware chip under test includes:

[0041] The timing sequence of the firmware chip under test when reading data is acquired using a logic analyzer.

[0042] In some embodiments, clock signals are identified and marked by the crystal oscillator components in the firmware chip under test;

[0043] Furthermore, the pins connected to the crystal oscillator are clock signal pins.

[0044] S120 measures and records the signal delay value of each pin signal to be identified in all clock cycles.

[0045] In some embodiments, the signal delay value is the difference between the time when the clock signal triggers the falling edge and the time when the corresponding transition of the pin signal to be identified occurs within one clock cycle.

[0046] In some embodiments, if the signal of the pin to be identified does not change within a certain clock cycle, the signal delay value within that clock cycle is not measured.

[0047] S130, calculate the average signal delay value of each pin to be identified. If the average signal delay value is within the preset signal delay value variation range M of a known firmware chip of the same type as the firmware chip under test, then the pin to be identified corresponding to the average signal delay value is a data pin.

[0048] In some embodiments, calculating the average signal delay value of each pin signal to be identified includes:

[0049] Calculate the ratio of the sum of the signal delay values ​​of each pin to be identified over all clock cycles to the sum of the number of times the pin to be identified and the clock signal trigger each other over all clock cycles.

[0050] In some embodiments, the preset signal delay value variation range M of a known firmware chip of the same type as the firmware chip under test is set by the following method:

[0051] Timing data is acquired from multiple known firmware chips of different types during data reading. The signal delay values ​​of each data signal in each type of firmware chip are measured and recorded over all clock cycles. The average signal delay value D of the data signals of each type of firmware chip is obtained. A delay deviation percentage T is set to obtain the range M of signal delay value variation for each type of firmware chip.

[0052] M = [D*(1-T), D*(1+T)]; 0 <T<=1。

[0053] In some embodiments, the type of firmware chip includes at least one of the following:

[0054] EPROM chips, SRAM chips, DRAM chips, NAND chips, and NOR chips.

[0055] In some embodiments, obtaining the average signal delay value D of the data signals of various types of firmware chips includes:

[0056] Based on the signal delay values ​​of each data signal in all clock cycles in each type of firmware chip, the average signal delay value of each data signal in each type of firmware chip is calculated. The average signal delay values ​​of each data signal obtained in each type of firmware chip are summed to obtain the total signal delay value of the data signals of each type of firmware chip. The total signal delay value is then compared with the total number of data pins of the corresponding type of firmware chip to obtain the average signal delay value D of the data signals of each type of firmware chip.

[0057] Figure 2 A schematic diagram illustrating the triggering relationship between the data signal and the clock signal provided in an embodiment of this disclosure is shown. Figure 2 As shown:

[0058] Figure 2 The signals in the signal include clock signal CLK, address signal Adr, and data signal Data;

[0059] During the first clock cycle, when the clock signal triggers its first falling edge, the data signal also triggers its falling edge, transitioning from a high level to a low level. At this point, the clock signal and the data signal have a triggering relationship. When the clock signal triggers its rising edge, the data signal remains at a low level, and there is no triggering relationship between the clock signal and the data signal. When the clock signal triggers its second falling edge, the data signal also triggers its rising edge, transitioning from a low level to a high level. At this point, the clock signal and the data signal have a triggering relationship.

[0060] During the first clock cycle, when the address signal triggers a falling edge, the data signal does not trigger a transition and remains at a low level.

[0061] Furthermore, there is no triggering relationship between the address signal and the data signal;

[0062] When the clock signal triggers a falling edge, it causes the data signal to be sent and change accordingly, thus creating a trigger relationship.

[0063] Figure 3 A schematic diagram illustrating the trigger delay of the data signal and clock signal provided in an embodiment of this disclosure is shown. Figure 3 As shown:

[0064] Figure 3 The signals in the signal include clock signal CLK, address signal Adr, and data signal Data;

[0065] When the clock signal triggers the falling edge for the first time, the data signal triggers the falling edge after a delay of T1 nanoseconds, changing from a high level to a low level, thus establishing a trigger relationship. When the clock signal triggers the falling edge for the second time, the address signal triggers the rising edge after a delay of T2 microseconds, changing from a low level to a high level, without establishing a trigger relationship. Here, T2 is greater than T1.

[0066] In some embodiments, the data signal changes with the clock signal, and the address signal also changes with the clock signal. However, the signal delay between the data signal and the clock signal is generally on the order of nanoseconds, while the signal delay between the address signal and the clock signal is generally on the order of microseconds. The delay between the address signal and the clock signal is too long, so there is a triggering relationship between the data signal and the clock signal, but no triggering relationship between the address signal and the clock signal.

[0067] In some embodiments, the signal delay values ​​between the data signal and the clock signal, and between the address signal and the clock signal, are determined by the implementation process of the firmware chip.

[0068] The above is an introduction to the method embodiments. The following specific embodiments using the method will further illustrate the solution described in this disclosure.

[0069] Assuming that the firmware chip under test is initially determined to be a 24C512EEPROM, and the preset signal delay value variation range for this type of firmware chip is M; where,

[0070] The method for setting M is as follows: acquire the timing data of multiple 24C512EEPROM chips, measure and record the signal delay value of each data signal in the chip over all clock cycles, obtain the average signal delay value D of the data signal, set the delay deviation percentage T, and obtain the signal delay value variation range M, M = [D*(1-T), D*(1+T)], 0 <T<=1;

[0071] Furthermore, the timing sequence of the firmware chip under test during data reading is acquired using a logic analyzer, and the clock signal and the signals of each pin to be identified are marked; among them,

[0072] Each pin signal to be identified includes unknown pin signals other than clock signals, such as address signals, data signals, etc.

[0073] Furthermore, since the signal delay between the data signal and the clock signal is on the order of nanoseconds, while the signal delay between the clock signal and other signals is on the order of much larger than nanoseconds (for example, the signal delay between the clock signal and the address signal is on the order of microseconds), the data pin can be identified based on the signal delay between the data signal and the clock signal.

[0074] Specifically, the signal delay value of each pin signal to be identified is measured and recorded in all clock cycles;

[0075] If the signal of the pin to be identified does not change within a certain clock cycle, the signal delay value within that clock cycle will not be measured; where,

[0076] The signal delay value is the difference between the time when the clock signal triggers the falling edge and the time when the corresponding transition of the signal of the pin to be identified occurs within one clock cycle.

[0077] Furthermore, the sum of the signal delay values ​​of a certain pin signal to be identified over all clock cycles is compared with the sum of the number of times the pin signal to be identified and the clock signal trigger each other over all clock cycles to obtain the average signal delay value of the pin signal to be identified; the average signal delay values ​​of the remaining pin signals to be identified are calculated in the same way.

[0078] Assume that the signals of each pin to be identified are labeled a1, a2, a3...an, and their average signal delay values ​​are b1, b2, b3...bn, respectively.

[0079] If b1 is within M, then the pin signal to be identified, a1, is a data signal, meaning the pin corresponding to a1 is a data pin; the identification method for the remaining pin signals to be identified is the same as the identification method for a1.

[0080] According to embodiments of this disclosure, by acquiring the timing data read by the firmware chip under test, the clock signal and each pin signal to be identified are marked; the signal delay value of each pin signal to be identified is measured and recorded over all clock cycles; the average signal delay value of each pin signal to be identified is calculated, and it is determined whether the average signal delay value of the pin signal to be identified is within the preset signal delay value variation range of a known firmware chip of the same type as the firmware chip under test. If it is within the variation range, the pin to be identified is a data pin. In this way, the data pins of the firmware chip can be correctly identified.

[0081] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, because according to this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0082] The above is an introduction to the method embodiments. The following describes the solution described in this disclosure further through device embodiments.

[0083] Figure 4 A structural diagram of a firmware chip data pin identification device according to an embodiment of this disclosure is shown. The device 200 includes:

[0084] The timing acquisition module 210 under test is used to acquire the timing of the firmware chip under test when reading data, and to mark the clock signal and the signals of each pin to be identified.

[0085] In some embodiments, module 210 is specifically used for:

[0086] The timing sequence for acquiring data from the firmware chip under test includes the timing sequence for acquiring data from the firmware chip under test using a logic analyzer.

[0087] The data pin identification module 220 is used to measure and record the signal delay value of each pin signal to be identified in all clock cycles.

[0088] Calculate the average signal delay value of each pin to be identified. If the average signal delay value is within the preset signal delay value variation range M of a known firmware chip of the same type as the firmware chip under test, then the pin to be identified corresponding to the average signal delay value is a data pin.

[0089] In some embodiments, module 220 is specifically used for:

[0090] The signal delay value is the difference between the time when the clock signal triggers the falling edge and the time when the corresponding transition of the pin signal to be identified occurs within one clock cycle.

[0091] In some embodiments, module 220 is further configured to:

[0092] The calculation of the average signal delay value of each pin signal to be identified includes:

[0093] Calculate the ratio of the sum of the signal delay values ​​of each pin to be identified over all clock cycles to the sum of the number of times the pin to be identified and the clock signal trigger each other over all clock cycles.

[0094] In some embodiments, module 220 is further configured to:

[0095] The preset signal delay value variation range M of a known firmware chip of the same type as the firmware chip under test is set by the following methods:

[0096] Timing data is acquired from multiple known firmware chips of different types during data reading. The signal delay values ​​of each data signal in each type of firmware chip are measured and recorded over all clock cycles. The average signal delay value D of the data signals of each type of firmware chip is obtained. A delay deviation percentage T is set to obtain the range M of signal delay value variation for each type of firmware chip.

[0097] M = [D*(1-T), D*(1+T)]; 0 <T<=1;

[0098] Furthermore, the type of firmware chip includes at least one of the following: EPROM chip, SRAM chip, DRAM chip, NAND chip, and NOR chip;

[0099] Furthermore, the average signal delay value D of the data signals of various types of firmware chips is obtained, including...

[0100] Based on the signal delay values ​​of each data signal in all clock cycles in each type of firmware chip, the average signal delay value of each data signal in each type of firmware chip is calculated. The average signal delay values ​​of each data signal obtained in each type of firmware chip are summed to obtain the total signal delay value of the data signals of each type of firmware chip. The total signal delay value is then compared with the total number of data pins of the corresponding type of firmware chip to obtain the average signal delay value D of the data signals of each type of firmware chip.

[0101] Understandable Figure 4 Each module / unit in the detection device 200 shown has the function of implementing each step in the detection method 100 provided in the embodiments of this disclosure, and can achieve its corresponding technical effect. For the sake of brevity, it will not be described in detail here.

[0102] The acquisition, storage, and application of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0103] Figure 5 A structural diagram of an exemplary electronic device capable of implementing embodiments of the present disclosure is shown. Electronic device 500 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic device 500 may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0104] like Figure 5As shown, the electronic device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. The RAM 503 may also store various programs and data required for the operation of the electronic device 500. The computing unit 501, ROM 502, and RAM 503 are interconnected via a bus 504. An I / O interface 505 is also connected to the bus 504.

[0105] Multiple components in electronic device 500 are connected to I / O interface 505, including: input unit 506, such as keyboard, mouse, etc.; output unit 507, such as various types of monitors, speakers, etc.; storage unit 508, such as disk, optical disk, etc.; and communication unit 509, such as network card, modem, wireless transceiver, etc. Communication unit 509 allows electronic device 500 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0106] The computing unit 501 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 501 performs the various methods and processes described above, such as method 100. For example, in some embodiments, method 100 may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 500 via ROM 502 and / or communication unit 509. When the computer program is loaded into RAM 503 and executed by the computing unit 501, one or more steps of method 100 described above may be performed. Alternatively, in other embodiments, the computing unit 501 may be configured to perform method 100 by any other suitable means (e.g., by means of firmware).

[0107] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0108] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0109] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0110] It should be noted that this disclosure also provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute method 100 and achieve the corresponding technical effects achieved by executing the method in the embodiments of this disclosure. For the sake of brevity, they will not be described in detail here.

[0111] In addition, this disclosure also provides a computer program product including a computer program that implements method 100 when executed by a processor.

[0112] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including voice input, speech input, or tactile input).

[0113] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0114] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0115] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0116] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for identifying firmware chip data pins, characterized in that, include: The timing sequence of the firmware chip under test when reading data is acquired, and the clock signal and the signals of each pin to be identified are marked. Measure and record the signal delay value of each pin to be identified in all clock cycles; Calculate the average signal delay value for each pin to be identified. If the average signal delay value is within a preset signal delay value variation range M of a known firmware chip of the same type as the firmware chip under test, then the pin to be identified corresponding to the average signal delay value is a data pin. The preset signal delay value variation range M of the known firmware chip of the same type as the firmware chip under test is set using the following method: Timing data is acquired from multiple known firmware chips of different types during data reading. The signal delay values ​​of each data signal in each type of firmware chip are measured and recorded over all clock cycles. The average signal delay value D of the data signals of each type of firmware chip is obtained. A delay deviation percentage T is set to obtain the range M of signal delay value variation for each type of firmware chip. M=[D (1-T),D (1+T)]; 0<T<=1; in which, The acquisition of the average signal delay value D of the data signals of various types of firmware chips includes: Based on the signal delay values ​​of each data signal in all clock cycles in each type of firmware chip, the average signal delay value of each data signal in each type of firmware chip is calculated. The average signal delay values ​​of each data signal obtained in each type of firmware chip are summed to obtain the total signal delay value of the data signals of each type of firmware chip. The total signal delay value is then compared with the total number of data pins of the corresponding type of firmware chip to obtain the average signal delay value D of the data signals of each type of firmware chip.

2. The method according to claim 1, characterized in that, The timing sequence for acquiring data from the firmware chip under test includes: The timing sequence of the firmware chip under test when reading data is acquired using a logic analyzer.

3. The method according to claim 1, characterized in that, The signal delay value is the difference between the time when the clock signal triggers the falling edge and the time when the corresponding transition of the pin signal to be identified occurs within one clock cycle.

4. The method according to claim 3, characterized in that, The calculation of the average signal delay value of each pin signal to be identified includes: Calculate the ratio of the sum of the signal delay values ​​of each pin to be identified over all clock cycles to the sum of the number of times the pin to be identified and the clock signal trigger each other over all clock cycles.

5. The method according to claim 1, characterized in that, The firmware chip type includes at least one of the following: EPROM chips, SRAM chips, DRAM chips, NAND chips, and NOR chips.

6. A firmware chip data pin identification device, characterized in that, include: The timing acquisition module under test is used to acquire the timing of the firmware chip under test when reading data, and to mark the clock signal and the signals of each pin to be identified. The data pin identification module is used to measure and record the signal delay value of each pin to be identified in all clock cycles. Calculate the average signal delay value for each pin to be identified. If the average signal delay value is within a preset signal delay value variation range M of a known firmware chip of the same type as the firmware chip under test, then the pin to be identified corresponding to the average signal delay value is a data pin. The preset signal delay value variation range M of the known firmware chip of the same type as the firmware chip under test is set using the following method: Timing data is acquired from multiple known firmware chips of different types during data reading. The signal delay values ​​of each data signal in each type of firmware chip are measured and recorded over all clock cycles. The average signal delay value D of the data signals of each type of firmware chip is obtained. A delay deviation percentage T is set to obtain the range M of signal delay value variation for each type of firmware chip. M=[D (1-T), D (1+T)]; 0<T<=1; in which, The acquisition of the average signal delay value D of the data signals of various types of firmware chips includes: Based on the signal delay values ​​of each data signal in all clock cycles in each type of firmware chip, the average signal delay value of each data signal in each type of firmware chip is calculated. The average signal delay values ​​of each data signal obtained in each type of firmware chip are summed to obtain the total signal delay value of the data signals of each type of firmware chip. The total signal delay value is then compared with the total number of data pins of the corresponding type of firmware chip to obtain the average signal delay value D of the data signals of each type of firmware chip.

7. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in any one of claims 1-5.

8. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-5.

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