Array substrate and display panel

Abstract

This application discloses an array substrate and a display panel. The array substrate includes a substrate, a first metal layer, a second metal layer, a pixel electrode layer, and a shielding layer. The first metal layer includes a common signal line, the second metal layer includes a data line, and the pixel electrode layer includes a plurality of pixel electrodes. The shielding layer is located between the second metal layer and the pixel electrode layer and includes a plurality of first shielding electrodes and second shielding electrodes spaced apart. The first shielding electrodes have the same potential as the pixel electrodes, and the second shielding electrodes have the same potential as the common signal line. The orthographic projection of the first shielding electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate. The orthographic projection of the second shielding electrode on the substrate covers the orthographic projection of the data line on the substrate and at least partially overlaps with the orthographic projection of the pixel electrode on the substrate, thus ensuring transmittance and liquid crystal efficiency.

Description

Technical Field

[0001] This application relates to the field of display, and more particularly to an array substrate and a display panel. Background Technology

[0002] The existing pixel structure (with the addition of a transparent electrode layer to replace the DBS (data line BM less)) overlaps with the data line, which can shield the electric field of the data line. The transparent electrode layer is set across the entire surface and forms a large transparent storage capacitance with the pixel electrode layer, which can significantly improve transmittance and storage capacitance. However, the transparent electrode layer set across the entire surface has an electric field sealing effect, and it forms a lateral electric field with the pixel electrode. This causes the liquid crystal tilt state to not reach the set ideal value, resulting in a reduction in liquid crystal efficiency. Summary of the Invention

[0003] This application provides an array substrate and a display panel, which can solve the technical problem that the formation of a lateral electric field between the transparent electrode layer and the pixel electrode in the existing array substrate leads to a reduction in liquid crystal efficiency.

[0004] To solve the above problems, the technical solution provided in this application is as follows:

[0005] This application provides an array substrate, comprising:

[0006] Base;

[0007] A first metal layer is located on the substrate and includes a common signal line;

[0008] A second metal layer is located on the side of the first metal layer opposite to the substrate and includes data lines;

[0009] A pixel electrode layer, located on the side of the second metal layer opposite to the first metal layer and comprising a plurality of pixel electrodes; and

[0010] A shielding layer is located between the second metal layer and the pixel electrode layer and includes a plurality of first shielding electrodes and second shielding electrodes spaced apart. The first shielding electrodes have the same potential as the pixel electrodes, and the second shielding electrodes have the same potential as the common signal line.

[0011] Wherein, the orthographic projection of the first shielding electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the second shielding electrode on the substrate covers the orthographic projection of the data line on the substrate, and at least partially overlaps with the orthographic projection of the pixel electrode on the substrate.

[0012] According to the array substrate provided in this application, the array substrate includes a plurality of pixel electrode regions and at least one driving circuit region located on one side of the pixel electrode regions, wherein the pixel electrodes are located in the pixel electrode regions;

[0013] The pixel electrode layer further includes a connection electrode that is connected to the pixel electrode and extends from the pixel electrode region to the driving circuit region, wherein the first shielding electrode is electrically connected to the connection electrode within the driving circuit region.

[0014] According to the array substrate provided in this application, the first shielding electrode includes a first sub-shielding electrode and a second sub-shielding electrode extending from one side of the first sub-shielding electrode; the first sub-shielding electrode is located in the pixel electrode region, and the second sub-shielding electrode is located at least in the driving circuit region, and the second sub-shielding electrode is electrically connected to the connection electrode in the driving circuit region.

[0015] According to the array substrate provided in this application, the second metal layer further includes a source and a drain that are spaced apart and located in the driving circuit area; the source is electrically connected to the data line, the second sub-shielding electrode is electrically connected to the drain through a first via, the connecting electrode overlaps with the second sub-shielding electrode in the first via through a second via, and the first via is connected to the second via.

[0016] According to the array substrate provided in this application, the array substrate further includes:

[0017] A color resist layer is formed between the second metal layer and the shielding layer; and

[0018] An insulating layer is disposed between the shielding layer and the pixel electrode layer;

[0019] The first via penetrates the color resist layer, and the second via penetrates the insulating layer.

[0020] According to the array substrate provided in this application, the second shielding electrode includes a third sub-shielding electrode and a fourth sub-shielding electrode whose extension direction is parallel to and connected to the data line. The third sub-shielding electrode is located on one side of the pixel electrode region, and the fourth sub-shielding electrode is located on one side of the driving circuit region. The orthographic projection of the third sub-shielding electrode on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate.

[0021] According to the array substrate provided in this application, the first metal layer further includes scan lines, which are arranged to intersect with the data lines;

[0022] The second shielding electrode further includes a fifth sub-shielding electrode that is parallel to the scan line and connected to the third sub-shielding electrode. The third sub-shielding electrode, the fourth sub-shielding electrode and the fifth sub-shielding electrode are connected in a grid, and each of the first shielding electrodes is located in a grid.

[0023] The orthogonal projection of the fifth sub-shielding electrode on the substrate overlaps the orthogonal projection of the scan line on the substrate.

[0024] According to the array substrate provided in this application, the width of the portion where the orthographic projection of the third sub-shielding electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate is greater than 5 micrometers.

[0025] According to the array substrate provided in this application, the ratio of the area of ​​the first sub-shielding electrode to the area of ​​the pixel electrode ranges from 30% to 85%.

[0026] This application provides a display panel, including:

[0027] As described above, array substrate;

[0028] A color filter substrate is disposed opposite to the array substrate; and

[0029] A liquid crystal layer is located between the array substrate and the color filter substrate.

[0030] The beneficial effects of this application are as follows: In the array substrate and display panel provided in the embodiments of this application, the shielding layer, which is formed over the entire surface, is divided into two parts: a first shielding electrode and a plurality of second shielding electrodes spaced apart. The first shielding electrode has the same potential as the pixel electrode, and the orthographic projection of the first shielding electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate. Since there is no voltage difference between the first shielding electrode and the pixel electrode, the lateral electric field between them is avoided from affecting the deflection angle of the liquid crystal. At the same time, the second shielding electrode has the same potential as the common signal line, and the orthographic projection of the second shielding electrode on the substrate covers the orthographic projection of the data line on the substrate and at least partially overlaps with the orthographic projection of the pixel electrode on the substrate. This is beneficial for increasing the storage capacitance between them and improving transmittance. Thus, both transmittance and liquid crystal efficiency are guaranteed. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1This is a schematic cross-sectional view of a display panel provided in an embodiment of this application;

[0033] Figure 2 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application;

[0034] Figure 3 This is a schematic diagram of a planar structure of an array substrate provided in an embodiment of this application;

[0035] Figure 4 for Figure 3 A schematic diagram showing the positional relationship between the data lines, pixel electrodes, and shielding layer of the array substrate;

[0036] Figure 5 for Figure 3 A schematic diagram showing the positional relationship between the pixel electrode region and the driving circuit region of the array substrate;

[0037] Figure 6 for Figure 3 A schematic diagram of the first planar structure of the shielding layer of the array substrate;

[0038] Figure 7 for Figure 6 A magnified view of the structure at position A in the diagram;

[0039] Figure 8 for Figure 3 A cross-sectional view of the array substrate cut through the third via;

[0040] Figure 9 for Figure 3 A schematic diagram of the second planar structure of the shielding layer of the array substrate;

[0041] Figure 10 for Figure 3 A schematic diagram of the third planar structure of the shielding layer of the array substrate.

[0042] Explanation of reference numerals in the attached figures:

[0043] 100. Array substrate; 101. Pixel electrode area; 102. Driving circuit area;

[0044] 10. Substrate; 20. First metal layer; 21. Common signal line; 22. Gate; 23. Scan line; 30. Second metal layer; 31. Data line; 32. Source; 33. Drain; 40. Pixel electrode layer; 41. Pixel electrode; 42. Connecting electrode; 50. Shielding layer; 51. First shielding electrode; 511. First sub-shielding electrode; 512. Second sub-shielding electrode; 52. Second shielding electrode; 521. Third sub-shielding electrode; 522. Fourth sub-shielding electrode; 523. Fifth sub-shielding electrode; 60. Active layer; 70. Color resist layer; 81. Gate insulating layer; 82. Insulating layer; 83. Passivation layer;

[0045] 100a, First via; 100b, Second via; 100c, Third via;

[0046] 200, Color filter substrate; 201, Color filter base; 202, Black matrix layer; 203, Common electrode layer;

[0047] 300, liquid crystal layer; 301, liquid crystal molecules;

[0048] 400. Support column. Detailed Implementation

[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0050] In the description of this application, it should be understood that the terms "upper," "lower," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0051] Reference numerals and / or reference letters may be repeated in different embodiments of this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0052] The array substrate and display panel provided in this application will be described in detail below with reference to specific embodiments and accompanying drawings.

[0053] Please see Figure 1 This application provides a display panel, which includes an array substrate 100, a color filter substrate 200, and a liquid crystal layer 300. The array substrate 100 and the color filter substrate 200 are disposed opposite to each other, and the liquid crystal layer 300 is located between the color filter substrate 200 and the array substrate 100. The liquid crystal layer 300 includes a plurality of liquid crystal molecules 301. There is a voltage difference between the array substrate 100 and the color filter substrate 200, which can drive the liquid crystal molecules 301 in the liquid crystal layer 300 to rotate, thereby realizing image display.

[0054] Please see Figures 2-4 This application provides an array substrate 100, which includes a substrate 10, a first metal layer 20, a second metal layer 30, a pixel electrode layer 40, and a shielding layer 50.

[0055] The first metal layer 20 is located on the substrate 10 and includes a common signal line 21. The second metal layer 30 is located on the side of the first metal layer 20 opposite to the substrate 10 and includes a data line 31. The pixel electrode layer 40 is located on the side of the second metal layer 30 opposite to the first metal layer 20 and includes a plurality of pixel electrodes 41 spaced apart. The shielding layer 50 is located between the second metal layer 30 and the pixel electrode layer 40 and includes a plurality of first shielding electrodes 51 and second shielding electrodes 52 spaced apart. The first shielding electrodes 51 have the same potential as the pixel electrodes 41, and the second shielding electrodes 52 have the same potential as the common signal line 21. The orthographic projection of the first shielding electrode 51 on the substrate 10 overlaps with the orthographic projection of the pixel electrode 41 on the substrate 10. The orthographic projection of the second shielding electrode 52 on the substrate 10 covers the orthographic projection of the data line 31 on the substrate 10 and at least partially overlaps with the orthographic projection of the pixel electrode 41 on the substrate 10.

[0056] It is understood that the second shielding electrode 52 has the same potential as the common signal line 21, and the orthographic projection of the second shielding electrode 52 on the substrate 10 overlaps with the orthographic projection of the data line 31 on the substrate 10, so that there is no voltage difference between the second shielding electrode 52 and the color filter substrate 200. This ensures that the liquid crystal above the data line 31 is in a dark state, acting as a black matrix and preventing light leakage from both sides of the data line 31. Furthermore, the orthographic projection of the second shielding electrode 52 on the substrate 10 at least partially overlaps with the orthographic projection of the pixel electrode 41 on the substrate 10, increasing the storage capacitance between the pixel electrode 41 and the shielding layer 50, which is beneficial for improving transmittance.

[0057] Meanwhile, the first shielding electrode 51 and the pixel electrode 41 have the same potential, so there is no voltage difference between the first shielding electrode 51 and the pixel electrode 41. This avoids the generation of a lateral electric field between them affecting the liquid crystal deflection angle, which is beneficial to improving liquid crystal efficiency. In this way, both transmittance and liquid crystal efficiency are guaranteed.

[0058] In this embodiment, the orthogonal projection of the pixel electrode 41 on the substrate 10 covers the orthogonal projection of the first shielding electrode 51 on the substrate 10.

[0059] The pixel electrode 41 is transparent and is made of indium tin oxide (ITO). Of course, the material of the pixel electrode 41 is not limited to ITO and can also be other transparent electrode materials.

[0060] In this embodiment, the shielding layer 50 is also transparent to avoid blocking the backlight provided by the backlight module located on one side of the array substrate 100.

[0061] In the embodiments of this application, please refer to Figure 5 The array substrate 100 includes at least one pixel electrode region 101 and at least one driving circuit region 102, wherein the driving circuit region 102 is located on one side of the pixel electrode region 101. The pixel electrode region 101 is used to house the pixel electrode 41, and the driving circuit region 102 is used to house the driving circuit for driving liquid crystal deflection. In this embodiment, the number of pixel electrode regions 101 is at least two, and one driving circuit region 102 is located between two adjacent pixel electrode regions 101.

[0062] In the embodiments of this application, please refer to Figure 2 and Figure 5The pixel electrode layer 40 further includes a connection electrode 42 extending from the pixel electrode region 101 to the driving circuit region 102 and connected to the pixel electrode 41. The first shielding electrode 51 is electrically connected to the connection electrode 42 in the driving circuit region 102, so that the first shielding electrode 51 and the pixel electrode 41 have the same potential without affecting the aperture ratio of the pixel electrode 41.

[0063] Specifically, in the embodiments of this application, please refer to... Figure 2 and Figure 6 The first shielding electrode 51 includes a first sub-shielding electrode 511 and a second sub-shielding electrode 512 extending from one side of the first sub-shielding electrode 511. The first sub-shielding electrode 511 is located in the pixel electrode region 101, and the second sub-shielding electrode 512 is located at least in the driving circuit region 102. The second sub-shielding electrode 512 is electrically connected to the connection electrode 42 within the driving circuit region 102. In this embodiment, the second sub-shielding electrode 512 is completely located in the driving circuit region 102.

[0064] Optionally, the shape of the orthographic projection of the second sub-shielding electrode 512 onto the substrate 10 may include one of the following: a rectangle, a rhombus, a triangle, or an irregular shape. The shape of the second sub-shielding electrode 512 is not limited to the above-described structure. In this embodiment, the shape of the orthographic projection of the second sub-shielding electrode 512 onto the substrate 10 is rectangular.

[0065] It should be noted that there are multiple ways to achieve the same potential between the first shielding electrode 51 and the pixel electrode 41. For example, in one embodiment, the first shielding electrode 51 and the pixel electrode 41 are electrically connected and connected to the same signal. In another embodiment, there is no connection between the first shielding electrode 51 and the pixel electrode 41, but they are connected to the same signal. Specifically, the first shielding electrode 51 is connected to a signal trace, which is the same signal trace as the signal trace electrically connected to the pixel electrode 41. In yet another embodiment, there is no connection between the first shielding electrode 51 and the pixel electrode 41, and they are connected to different signals, but they have the same potential. Specifically, the first shielding electrode 51 is connected to a signal trace, which is a different signal trace from the signal trace electrically connected to the pixel electrode 41.

[0066] The following embodiments of this application are illustrated using the example of the first shielding electrode 51 being electrically connected to the pixel electrode 41 and receiving the same signal. However, it should be noted that other embodiments are also within the protection scope of the technical solutions provided in this application.

[0067] In the embodiments of this application, please refer to Figures 2 to 6 The second metal layer 30 further includes a source electrode 32 and a drain electrode 33 spaced apart and located in the driving circuit region 102; the source electrode 32 is electrically connected to the data line 31, the second sub-shielding electrode 512 is electrically connected to the drain electrode 33 through a first via 100a, the pixel electrode 41 is connected to the second sub-shielding electrode 512 through a second via 100b in the first via 100a, and the first via 100a and the second via 100b are connected. Thus, the data signal enters sequentially from the data line 31 into the source 32, the drain 33, the second sub-shielding electrode 512, the connecting electrode 42, and the pixel electrode 41. The second sub-shielding electrode 512 and the pixel electrode 41 receive the same data signal, that is, no voltage difference is generated between them, and therefore no lateral electric field is generated. The liquid crystal molecule 301 located directly above the second sub-shielding electrode 512 is only subject to the vertical electric field formed between the pixel electrode 41 and the common electrode on the color filter substrate 200, and is not affected by the lateral electric field. As a result, the deflection angle of the liquid crystal molecule 301 can reach the expected value, which is beneficial to improving the liquid crystal efficiency.

[0068] In this embodiment, the first via 100a and the second via 100b overlap in the thickness direction of the array substrate 100 to reduce the space occupied by the first via 100a and the second via 100b in the driving circuit region 102, thereby leaving enough space for the arrangement of various traces in the driving circuit, so that the area of ​​the driving circuit region 102 is reduced and the area of ​​the pixel electrode region 101 is increased, thereby further improving the aperture ratio.

[0069] In other embodiments, the connecting electrode 42 may also be electrically connected to the drain electrode 33 through a via, and the connecting electrode 42 may be electrically connected to the second sub-shielding electrode 512 through another via; or, the connecting electrode 42 may be electrically connected to the drain electrode 33 through a via, and the second sub-shielding electrode 512 may be electrically connected to the drain electrode 33 through a via.

[0070] In this embodiment, the first metal layer 20 further includes scan lines 23 and gates 22. The scan lines 23 are intersecting with the data lines 31, and the extension direction of the scan lines 23 is perpendicular to the extension direction of the data lines 31. The area between two adjacent scan lines 23 and two adjacent data lines 31 defines a sub-pixel. Each sub-pixel includes a pixel electrode region 101 and a driving circuit region 102. In this embodiment, the scan lines 23 extend along the X direction and are spaced apart along the Y direction, and the data lines 31 extend along the Y direction and are spaced apart along the X direction.

[0071] The scan line 23 is electrically connected to the gate 22, and the source 32 and the drain 33 are respectively positioned opposite to the gate 22. The array substrate 100 also includes a gate insulating layer 82 and an active layer 60 located on one side of the first metal layer 20. The gate insulating layer 82 covers the first metal layer 20, and the active layer 60 is located on the side of the gate insulating layer 82 away from the substrate 10. The array substrate 100 also includes a plurality of transistors, each transistor including a gate 22, an active layer 60, and a source 32 and a drain 33 positioned opposite to the gate 22 and the active layer 60. A scan signal enters the gate 22 from the scan line 23 to control the switching on and off of the transistor. A common signal enters the first shielding electrode 51 from the common signal line 21, so that the signals of the first shielding electrode 51 and the common electrode layer 203 on the color filter substrate 200 are the same common signal, and there is no voltage difference between them.

[0072] In this embodiment, the array substrate 100 further includes a color resist layer 70 and an insulating layer 82. The color resist layer 70 is formed between the second metal layer 30 and the shielding layer 50. The insulating layer 82 is disposed between the shielding layer 50 and the pixel electrode layer 40. A first via 100a penetrates the color resist layer 70, and a second via 100b penetrates the insulating layer 82. The color resist layer 70 includes a plurality of color resist blocks, including a blue color resist block, a red color resist block, and a green color resist block.

[0073] In this embodiment, the array substrate 100 further includes a passivation layer 83, which covers the second metal layer 30, and the color resist layer 70 is located on the side of the passivation layer 83 away from the substrate 10. The first via 100a penetrates both the color resist layer 70 and the passivation layer 83. In this embodiment, the material of the passivation layer 83 includes an inorganic material, which may include one or more combinations of silicon nitride, silicon oxide, and silicon oxynitride.

[0074] In this embodiment, the second shielding electrode 52 includes a third sub-shielding electrode 521 and a fourth sub-shielding electrode 522 that are parallel to and connected to the data line 31. The third sub-shielding electrode 521 is located on one side of the pixel electrode region 101, and the fourth sub-shielding electrode 522 is located on one side of the driving circuit region 102. The orthographic projection of the third sub-shielding electrode 521 on the substrate 10 at least partially overlaps with the orthographic projection of the pixel electrode 41 on the substrate 10. That is, the third sub-shielding electrode 521 overlaps with the data line 31 and the pixel electrode 41. The portion of the third sub-shielding electrode 521 that overlaps with the data line 31 is used to prevent light leakage from the data line 31, and the portion that overlaps with the pixel electrode 41 is used to form a storage capacitor between the third sub-shielding electrode 521 and the pixel electrode 41 to improve transmittance.

[0075] The fourth sub-shielding electrode 522 partially overlaps with the data line 31 to prevent light leakage from the data line 31.

[0076] In this embodiment, the second shielding electrode 52 further includes a fifth sub-shielding electrode 523 that is parallel to the scan line 23 and connected to the third sub-shielding electrode 521. The third sub-shielding electrode 521, the fourth sub-shielding electrode 522 and the fifth sub-shielding electrode 523 are connected in a grid shape, and each first shielding electrode 51 is located in a grid. Specifically, the first sub-shielding electrode 511 and the second sub-shielding electrode 512 are both located in the same grid.

[0077] In this embodiment, the orthogonal projection of the fifth sub-shielding electrode 523 on the substrate 10 covers the orthogonal projection of the scan line 23 on the substrate 10, thereby shielding the scan line 23 and ensuring that the liquid crystal above the scan line 23 is in a dark state, acting as a black matrix and preventing light leakage on both sides of the scan line 23.

[0078] Understandably, if the overlapping area between the second shielding electrode 52 and the pixel electrode 41 is too large (i.e., the overlapping area between the first shielding electrode 51 and the pixel electrode 41 is too small), the storage capacitance between the second shielding electrode 52 and the pixel electrode 41 is large, resulting in high transmittance. However, the improvement effect of the first shielding electrode 51 on the lateral electric field formed between itself and the pixel electrode 41 is not significant, leading to low liquid crystal efficiency. Conversely, if the overlapping area between the second shielding electrode 52 and the pixel electrode 41 is too small (i.e., the overlapping area between the first shielding electrode 51 and the pixel electrode 41 is too large), the improvement effect of the first shielding electrode 51 on the lateral electric field formed between itself and the pixel electrode 41 is more significant, resulting in high liquid crystal efficiency. However, the storage capacitance between the second shielding electrode 52 and the pixel electrode 41 is smaller, leading to low transmittance. Therefore, a balance needs to be struck between the overlapping areas of the second shielding electrode 52 and the pixel electrode 41 and the overlapping areas of the first shielding electrode 51 and the pixel electrode 41 to simultaneously ensure high transmittance and liquid crystal efficiency.

[0079] Therefore, in the embodiments of this application, please refer to Figure 4 The width d1 of the portion where the orthographic projection of the third sub-shielding electrode 521 on the substrate 10 overlaps with the orthographic projection of the pixel electrode 41 on the substrate 10 is greater than 5 micrometers. Furthermore, the ratio of the area of ​​the first sub-shielding electrode 511 to the area of ​​the pixel electrode 41 is in the range of 30%-85% to ensure high transmittance and liquid crystal efficiency.

[0080] In the embodiments of this application, please refer to Figure 2 and Figure 7 The minimum spacing d2 between the third sub-shielding electrode 521 and the first sub-shielding electrode 511 is in the range of 4 micrometers to 10 micrometers, so as to avoid short circuit between the third sub-shielding electrode 521 and the first sub-shielding electrode 511 arranged in the same layer.

[0081] In the embodiments of this application, please refer to Figure 8 The array substrate 100 further includes a third via 100c, through which the second shielding electrode 52 and the common signal line 21 are electrically connected. The third via 100c penetrates the color resist layer 70, the passivation layer 83 and the gate 22 insulating layer 82.

[0082] The common signal line 21 includes a first common signal line and a second common signal line, which are perpendicularly connected. One of the first common signal line 21 and the second common signal line is parallel to the data line 31. The second shielding electrode 52 is electrically connected to one of the first common signal line and the second common signal line through the third via 100c. In this embodiment, the third via 100c may be located in the driving circuit area 102.

[0083] In this embodiment, the shape of the orthographic projection of the first sub-shielding electrode 511 onto the substrate 10 includes one of the following: a rectangle, a rhombus, a triangle, or an irregular shape. The shape of the first sub-shielding electrode 511 is not limited to the above-described structure. Specifically, as... Figure 6 As shown, the orthographic projection of the first sub-shielding electrode 511 onto the substrate 10 is rectangular. Figure 9 As shown, the orthographic projection of the first sub-shielding electrode 511 onto the substrate 10 is rhomboid in shape. Figure 10 As shown, the first sub-shielding electrode 511 has a hexagonal shape as its orthogonal projection onto the substrate 10. The hexagon is composed of two isosceles trapezoids, namely an upright isosceles trapezoid and an inverted isosceles trapezoid.

[0084] In the embodiments of this application, please refer to Figure 1 and Figure 2 The color filter substrate 200 includes a color filter base 201, a patterned black matrix layer 202 formed on the color filter base 201, and a common electrode formed on the color filter base 201 and covering the black matrix layer 202, wherein the common electrode faces the pixel electrode layer 40.

[0085] A support post 400 is also provided between the array substrate 100 and the color filter substrate 200. The support post 400 is correspondingly provided with the black matrix layer 202 and plays a supporting role.

[0086] Beneficial Effects: In the array substrate and display panel provided in this application, the shielding layer, which covers the entire surface, is divided into two parts: a first shielding electrode and multiple second shielding electrodes spaced apart. The first shielding electrode has the same potential as the pixel electrode, and the orthographic projection of the first shielding electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate. Since there is no voltage difference between the first shielding electrode and the pixel electrode, the lateral electric field between them is avoided from affecting the deflection angle of the liquid crystal. At the same time, the second shielding electrode has the same potential as the common signal line, and the orthographic projection of the second shielding electrode on the substrate covers the orthographic projection of the data line on the substrate and at least partially overlaps with the orthographic projection of the pixel electrode on the substrate. This helps to increase the storage capacitance between them and improve the transmittance. Thus, both transmittance and liquid crystal efficiency are guaranteed.

[0087] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0088] The above provides a detailed description of an array substrate and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, characterized in that, include: Base; A first metal layer is located on the substrate and includes a common signal line; A second metal layer is located on the side of the first metal layer opposite to the substrate and includes data lines; A pixel electrode layer is located on the side of the second metal layer opposite to the first metal layer and includes a plurality of pixel electrodes; as well as A shielding layer is located between the second metal layer and the pixel electrode layer and includes a plurality of first shielding electrodes and second shielding electrodes spaced apart. The first shielding electrodes have the same potential as the pixel electrodes, and the second shielding electrodes have the same potential as the common signal line. Wherein, the orthographic projection of the first shielding electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the second shielding electrode on the substrate covers the orthographic projection of the data line on the substrate, and at least partially overlaps with the orthographic projection of the pixel electrode on the substrate.

2. The array substrate according to claim 1, characterized in that, The array substrate includes multiple pixel electrode regions and at least one driving circuit region located on one side of the pixel electrode regions, wherein the pixel electrodes are located in the pixel electrode regions; The pixel electrode layer further includes a connection electrode that is connected to the pixel electrode and extends from the pixel electrode region to the driving circuit region, wherein the first shielding electrode is electrically connected to the connection electrode within the driving circuit region.

3. The array substrate according to claim 2, characterized in that, The first shielding electrode includes a first sub-shielding electrode and a second sub-shielding electrode extending from one side of the first sub-shielding electrode; the first sub-shielding electrode is located in the pixel electrode region, and the second sub-shielding electrode is located at least in the driving circuit region, and the second sub-shielding electrode is electrically connected to the connection electrode in the driving circuit region.

4. The array substrate according to claim 3, characterized in that, The second metal layer further includes a source and a drain that are spaced apart and located in the driving circuit area; the source is electrically connected to the data line, the second sub-shielding electrode is electrically connected to the drain through a first via, the connecting electrode is connected to the second sub-shielding electrode through a second via in the first via, and the first via is connected to the second via.

5. The array substrate according to claim 4, characterized in that, The array substrate further includes: A color resist layer is formed between the second metal layer and the shielding layer; and An insulating layer is disposed between the shielding layer and the pixel electrode layer; The first via penetrates the color resist layer, and the second via penetrates the insulating layer.

6. The array substrate according to claim 3, characterized in that, The second shielding electrode includes a third sub-shielding electrode and a fourth sub-shielding electrode whose extension direction is parallel to and connected to the data line. The third sub-shielding electrode is located on one side of the pixel electrode region, and the fourth sub-shielding electrode is located on one side of the driving circuit region. The orthographic projection of the third sub-shielding electrode on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate.

7. The array substrate according to claim 6, characterized in that, The first metal layer further includes scan lines, which are arranged to intersect with the data lines; The second shielding electrode further includes a fifth sub-shielding electrode that is parallel to the scan line and connected to the third sub-shielding electrode. The third sub-shielding electrode, the fourth sub-shielding electrode and the fifth sub-shielding electrode are connected in a grid, and each of the first shielding electrodes is located in a grid. The orthogonal projection of the fifth sub-shielding electrode on the substrate overlaps the orthogonal projection of the scan line on the substrate.

8. The array substrate according to claim 7, characterized in that, The width of the portion where the orthographic projection of the third sub-shielding electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate is greater than 5 micrometers.

9. The array substrate according to claim 8, characterized in that, The ratio of the area of ​​the first sub-shielding electrode to the area of ​​the pixel electrode ranges from 30% to 85%.

10. A display panel, characterized in that, include: The array substrate as described in any one of claims 1-9; A color filter substrate is disposed opposite to the array substrate; as well as A liquid crystal layer is located between the array substrate and the color filter substrate.

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