Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel. The array substrate comprises a substrate, a first conductive layer and a second conductive layer. The first conductive layer is arranged on the substrate, and the second conductive layer is arranged on the side of the first conductive layer away from the substrate. The first conductive layer comprises a plurality of data lines arranged in a first direction. The second conductive layer comprises a plurality of pixel electrodes. The orthogonal projection of the pixel electrodes on the substrate corresponds to and partially overlaps the orthogonal projection of two adjacent data lines with opposite polarities on the substrate. The array substrate provided by the application can shield a part of the data lines by the pixel electrodes and the orthogonal projection of the two adjacent data lines with opposite polarities on the substrate, so as to avoid the problem of light leakage caused by the liquid crystal near the data line being flipped by the electric field generated by the data line, and improve the aperture ratio of the array substrate. Meanwhile, the vertical crosstalk generated by the data line on the pixel electrode can be offset to a certain extent.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] In existing technology, during normal operation of a liquid crystal display panel, the electric field generated by the data lines on the array substrate may cause the liquid crystal near the data lines to flip, resulting in light leakage. To avoid light leakage, a black matrix (BM) can be placed above the data lines, and a shielding metal can be placed on the sides of the data lines to shield the electric field generated by the data lines, thereby mitigating the impact of the electric field generated by the data lines on the liquid crystal.

[0003] In some exemplary embodiments, the pixel electrode may cover part of the data line to shield the electric field generated by the data line, thereby reducing the amount of shielding metal and increasing the aperture ratio of the array substrate. However, this approach can create an electric field between the data line and the pixel electrode, resulting in vertical crosstalk to the pixel electrode. Summary of the Invention

[0004] This application provides an array substrate and a display panel, which aims to solve the problem that when the electric field generated by the data line is shielded by the pixel electrode, the electric field formed between the data line and the pixel electrode will cause vertical crosstalk to the pixel electrode.

[0005] This application provides an array substrate, the array substrate comprising:

[0006] Substrate;

[0007] A first conductive layer is disposed on the substrate, the first conductive layer comprising a plurality of data lines distributed sequentially along a first direction, wherein the polarities of two adjacent data lines are opposite;

[0008] The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes a plurality of pixel electrodes, and the orthographic projection of the pixel electrodes on the substrate partially overlaps with the orthographic projection of two adjacent data lines on the substrate.

[0009] In some embodiments, the pixel electrode includes two interconnected sub-electrodes, which are sequentially distributed along the second direction. The orthographic projections of the two sub-electrodes of the pixel electrode on the substrate correspond one-to-one with and partially overlap with the orthographic projections of two adjacent data lines on the substrate.

[0010] In some embodiments, the data line includes a plurality of first trace segments distributed sequentially along its length direction, and a second trace segment connected between two adjacent first trace segments. The first trace segments extend along a second direction, the second direction is set at an angle to the first direction, and the second trace segment is set at an angle to the first trace segment.

[0011] The orthographic projections of the two sub-electrodes onto the substrate correspond one-to-one with and at least partially overlap with the orthographic projections of the first trace segments of the two adjacent data lines onto the substrate.

[0012] In some embodiments, the data line includes a plurality of first trace segments distributed sequentially along its length direction, and a second trace segment connected between two adjacent first trace segments. The first trace segments extend along a second direction, the second direction is set at an angle to the first direction, and the second trace segment is set at an angle to the first trace segment.

[0013] The pixel electrode includes two interconnected sub-electrodes, which are distributed sequentially along the second direction. The orthographic projections of the two sub-electrodes of the pixel electrode on the substrate correspond one-to-one with and at least partially overlap with the orthographic projections of the first trace segments of the two adjacent data lines on the substrate.

[0014] In some embodiments, the first conductive layer includes a first storage electrode connected to the pixel electrode, and the array substrate further includes a third conductive layer located on the side of the first conductive layer away from the second conductive layer. The third conductive layer includes a second storage electrode, which is disposed opposite to the first storage electrode and forms a storage capacitor.

[0015] The first storage electrode is located between the two sub-electrodes of the corresponding pixel electrode, and a gap is formed between two adjacent first storage electrodes in the first direction for the second trace segment to pass through, the extension direction of the gap being consistent with the extension direction of the second trace segment.

[0016] In some embodiments, the first storage electrode is in the shape of a parallelogram; the outer contour of the pixel electrode is rectangular.

[0017] In some embodiments, the capacitance of the capacitor structure formed by the pixel electrode and the corresponding two data lines is equal.

[0018] In some embodiments, the sub-electrode includes a main electrode extending along the second direction, and a branch electrode connected to the main electrode, wherein the orthographic projection of the main electrode of the two sub-electrodes on the substrate corresponds one-to-one with and at least partially overlaps the orthographic projection of the two adjacent data lines on the substrate.

[0019] In some embodiments, the orthographic projection of the first trace segment on the substrate lies within the orthographic projection of the corresponding trunk electrode on the substrate.

[0020] In some embodiments, the width of the main electrode is greater than or equal to the width of the first trace segment.

[0021] This application embodiment also provides a display device, the display device comprising: a color filter substrate, an array substrate as described above, and a liquid crystal layer located between the array substrate and the color filter substrate, the array substrate comprising:

[0022] Substrate;

[0023] A first conductive layer is disposed on the substrate, the first conductive layer comprising a plurality of data lines distributed sequentially along a first direction, wherein the polarities of two adjacent data lines are opposite;

[0024] The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes a plurality of pixel electrodes, and the orthographic projection of the pixel electrodes on the substrate partially overlaps with the orthographic projection of two adjacent data lines on the substrate.

[0025] The array substrate provided in this application embodiment overlaps the orthographic projection of the pixel electrode on the substrate with the orthographic projections of two adjacent data lines of opposite polarity on the substrate. This allows the pixel electrode to shield a portion of the data lines, preventing the electric field generated by the data lines from causing liquid crystal flipping near the data lines and resulting in light leakage. Furthermore, it eliminates the need for shielding metal on the sides of the data lines, increasing the aperture ratio of the array substrate. Simultaneously, it can also mitigate vertical crosstalk between the data lines and the pixel electrodes to some extent, thereby improving the display panel's display performance. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0027] Figure 1 A partial view of one embodiment of the array substrate provided in this application;

[0028] Figure 2 for Figure 1 Enlarged view of point A in the middle;

[0029] Figure 3 for Figure 2 A cross-sectional view at point B, wherein the cutting plane is perpendicular to the second direction;

[0030] Figure 4 A cross-sectional view of one embodiment of the display panel provided in this application.

[0031] Display panel 100; array substrate 110; first conductive layer 111; data line 1111; first trace segment 1112; second trace segment 1113; source 1114; drain 1115; first storage electrode 1116; gap 1117; opening 1118; second conductive layer 112; pixel electrode 1121; sub-electrode 1122; main electrode 1123; branch electrode 1124; connection portion 1125; third conductive layer 113; scan line 1131; second storage electrode 1132; gate 1133; common connection line 1134; semiconductor layer 114; active layer 1141; thin film transistor 115; insulating layer 116; gate insulating layer 117; substrate 118; color filter substrate 120; liquid crystal layer 130; first direction X; second direction Y. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0033] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0034] This application provides an array substrate and a display panel. These will be described in detail below.

[0035] Figure 4 A cross-sectional view of one embodiment of the display panel provided in this application. Figure 4 As shown, the display panel 100 includes a color filter substrate 120, an array substrate 110, and a liquid crystal layer 130 located between the array substrate 110 and the color filter substrate 120. The array substrate 110 is used to control the deflection angle of liquid crystals at different positions in the liquid crystal layer 130, so that light from the side of the array substrate 110 away from the liquid crystal layer 130 passes through a portion of the liquid crystals and the color filter substrate 120, thereby realizing the image display of the display panel 100.

[0036] Figure 1 This is a partial view of one embodiment of the array substrate provided in this application. Figure 2 for Figure 1 A magnified view of point A in the middle. (See image below.) Figure 1 and Figure 2 As shown, the array substrate 110 includes data lines 1111, scan lines 1131, and arrayed thin-film transistors 115 and pixel electrodes 1121. The data lines 1111, scan lines 1131, and pixel electrodes 1121 are respectively connected to the thin-film transistors 115. The scan lines 1131 are used to provide scan signals to the thin-film transistors 115, and the data lines 1111 are used to provide data signals to the thin-film transistors 115, so as to provide driving voltage to the pixel electrodes 1121 through the thin-film transistors 115, thereby driving the liquid crystal corresponding to the pixel electrodes 1121 to rotate to a predetermined angle.

[0037] During normal operation of the display panel 100, the electric field generated by the data lines 1111 on the array substrate 110 may cause the liquid crystal near the data lines 1111 to flip, resulting in light leakage. To avoid light leakage, a black matrix (not shown in the figure) can be placed above the data lines 1111, and a shielding metal can be placed on the side of the data lines 1111 to shield the electric field generated by the data lines 1111, thereby reducing the impact of the electric field generated by the data lines 1111 on the liquid crystal. However, the placement of the shielding metal will affect the aperture ratio of the array substrate 110.

[0038] To avoid the above problems, this application provides an array substrate.

[0039] Figure 3 for Figure 2 A sectional view at point B, where the cutting plane is perpendicular to the second direction. (See figure.) Figure 2 and Figure 3As shown, the array substrate 110 includes a substrate 118, a first conductive layer 111, and a second conductive layer 112. The first conductive layer is disposed on the substrate 118, and the second conductive layer 112 is located on the side of the first conductive layer 111 facing away from the substrate 118. The substrate 118 can be made of an insulating and transparent material. The materials of the first conductive layer 111 and the second conductive layer 112 include metallic materials and conductive non-metallic materials. An insulating layer 116 can be disposed between the first conductive layer 111 and the second conductive layer 112 to separate them.

[0040] The first conductive layer 111 includes a data line 1111 for providing data signals. The second conductive layer 112 includes a plurality of pixel electrodes 1121 for generating an electric field to control the deflection of liquid crystal molecules from an initial direction to a predetermined angle.

[0041] Specifically, the array substrate 110 includes data lines 1111, scan lines 1131, thin-film transistors 115, and pixel electrodes 1121. The thin-film transistor 115 includes a source 1114, a drain 1115, a gate 1133, and an active layer 1141. The data lines 1111 are connected to the source 1114 of the thin-film transistor 115, the scan lines 1131 are connected to the gate 1133 of the thin-film transistor 115, and the pixel electrodes 1121 are connected to the drain 1115 of the thin-film transistor 115. The scan lines 1131 provide scan signals to the gate 1133 of the thin-film transistor 115, enabling the source 1114 and drain 1115 of the thin-film transistor 115 to conduct through the active layer 1141. The data line 1111 is used to provide data signals to the pixel electrode 1121 through the source 1114 and drain 1115 of the thin film transistor 115, so that the pixel electrode 1121 can generate an electric field to control the liquid crystal molecules to deflect from the initial direction to a predetermined angle.

[0042] In some embodiments, the orthographic projection of the pixel electrode 1121 of the second conductive layer 112 onto the substrate 118 partially overlaps with the orthographic projection of the data line 1111 of the first conductive layer 111 onto the substrate 118. Therefore, the pixel electrode 1121 can shield a portion of the data line 1111, thereby preventing light leakage caused by the electric field generated by the data line 1111 causing liquid crystal flipping near the data line 1111. Furthermore, compared to existing array substrates, the array substrate 110 provided in this embodiment does not require shielding metal on the sides of the data line 1111, thus avoiding the problem of reduced aperture ratio caused by the presence of shielding metal.

[0043] It should be noted that the orthographic projection of data line 1111 onto substrate 118 refers to the projection of data line 1111 onto substrate 118 along its thickness direction (perpendicular to the first direction X and the second direction Y, respectively). The orthographic projection of pixel electrode 1121 onto substrate 118 is the projection of pixel electrode 1121 onto substrate 118 along its thickness direction. Furthermore, the orthographic projections of multiple pixel electrodes 1121 of the second conductive layer 112 onto substrate 118 can overlap with the orthographic projection of data line 1111 of the first conductive layer 111 onto substrate 118, or the orthographic projection of a single pixel electrode 1121 of the second conductive layer 112 onto substrate 118 can overlap with the orthographic projection of data line 1111 of the first conductive layer 111 onto substrate 118. Of course, the former can further improve the shielding effect of data line 1111, thereby further preventing the electric field generated by data line 1111 from causing liquid crystal flipping near data line 1111.

[0044] like Figure 2 and Figure 3 As shown, the first conductive layer 111 of the array substrate 110 includes a plurality of data lines 1111 sequentially distributed along a first direction X. The polarities of two adjacent data lines 1111 are opposite. Each data line 1111 is connected to the source 1114 of a plurality of thin-film transistors 115.

[0045] In some embodiments, the orthographic projection of the pixel electrode 1121 on the substrate 118 overlaps with the orthographic projections of two adjacent data lines 1111 on the substrate 118. It is understood that, since the polarities of the two adjacent data lines 1111 are opposite, by making the orthographic projection of the pixel electrode 1121 on the substrate 118 overlap with the orthographic projections of two adjacent data lines 1111 with opposite polarities on the substrate 118, the vertical crosstalk generated by the data lines 1111 on the pixel electrode 1121 can be at least partially offset, thereby providing a better display effect for the display panel 100.

[0046] The pixel electrode 1121 includes two interconnected sub-electrodes 1122, which are sequentially distributed along the second direction Y. The orthographic projections of the two sub-electrodes 1122 on the substrate 118 correspond one-to-one with and partially overlap with the orthographic projections of two adjacent data lines 1111 on the substrate 118. Since the polarities of the data lines 1111 opposite to the two sub-electrodes 1122 of the pixel electrode 1121 are opposite, the vertical crosstalk generated by the two adjacent data lines 1111 to the pixel electrode 1121 can cancel each other out.

[0047] In some embodiments, the capacitance of the pixel electrode 1121 is equal to that of the capacitor structure formed by the two corresponding data lines 1111. Therefore, the pixel electrode 1121 has a capacitance equivalent to and opposite in polarity to the capacitance formed by the two adjacent data lines 1111, thereby better canceling the vertical crosstalk generated by the two adjacent data lines 1111 on the pixel electrode 1121.

[0048] like Figure 2 and Figure 3 As shown, the data line 1111 includes a plurality of first trace segments 1112 sequentially distributed along its length, and a second trace segment 1113 connecting two adjacent first trace segments 1112. The orthographic projection of the pixel electrode 1121 of the second conductive layer 112 onto the substrate 118 at least partially overlaps with the orthographic projection of the first trace segment 1112 of the data line 1111 onto the substrate 118. This allows the pixel electrode 1121 to shield at least a portion of the first trace segment 1112 of the data line 1111, thereby preventing light leakage caused by the electric field generated by the first trace segment 1112 of the data line 1111 causing liquid crystal flipping near the data line 1111.

[0049] like Figure 2 As shown, the first trace segment 1112 of data line 1111 extends along the second direction Y, which forms an angle with the first direction X. The second trace segment 1113 of data line 1111 forms an angle with the first trace segment 1112.

[0050] In some embodiments, the orthographic projection of the pixel electrode 1121 on the substrate 118 at least partially overlaps with the orthographic projection of the first trace segment 1112 of the two adjacent data lines 1111 on the substrate 118. Specifically, the orthographic projections of the two sub-electrodes 1122 of the pixel electrode 1121 on the substrate 118 correspond one-to-one with and at least partially overlap with the orthographic projections of the first trace segment 1112 of the two adjacent data lines 1111 on the substrate 118, thereby making the capacitance of the capacitor structure formed by the two sub-electrodes 1122 of the pixel electrode 1121 and the corresponding data lines 1111 as equal as possible.

[0051] like Figure 2 and Figure 3As shown, the sub-electrodes 1122 of the pixel electrode 1121 include a main electrode 1123 extending along the second direction Y, and a branch electrode 1124 connected to the main electrode 1123. The orthographic projections of the main electrodes 1123 of the two sub-electrodes 1122 on the substrate 118 can correspond one-to-one with and at least partially overlap with the orthographic projections of two adjacent data lines 1111 on the substrate 118. Alternatively, the orthographic projections of the branch electrodes 1124 of the two sub-electrodes 1122 on the substrate 118 can at least partially overlap with the orthographic projections of two adjacent data lines 1111 on the substrate 118. The former, of course, allows the pixel electrode 1121 to provide better shielding for the data lines 1111.

[0052] Specifically, the orthographic projections of the main electrodes 1123 of the two sub-electrodes 1122 onto the substrate 118 correspond one-to-one with and at least partially overlap with the orthographic projections of the first trace segments 1112 of the adjacent two data lines 1111 onto the substrate 118. Specifically, the orthographic projection of the first trace segment 1112 onto the substrate 118 lies within the orthographic projection of the corresponding main electrode 1123 onto the substrate 118. Thus, the orthographic projections of the main electrodes 1123 of the pixel electrode 1121 onto the substrate 118 and the first trace segments 1112 of the data lines 1111 onto the substrate 118 have a high degree of overlap, which greatly improves the shielding effect of the pixel electrode 1121 on the data lines 1111, thereby minimizing the possibility of liquid crystal flipping near the data lines 1111 caused by the electric field generated by the data lines 1111.

[0053] It should be noted that the orthographic projection of the first trace segment 1112 on the substrate 118 lies within the orthographic projection of the corresponding main electrode 1123 on the substrate 118. This can be either the orthographic projection of the first trace segment 1112 on the substrate 118 coincides with the orthographic projection of the corresponding main electrode 1123 on the substrate 118, or the orthographic projection of the first trace segment 1112 on the substrate 118 is completely covered by the orthographic projection of the corresponding main electrode 1123 on the substrate 118, with at least a portion of the edge of the orthographic projection of the first trace segment 1112 on the substrate 118 spaced apart from at least a portion of the edge of the orthographic projection of the corresponding main electrode 1123 on the substrate 118. The latter arrangement further improves the shielding effect of the pixel electrode 1121 on the data line 1111.

[0054] In some embodiments, the width of the main electrode 1123 is greater than or equal to the width of the first trace segment 1112, such that the orthographic projection of the first trace segment 1112 on the substrate 118 is completely covered by the orthographic projection of the corresponding main electrode 1123 on the substrate 118.

[0055] Specifically, the width of the orthographic projection of the main electrode 1123 onto the substrate 118 in the first direction X is greater than the width of the orthographic projection of the first trace segment 1112 onto the substrate 118 in the first direction X. Furthermore, the two side edges of the orthographic projection of the main electrode 1123 onto the substrate 118 in the first direction X are spaced apart from the two side edges of the orthographic projection of the first trace segment 1112 onto the substrate 118 in the first direction X. The distance between the two side edges of the orthographic projection of the first trace segment 1112 onto the substrate 118 and the orthographic projection of the main electrode 1123 onto the substrate 118 in the first direction X is the same.

[0056] like Figure 1 and Figure 2 As shown, the plurality of pixel electrodes 1121 of the second conductive layer 112 are arrayed along the first direction X and the second direction Y. The second direction Y can be perpendicular to the first direction X or at an acute angle. Specifically, the first direction X is perpendicular to the second direction Y, and both the first direction X and the second direction Y are perpendicular to the thickness direction of the substrate 118.

[0057] The first conductive layer 111 includes a first storage electrode 1116 connected to the pixel electrode 1121. The array substrate 110 also includes a third conductive layer 113 located on the side of the first conductive layer 111 away from the second conductive layer 112. The third conductive layer 113 includes a second storage electrode 1132. The second storage electrode 1132 is disposed opposite to the first storage electrode 1116 and forms a storage capacitor.

[0058] In some embodiments, the first storage electrode 1116 is located between two sub-electrodes 1122 of the corresponding pixel electrode 1121. A gap 1117 is formed between two adjacent first storage electrodes 1116 in the first direction X for a second trace segment 1113 to pass through. The extending direction of the gap 1117 is consistent with the extending direction of the second trace segment 1113. Thus, while the second trace segment 1113 can pass through the gap 1117 and connect with two adjacent first trace segments 1112, the width of the gap 1117 is as narrow as possible, thereby maximizing the area of ​​the first storage electrode 1116.

[0059] The first storage electrode 1116 is a parallelogram in shape. Therefore, a gap 1117 of uniform width can be formed between the hypotenuses of two adjacent first storage electrodes 1116 in the first direction X, and the extension direction of the gap 1117 is consistent with the extension direction of the second trace segment 1113. Specifically, the two sides of the first storage electrode 1116 along the second direction Y are parallel to the first direction X, and the first storage electrode 1116 extends along the length direction of the second trace segment 1113 along the two sides of the first direction X.

[0060] In some embodiments, the outer contour of the pixel electrode 1121 is rectangular. Therefore, the corresponding color resist shape can also be rectangular, thereby preventing changes in the shape of the pixel electrode 1121 from affecting the color resist manufacturing process and display effect.

[0061] like Figure 2 As shown, the first conductive layer 111 further includes a source 1114 connected to the data line 1111, and a drain 1115 connected to the pixel electrode 1121. The array substrate 110 also includes an active layer 1141 connected to the source 1114 and the drain 1115, which is located on the side of the third conductive layer 113 facing the first conductive layer 111. The drain 1115 is connected to the first storage electrode 1116, and the first storage electrode 1116 is connected to the pixel electrode 1121, thereby connecting the drain 1115 to the pixel electrode 1121.

[0062] In some embodiments, such as Figure 2 and Figure 3 As shown, the array substrate 110 also includes a first insulating layer 116 located between the first conductive layer 111 and the second conductive layer 112. The first insulating layer 116 has an opening 1118, through which the pixel electrode 1121 passes and connects to the first storage electrode 1116.

[0063] Specifically, the third conductive layer 113 includes a gate 1133, a scan line 1131, and a second storage electrode 1132. The scan line 1131 extends along a first direction X. There are multiple scan lines 1131, which are sequentially distributed along a second direction Y. Each of the multiple gates 1133 sequentially distributed along the first direction X is connected to a scan line 1131. The third conductive layer 113 includes multiple rows of second storage electrodes 1132 sequentially distributed along the second direction Y. Each row of second storage electrodes 1132 has multiple second storage electrodes 1132 sequentially distributed along the first direction X. The second storage electrodes 1132 are parallelograms in shape. The two edges of the second storage electrodes 1132 along the second direction Y are parallel to the first direction X, and the two edges of the second storage electrodes 1132 along the first direction X form an angle with the second direction Y.

[0064] The third conductive layer 113 also includes common connection lines 1134 distributed sequentially along the second direction Y, each common connection line 1134 extending along the first direction X. One common connection line 1134 is connected to a plurality of second storage electrodes 1132 in a row of second storage electrodes 1132.

[0065] The array substrate 110 includes a semiconductor layer 114 located on the side of the third conductive layer 113 away from the substrate 118. The semiconductor layer 114 includes a plurality of active layers 1141, each of which corresponds to a plurality of gates 1133. A gate insulating layer 117 is provided between the active layers 1141 and the gates 1133.

[0066] Multiple first trace segments 1112 of the data lines 1111 of the first conductive layer 111 extend along the second direction Y, and the multiple first trace segments 1112 are staggered in the second direction Y, so that the orthographic projection of the two sub-electrodes 1122 of the pixel electrode 1121 on the substrate 118 corresponds one-to-one with the orthographic projection of the first trace segments 1112 of the two adjacent data lines 1111 on the substrate 118 and at least partially overlaps.

[0067] The data line 1124 comprises multiple branch electrodes 1124, which are distributed on both sides of the main electrode 1123 along the first direction X. Branch electrodes 1124 located on the same side of the main electrode 1123 extend in the same direction and are sequentially spaced along the second direction Y. The orthographic projection of the first trace segment 1112 of the data line 1111 onto the substrate 118 lies within the orthographic projection of the corresponding pixel electrode 1121's main electrode 1123 onto the substrate 118. The second trace segment 1113 of the data line 1111 is connected to the source electrode 1114.

[0068] A portion of the orthographic projection of the first storage electrode 1116 on the substrate 118 lies between the orthographic projections of two adjacent sub-electrodes 1122 of the corresponding pixel electrode 1121 on the substrate 118, and another portion of the orthographic projection of the first storage electrode 1116 on the substrate 118 lies between the orthographic projections of two sub-electrodes 1122 of another pixel electrode 1121 adjacent to the corresponding pixel electrode 1121 on the substrate 118.

[0069] Pixel electrode 1121 includes a connecting portion 1125, the extending direction of which is consistent with the extending direction of the second trace segment 1113. Multiple branch electrodes 1124 of a sub-electrode 1122 of pixel electrode 1121 located on one side of the main electrode 1123 are connected to the connecting portion 1125. The main electrode 1123 of a sub-electrode 1122 of pixel electrode 1121 is connected to the connecting portion 1125. The orthographic projection of the opening 1118 of insulating layer 116 onto substrate 118 lies within the orthographic projection of the first storage electrode 1116 onto substrate 118, and the orthographic projection of the opening 1118 onto substrate 118 lies within the orthographic projection of the connecting portion 1125 onto substrate 118, allowing the connecting portion 1125 to pass through the opening 1118 and connect to the first storage electrode 1116, thereby achieving the connection between pixel electrode 1121 and the first storage electrode 1116.

[0070] This application also provides a display panel, which includes an array substrate. The specific structure of the array substrate is as described in the above embodiments. Since this display panel adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0071] Among them, such as Figure 4 As shown, the display panel 100 includes a color filter substrate 120, an array substrate 110, and a liquid crystal layer 130 located between the array substrate 110 and the color filter substrate 120. The structure of the array substrate 110 can refer to the above embodiments, and the structures of the color filter substrate 120 and the liquid crystal layer 130 can be existing color filter substrates and liquid crystal layers, which will not be described in detail here.

[0072] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0073] The above provides a detailed description of an array substrate and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, characterized in that, The array substrate includes: Substrate; A first conductive layer is disposed on the substrate, the first conductive layer comprising a plurality of data lines distributed sequentially along a first direction, wherein the polarities of two adjacent data lines are opposite; The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes a plurality of pixel electrodes, and the orthographic projection of the pixel electrodes on the substrate partially overlaps with the orthographic projection of two adjacent data lines on the substrate. The array substrate includes a thin-film transistor connected to the data line; the pixel electrode includes two sub-electrodes connected to each other, the two sub-electrodes are distributed sequentially along a second direction, the thin-film transistor is located between the two sub-electrodes, the orthographic projection of the two sub-electrodes of the pixel electrode on the substrate corresponds one-to-one with and partially overlaps the orthographic projection of the two adjacent data lines on the substrate, and the second direction is set at an angle to the first direction.

2. The array substrate as described in claim 1, characterized in that, The data line includes a plurality of first trace segments distributed sequentially along its length, and a second trace segment connected between two adjacent first trace segments. The first trace segments extend along a second direction, and the second trace segment is set at an angle to the first trace segment. The orthographic projections of the two sub-electrodes on the substrate correspond one-to-one with the orthographic projections of the first trace segments of the two adjacent data lines on the substrate and at least partially overlap.

3. The array substrate as described in claim 2, characterized in that, The first conductive layer includes a first storage electrode connected to the pixel electrode. The array substrate also includes a third conductive layer located on the side of the first conductive layer away from the second conductive layer. The third conductive layer includes a second storage electrode, which is disposed opposite to the first storage electrode and forms a storage capacitor. The first storage electrode is located between the two sub-electrodes of the corresponding pixel electrode, and a gap is formed between two adjacent first storage electrodes in the first direction for the second trace segment to pass through, the extension direction of the gap being consistent with the extension direction of the second trace segment.

4. The array substrate as described in claim 3, characterized in that, The first storage electrode is in the shape of a parallelogram; the outer contour of the pixel electrode is rectangular.

5. The array substrate as described in any one of claims 1 to 4, characterized in that, The capacitance of the capacitor structure formed by the pixel electrode and the corresponding two data lines is equal.

6. The array substrate as described in any one of claims 2 to 4, characterized in that, The sub-electrode includes a main electrode extending along the second direction, and a branch electrode connected to the main electrode. The orthographic projection of the main electrode of the two sub-electrodes on the substrate corresponds one-to-one with the orthographic projection of the two adjacent data lines on the substrate and at least partially overlaps.

7. The array substrate as described in claim 6, characterized in that, The orthographic projection of the first trace segment on the substrate lies within the orthographic projection of the corresponding main electrode on the substrate.

8. The array substrate as claimed in claim 7, characterized in that, The width of the main electrode is greater than or equal to the width of the first trace segment.

9. A display panel, characterized in that, include: A color filter substrate, an array substrate as described in any one of claims 1 to 8, and a liquid crystal layer located between the array substrate and the color filter substrate.

Images