A data power-on processing method, system, device, and computer storage medium

Abstract

This application discloses a data power-on processing method, system, device, and computer storage medium, relating to the field of storage technology. After power-on, the method reads first data and its first LBA address in a TLC (Transmission Controlled Library) into memory. The first data includes data not written to the TLC after power failure. The method determines the storage location of the first data in memory and establishes a mapping relationship between the storage location and the corresponding first LBA address. In response to a simulated read instruction, the method uses the mapping relationship to read second data to be written to the TLC from memory or the TLC and stores it in a cache. The simulated read instruction includes instructions obtained by simulating read instructions from the host side. In response to a simulated write instruction, the method writes the second data into the TLC according to the minimum write amount of the TLC. The simulated write instruction includes instructions obtained by simulating write instructions from the host side. This method improves data recovery efficiency by utilizing memory, mapping relationships, simulated read instructions, cache, and simulated write instructions.

Description

Technical Field

[0001] This application relates to the field of storage technology, and more specifically, to a data power-on processing method, system, device, and computer storage medium. Background Technology

[0002] Currently, in the application of SSDs (Solid State Disks) for data storage, data security and integrity are extremely important. Data loss or errors can cause incalculable losses to customers. Since power outages or disk insertions / removals can occur at any time during data writing to the host, ensuring data security in such situations is a crucial issue that the storage industry needs to focus on and resolve. Especially in sequential write scenarios such as ZNS, combined with the read / write characteristics of NAND, upon power-up, it is necessary to handle data ownership logic, data migration, and cache recovery logic. This increases software complexity and the coupling of data partitioning, reducing the SSD's recovery efficiency after power-up.

[0003] In conclusion, improving the data recovery efficiency of SSDs after power-on is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a data power-on processing method, which can, to some extent, solve the technical problem of how to improve the data recovery efficiency of SSDs after power-on. This application also provides a data power-on system, an electronic device, and a computer-readable storage medium.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] A data power-on processing method, comprising:

[0007] After power-on, the first data stored and the first LBA address of the first data in the TLC are read into memory. The first data includes data that was not written to the TLC after power failure.

[0008] Determine the storage location of the first data in the memory, and establish a mapping relationship between the storage location and the corresponding first LBA address;

[0009] In response to a simulated read instruction, the second data to be written to the TLC is read from the memory or the TLC and placed into the cache using the mapping relationship. The simulated read instruction includes an instruction obtained by simulating a read instruction on the host side.

[0010] In response to a simulated write command, the second data is written into the TLC according to the minimum write amount of the TLC, wherein the simulated write command includes an instruction obtained by simulating the write command on the host side.

[0011] Preferably, reading the stored first data and the first LBA address of the first data in the TLC into memory includes:

[0012] Read the first data and the first LBA address stored in each page of the SLC, and transfer the first data and the first LBA address to the corresponding memory space of the memory, wherein the size of the memory space is equal to the size of the page of the SLC;

[0013] Determining the storage location of the first data in memory and establishing a mapping relationship between the storage location and the corresponding first LBA address includes:

[0014] The memory space is divided according to the unit size value of LBA to obtain memory subspaces;

[0015] The storage location of the first data in the memory is determined on a unit basis, using the memory subspace as the unit;

[0016] Establish the mapping relationship between the storage location and the corresponding first LBA address.

[0017] Preferably, the step of transferring the first data and the first LBA address to the corresponding memory space of the memory includes:

[0018] Using the zone to which the first data belongs in the TLC as a unit, the first data and the first LBA address are transferred to the memory space in the memory corresponding to the zone;

[0019] Establishing the mapping relationship between the storage location and the corresponding first LBA address includes:

[0020] Using the zone as a unit, establish the mapping relationship between the storage location to which the zone belongs and the corresponding first LBA address.

[0021] Preferably, the step of responding to a simulated read instruction and applying the mapping relationship to read the second data to be written to the TLC into the cache includes:

[0022] In response to the simulated read instruction, determine whether a second LBA address corresponding to the simulated read instruction exists in the mapping relationship;

[0023] If the second LBA address exists in the mapping relationship, then according to the mapping relationship, the second data is read from the storage location corresponding to the second LBA address and the second data is transferred to the cache;

[0024] If the second LBA address does not exist in the mapping relationship, then the second data corresponding to the second LBA address is read from the TLC and the second data is transferred to the cache.

[0025] Preferably, the step of responding to a simulated read instruction and applying the mapping relationship to read the second data to be written to the TLC into the cache includes:

[0026] In response to a simulated read instruction that sequentially reads data corresponding to the LBA addresses of the TLC, the second data to be written to the TLC is read from the memory or the TLC and placed into the cache using the mapping relationship.

[0027] Preferably, the step of responding to a simulated write command and writing the second data into the TLC according to the minimum write amount of the TLC includes:

[0028] Determine the number of LBA addresses corresponding to the minimum write limit of the TLC;

[0029] Use the minimum LBA address of the second data as the current starting address, and determine the maximum LBA address of the second data;

[0030] In the cache, it is determined whether the numerical LBA addresses starting from the current starting address are consecutive;

[0031] If the number of LBA addresses starting from the current starting address are consecutive, then the second data corresponding to the number of LBA addresses starting from the current starting address is written into the TLC;

[0032] If the numerical LBA addresses starting from the current starting address are not consecutive, then the second data corresponding to the numerical LBA addresses starting from the current starting address remains unchanged in the cache;

[0033] Determine whether the current starting address is less than the maximum LBA address;

[0034] If the current starting address is less than the maximum LBA address, then the sum of the lengths of the current starting address and the LBA address corresponding to the minimum write amount is taken as the latest current starting address, and the process returns to the step of determining whether the number of LBA addresses starting from the current starting address are consecutive.

[0035] If the current starting address is greater than or equal to the maximum LBA address, then the process ends.

[0036] Preferably, after responding to the simulated write command and writing the second data into the TLC according to the minimum write amount of the TLC, the method further includes:

[0037] Clear the mapping relationship;

[0038] Release the memory and the cache.

[0039] A data power-on processing system, comprising:

[0040] The first reading module is used to read the stored first data and the first LBA address of the first data in the TLC into memory after power-on. The first data includes data that was not written to the TLC after power-off.

[0041] The first establishment module is used to determine the storage location of the first data in the memory and establish a mapping relationship between the storage location and the corresponding first LBA address;

[0042] The second read module is used to respond to a simulated read instruction and apply the mapping relationship to read the second data to be written to the TLC from the memory or the TLC and put it into the cache. The simulated read instruction includes an instruction obtained by simulating a read instruction on the host side.

[0043] The first write module is configured to respond to a simulated write instruction and write the second data into the TLC according to the minimum write amount of the TLC, wherein the simulated write instruction includes an instruction obtained by simulating the write instruction on the host side.

[0044] An electronic device, comprising:

[0045] Memory, used to store computer programs;

[0046] A processor, configured to implement the steps of any of the above-described data power-on processing methods when executing the computer program.

[0047] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the above-described data power-on processing methods.

[0048] This application provides a data power-on processing method. After power-on, the method reads the stored first data and the first LBA address of the first data in the TLC into memory. The first data includes data that was not written to the TLC after power failure. The method determines the storage location of the first data in memory and establishes a mapping relationship between the storage location and the corresponding first LBA address. In response to a simulated read instruction, the method uses the mapping relationship to read the second data to be written to the TLC from memory or the TLC into a cache. The simulated read instruction includes an instruction obtained by simulating a read instruction from the host side. In response to a simulated write instruction, the method writes the second data into the TLC according to the minimum write amount of the TLC. The simulated write instruction includes an instruction obtained by simulating a write instruction from the host side. In this application, after the SSD powers on, the first data and the first LBA address that were not written to the TLC after power failure are read into memory, and a mapping relationship between the first LBA address and the storage location is established. This allows for rapid application of the mapping relationship to find the corresponding first data in memory. Subsequently, a simulated read instruction is used to apply the mapping relationship to read the second data into the cache. Finally, a simulated write instruction is used to write the second data into the TLC according to the minimum write amount of the TLC. This allows for rapid data writing to the TLC after the SSD powers on, even with limited DDR memory, improving the data recovery efficiency of the SSD after power-on. The data power-on processing system, electronic device, and computer-readable storage medium provided in this application also solve the corresponding technical problems. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0050] Figure 1 A first flowchart of a data power-on processing method provided in an embodiment of this application;

[0051] Figure 2 This is a schematic diagram of the internal structure of a NAND flash memory.

[0052] Figure 3 A diagram illustrating the amount of data written in a single TLC NAND flash memory operation;

[0053] Figure 4 A second flowchart of a data power-on processing method provided in an embodiment of this application;

[0054] Figure 5 This is a schematic diagram of the memory structure;

[0055] Figure 6This is a diagram illustrating the zone divisions within a ZNS.

[0056] Figure 7 A third flowchart of a data power-on processing method provided in an embodiment of this application;

[0057] Figure 8 A schematic diagram illustrating data recovery and mapping table creation;

[0058] Figure 9 A flowchart for data integration;

[0059] Figure 10 A fourth flowchart of a data power-on processing method provided in an embodiment of this application;

[0060] Figure 11 This is a schematic diagram illustrating data integration and recovery as an example.

[0061] Figure 12 A schematic diagram of a data power-on processing system provided in this application embodiment.

[0062] Figure 13 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0063] Figure 14 This is another structural schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0064] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0065] Please see Figure 1 , Figure 1 This is a first flowchart of a data power-on processing method provided in an embodiment of this application.

[0066] This application provides a data power-on processing method, which may include the following steps:

[0067] Step S101: After power-on, read the stored first data and the first LBA address of the first data in the TLC into memory. The first data includes data that was not written to the TLC after power-off.

[0068] In practical applications, after an SSD loses power, some data is not written to the TLC. That is, there is first data that was not written to the TLC after the SSD lost power. At this time, it is necessary to store the first data so that it can continue to be written to the TLC after the SSD is powered on. Therefore, in the data recovery process after the SSD is powered on, the stored first data and the first LBA address of the first data in the TLC can be read first, and the first data and the first LBA address can be stored in memory for subsequent processing of the first data and the first LBA address.

[0069] It should be noted that after the SSD loses power, the storage method of the first data and the first LBA address can be flexibly determined according to actual needs, and the amount of the first data can be determined according to the specific application scenario. This application does not make specific limitations here.

[0070] It should be noted that the LBA (Logical Block Address) in this application is a general mechanism used to represent the location of data, referring to the logical address of a data block, and its size can be determined according to the SSD's data format. Based on this, the LBA also needs to rely on the PBA (Physical Block Address) to interact with the SSD. The PBA refers to the actual physical address after the LBA data is written to the SSD's NAND flash memory. During firmware management, the size of a PBA can be fixed at 4KB, and one PBA can correspond to one or more LBAs, etc.

[0071] Step S102: Determine the storage location of the first data in memory and establish a mapping relationship between the storage location and the corresponding first LBA address.

[0072] In practical applications, in order to facilitate the quick retrieval of the first data in memory, and considering that the data is written to the TLC according to the LBA address, we can first determine the storage location of the first data in memory, and then establish a mapping relationship between the storage location and the corresponding first LBA address. In this way, we can use this mapping relationship to quickly find the first data corresponding to the first LBA address stored in memory.

[0073] Step S103: In response to the simulated read instruction, the second data to be written to the TLC is read from the memory or TLC into the cache using the mapping relationship. The simulated read instruction includes the instruction obtained by simulating the read instruction on the host side.

[0074] In practical applications, considering that the host can perform data reading operations on the SSD by issuing read commands, that is, the SSD has the function of responding to the host's read commands, this application can simulate the host's read commands to process the first data and the first LBA address. In other words, in response to the simulated read command, the second data to be written to the TLC can be read from the memory or TLC into the cache by applying the mapping relationship.

[0075] It should be noted that this simulated read instruction is obtained by simulating the read instruction on the host side. Its function is to read data from memory or TLC into a buffer so that the second data to be written to TLC can be processed in the buffer. It should also be noted that because data writing to TLC must meet the TLC's minimum write limit, and this limit is affected by power loss, the data meeting the TLC's minimum write limit may exist in either memory or the TLC. Therefore, it is necessary to read the second data to be written to TLC from memory or TLC into the buffer.

[0076] It should be noted that the second data and the first data are divided according to their storage relationship. The first data is the data that needs to be stored in memory, while the second data is the data that needs to be stored in the cache.

[0077] Step S104: In response to the simulated write command, write the second data into the TLC according to the minimum write amount of the TLC. The simulated write command includes the command obtained by simulating the write command on the host side.

[0078] In practical applications, in response to the read command from the host, and considering that the SSD has the function of responding to the write command from the host, this application can simulate the write command from the host to write the second data into the TLC. Furthermore, considering that the data writing in the TLC must meet the minimum write volume of the TLC, the second data can be written into the TLC in response to the simulated write command, according to the minimum write volume of the TLC.

[0079] It should be noted that this simulated write instruction is the instruction obtained by simulating the write instruction on the host side. In the process of writing the second data into the TLC according to the minimum write limit of the TLC, the second data that meets the minimum write limit of the TLC can be directly written into the TLC, such as writing it into a new block in the TLC. However, the second data that does not meet the minimum write limit of the TLC can be saved in the cache. After the SSD receives new data or performs other operations to make the second data meet the minimum write limit of the TLC, the second data can then be written into the TLC.

[0080] In practical applications, after responding to the simulated write command and writing the second data into the TLC according to the minimum write amount, the mapping relationship can be cleared and the memory and cache can be released to facilitate the next data processing after the SSD is powered on.

[0081] It should be noted that NAND flash memory has limitations on the amount of data that can be written. Figure 2 Taking the internal architecture of the plane TLC as an example, NAND has two LUNs. The LUN is the smallest independent unit in NAND that can execute commands and report its own status. The plane is the smallest unit in NAND that can be operated according to read, write, erase and other commands. A plane is a storage matrix containing several blocks. The block is the smallest unit of the erase command, which contains several pages. The page is the smallest unit in flash memory that can be read and written. The size of each page can be 16KB, etc. Taking the 4KB format of SSD disk as an example, 4 LBAs (1 LBA 4KB) can be written in one page. When writing 4KB of data, the entire page must be written at the NAND level, resulting in an actual data write of 16KB. If multi-plane page programming is used, a single write command operates on pages with the same number in both plane 0 and plane 1. However, with TLC NAND, three pages need to be written simultaneously. For example, if the data written in one operation consists of pages 0, 1, and 2 in plane 0 and pages 0, 1, and 2 in plane 1, then 16KB * 2 * 3 = 96KB of data needs to be written at once. The write volume in a single TLC programming operation is as follows... Figure 3 As shown. Furthermore, in order to meet the characteristics of NAND, after a write command is issued, the data will first be cached in a segment of DDR memory. When the required 96KB of data for a single write command is accumulated, it will be actually written to NAND. In other words, a single data write to TLC NAND contains multiple LBAs and is written to multiple PBAs.

[0082] This application provides a data power-on processing method. After power-on, the method reads the stored first data and the first LBA address of the first data in the TLC into memory. The first data includes data that was not written to the TLC after power failure. The method determines the storage location of the first data in memory and establishes a mapping relationship between the storage location and the corresponding first LBA address. In response to a simulated read instruction, the method uses the mapping relationship to read the second data to be written to the TLC from memory or the TLC into a cache. The simulated read instruction includes an instruction obtained by simulating a read instruction from the host side. In response to a simulated write instruction, the method writes the second data into the TLC according to the minimum write amount of the TLC. The simulated write instruction includes an instruction obtained by simulating a write instruction from the host side. In this application, after the SSD is powered on, the first data and the first LBA address that were not written to the TLC after power failure are read into memory, and a mapping relationship between the first LBA address and the storage location is established so that the corresponding first data can be quickly found in memory by applying the mapping relationship. Subsequently, the second data is read into the cache by simulating read instructions. Finally, the second data is written into the TLC according to the minimum write amount of the TLC by simulating write instructions. This allows data to be quickly written to the TLC after the SSD is powered on when using a small amount of DDR, thus improving the data recovery efficiency of the SSD after power-on.

[0083] Please see Figure 4 , Figure 4 This is a second flowchart of a data power-on processing method provided in an embodiment of this application.

[0084] This application provides a data power-on processing method, which may include the following steps:

[0085] Step S201: After power-on, read the first data and the first LBA address stored in each page of the SLC, and transfer the first data and the first LBA address to the corresponding memory space in the memory. The size of the memory space is equal to the size of the page of the SLC. The first data includes the data that was not written to the TLC after power failure.

[0086] In practical applications, the first data and first LBA address after an SSD power failure can be stored in the SLC. Correspondingly, when reading the stored first data and its first LBA address from the TLC to memory, the first data and first LBA address stored in each page of the SLC can be read and transferred to the corresponding memory space. The size of this memory space can be set to be equal to the size of a page in the SLC. An SLC page, also known as a multiplane page, can be 16KB * 2planes = 32KB in size. In this case, the memory can... Figure 5As shown, the buffer is a contiguous segment of DDR memory allocated in advance.

[0087] Step S202: Divide the memory space according to the unit size value of LBA to obtain memory subspaces.

[0088] Step S203: Determine the storage location of the first data in memory, using memory subspaces as units.

[0089] Step S204: Establish the mapping relationship between the storage location and the corresponding first LBA address.

[0090] In practical applications, when determining the memory location of the first data and establishing the mapping between that location and the corresponding first LBA address, the memory space can be divided according to the unit size of the LBA, resulting in memory subspaces. Each subspace's size is equal to the unit size of the LBA, for example, a memory subspace could be 4KB. Using these subspaces as units, the memory location of the first data is determined, for example, the location could be a specific 4KB position within memory. A mapping between these locations and the corresponding first LBA address is then established. In this way, the buffer index value can be directly obtained by looking up the TLC LBA table, and then the buffer can be accessed directly using the buffer index value to retrieve the TLC LBA data. In other words, this mapping relationship can be used to quickly find the first data corresponding to a single LBA address in memory.

[0091] It should be noted that when ZNS (Zoned Namespace) technology is applied to an SSD, it divides the entire LBA range of the SSD namespace into several equal-length intervals. These equal-length LBA intervals are called a zone; that is, a zone is a continuous and non-overlapping range of LBAs. Figure 6As shown, assuming each zone has n LBAs, where LBA 0 is the smallest LBA in zone 0 and LBA n-1 is the largest LBA in zone 0, for zone 1, LBAn is the smallest LBA and LBA 2n-1 is its largest LBA. Therefore, the smallest LBA in zone m is LBA n*(m-1), and the largest LBA is LBA nm-1. Furthermore, the ZNS protocol stipulates that data can be read in any order within each zone, but must be written sequentially, i.e., it supports random reads and sequential writes. Therefore, the host needs to ensure that the transmitted LBAs are ordered and non-repeating. According to the protocol specification, each zone has its own independent state management. Before rewriting, the zone's state management information must be reset, and then writing must start from LBA 0. Therefore, to enable the SSD to meet the corresponding ZNS operations, when transferring the first data and the first LBA address to the corresponding memory space in memory, the first data and the first LBA address can be transferred to the memory space corresponding to the zone in the TLC on a unit basis. Similarly, in establishing the mapping relationship between the storage location and the corresponding first LBA address, the mapping relationship can be established on a zone-by-zone basis, between the storage location of the zone and the corresponding first LBA address. This allows for the rapid application of this mapping relationship to search and process the data corresponding to a single zone.

[0092] Step S205: In response to the simulated read instruction, the second data to be written to the TLC is read from the memory or TLC into the cache using the mapping relationship. The simulated read instruction includes the instruction obtained by simulating the read instruction on the host side.

[0093] Step S206: In response to the simulated write command, write the second data into the TLC according to the minimum write amount of the TLC. The simulated write command includes the command obtained by simulating the write command on the host side.

[0094] Please see Figure 7 , Figure 7 This is a third flowchart of a data power-on processing method provided in an embodiment of this application.

[0095] This application provides a data power-on processing method, which may include the following steps:

[0096] Step S301: After power-on, read the stored first data and the first LBA address of the first data in the TLC into memory. The first data includes data that was not written to the TLC after power-off.

[0097] Step S302: Determine the storage location of the first data in memory and establish a mapping relationship between the storage location and the corresponding first LBA address.

[0098] Step S303: In response to the simulated read instruction, determine whether there is a second LBA address corresponding to the simulated read instruction in the mapping relationship; if there is a second LBA address in the mapping relationship, then execute step S304; if there is no second LBA address in the mapping relationship, then execute step S305.

[0099] Step S304: According to the mapping relationship, read the second data from the storage location corresponding to the second LBA address and transfer the second data to the cache.

[0100] Step S305: Read the second data corresponding to the second LBA address from the TLC and transfer the second data to the cache.

[0101] In practical applications, when responding to a simulated read instruction and using a mapping relationship to read the second data to be written to the TLC and then into the cache, considering that data not recorded in the mapping relationship may have already been written to the TLC, and that both the mapping relationship and the data in the TLC have corresponding LBA addresses in the TLC, the mapping relationship can be used as a reference to read data using LBA addresses. That is, in response to a simulated read instruction, it can be determined whether the mapping relationship contains a second LBA address corresponding to the simulated read instruction; if the mapping relationship contains a second LBA address, then according to the mapping relationship, the second data is read from the storage location corresponding to the second LBA address and transferred to the cache; if the mapping relationship does not contain a second LBA address, then the second data corresponding to the second LBA address is read from the TLC and transferred to the cache.

[0102] In a specific application scenario, assuming the first data and the first LBA address are stored in the SLC, and 0xFFF is used in the buffer to indicate that the first data and the first LBA address have not been written to this memory subspace, then the process of reading the first data and the first LBA address from the SLC into memory can be as follows: Figure 8 As shown, the SLC nand stores data for zone 0 and zone 1, and two mapping tables are allocated in the buffer: table 0 for zone 0 and table 1 for zone 1. After the data in the SLC is read out in sequence, the mapping table is selected according to the zone ID, and the position of the data in the buffer is recorded in the corresponding mapping table according to the TLC LBA of the data.

[0103] It should be noted that after data is read into the buffer, the data in an index (8 LBAs) may not be contiguous, or may be less than 8 LBAs. This could be due to reasons such as removing invalid data based on the TLC LBA mapping relationship of the record. Figure 8For example, data is read from pages 0-5 of the SLC NAND and placed into the buffer. The data in page 1 is not sequential (TLC LBA 32, 33, 34, 41, 42, 43, 44, 45), and page 5 contains only one 4KB block of valid data (TLC LBA31). However, considering that the ZNS protocol stipulates that data can be read in any order within each zone, but must be written sequentially, to ensure the SSD meets the sequential write requirement of the ZNS protocol, when responding to a simulated read command and applying the mapping relationship to read the second data to be written to the TLC from memory or the TLC into the cache, it can respond to a simulated read command that sequentially reads the data corresponding to the LBA addresses of the TLC, applying the mapping relationship to read the second data to be written to the TLC from memory or the TLC into the cache. It should be noted that since the LBA addresses of the TLC are read sequentially, the second data read into the cache is sorted according to the LBA addresses, which facilitates the subsequent sequential writing into the TLC. Of course, the second data can also be read into the cache first and then sorted according to the LBA addresses, etc. This application does not make any specific restrictions here.

[0104] It should be noted that the write volume of a zone is persistently recorded when power is off. Therefore, when power is on, it is known which LBA the zone has written to. Thus, the cutoff LBA for read commands is the LBA that the zone finally wrote to. In other words, there is no need to issue corresponding simulated read commands to other LBAs after the LBA that the zone finally wrote to.

[0105] Step S306: In response to the simulated write command, write the second data into the TLC according to the minimum write amount of the TLC. The simulated write command includes the command obtained by simulating the write command on the host side.

[0106] In specific application scenarios, Figure 8Based on the zone table shown, in response to a simulated read command that sequentially reads data corresponding to the LBA addresses of the TLC, it can start from LBA 0 of the zone and read the data of that zone sequentially until it reaches the maximum LBA that can be written to that zone. For example, if the first read command reads LBAs 0-7, it first checks if the buffer index of this LBA in the corresponding zone table is valid. The initial value is 0xFFFF; values ​​other than 0xFFFF are considered valid. If valid, the data is directly copied from the buffer using the buffer index and stored in the cache. If invalid, it means the data is in the TLC, and it is directly read from the TLC. The read data is also stored in the cache. When the cache is full for a single TLC data write, a simulated host write command is used to write the data to a new block. Data that does not meet the TLC's write capacity remains in the cache and is written to the TLC later when host data is received and sufficient data is accumulated. The entire process can be described as follows: Figure 9 As shown, x represents the currently selected mapping relationship in the mapping table, and max zone table cnt represents the maximum number of mapping relationships in the mapping table.

[0107] Please see Figure 10 , Figure 10 This is a fourth flowchart of a data power-on processing method provided in an embodiment of this application.

[0108] This application provides a data power-on processing method, which may include the following steps:

[0109] Step S401: After power-on, read the stored first data and the first LBA address of the first data in the TLC into memory. The first data includes data that was not written to the TLC after power-off.

[0110] Step S402: Determine the storage location of the first data in memory and establish a mapping relationship between the storage location and the corresponding first LBA address.

[0111] Step S403: In response to the simulated read instruction, the second data to be written to the TLC is read from the memory or TLC into the cache using the mapping relationship. The simulated read instruction includes the instruction obtained by simulating the read instruction on the host side.

[0112] Step S404: Determine the number of LBA addresses corresponding to the minimum write limit of the TLC.

[0113] Step S405: Use the minimum LBA address of the second data as the current starting address, and determine the maximum LBA address of the second data.

[0114] In practical applications, when multiple LBA addresses of the second data are consecutive and the number of consecutive addresses reaches the minimum write limit of the TLC, it can be determined that the multiple second data satisfy the minimum write limit of the TLC. Therefore, it can be determined whether the second data has reached the minimum write limit of the TLC based on whether the number of consecutive LBA addresses of the second data reaches this value. That is, when responding to the simulated write instruction and writing the second data into the TLC according to the minimum write limit of the TLC, the number of LBA addresses corresponding to the minimum write limit of the TLC can be determined; the minimum LBA address of the second data is used as the current starting address, and the maximum LBA address of the second data is determined.

[0115] Step S406: In the cache, determine whether the number of LBA addresses starting from the current starting address are consecutive; if the number of LBA addresses starting from the current starting address are consecutive, proceed to step S407; if the number of LBA addresses starting from the current starting address are not consecutive, proceed to step S408.

[0116] Step S407: Write the second data corresponding to the first number of LBA addresses starting from the current starting address into the TLC, and then execute step S409.

[0117] Step S408: Keep the second data corresponding to the numerical LBA addresses starting from the current starting address unchanged in the cache, and proceed to step S409.

[0118] Step S409: Determine whether the current starting address is less than the maximum LBA address; if the current starting address is less than the maximum LBA address, proceed to step S410; if the current starting address is greater than or equal to the maximum LBA address, proceed to step S411.

[0119] Step S410: Use the sum of the length values ​​of the current starting address and the LBA address corresponding to the minimum write amount as the latest current starting address, and return to execute step S406.

[0120] Step S411: End.

[0121] In practical applications, after determining the number of values, the current starting address, and the maximum LBA address, we can check in the cache whether the number of LBA addresses starting from the current starting address are consecutive. If the number of LBA addresses starting from the current starting address are consecutive, it can be determined that the data corresponding to the number of LBA addresses starting from the current starting address meets the minimum write limit of the TLC, and the second data corresponding to the number of LBA addresses starting from the current starting address can be written into the TLC. If the number of LBA addresses starting from the current starting address are not consecutive, the second data corresponding to the number of LBA addresses starting from the current starting address can be kept unchanged in the cache. We then check whether the current starting address is less than the maximum LBA address. If the current starting address is less than the maximum LBA address, the sum of the lengths of the current starting address and the LBA address corresponding to the minimum write limit is taken as the latest current starting address, and we return to execute the step of checking whether the number of LBA addresses starting from the current starting address are consecutive. If the current starting address is greater than or equal to the maximum LBA address, the process can end.

[0122] To facilitate understanding of the data power-on processing scheme provided in this application, it is assumed that... Figure 8 The data for zone 0 and zone 1 shown exists in the TLC NAND and buffer, so the data processing procedure can be as follows: Figure 11 As shown.

[0123] Taking the processing of zone 1 data as an example, the front-end simulates the host sending a sequential read command to read data from LBAs 0 to 7. This LBA first queries the zone 1 mapping table. If the buffer index for LBAs 0 to 7 in the mapping table is 0xFFFF, then the data is considered not in the buffer and needs to be read from the corresponding PBA position in the NAND. Similarly, LBAs 8 to 15 and LBAs 16 to 23 are read from the TLC NAND. When a TLC write operation is complete, the simulated host sends a write command, writing LBAs 0 to 23 into a new block. When reading LBAs 24 to 31 of zone 1, the zone 1 mapping table is queried. The buffer index for LBA 24 is 33, meaning the data for LBA 24 is located at the 33rd 4KB starting from the buffer's beginning address, and LBA 25 is located at the 34th 4KB starting from the buffer's beginning address. Similarly, the other LBAs of this read command can find their corresponding buffer positions in the mapping table and copy this data to the cache.

[0124] It's important to note that the write volume of a zone is persistently recorded upon power-down. Therefore, upon power-up, it's known that zone 1 has written to LBA 31, and no further read commands will be issued after LBA 31. Meanwhile, LBAs 24-31 haven't accumulated a single TLC write, so the data exists in the cache and will be written later once they are full.

[0125] Please see Figure 12 , Figure 12 This is a schematic diagram of the structure of a data power-on processing system provided in an embodiment of this application.

[0126] This application provides a data power-on processing system, which may include:

[0127] The first reading module 101 is used to read the stored first data and the first LBA address of the first data in the TLC into memory after power-on. The first data includes data that was not written to the TLC after power-off.

[0128] The first establishment module 102 is used to determine the storage location of the first data in memory and establish a mapping relationship between the storage location and the corresponding first LBA address;

[0129] The second reading module 103 is used to respond to a simulated read command and apply a mapping relationship to read the second data to be written to the TLC from memory or TLC into the cache. The simulated read command includes the command obtained by simulating the read command on the host side.

[0130] The first write module 104 is used to respond to the simulated write command and write the second data into the TLC according to the minimum write amount of the TLC. The simulated write command includes the command obtained by simulating the write command on the host side.

[0131] This application provides a data power-on processing system, wherein the first reading module may include:

[0132] The first reading unit is used to read the first data and the first LBA address stored in each page of the SLC, and transfer the first data and the first LBA address to the corresponding memory space in the memory, the size of which is equal to the size of the page of the SLC.

[0133] The first module may include:

[0134] The first partitioning unit is used to divide the memory space according to the unit size value of LBA to obtain memory subspaces;

[0135] The first determining unit is used to determine the storage location of the first data in memory, on a unit basis of memory subspace;

[0136] The first establishment unit is used to establish the mapping relationship between the storage location and the corresponding first LBA address.

[0137] The data power-on processing system provided in this application embodiment includes a first reading unit that can be specifically used to: transfer the first data and the first LBA address to the memory space corresponding to the zone in the TLC, taking the zone to which the first data belongs as the unit;

[0138] The first establishment unit can be specifically used to: establish a mapping relationship between the storage location of a zone and its corresponding first LBA address, taking a zone as the unit.

[0139] This application provides a data power-on processing system, wherein the second reading module may include:

[0140] The first judgment unit is used to respond to the simulated read instruction and determine whether there is a second LBA address corresponding to the simulated read instruction in the mapping relationship; if there is a second LBA address in the mapping relationship, then according to the mapping relationship, the second data is read from the storage location corresponding to the second LBA address and the second data is transferred to the cache; if there is no second LBA address in the mapping relationship, then the second data corresponding to the second LBA address is read from the TLC and the second data is transferred to the cache.

[0141] This application provides a data power-on processing system, wherein the second reading module may include:

[0142] The second read unit is used to respond to a simulated read instruction that sequentially reads the data corresponding to the LBA address of the TLC, and uses the mapping relationship to read the second data to be written to the TLC from memory or TLC into the cache.

[0143] This application provides a data power-on processing system, wherein the first writing module may include:

[0144] The second determining unit is used to determine the number of LBA addresses corresponding to the minimum write amount of the TLC;

[0145] The third determining unit is used to take the minimum LBA address of the second data as the current starting address and determine the maximum LBA address of the second data.

[0146] The second judgment unit is used to determine in the cache whether the number of LBA addresses starting from the current starting address are consecutive; if the number of LBA addresses starting from the current starting address are consecutive, the second data corresponding to the number of LBA addresses starting from the current starting address is written into the TLC; if the number of LBA addresses starting from the current starting address are not consecutive, the second data corresponding to the number of LBA addresses starting from the current starting address is kept unchanged in the cache.

[0147] The third judgment unit is used to determine whether the current starting address is less than the maximum LBA address. If the current starting address is less than the maximum LBA address, the sum of the length values ​​of the current starting address and the LBA address corresponding to the minimum write amount is taken as the latest current starting address, and the step of judging whether the number of LBA addresses starting from the current starting address are consecutive is returned. If the current starting address is greater than or equal to the maximum LBA address, the process ends.

[0148] The data power-on processing system provided in this application embodiment may further include:

[0149] The first processing module is used to respond to the simulated write instruction, write the second data into the TLC according to the minimum write amount of the TLC, clear the mapping relationship, and release memory and cache.

[0150] This application also provides an electronic device and a computer-readable storage medium, both of which have the corresponding effects of the data power-on processing method provided in the embodiments of this application. Please refer to... Figure 13 , Figure 13 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0151] An electronic device provided in this application includes a memory 201 and a processor 202. The memory 201 stores a computer program, and when the processor 202 executes the computer program, it implements the steps of the data power-on processing method described in any of the above embodiments.

[0152] Please see Figure 14 Another electronic device provided in this application embodiment may further include: an input port 203 connected to the processor 202 for transmitting commands input from the outside to the processor 202; a display unit 204 connected to the processor 202 for displaying the processing results of the processor 202 to the outside; and a communication module 205 connected to the processor 202 for realizing communication between the electronic device and the outside. The display unit 204 may be a display panel, a laser scanner, or the like; the communication method adopted by the communication module 205 includes, but is not limited to, Mobile High-Definition Link (MHL), Universal Serial Bus (USB), High-Definition Multimedia Interface (HDMI), wireless connectivity: Wireless Fidelity (WiFi), Bluetooth communication technology, Bluetooth Low Energy communication technology, and communication technology based on IEEE 802.11s.

[0153] This application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the steps of the data power-on processing method described in any of the above embodiments.

[0154] The computer-readable storage media involved in this application include random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs (Compact Disc Read-Only Memory), or any other form of storage media known in the art.

[0155] For descriptions of relevant parts in the data power-on processing system, electronic device, and computer-readable storage medium provided in the embodiments of this application, please refer to the detailed descriptions of the corresponding parts in the data power-on processing method provided in the embodiments of this application, which will not be repeated here. Furthermore, parts of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0156] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0157] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data power-on processing method, characterized in that, include: After power-on, the first data stored and the first LBA address of the first data in the TLC are read into memory. The first data includes data that was not written to the TLC after power failure. Determine the storage location of the first data in the memory, and establish a mapping relationship between the storage location and the corresponding first LBA address; In response to a simulated read instruction, the second data to be written to the TLC is read from the memory or the TLC and placed into the cache using the mapping relationship. The simulated read instruction includes an instruction obtained by simulating a read instruction on the host side. In response to a simulated write command, the second data is written into the TLC according to the minimum write amount of the TLC, wherein the simulated write command includes an instruction obtained by simulating the write command on the host side; The step of reading the stored first data and the first LBA address of the first data in the TLC into memory includes: Read the first data and the first LBA address stored in each page of the SLC, and transfer the first data and the first LBA address to the corresponding memory space of the memory, wherein the size of the memory space is equal to the size of the page of the SLC; Determining the storage location of the first data in memory and establishing a mapping relationship between the storage location and the corresponding first LBA address includes: The memory space is divided according to the unit size value of LBA to obtain memory subspaces; The storage location of the first data in the memory is determined on a unit basis, using the memory subspace as the unit; Establish the mapping relationship between the storage location and the corresponding first LBA address.

2. The method according to claim 1, characterized in that, The step of transferring the first data and the first LBA address to the corresponding memory space of the memory includes: Using the zone to which the first data belongs in the TLC as a unit, the first data and the first LBA address are transferred to the memory space corresponding to the zone in the memory. Establishing the mapping relationship between the storage location and the corresponding first LBA address includes: Using the zone as a unit, establish the mapping relationship between the storage location to which the zone belongs and the corresponding first LBA address.

3. The method according to claim 1, characterized in that, The step of responding to a simulated read command by applying the mapping relationship to read the second data to be written to the TLC from the memory or the TLC and then into the cache includes: In response to the simulated read instruction, determine whether a second LBA address corresponding to the simulated read instruction exists in the mapping relationship; If the second LBA address exists in the mapping relationship, then according to the mapping relationship, the second data is read from the storage location corresponding to the second LBA address and the second data is transferred to the cache; If the second LBA address does not exist in the mapping relationship, then the second data corresponding to the second LBA address is read from the TLC and the second data is transferred to the cache.

4. The method according to claim 1, characterized in that, The step of responding to a simulated read command by applying the mapping relationship to read the second data to be written to the TLC from the memory or the TLC and then into the cache includes: In response to a simulated read instruction that sequentially reads data corresponding to the LBA addresses of the TLC, the second data to be written to the TLC is read from the memory or the TLC and placed into the cache using the mapping relationship.

5. The method according to claim 1, characterized in that, The step of responding to a simulated write command and writing the second data into the TLC according to the minimum write amount of the TLC includes: Determine the number of LBA addresses corresponding to the minimum write limit of the TLC; Use the minimum LBA address of the second data as the current starting address, and determine the maximum LBA address of the second data; In the cache, it is determined whether the numerical LBA addresses starting from the current starting address are consecutive; If the number of LBA addresses starting from the current starting address are consecutive, then the second data corresponding to the number of LBA addresses starting from the current starting address is written into the TLC; If the numerical LBA addresses starting from the current starting address are not consecutive, then the second data corresponding to the numerical LBA addresses starting from the current starting address remains unchanged in the cache; Determine whether the current starting address is less than the maximum LBA address; If the current starting address is less than the maximum LBA address, then the sum of the lengths of the current starting address and the LBA address corresponding to the minimum write amount is taken as the latest current starting address, and the process returns to the step of determining whether the number of LBA addresses starting from the current starting address are consecutive. If the current starting address is greater than or equal to the maximum LBA address, then the process ends.

6. The method according to claim 1, characterized in that, After responding to the simulated write command and writing the second data into the TLC according to the minimum write amount of the TLC, the method further includes: Clear the mapping relationship; Release the memory and the cache.

7. A data power-on processing system, characterized in that, include: The first reading module is used to read the stored first data and the first LBA address of the first data in the TLC into memory after power-on. The first data includes data that was not written to the TLC after power-off. The first establishment module is used to determine the storage location of the first data in the memory and establish a mapping relationship between the storage location and the corresponding first LBA address; The second read module is used to respond to a simulated read instruction and apply the mapping relationship to read the second data to be written to the TLC from the memory or the TLC and put it into the cache. The simulated read instruction includes an instruction obtained by simulating a read instruction on the host side. The first writing module is configured to respond to a simulated write instruction and write the second data into the TLC according to the minimum write amount of the TLC. The simulated write instruction includes an instruction obtained by simulating the write instruction on the host side. The first reading module includes: The first reading unit is used to read the first data and the first LBA address stored in each page of the SLC, and transfer the first data and the first LBA address to the corresponding memory space of the memory, wherein the size of the memory space is equal to the size of the page of the SLC; The first establishment module includes: The first partitioning unit is used to divide the memory space according to the unit size value of LBA to obtain memory subspaces; The first determining unit is configured to determine the storage location of the first data in the memory, taking the memory subspace as a unit; The first establishment unit is used to establish the mapping relationship between the storage location and the corresponding first LBA address.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the data power-on processing method as described in any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the data power-on processing method as described in any one of claims 1 to 6.

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