Adder circuit, memory, and electronic device

Abstract

The application provides a multiply-add circuit, a memory and an electronic device to improve the problems of power consumption and time waste in the multiply-add circuit, and the multiply-add circuit comprises at least one multiply-add unit, the multiply-add unit comprises a successive approximation register analog-to-digital converter (SAR ADC), a bit width control circuit, a sum bus and a plurality of multiplication circuits; the plurality of multiplication circuits are connected with the SAR ADC through the sum bus; the multiplication circuit is used for multiplying single-bit input data and weight data to obtain a product analog quantity; the SAR ADC is used for analog-to-digital conversion of a multiply-add result; and the bit width control circuit is used for summing the single-bit input data of the plurality of multiplication circuits connected with the same sum bus and controlling a starting bit of a capacitance array of the SAR ADC in a bit-by-bit comparison stage according to a sum result, for example, adjusting the starting bit from the highest bit to a lower bit or a number of bits, so as to reduce conversion power consumption and time.

Description

Technical Field

[0001] This application relates to the field of in-memory computing technology, and in particular to a multiply-accumulate circuit, a memory, and an electronic device. Background Technology

[0002] The charge-accumulation type multiply-accumulate circuit needs to use a successive approximation register analog-to-digital converter (SAR ADC) to convert the multiplication-accumulation result into an analog-to-digital value. The SAR ADC includes a binary weighted capacitor array. Each analog-to-digital conversion requires charging and discharging the capacitors from the most significant bit to the least significant bit in sequence. This charging and discharging process generates a large amount of power consumption.

[0003] The process of analog-to-digital conversion of SAR ADC is similar to that of weighing on a balance. It starts charging and discharging from the highest capacitor and compares each bit. First, the voltage of the input signal is compared with half of the reference voltage, and then it is compared with different proportions of the reference voltage multiple times, so that the output digital quantity gradually approximates the input analog quantity.

[0004] In the multiply-accumulate circuit, due to the different sparsity of the input data and the weight data, there are four multiplication operations for the multiplier: 0×1, 1×1, 1×0, and 0×0. When the 1×1 case occurs less frequently, the multiply-accumulate result may be relatively small, for example, less than 1 / 2 of the voltage of the SAR ADC reference signal. Furthermore, the sparsity of the input data is generally greater than that of the weight data. When the sparsity of the input data is large and the multiply-accumulate result may be small, using the highest bit capacitor as the starting bit for bit-by-bit comparison results in wasted power consumption and conversion time. Summary of the Invention

[0005] This application provides a multiply-accumulate circuit, a memory, and an electronic device that can improve the problems of wasted power consumption and conversion time in existing multiply-accumulate circuits.

[0006] In a first aspect, embodiments of this application provide a multiply-accumulate circuit, comprising: at least one multiply-accumulate unit, the multiply-accumulate unit including a successive approximation analog-to-digital converter (SAR ADC), a bit-width control circuit, a summation bus, and multiple multiplication circuits; the multiple multiplication circuits are connected to the input signal terminals of the SAR ADC via the summation bus; the multiplication circuits are used to multiply a single bit of input data with a single bit of weight data to obtain an analog product; wherein, the sparsity of the input data is greater than the sparsity of the weight data, that is, the number of 0s in the input data is greater than the number of 0s in the weight data; the summation bus accumulates the multiplication results output by the multiple multiplication circuits and transmits the multiply-accumulate result to the SAR ADC, the SAR ADC being used to perform analog-to-digital conversion on the multiply-accumulate result; the SAR ADC includes a digital-to-analog converter (DAC) capacitor array, the bit-width control circuit is connected to the SAR ADC, the bit-width control circuit is used to sum the single-bit input data of the multiple multiplication circuits connected to the same summation bus, and controls the start bit of the capacitors in the bit-by-bit comparison stage of the DAC capacitor array according to the summation result, a conventional SAR In the bit-by-bit comparison stage of an ADC, the charging and discharging comparison begins with the most significant bit capacitor. That is, the input signal (multiply-accumulate result) is first compared with half the SAR ADC reference voltage, and this comparison continues until the output quantized value matches the input signal. However, when the input signal (i.e., the multiply-accumulate result) of the SAR ADC is small, starting the comparison from the most significant bit capacitor results in wasted power consumption and conversion time. Since the multiply-accumulate result is obtained by adding the products of multiple single-bit multiplications, when the sparsity of the input data is greater than the sparsity of the weight data, the summation result of the input data can be used to indicate the magnitude of the multiply-accumulate result. In the embodiments of this application, the starting bit of the capacitor in the bit-by-bit comparison stage of the SAR ADC is adjusted by summing the input data, for example, by reducing it by one or more bits from the most significant bit. This reduces the number of capacitors that need to be charged and discharged in the bit-by-bit comparison stage, lowers power consumption, reduces the number of comparisons, and shortens the time required for analog-to-digital conversion.

[0007] In one possible implementation, the bit-width control circuit includes an adder circuit and a decoder. The adder circuit sums the single-bit input data of multiple multiplication circuits. The decoder compares the summation result with a preset threshold value, which can be set according to the output range of the SAR ADC or the magnitude of the reference voltage. For example, the threshold value can be the quantization value corresponding to half of the reference voltage or a lower value. When the summation result is less than the preset threshold value, the multiplication-addition result will also be less than half of the reference voltage. This eliminates the need for bit-by-bit comparison starting from the highest bit of the SAR ADC's capacitor array. The decoder adjusts the start bit from the highest bit to the preset bit, which is at least one bit lower than the highest bit. For example, the preset bit can be the second highest bit, which is one bit lower than the highest bit, thus reducing power consumption and conversion time. Alternatively, the preset bit can be an even lower bit. The lower the start bit, the lower the power consumption and the less time required for the SAR ADC to complete the analog-to-digital conversion.

[0008] In one possible implementation, the result of the summation, a, satisfies: 2 m-1 ≤a<2 m At this time, the decoder determines that the preset bit is nm bits lower than the most significant bit, where m and n are positive integers, n is the bit width of the SAR ADC, m < n, and the preset threshold value is 2. m and 2 m-1 By comparing the summation result with a preset threshold value according to different ratios of the SAR ADC reference voltage, the range of the multiplication and addition result is determined in advance, and the starting bit of the bit-by-bit comparison stage of the SAR ADC is determined. This can reduce the number of capacitors that need to be charged and discharged and the number of comparisons required in the bit-by-bit comparison stage of the SAR ADC, thereby reducing power consumption and conversion time.

[0009] In one possible implementation, the SAR ADC includes a comparator, and the DAC capacitor array includes a common terminal. The first plate of the capacitors in the DAC capacitor array is connected to the common terminal, and the common terminal is connected to the first input terminal of the comparator. The second plate of the capacitors in the DAC capacitor array is used to connect to the input signal terminal or the reference signal terminal of the SAR ADC. When the decoder adjusts the start bit from the most significant bit to the preset bit, it controls the first plate of the capacitor from the most significant bit to the previous bit in the DAC capacitor array to disconnect from the common terminal, and the second plate to disconnect from the input signal terminal and the reference signal terminal. This disconnects the capacitors before the preset bit capacitor from the DAC capacitor array, preventing charge from flowing to the capacitors before the preset bit capacitor during bit-by-bit comparison, thus avoiding affecting the accuracy of the SAR ADC output data.

[0010] In one possible implementation, the SAR ADC includes at least one switching switch; the first plates of the capacitors from the most significant bit to the previous bit of the preset bit are respectively connected to the common terminal through the switching switch; when the decoder adjusts the start bit from the most significant bit to the preset bit, the switching switch is opened, thereby disconnecting the capacitors before the preset bit (or start bit) from the DAC capacitor array to avoid affecting the accuracy of the SAR ADC.

[0011] In one possible implementation, the SAR ADC includes at least one switching switch; in the capacitor array, the first plate of the least significant capacitor is connected to a common terminal, and a switching switch is provided between the first plates of any two adjacent capacitors between the most significant and the second least significant capacitors; when the decoder adjusts the start bit from the most significant bit to a preset bit, the switching switch between the most significant bit capacitor and the preset bit capacitor is disconnected.

[0012] In one possible implementation, the SAR ADC also includes multiple selection switches. The second plate of each capacitor in the DAC capacitor array is connected to a selection switch. The selection switches are used to connect the second plate to the input signal terminal, the reference signal terminal, or ground. When the decoder adjusts the start bit from the most significant bit to the preset bit, it controls the selection switches to ground the first plate of the capacitor from the most significant bit to the previous bit in the DAC capacitor array. This avoids charging and discharging the capacitors before the preset bit (or start bit) and reduces the power consumption of the SAR ADC.

[0013] In one possible implementation, the multiplication circuit includes a multiplier and a capacitor, with the output of the multiplier connected to one side of the capacitor and the other side of the capacitor connected to a summation bus.

[0014] Secondly, embodiments of this application provide a memory, which includes a storage area and a multiply-accumulate circuit as provided in any of the implementations of the first aspect above; the storage area includes a plurality of storage units, and the multiply-accumulate circuit is used to perform multiply-accumulate operations on the data stored in the storage units.

[0015] Thirdly, embodiments of this application provide an electronic device, which includes a circuit board and a memory electrically connected to the circuit board, wherein the memory is the memory provided in the second aspect. Attached Figure Description

[0016] Figure 1 A schematic diagram of convolution calculation is provided for embodiments of this application;

[0017] Figure 2 Schematic diagrams of several multiply-accumulate operation circuits provided in the embodiments of this application;

[0018] Figure 3A schematic diagram of a SAR ADC provided in an embodiment of this application;

[0019] Figure 4 This is a schematic diagram illustrating the working principle of the SAR ADC provided in the embodiments of this application;

[0020] Figure 5 This is a schematic diagram of the structure of the SAR ADC provided in the embodiments of this application;

[0021] Figure 6 This is a schematic diagram of the sampling stage of the SAR ADC provided in the embodiments of this application;

[0022] Figure 7 This is a schematic diagram of the holding phase of a SAR ADC provided in an embodiment of this application;

[0023] Figure 8 This is a schematic diagram of the first comparison of the SAR ADC provided in an embodiment of this application;

[0024] Figure 9 A schematic diagram of the second comparison of the SAR ADC provided in the embodiments of this application;

[0025] Figure 10 A schematic diagram of the fourth comparison of the SAR ADC provided in an embodiment of this application;

[0026] Figure 11a This is a schematic diagram illustrating the principle of a scheme to reduce the power consumption of a SAR ADC.

[0027] Figure 11b This is a schematic diagram of an 8-bit comparator;

[0028] Figure 12 A schematic diagram of a memory provided for an embodiment of this application;

[0029] Figure 13 Another schematic diagram of the memory provided in the embodiments of this application;

[0030] Figure 14 A schematic diagram of a multiply-accumulate operation circuit provided in an embodiment of this application;

[0031] Figure 15 Another schematic diagram of the multiply-accumulate operation circuit provided in the embodiments of this application;

[0032] Figure 16 A schematic diagram illustrating the working principle of the multiplication circuit over multiple cycles provided in this application embodiment;

[0033] Figure 17a This is a schematic diagram of the input data with the same weight provided in the embodiments of this application;

[0034] Figure 17bA schematic diagram illustrating the workflow of the multiply-accumulate circuit provided in an embodiment of this application;

[0035] Figure 18 A schematic diagram of an addition tree provided for an embodiment of this application;

[0036] Figure 19 A schematic diagram of another multiply-accumulate operation circuit provided in an embodiment of this application;

[0037] Figure 20 This is a schematic diagram illustrating the bit-by-bit comparison of the SAR ADC provided in this application embodiment, starting with the second-highest bit.

[0038] Figure 21 A schematic diagram of another SAR ADC provided in an embodiment of this application;

[0039] Figure 22 This is a schematic diagram illustrating the bit-by-bit comparison performed by the SAR ADC provided in this application embodiment, starting from the second least significant bit.

[0040] Figure 23 A schematic diagram of another SAR ADC provided in an embodiment of this application;

[0041] Figure 24 This is a flowchart illustrating the process by which the decoder compares the summation result with a preset threshold value.

[0042] Figure 25 A schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0043] Currently, the mainstream computer architecture adopts the von Neumann architecture, which consists of five parts: arithmetic logic unit (ALU), control unit, memory, input devices, and output devices.

[0044] The arithmetic logic unit (ALU) is the component in a computer that performs various arithmetic and logical operations. Its basic operations include addition, subtraction, multiplication, and division; logical operations such as AND, OR, NOT, and XOR; and operations such as shifting, comparison, and transfer. It is also known as the arithmetic logic unit.

[0045] The control unit consists of a program counter, instruction register, instruction decoder, timing generator, and operation controller. It is the "decision-making body" that issues commands, coordinating and directing the operation of the entire computer system. The arithmetic logic unit (ALU) and control unit are collectively called the central processing unit (CPU). The CPU is the heart of the computer.

[0046] Storage is divided into main memory and secondary storage. Main memory is the computer's memory component, used to store raw data, intermediate results, and programs that instruct the computer to perform its tasks. Secondary storage is used to store programs or data that need to be preserved for a long time and will not be lost after a power outage. It has a larger capacity but slower access speed. When the computer needs to execute a program or process data in secondary storage, it must first read the data from secondary storage into main memory before the central processing unit (CPU) can process it. Secondary storage includes hard drives, optical discs, and USB flash drives.

[0047] Input devices are devices used to input data and information into a computer. They act as a bridge for communication between the computer and the user or other devices. Input devices are one of the main devices for information exchange between the user and the computer system. Keyboards, mice, cameras, scanners, and light pens are all examples of input devices.

[0048] Output devices are terminal devices in a computer hardware system, used for receiving computer data, displaying it, printing it, producing sound, and controlling peripheral devices. They represent various calculation results or information in the form of numbers, characters, images, and sound. Common output devices include monitors and printers.

[0049] The von Neumann architecture has two inherent problems: the so-called memory wall problem and the power wall problem.

[0050] The memory wall problem refers to the fact that the current central processing unit's processing speed is much faster than the data access speed of the memory, making memory the main bottleneck restricting the improvement of data processing speed.

[0051] The power wall problem refers to the fact that the central processing unit (CPU) and memory are separated and connected by a data bus. During operation, data needs to be frequently transferred between the CPU and memory. The power consumption generated by this process is extremely high, sometimes hundreds of times higher than the power consumption actually used for data processing. Studies have shown that about 62.7% of the power consumption of a computer system is spent on CPU and memory read and write operations. The high latency and high power consumption caused by the traditional von Neumann architecture have become urgent problems to be solved, and the bottleneck of memory has become the main constraint on improving data processing speed.

[0052] To overcome the von Neumann bottleneck and build more efficient hardware and computing architectures in the context of intelligent big data, researchers have proposed in-memory computing. This technology integrates computing and storage, embedding computing units within memory, hence it is also known as in-memory computing. In-memory computing allows data to be processed directly in memory and the final results fed back to the central processing unit, thereby significantly reducing the time and power consumption of reading data from memory and transferring data on the bus. In-memory computing can effectively eliminate the high power consumption and limited speed of data transfer between memory and computing units, thus effectively solving the von Neumann bottleneck.

[0053] Matrix multiplication and accumulation (MAC) algorithms are a key research area in in-memory computing. As the name suggests, MAC algorithms can perform operations on two matrices, such as matrices... With matrix B Multiplying them together yields matrix C, and the elements of matrix C are:

[0054]

[0055] Multiplying two matrices requires multiplying each row of matrix A by each column of matrix B and then summing the results. If the product of matrices A and B is matrix C, then any element C in matrix C... ij for:

[0056] C ij =a i1 b ij +a i2 b 2j +…a in b nj .

[0057] The elements in the i-th row and j-th column of matrix C are the sum of the corresponding multiplications of the data in the i-th row of matrix A and the data in the j-th column of matrix B. More than 95% of the in-memory calculations are multiplication-addition operations. Many operations (such as convolution, dot product, matrix operations, digital filter operations, and even polynomial evaluation operations) can be decomposed into several multiplication-addition operations.

[0058] Taking computer vision (CV) as an example, in image processing, convolution operations are typically used to extract image features. Convolution is the process of obtaining another image by weighted averaging of input data (image data). Essentially, convolution is a process of multiplying and adding input data and feature data. The input data is a set of multiple pixels, which, after quantization, can be arranged in a matrix. The feature data, also known as weight data, is also arranged in a matrix; this weight matrix is ​​usually called the convolution kernel. Figure 1 As shown, the convolution process involves covering the input data with a weight matrix, multiplying corresponding positions by weight, and using the sum as a pixel in the result. This weight matrix slides across the input data with a certain stride, and the final result forms a new matrix called a feature map. This process is a continuous repetition of multiplication and addition operations.

[0059] When implementing multiplication and addition operations using circuits, there are generally four technical approaches: current accumulation type, charge accumulation type, digital accumulation type, and pulse accumulation type.

[0060] Figure 2 In the diagram, a, b, c, and d represent the schematic diagrams of the charge accumulation type multiply-accumulate circuit, the current accumulation type multiply-accumulate circuit, the digital accumulation type multiply-accumulate circuit, and the pulse accumulation type multiply-accumulate circuit, respectively.

[0061] A charge-accumulating multiply-accumulate circuit includes one or more multiplication circuits, a summation bus, and an analog-to-digital converter (ADC). The one or more multiplication circuits are arranged in an array. Figure 2 The charge-accumulating multiply-add circuit shown in Figure a includes a series of multiplication circuits, each corresponding to an analog-to-digital converter (ADC). This series of multiplication circuits is connected to the ADC via a summation bus. Each multiplication circuit performs a single-bit multiplication of one bit of input data and one bit of weight data to obtain the product. Here, a single-bit operation means that the multiplication circuit performs only one bit multiplication in one clock cycle. For example, if the bit width of the input data and weight data is 8 bits, the multiplication circuit performs a multiplication operation on the most significant bit of the input data and the most significant bit of the weight data, or on the second most significant bit of the input data and the second most significant bit of the weight data, etc. The summation bus is used to add the products calculated by this series of multiplication circuits to obtain the multiply-add result (of the single-bit operation). The ADC performs analog-to-digital conversion on the multiply-add result to obtain the multiply-add result of the digital signal. In subsequent calculations, other digital logic can shift and accumulate multiple intermediate multiply-add results to finally obtain the multiply-add result of the input data and weight data.

[0062] In a charge-accumulating multiply-add circuit, the summation bus uses charge accumulation to sum the results of each multiplication circuit. Specifically, each multiplication circuit includes a multiplier and a capacitor. After completing a single-bit multiplication operation, the multiplier charges the capacitor based on the product. For example, the capacitor is charged when the product is 1, and not charged when the product is 0. The capacitors of multiple multiplication circuits are connected to the same summation bus, and the accumulated voltage on the summation bus is the multiplication-addition result. Different numbers of capacitors charged result in different voltages on the summation bus. The summation bus is connected to the input signal terminal of an ADC (Analog-to-Digital Converter), which performs analog-to-digital conversion on the multiplication-addition result of the analog signal to obtain a digital signal.

[0063] The multiplier described above is used to perform multiplication operations on single-bit data. In one possible implementation, the multiplication circuit can be an XOR gate or other multiplication circuits.

[0064] For input data or weight data with multiple bits, a time-division multiplexing approach is generally used. For example, if the input data and weight data have a bit width of 8 bits, then 8 clock cycles are needed to complete the multiplication and addition operation of the input data and weight data. One bit is multiplied and added in each of the 8 clock cycles. For instance, in the first cycle, the first multiplication circuit completes the multiplication of the most significant bit of input data x1 with the most significant bit of weight data w1; the second multiplication circuit completes the multiplication of the most significant bit of input data x2 with the most significant bit of weight data w2; and so on. n The highest bit of the input data and the weight data w n The highest-order multiplication operation, where the highest-order bits of x1, x2, and x... n The highest bits of each input data point have the same binary weight, hence they are called the same-weight bits of the input data, or they can be considered as a single data column, called the same-weight column of the input data. Similarly, the highest bits of weighted data w1, the highest bits of weighted data w2, and the highest bits of weighted data w... n The highest bits are all the highest bits of the weighted data. They have the same weight, so they are called the same weighted column of the weighted data. This column of multiplication circuits accumulates the results of multiplying the same weighted column of the input data with the same weighted column of the weighted data. The ADC performs analog-to-digital conversion on the sum of the products of this column of multiplication circuits. The converted result is stored in a register for further shifting and summing.

[0065] Then, in the second clock cycle, the first multiplication circuit performs the multiplication of the second most significant bit of input data x1 with the second most significant bit of weight data w1, the second multiplication circuit performs the multiplication of the second most significant bit of input data x2 with the second most significant bit of weight data w2, and the nth multiplication circuit performs the multiplication of input data x... n The second highest position and weighted data w n For the second-highest bit multiplication operation, the ADC performs analog-to-digital conversion on the sum of the products of this series of multiplication circuits, and stores the converted result in a register for further shifting and summing.

[0066] In this way, one bit multiply-accumulate operation is completed in each clock cycle. After all the single-bit multiply-accumulate operations are completed, the results of the operations over 8 cycles are accumulated and integrated. Then, the digital logic shifts and sums the results of the multiply-accumulate operations from the most significant bit to the least significant bit, and finally obtains the overall result of the multiply-accumulate operation.

[0067] The principle of current-accumulating multiply-add circuit is similar to that of charge-accumulating multiply-add circuit. The difference lies in the implementation of the summation bus. In the charge-accumulating multiply-add circuit, each multiplier circuit includes a controlled current source. The on / off state of the controlled current source is controlled according to the calculation result of the multiplier. The output of the controlled current source is connected to the summation bus. In this way, the current signal output by the controlled current source corresponding to this series of multiplier circuits can be accumulated on the summation bus to obtain the multiply-add result. The number of controlled current sources that are turned on and off is different, so the multiply-add result obtained by summing is also different. The multiply-add result is transmitted to the ADC by the summation bus. The ADC performs analog-to-digital conversion on the summation result and outputs a digital signal.

[0068] The digital cumulative multiply-add circuit uses a digital adder to sum the product results of a series of multiplication circuits and outputs the result of the multiplication-addition operation; the pulse cumulative multiply-add circuit uses a time-to-digital converter (TDC) to sum the product results of a series of multiplication circuits.

[0069] Among these four different computing circuits, the charge-accumulation multiply-accumulate circuit is more widely used in model scenarios with precision below 8 bits because it can simultaneously achieve a balance in computing power per unit area, parameter storage capacity per unit area, and computing power per unit power consumption.

[0070] Both charge-accumulating and current-accumulating multiply-accumulate circuits require the use of an ADC to convert the multiplication and addition results from analog to digital quantities. The power consumption of the ADC is also an important component of the computational power consumption of the in-memory computing memory.

[0071] Among all ADC schemes, the successive approximation register (SAR) ADC is the most widely used for low bit precision. Its basic structure is as follows: Figure 3 As shown, it mainly includes a sample-and-hold circuit, a comparator, a digital-to-analog converter (DAC), and SAR logic. In addition, there are some other auxiliary analog circuits.

[0072] The SAR logic includes control logic circuits and successive approximation registers. The control logic circuits mainly generate some circuit control signals, such as sampling and conversion, and clock signal generation. The successive approximation registers mainly generate switching signals from high-order bits to low-order bits in sequence.

[0073] The sample-and-hold circuit samples the analog signal and ensures the stability of the input voltage during the conversion. A comparator is connected after the sample-and-hold circuit. It generates the valid bits of the digital signal by successive approximation. These valid bits are fed back to a DAC to close the loop, so that the successive approximation register compares the input voltage with the next binary value.

[0074] like Figure 4 As shown, the essence of SAR ADC operation is a binary search algorithm. This algorithm requires multiple clock cycles for analog-to-digital conversion, with each clock cycle comparing and obtaining one quantized value. The number of clock cycles required to complete the conversion is the same as the bit width of the SAR ADC. The SAR ADC determines the next significant bit by utilizing the previously determined significant bit information. Its workflow is as follows: First, the input signal Vin is sampled, ensuring that the sampled value does not change within one conversion cycle. Capacitors are typically used to store the input signal. Then, the hold phase begins, and the conversion starts. First, the control logic is initialized, setting the shift register to the intermediate code, i.e., the most significant bit (MSB) is 1, and all other bits are 0, such as 1000. This causes the DAC to generate an analog voltage Vref / 2. DAC The value of the most significant bit (MSB) can be obtained by comparing the sampled input signal Vin with Vref / 2. If Vin is greater than Vref / 2, then the most significant bit MSB is 1, otherwise it is 0. After the comparison of the most significant bit is completed, the SAR logic sets the second most significant bit to 1 and continues to compare. This process is repeated until all n-bit output codes are determined, resulting in the n-bit digital code output of the SAR ADC analog input signal Vin.

[0075] Compared to other ADCs, SAR ADCs have the advantages of low power consumption and small area. The disadvantage is that they need to compare data one by one and have a low operating frequency. Therefore, most improvements are focused on how to increase the operating frequency based on the usage and further reduce power consumption.

[0076] Depending on the DAC type, SAR ADCs can be divided into several different types: voltage-calibrated, current-calibrated, and charge-calibrated. Among them, the charge-calibrated SAR ADC, also known as the charge-redistribution SAR ADC, uses a capacitor array to store information, eliminating the need for additional sample-and-hold circuitry, thus reducing circuit size. Furthermore, the DAC has no current path, resulting in lower power consumption. In addition, the capacitors have better matching with resistors and MOSFETs, better temperature stability, and can achieve higher resolution. Therefore, the charge-redistribution SAR ADC is widely used.

[0077] Figure 5A 4-bit charge redistribution type SAR ADC is shown. Its DAC capacitor array consists of a set of binary-weighted capacitors (C0 to C3) and a redundant capacitor Cc with the same value as the least significant bit (LSB) capacitor C0. The capacitance value of the LSB capacitor C0 and the redundant capacitor Cc is C. The higher the binary weight of the capacitor, the larger its capacitance value. The capacitance value of the adjacent higher-weighted capacitor is twice the capacitance value of the lower-weighted capacitor. The capacitance values ​​from the LSB capacitor C0 to the LSB capacitor C3 are C, 2C, 4C and 8C, respectively. The total capacitance value of the DAC capacitor array is 16C.

[0078] The first plates of each capacitor are connected together to the input of the comparator, and this is called the common terminal of the DAC capacitor array, denoted as Vx. For example... Figure 5 As shown, the common terminal Vx of the DAC capacitor array is connected to the inverting input of the comparator; the non-inverting input of the comparator is grounded, and the inverting input is connected to the output of the comparator through switch S1; the second plate of the capacitor can be grounded using a selection switch, connected to the input signal terminal to connect to the input signal Vin, or connected to the reference signal terminal to connect to the reference voltage Vref, therefore the second plate of the capacitor is also called the free terminal. Figure 5 As shown, the highest capacitor C3 is connected to selector switch Sb1, the second highest capacitor C2 is connected to selector switch Sb2, capacitor C1 is connected to selector switch Sb3, the lowest capacitor C0 is connected to selector switch Sb4, and the redundant capacitor Cc is connected to selector switch Sb5. Sb1 and Sb5 can be connected to the input signal terminal (to connect the input signal Vin), the reference signal terminal (to connect the reference voltage Vref), and the ground terminal, respectively. In this embodiment, the first plate connected to the capacitor and the common terminal Vx is also called the upper plate, and the second plate is called the lower plate.

[0079] The working principle of a SAR ADC consists of three stages: sampling, holding, and bit-by-bit comparison. The following section will explain... Figure 5 Taking the 4-bit SAR ADC shown as an example, the three stages will be introduced separately. The SAR ADC with charge redistribution structure uses the principle of charge conservation to redistribute the total charge stored in the capacitor array, compare it, and finally output the 4-bit quantized values ​​b1, b2, b3, and b4 corresponding to the input signal Vin. The principle of each stage of the SAR ADC will be introduced below with reference to the attached diagram.

[0080] Sampling phase:

[0081] like Figure 6As shown, switch S1 on the comparator is closed, forming a feedback loop. Since the non-inverting input of the comparator is grounded, the voltage at the inverting input (i.e., the common terminal Vx) is also 0. The input signal Vin is connected to the lower plate of the capacitor through switches Sb1 to Sb5, charging the capacitor plate, so the voltage at the lower plate of the capacitor is Vin. The total capacitance of the capacitor array is 16C, i.e., 2... 4 C, so the total charge stored in the capacitor is Q = 2. 4 C Vin.

[0082] Maintenance phase:

[0083] Combination Figure 7 When switch S1 on the comparator is open and switches Sb1 to Sb5 are grounded, the charge stored in the capacitor will not be released, and the lower plate of the capacitor is grounded. The voltage changes from Vin in the sampling stage to 0. At this time, the voltage of the upper plate of each capacitor in the capacitor array (that is, the voltage of the common terminal Vx) changes from 0 to 0-Vin=-Vin.

[0084] Bit-by-bit comparison stage:

[0085] The comparison proceeds sequentially from the most significant bit to the least significant bit, gradually approaching the register output of 1000. This involves first connecting the active terminal (Sb1) of the most significant bit capacitor to the reference signal terminal; that is, connecting the lower plate of the most significant bit capacitor to the reference voltage Vref, while grounding the lower plates of the other capacitors. For example... Figure 8 As shown, the charge stored in the capacitor array will be redistributed. Applying charge conservation at the common terminal Vx, we have:

[0086] -Vin·2 4 C = Vx2 3 C + (Vx - Vref)² 3 C

[0087] -Vin·2 on the left side of the equal sign in the formula 4 C refers to the total charge stored in the capacitor array before the first comparison, Vx is the voltage at the inverting terminal of the comparator (i.e., the common terminal Vx of the capacitor array), and (Vx-Vref)·2 on the right side of the equation. 3 C is the charge stored in the highest-order capacitance, Vx·2 3 C represents the charge stored in the other capacitors in the capacitor array. Simplifying the above equation, we get:

[0088] -2Vin=2Vx-Vref

[0089]

[0090] After simplification, the voltage at the common terminal Vx, which is also the inverting input of the comparator, is 1 / 2Vref - Vin. This is equivalent to adding 1 / 2Vref to the source voltage. If Vx < 0, the comparator outputs a high level (1), indicating that Vref / 2 - Vin < 0, meaning Vin is greater than Vref / 2, and Sb1 remains closed. The first bit b1 = 1 is sent to the register for storage, and the lower plate of the MSB capacitor remains unchanged. If Vx > 0, the comparator outputs a low level (0), indicating that Vref / 2 - Vin > 0, meaning Vin is less than Vref / 2. Sb1 is changed from being connected to the reference signal terminal to ground, MSB = 0 is sent to the register for storage, and the lower plate of the MSB capacitor is grounded.

[0091] At this point, the value of b1 is determined, and Vx = -Vin + b1 * (Vref / 2).

[0092] Next, combined Figure 9 Connect the free end of the second-highest capacitor to the reference signal terminal, thus setting the lower plate of the second-highest capacitor as the reference voltage Vref. Similarly, using charge conservation at the common terminal, the voltage Vx is equivalent to the original voltage plus 1 / 4 Vref, i.e., Vx = -Vin + b1*(Vref / 2) + Vref / 4. If Vx < 0, the comparator outputs a high level (1), b2 = 1 remains unchanged, and switch Sb2 remains connected to the reference signal terminal with the reference voltage Vref unchanged. If Vx > 0, the comparator outputs a low level (0), b2 = 0 changes, and switch Sb2 is grounded.

[0093] At this point, the value of b2 is determined, and Vx = -Vin + b1*(Vref / 2) + b2*(Vref / 4).

[0094] This process continues until the calculation of the least significant bit, b4.

[0095] For example, combining Figure 10 Let b4 = 1, close Sb4 to the reference signal terminal. The voltage of the lower plate of the lowest capacitor C0 is Vref, and the voltage of the common terminal of the capacitor array is Vx. At this time, Vx = -Vin + b1*(Vref / 2) + b2*(Vref / 4) + b3*(Vref / 8) + b4*(Vref / 16). If Vx < 0, the comparator output is high, b4 = 1 remains unchanged, and the closing selection of switch Sb4 remains unchanged. If Vx > 0, the comparator output is low, b4 = 0 changes, and switch Sb4 is grounded.

[0096] At this point, the SAR ADC completes the full comparison process from the most significant bit to the least significant bit, outputting a complete 4-bit quantized digital value, with the most significant bit being b1, the second most significant bit being b2, and so on down to b3 and the least significant bit being b4.

[0097] During the SAR ADC conversion process, the capacitor needs to be charged and discharged multiple times. After each bit value is compared, the charge in the capacitor is released to clear it to 0 in preparation for the next comparison. This process is repeated from the most significant bit (MSB) to the least significant bit (LSB). The charging and discharging process of the capacitor generates a large amount of power consumption.

[0098] In charge-accumulation type multiply-accumulate circuits, SAR ADCs are used to convert the analog multiply-accumulate result into a digital value. During the multiply-accumulate operation, if the sparsity of the input data and weight data is high, that is, if there are many 0s in the binary representation of the input data and weight data, the resulting value will be small. Since the SAR ADC starts charging and discharging from the most significant bit when performing bit-by-bit comparisons, using the most significant bit as the comparison start bit during the bit-by-bit comparison process will result in wasted power consumption when the multiply-accumulate result is small. This is because the value of the multiply-accumulate result may be much smaller than 1 / 2Vref, or even 1 / 4Vref or 1 / 8Vref. Therefore, it is unnecessary to compare the multiply-accumulate result to 1 / 2Vref or 1 / 4Vref during the analog-to-digital conversion process, resulting in a large amount of wasted power consumption and increasing the time required for analog-to-digital conversion.

[0099] To reduce the power consumption of the SAR ADC during multiply-accumulate operations, the bit width of the SAR ADC can be determined by the sparsity of the input data and the corresponding column of feature data of the SAR ADC. One or more capacitors starting from the most significant bit can be skipped to reduce the power consumption generated by charging and discharging the capacitors.

[0100] For example, in a multiply-accumulate circuit, a column of computing units may perform 1-bit multiplications with more cases of 1×0, 0×1, and 0×0, while 1×1 cases are less than 1 / 4 of the number of computing units in that column. This results in a relatively small accumulated value after multiplication, for example, less than 1 / 4 of the SAR ADC reference voltage. Therefore, during the bit-by-bit comparison stage of the SAR ADC, the capacitors of the first two bits (the most significant and the second most significant bits) can be skipped, and charging and discharging can begin from the third bit capacitor. This can significantly reduce the number of capacitors that need to be charged and discharged in the capacitor array during analog-to-digital conversion, thereby greatly saving power consumption in analog-to-digital conversion.

[0101] One possible implementation is to control the starting comparison bit of the SAR ADC by minimizing the number of 1 values ​​in the input column data and the weight column. For example, combining... Figure 11aThe real-time bit width of the SAR ADC can be calculated as ceil(log2(min(X,W)+1)), where ceil is the floor function, min is the minimum function, X is the number of 1s in a single bit of input data, which can be calculated using an addition tree, and W is the number of 1s stored in the weight data corresponding to a column of computing units, which can be calculated on-chip and stored in the SAR logic when the data is stored in the computing unit array.

[0102] After calculating the minimum value and converting it into the corresponding logarithmic code, it is determined that some capacitors can be skipped, such as skipping the first two capacitors. Then, the following configuration is required: the lower plates of the first two capacitors of the DAC capacitor array, namely the highest and second highest capacitors, are grounded. This is to prevent unconditionally activating all capacitors in the DAC capacitor array for digital-to-analog conversion, thus saving energy.

[0103] This approach reduces the number of capacitors that need to be charged and discharged based on the sparsity of the input and weight data, thus lowering the power consumption of the SAR ADC. However, the min function requires a multi-bit comparator, which is implemented by cascading 2-bit comparators one after another, consuming a significant area. For example, an 8-bit comparator comparing 8 bits of data a[a7a6a5a4a3a2a1a0] with 8 bits of data b[b7b6b5b4b3b2b1b0] ultimately requires approximately 50 gate circuits to implement. Figure 11b As shown, it is mainly formed by connecting several NOT gates, AND gates, OR gates, NAND gates and NOR gates according to a specific logical relationship, comparing data a and data b bit by bit, and finally obtaining the comparison result of a and b.

[0104] The implementation of the min function circuit requires a lot of area to find the minimum number of 1s in the input data and weight data. However, in some technical fields, such as the field of computer vision (CV), the sparsity of image data (i.e., input data) is often greater than that of feature data (weight data). That is, the number of 0s in the input data is greater than the number of 0s in the weight data, and the number of 1s in the weight data is greater than the number of 1s in the input data. Therefore, the min circuit is not needed in this case. In this case, the min circuit part wastes area. Moreover, each column of calculation unit needs to set a min circuit, and the area occupied is proportional to the number of columns of multiplication circuits in the multiplication-addition operation circuit.

[0105] In addition, the above scheme only grounds the lower plates of the skipped highest bit capacitor and other capacitors. However, since the upper plates of the capacitors are connected to the common terminal of the capacitor array, the charge on the capacitors will still flow to these capacitors during the bit-by-bit comparison process, which will actually reduce the calculation accuracy.

[0106] To address these issues, this application provides a solution that controls the starting position of capacitor charging and discharging for each column of the SAR ADC in the entire multiply-accumulate circuit, as well as the logic control during the comparison process, solely based on the number of 1s in the input data. For capacitors with high-bit values ​​that do not require comparison, the system grounds them and disconnects the other end of the capacitor from the interconnection line with other capacitors, completely isolating the capacitors that do not require comparison from the other capacitor arrays that do require comparison. This reduces the number of capacitors requiring charging and discharging, thereby lowering the power consumption of the operation.

[0107] The multiply-accumulate circuit provided in the embodiments of this application can be applied to in-memory computing memory, for example, in combination with... Figure 12 As shown, the memory includes a storage area and an arithmetic circuit. The storage area has multiple storage cells for storing data. The arithmetic circuit can read the data stored in the storage cells in the storage area to perform calculations, and the calculation results can be output to the processor.

[0108] For example, in combination Figure 13 The storage area includes multiple first storage units X1 to Xn and second storage units W1 to Wn corresponding to the number of first storage units. The first storage units store single bits of input data, and the second storage units store single bits of weight data. The first and second storage units can be any storage circuit, such as a register, a single storage unit, a word line, a bit line, or other circuit structures with storage functions. In some other possible implementations, the second storage unit for storing weight data can also be located within the arithmetic circuit.

[0109] As one possible implementation, the first storage unit stores a single bit of the input data. This can be achieved by outputting the input data bit by bit to the first storage unit according to the weights of the data in a preset clock cycle. For example, in the first clock cycle, the first storage unit X1 stores the most significant bit of the input data x1; the first storage unit X2 stores the most significant bit of the input data x2; and so on, the first storage unit Xn stores the most significant bit of the input data xn.

[0110] The second storage unit stores the weight data in the same way as the first storage unit stores the input data. In the first clock cycle, the second storage unit W1 stores the highest bit of the weight data w1, the second storage unit W2 stores the highest bit of the weight data w2, and so on, the second storage unit Wn stores the highest bit of the weight data wn.

[0111] Based on this, in the second clock cycle, the first storage unit is used to store the next weight bit of the input data, and the second storage unit is used to store the next weight bit of the weight data. For example, in the second clock cycle, the first storage unit X1 stores the second most significant bit of the input data x1, and the second storage unit W2 stores the second most significant bit of the weight data w1; the first storage unit X2 stores the second most significant bit of the input data x2, and the second storage unit W2 stores the second most significant bit of the weight data w2... the first storage unit Xn stores the second most significant bit of the input data xn, and the second storage unit Wn stores the second most significant bit of the weight data wn.

[0112] For example, in combination Figure 14 The aforementioned operational circuit may include at least one multiply-accumulate operational circuit, which includes at least one charge-accumulating multiply-accumulate operational unit. Figure 14 The multiply-accumulate circuit shown includes m multiply-accumulate units, each of which includes a successive approximation register analog-to-digital converter (SAR ADC), a bit-width control circuit, a summation bus, and multiple multiplication circuits.

[0113] The multiplication circuit is used to multiply a single bit of input data with a single bit of weight data to obtain an analog product. In the charge accumulation type multiply-add unit, the multiplication circuit converts the digital product into a voltage signal.

[0114] Multiple multiplication circuits are connected to the input signal terminal of the SAR ADC through a summation bus. The summation bus accumulates the multiplications output by the multiple multiplication circuits and transmits the result to the SAR ADC. The voltage output by each multiplication circuit is accumulated and added on the summation bus. The voltage on the summation bus represents the sum of the multiplications output by the multiple multiplication circuits, i.e., the multiplication result. The SAR ADC is used to perform analog-to-digital conversion on the summation result.

[0115] SAR ADC includes a digital-to-analog converter (DAC) and a capacitor array. During analog-to-digital conversion, the input signal (i.e., the voltage of the summation bus) is converted in three steps: sampling, holding, and bit-by-bit comparison. In the bit-by-bit comparison stage, the capacitors in the DAC capacitor array are charged and compared sequentially from the most significant bit to the least significant bit.

[0116] The bit width control circuit is connected to the SAR ADC. The bit width control circuit is used to sum the single-bit input data of multiple multiplication circuits and control the starting bit of the capacitor in the DAC capacitor array during the bit-by-bit comparison stage according to the summation result. For example, the starting bit is adjusted from the most significant bit to a preset bit, which can be the second most significant bit or a lower bit. This reduces the number of capacitors charged and discharged in the capacitor array by the SAR ADC during the bit-by-bit comparison stage and reduces the time required for the SAR ADC to complete the analog-to-digital conversion.

[0117] For example, the bit width control circuit includes an adder circuit and a decoder. The adder circuit is used to sum the single-bit input data of multiple multiplication circuits connected to the same summation bus, that is, to determine the number of 1s in the single-bit input data of the multiple multiplication circuits. The decoder is used to control the start bit of the capacitor array of the SAR ADC in the bit-by-bit comparison stage according to the summation result of the adder circuit.

[0118] Here, the starting bit refers to which capacitor to start comparing in the bit-by-bit comparison phase. Generally speaking, the starting bit of the SARADC in the bit-by-bit comparison phase is the most significant bit. That is, the plates of the most significant bit capacitor are charged first. The input signal is then compared with Vref / 2 to determine the quantization value of the most significant bit, which is 1 or 0. If it is greater than Vref / 2, it is 1; if it is less than Vref / 2, it is 0. Then, in the next comparison, the plates of the next most significant bit capacitor are charged. Based on the first comparison, the input signal is compared with the result of the first comparison plus Vref / 4. This process continues until the quantization value of the least significant bit is determined.

[0119] The decoder is used to control the start bit of the SAR ADC capacitor array in the bit-by-bit comparison stage based on the summation result of the above-mentioned adder circuit. For example, the second highest bit can be set as the start bit, so that the highest bit capacitor will not be charged and compared in the bit-by-bit comparison stage, which can reduce the power consumption of the SAR ADC and the time required for analog-to-digital conversion.

[0120] The following detailed description of the solutions in the embodiments of this application, with reference to specific examples, will be provided below.

[0121] Please continue reading. Figure 15 The multiply-add unit includes multiple multiplication circuits, which can be arranged in rows and columns. Multiplication circuits located in the same row can multiply the same input data with different weight data; for example, x1×w 1,1 x1×w 2,1 x n ×w m,1 Multiplication circuits located in the same column multiply different input data with different weight data, for example, x1×w 1,1 x2×w 1,2 x n×w 1,n Furthermore, multiple multiplication circuits located in the same column are connected to the same summation bus, which is connected to the SAR ADC. In this way, the SAR ADC can perform analog-to-digital conversion on the multiplication and summation results of a column of multiplication circuits.

[0122] Here, the multiply-accumulate unit can be a charge-accumulating type. For example, the multiplication circuit includes a multiplier and a capacitor. The output of the multiplier is connected to one plate of the capacitor, and the other plate of the capacitor is connected to the summation bus. The multiplier multiplies the single-bit input data and the single-bit weighted data, and uses the product to charge the capacitor. When the product is 1, the capacitor is charged; when the product is 0, the capacitor is not charged. This converts the product output by the digital multiplier into an analog quantity, i.e., the voltage of the capacitor. Multiplication circuits located in the same column are connected to the same summation bus, and further connected to the same SAR ADC through the summation bus. Thus, the SAR ADC can convert the sum of the products of multiplication circuits located in the same column into a digital signal.

[0123] In some other possible implementations, the multiply-accumulate unit can also be a current-accumulating type. Unlike the charge-accumulating type, the current-accumulating type sums multiple products by accumulating current. The multiplication circuit includes a multiplier and a controlled current source. The multiplier multiplies a single bit of input data and a single bit of weight data and outputs a product. The product is used to control the on / off state of the current source. For example, the current source is on when the product is 1 and off when the product is 0. Multiplication circuits located in the same column are connected to the same summation bus. When the current source is on, the current signal is accumulated on the summation bus. Since the SARADC performs analog-to-digital conversion on the voltage signal, a capacitor can be set on the summation bus to convert the accumulated current into a voltage signal. In this way, the SAR ADC can convert the sum of the products of the multiplication circuits located in the same column into a digital signal.

[0124] For example, the number of multiplication circuits in the multiply-add unit can be matched with the number of the first or second memory units. Each multiplier is used to perform multiplication of a single bit of input data with a single bit of weight data. Since the bit width of the input data and weight data is more than 1 bit in some cases, for multiply-add operations of multi-bit input data and weight data, it can be decomposed into bit-by-bit single-bit multiplication operations according to the binary weight. After obtaining the multiply-add result of the single-bit operation, it can be summed by digital logic shifting. In this way, the multiply-add result of multi-bit input data and weight data can be obtained.

[0125] For example, if the input data x1 and the weight data w1 have a bit width of 8 bits, for a single multiplication circuit, since the multiplication circuit performs one bit multiplication per clock cycle, it takes 8 cycles to complete the bit-by-bit multiplication of the input data and the weight data with the same weight bits. See [link to relevant documentation] Figure 16 The first clock cycle calculates the multiplication of the most significant bit of the input data with the most significant bit of the weight data; the second clock cycle calculates the multiplication of the second most significant bit of the input data with the second most significant bit of the weight data; and the eighth clock cycle calculates the multiplication of the least significant bit of the input data with the least significant bit of the weight data.

[0126] For multiple multiplication circuits connected to the same summation bus, in the first clock cycle, the first multiplication circuit is used to multiply the most significant bit of the input data x1 with the most significant bit of the weight data w1; the second multiplication circuit is used to multiply the most significant bit of the input data x2 with the most significant bit of the weight data w2, and so on. The nth multiplication circuit is used to multiply the input data x... n The highest bit and weight data w n The highest bit of the multiplication, the summation bus accumulates the output results of n multiplication circuits to obtain the multiplication and addition result of the single-bit multiplication of the input data and the weight data, which can also be called the intermediate multiplication and addition result.

[0127] In the second clock cycle, the first multiplication circuit is used to multiply the second most significant bit of input data x1 with the second most significant bit of weight data w1; the second multiplication circuit is used to multiply the second most significant bit of input data x2 with the second most significant bit of weight data w2... and so on. The nth multiplication circuit is used to multiply the input data x... n The second highest position and weighted data w n The second-highest bit multiplication, the summation bus accumulates the output results of n multiplication circuits to obtain the multiplication and addition result of the single-bit multiplication of input data and weight data.

[0128] Taking an input data and weight data with a bit width of 8 as an example, it takes at least 8 clock cycles to complete the multiplication and addition operation of all weight bits of the input data and weight data. In each clock cycle, the SAR ADC performs analog-to-digital conversion on the multiplication and addition result, takes the voltage on the summation bus as the input signal, compares it bit by bit, and outputs a digital signal after quantizing the input signal.

[0129] By shifting and accumulating the intermediate multiplication and addition results of the digital signal over 8 cycles, the complete multiplication and addition result of the input data and weight data can be obtained.

[0130] To reduce the power consumption of the SAR ADC when performing analog-to-digital conversion on the multiplication-accumulation results, the solution provided in this application controls the starting position of the capacitor charging and discharging during the bit-by-bit comparison stage of the SAR ADC based on the sum of the single-bit input data of a column of multiplication circuits corresponding to the SAR ADC.

[0131] In fields such as computer vision, the sparsity of input data is much greater than that of weight data. That is, in binary representation, the number of 1s in the weight data is greater than the number of 1s in the input data. The multiplication circuit performs single-bit multiplication of the input data and weight data, namely 1×1, 1×0, 0×1, and 0×0. Since the number of 1s in the weight data is greater than the number of 1s in the input data, the more 1s in the input data, the larger the final multiplication-addition result. Therefore, the number of 1s in the single-bit input data of multiple multiplication circuits connected to the same summation bus can be determined, that is, the summation of the single-bit input data of these multiple multiplication circuits can be used to control the starting position of capacitor charging and discharging in the bit-by-bit comparison stage of the SAR ADC.

[0132] Since multiple multiplication circuits connected to the same summation bus are used to perform one-to-one multiplication of multiple input data with multiple weight data, and when the bit width of the input data and weight data is greater than 1, the multiplication circuit performs multiplication bit by bit. Within one clock cycle, the binary weights of the single-bit input data of the multiple multiplication circuits connected to the same summation bus are also the same. That is, within the same clock cycle, the first multiplication circuit multiplies the most significant bit of the first input data with the most significant bit of the first weight data, the second multiplication circuit multiplies the most significant bit of the second input data with the most significant bit of the second weight data, and so on, with the nth multiplication circuit multiplying the most significant bit of the nth input data with the most significant bit of the nth weight data. Therefore, the single-bit input data of the multiplication circuits connected to the same summation bus can be called a column with the same weight.

[0133] For example, in combination Figure 17a The input data has the same bit width. For example, if the input data has a bit width of 8 bits, the input data x1 to x2... n The same weighted bits constitute a weighted column. For example, it could refer to the highest bit (first bit) of input data x1, the highest bit (first bit) of input data x2, and so on up to the highest bit (first bit) of input data x... n The highest bit (first bit); or the second bit of input data x1, the second bit of input data x2 to the input data x n The second column, or other columns with the same weight, etc.

[0134] When multiplying a single bit of input data with a single bit of weight data, there are four possibilities: 0×0, 0×1, 1×0, and 1×1. However, in the field of computer vision (CV), the sparsity of weight data is generally much smaller than that of input data. In practical applications, the composition of weight column data is not sparse but rather dense. Denseness means that the number of 1s in the weight column data is relatively large. Therefore, the number of 1s in the weight data is generally greater than the number of 1s in the input data. In this embodiment, the first storage unit stores the input data, and the second storage unit stores the weight data. Therefore, when the multiplication circuit performs a single-bit multiplication operation, the multiplier provided by the second storage unit is usually 1, while the multiplier provided by the first storage unit may be 1 or 0. That is to say, the actual multiplication should be 1×1 or 0×1 in most cases. Only in the case of 1×1 will there be current or voltage on the summation bus, and the result of this multiplication operation will be accumulated. The more frequently the 1×1 case occurs, the larger the final accumulated result will be. When an ADC performs analog-to-digital conversion on a signal, it compares signals from largest to smallest. First, it compares the input signal (the result of multiplication and addition) with half of the reference voltage. Based on the first comparison, it then adds half of the reference voltage for comparison until the lowest resolution is reached. If there are more 1s in the same weight column of the input data, that is, if there are more 1×1 cases in the multiplication operations performed by each multiplier, then the accumulated result of multiplication and addition will be larger. If there are fewer 1s in the same weight column of the input data, then the accumulated result of multiplication and addition will be smaller.

[0135] If the multiplication-accumulation result is less than 1 / 4 of the reference voltage, the process of charging and discharging the most significant bit capacitor in the bit-by-bit comparison stage of the SAR ADC can be omitted. This is because charging and discharging the most significant bit capacitor is used to compare the intermediate multiplication-accumulation result with 1 / 2 of the reference voltage. Furthermore, the higher the number of bits in the capacitor, the larger the capacitance value, and the higher the power consumption required for charging and discharging. Therefore, when the number of 1s in the same weight column of the input data is small, i.e., when the multiplication-accumulation result is small, omitting this part of the comparison process can greatly save the power consumption of the SAR ADC and also reduce the power consumption of the in-memory memory.

[0136] For example, a 4-bit SAR ADC can output digital signals ranging from binary 0000 to 1111, or decimal 0 to 15. When performing bit-by-bit comparisons in this 4-bit SAR ADC, the DAC capacitor array first charges the most significant bit capacitor, leaving the other bits uncharged. The input signal is compared to (binary) 1000. If the result is greater than 1000, the most significant and second-most significant bit capacitors are charged in the next comparison, while the other bits remain uncharged. The input signal is then compared to 1100. If the result is less than 1000, the second-most significant bit is charged, while the other bits remain uncharged. The input signal is then compared to 0100. This process continues bit-by-bit comparisons until the output result is obtained.

[0137] However, if the voltage of the input signal (i.e., the result of multiplying and adding multiple single-bit input data and weighted data) is small, then one or more bits of capacitors can be skipped to reduce the power consumption wasted on charging and discharging these capacitors. For example, if the intermediate multiplication and addition result is less than 0100, then the highest bit capacitor can be skipped, and the comparison can start directly from the second highest bit capacitor.

[0138] However, during the calculation process, the magnitude of the multiplication-accumulation result needs to be determined by the SAR ADC after analog-to-digital conversion. Before that, the specific magnitude of the multiplication-accumulation result cannot be determined, and therefore the starting position of capacitor charging and discharging in the bit-by-bit comparison stage of the SAR ADC cannot be determined based on the multiplication-accumulation result.

[0139] However, the multiply-accumulate result converted by the SAR ADC is obtained by accumulating the products calculated by the various multiplication circuits connected to the summation bus. The intermediate multiply-accumulate results cannot be known before the SAR ADC performs analog-to-digital conversion, but the individual bits of data used in the multiplication operation are known.

[0140] Furthermore, the SAR ADC is used to perform analog-to-digital conversion on the summation of the products output by the multiplication circuit connected to the summation bus. The product here exists in only four forms: 0×0, 0×1, 1×0, and 1×1. The product will be accumulated only when both the single bit of the input data and the single bit of the weight data are 1. Therefore, the intermediate multiplication result after accumulation can be represented by the number of 1s in the single bit of the input data and the weight data.

[0141] For example, the input data column with the same weight contains p 1s, and the corresponding weight data column with the same weight contains q 1s. Since the results of 0×0, 0×1, and 1×0 are all 0, and only the result of 1×1 is 1, the result of multiplying the input data column with the corresponding weight data column with the same weight is at most min(p,q), that is, the smaller of p and q.

[0142] For example, if there are 8 input data points and 8 weight data points, and the input data with the same weight column includes 5 ones and 3 zeros, while the corresponding weight data with the same weight column includes 7 ones and 1 zero, then the product of the two will have a maximum of 5 ones, and the sum will be a maximum of 5. If the input data with the same weight column includes 4 ones and 4 zeros, while the corresponding weight data with the same weight column includes 7 ones and 1 zero, then the product of the two will have a maximum of 4 ones, and the sum will be a maximum of 4.

[0143] In the field of CV technology, the sparsity of weight data is generally much smaller than that of input data. That is, the number of 1s in the same weight column of weight data is much larger than the number of 1s in the same weight column of input data. If a circuit is used to determine the smaller value of the number of 1s in the input data or weight data, a large area in the chip will be wasted. Therefore, the solution provided in this application uses a bit width control circuit to adjust the starting position of charging and discharging in the bit-by-bit comparison stage of SAR ADC according to the number of 1s in the input data.

[0144] For example, the bit-width control circuit includes an adder circuit and a decoder. The adder circuit sums the single-bit input data of multiple multiplication circuits connected to the summation bus. The summation result is transmitted to the decoder, which decodes the summation result and outputs a capacitor switching sequence instruction. The capacitor switching sequence instruction is used to indicate the starting position of capacitor charging and discharging in the bit-by-bit comparison stage of the SAR ADC. One or more switches are used to disconnect the skipped capacitors from the capacitor array. Generally, capacitor charging and discharging in the bit-by-bit comparison stage of the SAR ADC starts from the most significant bit. The capacitor switching sequence instruction can be used to indicate skipping a portion of the capacitors, for example, skipping one bit, i.e., starting charging and discharging from the second most significant bit, or skipping two bits, i.e., starting charging and discharging from the next most significant bit.

[0145] For example, the adder circuit can use an adder tree to sum the single-bit input data of multiple multiplier circuits connected to the same summation bus, and the summation result is output to the decoder.

[0146] Figure 17b The diagram illustrates the workflow of the multiply-add operation circuit provided in this embodiment. For example, taking a multiply-add operation unit comprising eight multiplication circuits, the addition tree needs to sum eight single-bit input data. Figure 18 As shown, the structure of the addition tree is similar to that of a binary tree. After adding the data to be added in pairs at each level, the final output is the sum. It should be noted that x1 to x8 in the figure are single-bit input data of the multiplication circuit.

[0147] The summation result for 8-bit single-bit input data ranges from 0000 to 1000. The minimum summation result is 0000 when all single-bit input data are 0, and the maximum summation result is 1000 when all single-bit input data are 1.

[0148] For example, the decoder compares the summation result with a preset threshold value. When the summation result is less than the preset threshold value, the decoder adjusts the start bit from the most significant bit to a preset bit, where the preset bit is at least one bit lower than the most significant bit.

[0149] In traditional SAR ADCs, one side of each capacitor in the DAC capacitor array is connected to the common terminal Vx of the DAC capacitor array, while the other side is a free terminal. Even if the free terminal of the capacitor is grounded, during the bit-by-bit comparison stage, since one side of the capacitor is always connected to the common terminal, the charge on the capacitor charged during the bit-by-bit comparison stage will still flow to these skipped capacitors, which will actually reduce the calculation accuracy.

[0150] Therefore, the SAR ADC provided in this application embodiment has a switching switch between each capacitor in the DAC capacitor array and the common terminal of the DAC capacitor array. The decoder is connected to these switching switches, so that the on / off state of these switching switches can be controlled by outputting different decoding values.

[0151] One possible implementation is as follows Figure 19 As shown, Figure 19 A multiply-accumulate circuit is shown, which includes a SAR ADC, for example, with a bit width of 4. Its DAC capacitor array includes a set of binary weighted capacitors and a redundant capacitor Cc. The number of binary weighted capacitors is the bit width of the SAR ADC. Here, there are 4 binary weighted capacitors. The capacitance values ​​from the least significant bit capacitor C0 to the most significant bit capacitor C3 increase sequentially, namely C, 2C, 4C, and 8C, respectively. The capacitance value of the redundant capacitor Cc is the same as that of the least significant bit capacitor C0, which is C.

[0152] The DAC capacitor array includes a common terminal Vx, which is connected to the first input terminal of the comparator, such as... Figure 19 As shown, the common terminal Vx is connected to the inverting input of the inverter; the non-inverting input of the comparator is grounded, and the inverting input is also connected to the output of the comparator through switch S1. In the DAC capacitor array, the first plate of the capacitor is connected to the common terminal, and the second plate is used to connect to the input signal terminal, the reference signal terminal, or ground.

[0153] To ensure that when the start bit of the DAC capacitor array is adjusted from the most significant bit to a preset bit, the skipped capacitors are completely disconnected from other capacitors in the array, thus not affecting the calculation accuracy, the SAR ADC provided in this application includes multiple switching switches. The first plate of each capacitor in the DAC capacitor array is connected to a common terminal through a switching switch. These switching switches are connected to a decoder and can switch the switch state according to the decoded value output by the decoder. In addition, the second plate of each capacitor is connected to a selection switch, which can be used to connect to a reference signal terminal, an input signal terminal, or ground. These selection switches are connected to SAR logic (not shown in the figure) and can switch the connection according to the control of the SAR logic.

[0154] For example, combining Figure 19 The first plate of the highest capacitor C3 is connected to the common terminal Vx through the switching switch Sk1; the first plate of the second highest capacitor C2 is connected to the common terminal Vx through the switching switch Sk2; the first plate of the second lowest capacitor C1 is connected to the common terminal Vx through the switching switch Sk3; the first plate of the lowest capacitor C0 is connected to the common terminal Vx through the switching switch Sk4; and the first plate of the redundant capacitor Cc is connected to the common terminal Vx through the switching switch Sk5.

[0155] The second plate of the highest capacitor is connected to selection switch Sb1, the second highest capacitor to selection switch Sb2, the second lowest capacitor to selection switch Sb3, the lowest capacitor to selection switch Sb4, and the redundant capacitor to selection switch Sb5. All selection switches Sb1 to Sb5 are three-to-one switches, which can be used to connect to the input signal terminal, reference signal terminal, or ground of the SAR ADC.

[0156] In this case, taking the highest bit capacitor C3 as an example, when the decoder controls the Sk1 corresponding to the highest bit capacitor C3 to be disconnected and the SAR logic control selection switch Sb1 is grounded, the upper and lower plates of the highest bit capacitor C3 are completely disconnected from the DAC capacitor array. During the bit-by-bit comparison stage, the highest bit capacitor can be skipped, and the highest bit capacitor is not charged or discharged, thus reducing power consumption. At the same time, the process of comparing one capacitor is reduced, which can reduce the conversion time.

[0157] During the multiplication-addition operation, the decoder compares the summation result with a preset threshold value. When the summation result is less than the preset threshold value, the start bit is adjusted from the most significant bit to the preset bit. Here, the preset bit is at least one bit lower than the most significant bit. For example, multiple threshold values ​​can be preset, and the summation result can be compared with different preset threshold values ​​to determine the start bit of the SAR ADC in the bit-by-bit comparison stage.

[0158] For example, the preset threshold value can be set according to the output range of the SAR ADC. For instance, if the maximum digital signal output by a 5-bit SAR ADC is 11111, then the summation result can be compared with 10000. It can be seen that the preset threshold value here is actually the digital signal corresponding to different voltage values ​​output by the DAC capacitor array. For example, 10000 corresponds to a voltage of 1 / 2 Vref. Therefore, for... Figure 19 The 4-bit SAR ADC shown can have its preset threshold value set to 1000, and the summation result is compared with 1 / 2Vref.

[0159] Alternatively, in other words, if the bit width of the SAR ADC is n, the preset threshold value can be 2. n-1 For example, if the bit width of a SAR ADC is 4, then the preset threshold value can be 1000 (i.e., 2^35). 3 When the summation result of the adder circuit is less than 1000, the starting bit of the DAC capacitor array of the SAR ADC in the bit-by-bit comparison stage is set to the second highest bit.

[0160] In other words, after sampling and holding, during the bit comparison phase, the second-highest bit is used as the starting bit to charge and compare the capacitor C2. This comparison is similar to the second comparison after confirming that bit b1 is 0. Figure 20 As shown, Figure 20 The multiplication circuit, summation bus, and bit width control circuit have been simplified. After the sampling and holding stages, the voltage of the upper plate of the capacitor array is -Vin, and the total charge stored in the capacitor array is -Vin·16C.

[0161] When skipping the highest-order capacitor C3 and using the second-highest-order capacitor C2 as the starting bit for bit-by-bit comparison, the highest-order capacitor C3 does not participate in the comparison because its first plate is disconnected from the common terminal Vx of the DAC capacitor array and its second plate is grounded.

[0162] Applying charge conservation to the capacitor array, we have:

[0163] -Vin·16C=Vx·4C+(Vx-Vref)·4C

[0164] In the equation, -Vin·16C on the left side of the equation refers to the total charge stored in the capacitor array after sampling and holding, Vx is the voltage at the inverting terminal of the comparator (i.e., the common terminal of the capacitor array), and (Vx-Vref)·4C on the right side of the equation is the charge stored in the second-highest (starting) capacitor C2, and Vx·4C is the charge stored in the other capacitors in the capacitor array (the second-lowest capacitor C1, the lowest capacitor C0, and the redundant capacitor Cc). Simplifying the above equation, we get:

[0165] Vx = -2Vin + Vref / 2

[0166] After simplification, the voltage at the common terminal, i.e., the inverting input of the comparator, is Vx = -2Vin + Vref / 2. If Vx < 0, the comparator outputs a high level (1), indicating that -2Vin + Vref / 2 < 0, meaning Vin is greater than Vref / 4. Sb2 remains closed. b2 = 1 is sent to the register for storage, and the lower plate of the second-highest capacitor C2 remains unchanged. If Vx > 0, the comparator outputs a low level (0), indicating that -2Vin + Vref / 2 > 0, meaning Vin is less than Vref / 4. Sb2 is changed from being connected to Vref to being connected to GND, b2 = 0 is sent to the register for storage, and the lower plate of the second-highest capacitor C2 is grounded.

[0167] Since the highest-order capacitor C3 is skipped and the second-highest-order capacitor C2 is used as the starting bit for comparison, the highest-order bit b1 = 0. After determining the value of the second-highest-order bit b2, subsequent bit-by-bit comparisons are performed sequentially until the quantized values ​​of bits b3 and b4 are determined, and the quantized digital signal of the multiplication-addition result is output.

[0168] As can be seen from the above, when the summation result of the adder circuit is less than 1000, setting the start bit of the DAC capacitor array of the SAR ADC to the second-highest bit in the bit-by-bit comparison stage results in the same digital signal output as the digital signal output with the highest bit as the start bit, without compromising output accuracy. Using the second-highest bit as the start bit means the highest bit's value is defaulted to 0. Only 3 comparisons are needed to complete the analog-to-digital conversion. Compared to the traditional analog-to-digital conversion process, this eliminates the need to charge and discharge the highest bit capacitor. The highest bit capacitor, C3, is the largest capacitor in the DAC capacitor array; omitting this process reduces power consumption and the number of comparisons. Originally, a 4-bit SAR ADC required 4 comparisons, but by setting the second-highest bit as the start bit, only 3 comparisons are needed, thus reducing the number of comparisons and shortening the analog-to-digital conversion time.

[0169] In the SAR ADC analog-to-digital conversion process, reducing the comparison start bit of the DAC capacitor array in the bit-by-bit comparison stage by at least one bit from the most significant bit can reduce power consumption and conversion time. In this case, the SAR ADC only needs to be able to disconnect the most significant bit capacitor C3 from the DAC capacitor array, that is, to set a switching switch Sk1 between the first plate of the most significant bit capacitor C3 and the common terminal of the DAC capacitor array, such as... Figure 21 As shown, the first plate of the remaining capacitors does not need to be switched with the common terminal of the DAC capacitor array, which can reduce circuit complexity and reduce component cost.

[0170] The aforementioned switching switch Sk1 can be a transistor, such as a MOSFET. The MOSFET can switch its state according to the decoded value output by the decoder. For example, the decoder can be connected to the control terminal of the MOSFET, the first terminal of the MOSFET can be connected to the common terminal Vx of the DAC capacitor array, and the second terminal of the MOSFET can be connected to the first plate of the highest-order capacitor C3. When the decoded value output by the decoder to the control terminal of the MOSFET is 1 (high-level signal), the MOSFET is turned on; when the decoded value output by the decoder to the control terminal of the MOSFET is 0 (low-level signal), the MOSFET is turned off. Alternatively, the MOSFET can be turned on when the decoded value is 0 and turned off when the decoded value is 1. Different control methods can be set according to the selection of the MOSFET.

[0171] In the above example, the working principle of the multiplication and addition unit provided in this application embodiment is introduced by taking the case where the preset bit is one bit lower than the highest bit, that is, the preset bit is the second highest bit. In other implementation methods, the result of the summation of the addition circuit can be compared with multiple preset threshold values ​​to determine the specific position of the preset bit.

[0172] For example, the maximum digital signal that a 5-bit SAR ADC can output is 11111. The summation result can be compared with 10000, 01000, 00100, and 00010 in sequence. It can be seen that the preset threshold value here is actually the digital signal corresponding to different voltage values ​​when the DAC capacitor array outputs. For example, the voltage value corresponding to 10000 is 1 / 2Vref, 01000 is 1 / 4Vref, 00100 is 1 / 8Vref, and 00010 is 1 / 16Vref.

[0173] So for Figure 19 The 4-bit SAR ADC shown can have its threshold values ​​set to 1000, 0100, and 0010 respectively.

[0174] In other words, when the summation result 'a' of the adder circuit satisfies: 2 m-1 ≤a<2 m At this time, the decoder determines that the preset bit is nm bits lower than the highest bit, where m and n are positive integers, n is the bit width of the SAR ADC, and m < n.

[0175] The preceding content has described the bit-by-bit comparison process of a SAR ADC. Comparisons begin with the most significant bit, successively approximating the input signal, and outputting a digital signal that is closest to the input signal. If the adder circuit sums the single-bit input data of the multiplier circuit connected to the same summing bus, and the summation result is relatively small, for example, less than 1 / 4 or 1 / 8 of the reference voltage, the voltage of the SAR ADC's input signal will also be small. In such cases, simply lowering the start bit by one bit may result in wasted power consumption and conversion time.

[0176] Therefore, this application provides another method for determining the starting bit of the capacitors in the bit-by-bit comparison stage of the DAC capacitor array. The starting bit is adjusted from the most significant bit to a preset bit, and the specific position of the preset bit is determined based on the range of the summation result 'a'. For example, when the summation result 'a' of the addition tree is determined to satisfy: 2 m-1 ≤a<2 m At this time, the decoder is used to determine the preset bit width (nm bits lower than the most significant bit). Here, n refers to the bit width of the SAR ADC; for example, in a 4-bit SAR ADC, n is 4. m-1 With 2 m The threshold value is a preset value, where m is less than n.

[0177] For example, taking a 4-bit SAR ADC as an example, if the summation result 'a' satisfies 2 2 ≤a<2 3 When m is 3, which is equivalent to 0100≤a<1000 in binary, the preset bit is determined to be 4-3=1 bits lower than the highest bit, meaning the starting bit is the second highest bit.

[0178] This situation is similar to the case described above, which uses a 4-bit SAR ADC as an example, where the summation result of the adder circuit is less than 1000. It will not be described in detail here.

[0179] For example, again using a 4-bit SAR ADC, if the summation result 'a' of the addition tree satisfies 2... 1 ≤a<2 2 When m is 2, which is 0010 ≤ a < 0100 in binary, the preset bit is determined to be 4-2 bits lower than the highest bit, such as... Figure 22 As shown, the starting bit is the second lowest bit.

[0180] In the example above, in a 4-bit SAR ADC, after the sampling and holding phase, bit-by-bit comparison is performed starting with the second-lowest bit. Therefore, the capacitors of the most significant bit and the second-highest bit need to be disconnected from the DAC capacitor array. In other cases, the capacitor of the least significant bit may be used as the starting bit. In this case, multiple switching switches need to be set in the DAC capacitor array of the SAR ADC to meet the requirement of being able to disconnect multiple binary weight bit capacitors from the DAC capacitor array.

[0181] One possible implementation is as shown in the figure above. Figure 19 As shown, the first plate of each capacitor is connected to the common terminal of the capacitor array via a switching switch. When it is necessary to skip a certain capacitor, the switching switch connected to its first plate is disconnected, and its second plate is grounded.

[0182] Another connection method is also provided here. In the DAC capacitor array, the first plate of the least significant capacitor C0 is connected to the common terminal Vx of the DAC capacitor array, and a switching switch is set between the first plates of any two adjacent capacitors between the most significant capacitor C3 and the second least significant capacitor C0.

[0183] like Figure 23 As shown, the first plate of the highest capacitor C3 is connected to the first plate of the second highest capacitor C2 through a switching switch Sk1; the first plate of the second highest capacitor C2 is connected to the first plate of the second lowest capacitor C1 through a switching switch Sk2; the first plate of the second lowest capacitor C1 is connected to the first plate of the lowest capacitor C0 through a switching switch Sk3; and the first plates of the lowest capacitor C0 and the redundant capacitor Cc are connected to the common terminal Vx.

[0184] When the decoder adjusts the start bit from the most significant bit to the preset bit, the switch controlling the switching between the most significant bit capacitor C3 and the preset bit capacitor is disconnected, and the second plate of the skipped capacitor is grounded. This completely disconnects it from the DAC capacitor array, preventing it from participating in the bit-by-bit comparison process.

[0185] Continuing with the example above, in a 4-bit SAR ADC, after the sampling and holding phase, we take the second-lowest bit as the starting bit for bit-by-bit comparison. If we take the second-lowest bit as the starting bit for bit-by-bit comparison, then we need to disconnect the first plate of the highest bit capacitor C3 and the second-highest bit capacitor C2 from the common terminal Vx of the DAC capacitor array, and ground the second plate of the highest bit and the second-highest bit capacitors.

[0186] After sampling and holding, in the bit-by-bit comparison phase, the capacitor of the second-lowest bit is charged and compared, starting with the second-lowest bit. This comparison is similar to the third comparison after confirming that bits b1 and b2 are 0. Figure 23As shown, after the sampling and holding phases, the voltage of the upper plate in the DAC capacitor array is -Vin, and the total charge stored in the DAC capacitor array is -Vin·16C.

[0187] When skipping the highest-order capacitor C3 and the second-highest-order capacitor C2, and using the second-lowest-order capacitor C1 as the starting bit for bit-by-bit comparison, since the first plate of the highest-order capacitor C3 and the second-highest-order capacitor C2 is disconnected from the common terminal Vx of the DAC capacitor array and the second plate is grounded, the highest-order capacitor C3 and the second-lowest-order capacitor C2 do not participate in the comparison.

[0188] Applying charge conservation to the capacitor array, we have:

[0189] -Vin·16C=Vx·2C+(Vx-Vref)·2C

[0190] In the equation, -Vin·16C on the left side of the equation refers to the total charge stored in the capacitor array after sampling and holding, Vx is the voltage at the inverting terminal of the comparator (i.e., the common terminal of the capacitor array), and (Vx-Vref)·2C on the right side of the equation is the charge stored in the second lowest bit (starting bit) capacitor C1, and Vx·2C is the charge stored in the other capacitors in the capacitor array (the lowest bit capacitor C0 and the redundant capacitor Cc). Simplifying the above equation, we get:

[0191] Vx = -1 / 4Vin + Vref / 2

[0192] The voltage at the common terminal, which is also the inverting input of the comparator, is -1 / 4Vin + Vref / 2. If Vx < 0, the comparator outputs a high level (1), indicating that -1 / 4Vin + Vref / 2 < 0, meaning Vin is greater than Vref / 8. Sb3 remains closed. b3 = 1 is sent to the register for storage, and the lower plate of the second-lowest capacitor C1 remains unchanged. If Vx > 0, the comparator outputs a low level (0), indicating that -1 / 4Vin + Vref / 2 > 0, meaning Vin is less than Vref / 8. Sb3 is changed from being connected to Vref to being grounded, b3 = 0 is sent to the register for storage, and the lower plate of the second-lowest capacitor C1 is grounded.

[0193] Since the highest-order capacitor C3 and the second-highest-order capacitor C2 are skipped, and the second-lowest-order capacitor C1 is used as the starting bit for comparison, then the highest-order bit b1 = 0 and the second-highest-order bit b2 = 0. After determining the value of the second-lowest-order bit b3, subsequent bit-by-bit comparisons are performed sequentially until the quantized value of the lowest-order bit b4 is determined, and the quantized digital signal of the multiplication-addition result is output.

[0194] As can be seen from the above, when the summation result of the adder circuit is 0010≤a<0100, setting the starting bit of the DAC capacitor array of the 4-bit SAR ADC in the bit-by-bit comparison stage to the second-lowest bit results in the same digital signal output as the digital signal output with the highest bit as the starting bit, without compromising output accuracy. With the second-lowest bit as the starting bit, the values ​​of the highest and second-highest bits are defaulted to 0. Analog-to-digital conversion can be completed with only 2 comparisons, eliminating the need to charge and discharge the highest bit capacitor C3 and the second-highest bit capacitor C2, which can reduce power consumption, reduce the number of comparisons, and shorten the time required for analog-to-digital conversion.

[0195] The decoder needs to compare the sum of the addition tree with a preset threshold value to determine whether the sum is greater than, equal to or less than a certain preset threshold value. The following is a specific implementation method.

[0196] For example, taking a SAR ADC with a bit width of 5 as an example, the preset threshold value here can be set sequentially to 10000(2). 4 ), 01000(2 3 ), 00100(2 2 ), 00010(2 1 The preset threshold value can be set by shifting each 1-bit bit to the right by one bit.

[0197] When comparing the summation result with the preset threshold value, the bit width of the summation result should be padded first. For example, if the bit width of SARADC is 5 and the preset threshold values ​​are 10000, 01000, 00100, and 00010, then the summation result should be padded to five bits. If it is less than five bits, 0s can be added to make up the difference. For example, if the summation result is 1011, it can be padded to 01011.

[0198] For example, see Figure 24 When comparing the summation result with 10000, first determine whether the bit corresponding to the 1 bit of the preset threshold value is 1. For example, if the summation result is 01011, then the bit corresponding to the 1 bit of the threshold value is the highest bit. Here, the highest bit of 01011 is 0, so it can be determined that the summation result is less than the threshold value. Then, shift the 1 bit of the preset threshold value one bit to the right and compare again.

[0199] After shifting 1 bit to the right by one bit, the summation result 01011 is compared with the preset threshold value 01000. Here, the 1 bit of the preset threshold value is the second bit, so the position corresponding to the 1 bit of the threshold value is the second bit. Here, the second bit of 01011 is 1. When the 1 bit is 1, it is determined whether the sum of all bits to the right of the 1 bit is greater than or equal to 0. If it is greater than 0, the output is greater than; if it is equal to 0, the output is equal.

[0200] For example, if 01011 is compared with the preset threshold value 01000, and the bit corresponding to the first bit (i.e., the second bit) of the threshold value is 1, then it is determined whether each bit to the right of the first bit of the summation result is greater than or equal to 0. Here, the bits to the right of the first bit of the summation result are 0, 1, and 1 respectively, and their sum is greater than 0. Therefore, the output result is that the summation result is less than 10000 and greater than 01000.

[0201] If the summation result is 01000, it is compared with the threshold value 01000. The bit corresponding to the first bit (i.e., the second bit) of the threshold value is 1. Then, it is determined whether each bit to the right of the first bit of the summation result is greater than or equal to 0. Here, the bits to the right of the first bit of the summation result are 0, 0, and 0, and their sum is equal to 0. Therefore, the output result is that the summation result is equal to 01000.

[0202] The decoder outputs a decoded value based on the comparison result of the summation result and a preset threshold value. The decoded value is used to control the start bit of the SAR ADC during the bit-by-bit comparison stage. Here, the decoder uses the decoded value to control the on / off state of the switches connected to the first plates of each capacitor in the capacitor array of the SAR ADC. For example, in a 5-bit SAR ADC, the first plates from the most significant bit capacitor C4 to the least significant bit capacitor C0 are connected to the common terminal Vx of the DAC capacitor array through switches Sk1, Sk2, Sk3, Sk4, and Sk5, respectively. The decoded value can then be used to control the on / off state of these five switches, thereby adjusting the start bit capacitor of the SAR ADC during the bit-by-bit comparison stage.

[0203] Table 1

[0204] 10000 00000 01000 10000 00100 11000 00010 11100

[0205] For example, referring to Table 1, if the summation result is greater than 10000, then the output decoded value is 00000, that is, Sk1 to Sk5 are all closed in the bit-by-bit comparison stage, and the highest bit is used as the starting bit for bit-by-bit comparison.

[0206] If the summation result is greater than 01000, then the output decoded value is 10000. That is, during the bit-by-bit comparison stage, Sk1 is opened and Sk2 to Sk5 are all closed, and the second highest bit is used as the starting bit for bit-by-bit comparison.

[0207] If the summation result is greater than 00100, then the output decoded value is 11000. That is, during the bit-by-bit comparison stage, Sk1 and Sk2 are disconnected, while Sk3 to Sk5 are all closed, and the third capacitor is used as the starting bit for bit-by-bit comparison.

[0208] If the summation result is greater than 00010, then the output decoded value is 11100. That is, during the bit-by-bit comparison stage, Sk1, Sk2, and Sk3 are disconnected, while Sk4 to Sk5 are all closed, and the fourth capacitor is used as the starting bit for bit-by-bit comparison.

[0209] The decoder can also send the decoded value to the SAR logic. The SAR logic can then determine the start bit of the capacitor in the bit-by-bit comparison stage based on the decoded value. For example, if the output decoded value is 11100, the 5-bit SAR ADC will use the fourth capacitor as the start bit of the bit-by-bit comparison stage, without charging the first three capacitors, and disconnecting these three capacitors from the common terminal Vx of the DAC capacitor array. This reduces the conversion power consumption and conversion time without affecting the accuracy of the SAR ADC output comparison result.

[0210] This application also provides an electronic device, such as... Figure 25 As shown, the electronic device includes a circuit board and a memory, processor, etc., electrically connected to the circuit board. The memory is the in-memory computing memory provided in the foregoing embodiments of this application. The in-memory computing memory includes a storage area and a computing circuit. The storage area includes multiple storage units, which can be used to store data. The processor can read data from or write data to the memory. The computing circuit in the memory can perform operations on the data stored in the storage area, such as multiplication and addition operations. The computing circuit can send the operation results to the processor. This can improve the memory wall and power consumption wall caused by the speed mismatch between the memory and the processor.

[0211] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A multiply-accumulate operation circuit, characterized in that, include: At least one multiply-accumulate operation unit, the multiply-accumulate operation unit including a successive approximation analog-to-digital converter (SAR ADC), a bit width control circuit, a summation bus, and multiple multiplication circuits; Multiple multiplication circuits are connected to the input signal terminal of the SAR ADC via the summation bus; The multiplication circuit is used to multiply a single bit of input data with a single bit of weight data to obtain an analog product; wherein, the input data includes image data processed by computer vision, and the sparsity of the input data is greater than the sparsity of the weight data; The summation bus adds up the multiplying results from the outputs of the multiple multiplication circuits and transmits the result to the SARADC. The SARADC is used to perform analog-to-digital conversion on the result. The SAR ADC includes a digital-to-analog converter (DAC) capacitor array. The bit width control circuit is connected to the SAR ADC. The bit width control circuit is used to sum the single-bit input data of multiple multiplication circuits connected to the same summation bus, and control the start bit of the capacitors in the DAC capacitor array during the bit-by-bit comparison stage according to the summation result. The bit width control circuit includes an adder circuit and a decoder. The adder circuit is used to sum the single-bit input data of multiple multiplication circuits; The decoder compares the summation result with a preset threshold value, thereby adjusting the start bit from the highest bit to the preset position. The preset threshold value is set by shifting 1 bit to the right one bit at a time. When the summation result a satisfies: 2 m-1 ≤a<2 m At that time, the decoder determines that the preset bit is nm bits lower than the highest bit, where m and n are positive integers, n is the bit width of the SAR ADC, and m < n.

2. The multiply-accumulate circuit according to claim 1, characterized in that, The SAR ADC includes a comparator, the DAC capacitor array includes a common terminal, the first plate of the capacitor in the DAC capacitor array is connected to the common terminal, and the common terminal is connected to the first input terminal of the comparator. The second plate of the capacitor in the DAC capacitor array is used to connect to the input signal terminal or the reference signal terminal of the SAR ADC; When the decoder adjusts the start bit from the highest bit to the preset bit, it controls the first plate of the capacitor preceding the preset bit in the DAC capacitor array to disconnect from the common terminal and the second plate to disconnect from the input signal terminal and the reference signal terminal.

3. The multiply-accumulate circuit according to claim 2, characterized in that, The SAR ADC includes at least one switching switch; The first plates of the highest-position capacitor to the capacitor preceding the preset position are respectively connected to the common terminal through the switching switch; When the decoder adjusts the start bit from the highest bit to the preset bit, it controls the switching switch to turn off.

4. The multiply-accumulate circuit according to claim 2, characterized in that, The SAR ADC includes at least one switching switch; In the capacitor array, the first plate of the lowest-position capacitor is connected to the common terminal, and a switching switch is provided between the first plates of any two adjacent capacitors between the highest-position capacitor and the second-lowest-position capacitor. When the decoder adjusts the start bit from the highest bit to the preset bit, the switching switch between the highest bit capacitor and the preset bit capacitor is disconnected.

5. The multiply-accumulate circuit according to claim 2, characterized in that, The SAR ADC also includes multiple selection switches. The second plate of each capacitor in the DAC capacitor array is connected to a selection switch. The selection switch is used to connect the second plate to the input signal terminal, the reference signal terminal, or ground. When the decoder adjusts the start bit from the highest bit to the preset bit, it controls the selection switch to ground the first plate of the highest bit capacitor in the DAC capacitor array to the previous bit capacitor of the preset bit.

6. The multiply-accumulate circuit according to claim 1, characterized in that, The multiplication circuit includes a multiplier and a capacitor; The output of the multiplier is connected to one side of the capacitor, and the other side of the capacitor is connected to the summation bus.

7. A memory, characterized in that, The memory includes a storage area and a multiply-accumulate operation circuit as described in any one of claims 1 to 6; the storage area includes a plurality of storage units, and the multiply-accumulate operation circuit is used to perform multiply-accumulate operations on the data stored in the storage units.

8. An electronic device, characterized in that, The electronic device includes a circuit board and a memory electrically connected to the circuit board, wherein the memory is the memory as described in claim 7.

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