Method, device, storage medium and electronic device for manufacturing multilayer circuit board

Abstract

The embodiment of the application provides a kind of multilayer circuit board preparation method and device, storage medium and electronic device, wherein the multilayer circuit board preparation method comprises: obtaining the first absolute time sent by terminal equipment corresponding to real-time operating system, and the first relative time of the real-time operating system, wherein the first relative time is used to indicate the time when the real-time operating system receives the first absolute time;According to the first relative time and the first absolute time, the target reference time of the real-time operating system is determined;In the case where the query request for querying the absolute time of real-time operating system is received, the second relative time of the real-time operating system is obtained, and the second absolute time of the real-time operating system is determined according to the target reference time and the second relative time, wherein the second relative time is used to indicate the time when the real-time operating system receives the query request.

Description

Technical Field

[0001] This application relates to the field of communications, and more specifically, to a method, apparatus, storage medium, and electronic device for fabricating a multilayer circuit board. Background Technology

[0002] Servers are extremely complex systems composed of a large number of computing, storage, and management chips, requiring circuit boards (PCBs) to support and connect the numerous functional modules.

[0003] With the development of cloud computing applications, information technology is gradually covering all aspects of society. People are increasingly communicating through the internet in their daily work and life, and the amount of network data is constantly increasing, placing higher demands on server performance.

[0004] However, as signal speeds increase exponentially and chip computing speeds grow year-on-year, power consumption also increases accordingly. But server chassis structures cannot be expanded blindly; they must meet industry standards. Therefore, the internal space of the server chassis is limited. The PCB board area doesn't increase, but the ever-increasing number of electronic components and connectors must be neatly arranged on the PCB surface, simultaneously increasing the number of interconnections between electronic modules.

[0005] To ensure that these newly added interconnect designs are on the PCB, the area of ​​the PCB traces needs to be expanded, that is, by increasing the number of PCB layers to expand the area available for traces. However, in the process of increasing the number of PCB layers, the influence of PCB layer offset will bring difficulties to the manufacturing process.

[0006] The problem that the increasing layer offset of each layer in high-layer PCBs makes the fabrication of high-layer PCBs difficult has not been effectively solved in existing technologies. Summary of the Invention

[0007] This application provides a method, apparatus, storage medium, and electronic device for fabricating multilayer circuit boards, which at least solves the problem in the related art that the continuous increase in the layer offset of each layer in a high-layer PCB board leads to difficulties in fabricating high-layer PCB boards.

[0008] According to one embodiment of this application, a method for fabricating a multilayer circuit board is provided, comprising: determining N groups of circuit boards corresponding to a plurality of circuit boards, wherein the N groups of circuit boards are N groups of circuit boards evenly divided according to a preset rule, each of the plurality of circuit boards includes a pattern, the number of patterns on the plurality of circuit boards and the position of the patterns on the circuit boards are the same, the number of patterns is N, and N is a positive integer; pressing each group of circuit boards in the N groups of circuit boards to obtain N pressed first multilayer circuit boards; splicing the patterns at the same position in the N first multilayer circuit boards to form N spliced ​​second multilayer circuit boards; and soldering N second multilayer circuit boards to fabricate a multilayer circuit board.

[0009] In one exemplary embodiment, determining N groups of circuit boards corresponding to a plurality of circuit boards includes: determining the thickness of the dielectric layer of each of the plurality of circuit boards; and determining an allowable range of dielectric layer thickness for each group of circuit boards in the N groups of circuit boards; and determining the N groups of circuit boards corresponding to the plurality of circuit boards based on the dielectric layer thickness of each of the circuit boards and the allowable range of thickness.

[0010] In one exemplary embodiment, before each of the N sets of circuit boards is pressed together, the method further includes: cleaning each set of circuit boards using a target tool; rinsing each set of circuit boards after cleaning; and heating each set of circuit boards after rinsing to dry them.

[0011] In one exemplary embodiment, pressing each of the N groups of circuit boards separately includes: obtaining the size of each of the N groups of circuit boards; adjusting the pressing parameters used by the pressing assembly when pressing each of the N groups of circuit boards according to the size of each of the N groups of circuit boards; wherein the pressing parameters include: pressing time, the size of the pressing head of the pressing assembly; and controlling the pressing assembly to press each of the N groups of circuit boards separately according to the parameters corresponding to the size of each of the N groups of circuit boards.

[0012] In an exemplary embodiment, splicing patterns at the same positions in N first multilayer circuit boards to form N spliced ​​second multilayer circuit boards includes: for the N first multilayer circuit boards, numbering the N patterns in each first multilayer circuit board in the same order; for each numbered first multilayer circuit board, trimming according to the border of the pattern on each first multilayer circuit board to determine a plurality of numbered multilayer circuit boards corresponding to each first multilayer circuit board, wherein the first multilayer circuit board includes a plurality of multilayer circuit boards; determining a plurality of multilayer circuit boards with the same number from the plurality of multilayer circuit boards corresponding to the N first multilayer circuit boards; obtaining the wire layouts corresponding to the plurality of multilayer circuit boards with the same number; determining the splicing order of the plurality of multilayer circuit boards with the same number according to the wire layouts corresponding to the multilayer circuit boards; and splicing the plurality of multilayer circuit boards with the same number according to the splicing order to form N spliced ​​second multilayer circuit boards.

[0013] In an exemplary embodiment, after splicing patterns at the same positions in N first multilayer circuit boards to form N spliced ​​second multilayer circuit boards, the method further includes: performing reliability tests on the N spliced ​​second multilayer circuit boards respectively; providing feedback on information of the second multilayer circuit boards that failed the reliability test; and repairing the second multilayer circuit boards that failed the reliability test based on the information.

[0014] In one exemplary embodiment, soldering N second multilayer circuit boards to fabricate a multilayer circuit board includes: determining a plurality of through-holes in each of the N second multilayer circuit boards; determining a plurality of solder points in each second multilayer circuit board based on the plurality of through-holes; and soldering the N second multilayer circuit boards based on the plurality of solder points to fabricate the multilayer circuit board.

[0015] According to another embodiment of this application, a fabrication apparatus for a multilayer circuit board is provided, comprising: a determining module for determining N groups of circuit boards corresponding to a plurality of circuit boards, wherein the N groups of circuit boards are N groups of circuit boards evenly divided according to a preset rule, each of the plurality of circuit boards includes a pattern, the number of patterns on the plurality of circuit boards and the position of the patterns on the circuit boards are the same, the number of patterns is N, and N is a positive integer; a pressing module for pressing each group of circuit boards in the N groups of circuit boards to obtain N pressed first multilayer circuit boards; a splicing module for splicing the patterns at the same position in the N first multilayer circuit boards to form N spliced ​​second multilayer circuit boards; and a welding module for welding the N second multilayer circuit boards to fabricate a multilayer circuit board.

[0016] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0017] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0018] This application addresses the problem in related technologies where multiple circuit boards are divided into N groups, each with a pattern, and all circuit boards have N patterns positioned identically. The N groups of circuit boards are then laminated to obtain N laminated first multilayer circuit boards. Patterns at the same position in these N laminated first multilayer circuit boards are then joined to form a joined second multilayer circuit board. These second multilayer circuit boards are then soldered to fabricate a multilayer circuit board. This solution overcomes the difficulty in fabricating high-layer PCBs caused by the continuously increasing layer offset in high-layer PCBs. Attached Figure Description

[0019] Figure 1 This is a hardware structure block diagram of a PCB board processing equipment for a method of fabricating a multilayer circuit board according to an embodiment of this application.

[0020] Figure 2 This is a flowchart of a method for fabricating a multilayer circuit board according to an embodiment of this application;

[0021] Figure 3 This is a diagram (a) illustrating the PCB board lamination process according to an exemplary embodiment of this application;

[0022] Figure 4 This is a PCB board lamination process diagram (II) according to an exemplary embodiment of this application;

[0023] Figure 5 This is a PCB board lamination process diagram (III) according to an exemplary embodiment of this application;

[0024] Figure 6 This is a PCB board splicing diagram according to an exemplary embodiment of this application;

[0025] Figure 7 This is a schematic diagram of segmented control of a PCB board according to an exemplary embodiment of this application;

[0026] Figure 8 This is a schematic diagram illustrating the splicing of various segmented graphics according to an exemplary embodiment of this application;

[0027] Figure 9 This is a schematic diagram of the connection between segments according to an exemplary embodiment of this application;

[0028] Figure 10 This is a structural block diagram of a multilayer circuit board fabrication apparatus according to an embodiment of this application. Detailed Implementation

[0029] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0031] The methods and embodiments provided in this application can be executed in PCB board processing equipment or similar processing apparatus. Taking a PCB board processing equipment as an example, Figure 1 This is a hardware structure block diagram of a PCB board processing equipment according to an embodiment of the present application for a method of fabricating a multilayer circuit board. For example... Figure 1 As shown, PCB board processing equipment may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The PCB fabrication equipment may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the PCB board processing equipment described above. For example, the PCB board processing equipment may also include... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0032] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the method for fabricating a multilayer circuit board in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the aforementioned method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to server devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0033] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the server device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0034] This embodiment provides a method for fabricating a multilayer circuit board. Figure 2 This is a flowchart of a method for fabricating a multilayer circuit board according to an embodiment of this application, applied to the aforementioned PCB board processing equipment, such as... Figure 2 As shown, the process includes the following steps:

[0035] Step S202: Determine N groups of circuit boards corresponding to multiple circuit boards, wherein the N groups of circuit boards are N groups of circuit boards that are evenly divided according to a preset rule, each of the multiple circuit boards includes a pattern, the number of patterns set on the multiple circuit boards and the position of the patterns on the circuit boards are the same, and the number of patterns is N, where N is a positive integer;

[0036] With the above technical solution, since the raw material size of the PCB board (equivalent to the above circuit board) used in the actual factory is several times larger than that of the pre-designed PCB board, multiple pre-designed PCB boards can be spliced ​​together for processing to form multiple circuit boards used in the actual factory.

[0037] Each of the multiple circuit boards contains N patterns. Each of the N patterns in each of the multiple circuit boards can be copied multiple times from one of the patterns to obtain N patterns. In other words, the N patterns in each of the multiple circuit boards can be the same, and the patterns corresponding to each of the multiple circuit boards can be different.

[0038] Step S204: Press each of the N sets of circuit boards together to obtain N pressed first multilayer circuit boards.

[0039] Step S206: The patterns at the same position in N first multilayer circuit boards are spliced ​​together to form N spliced ​​second multilayer circuit boards.

[0040] Step S208: Solder N second multilayer circuit boards to prepare a multilayer circuit board.

[0041] Through the above steps, multiple circuit boards are divided into N groups, each of which has a pattern. Each group of circuit boards has N patterns, and the patterns are positioned identically on the boards. The N groups of circuit boards are then laminated to obtain N laminated first multilayer circuit boards. Patterns in the same position from these N laminated first multilayer circuit boards are then joined to form a joined second multilayer circuit board. This second multilayer circuit board is then soldered to fabricate a multilayer circuit board. This process solves the problem in related technologies where the layer offset of each layer in a high-layer PCB increases continuously, leading to difficulties in fabricating high-layer PCBs.

[0042] Optionally, step S202 may further include: determining N groups of circuit boards corresponding to the plurality of circuit boards, including: determining the thickness of the dielectric layer of each of the plurality of circuit boards; and determining the allowable range of the dielectric layer thickness of each group of circuit boards in the N groups of circuit boards; and determining the N groups of circuit boards corresponding to the plurality of circuit boards based on the thickness of the dielectric layer of each of the circuit boards and the allowable range of the thickness.

[0043] It is understandable that multiple circuit boards can be grouped based on the thickness of the dielectric layer of each circuit board in the multiple circuit boards. Specifically, before grouping, the range of dielectric layer thickness in each group in the preset group is determined, and the multiple circuit boards are grouped based on the range of dielectric layer thickness in each group in the preset group and the thickness of the dielectric layer of each circuit board in the multiple circuit boards.

[0044] In other words, the sum of the thicknesses of the dielectric layers of each of the N groups of circuit boards must be within the allowable range of the dielectric layer thicknesses of each group in the preset grouping.

[0045] For example, if 40 circuit boards are divided into 4 groups, and the allowable range of dielectric layer thickness for each group of circuit boards is 13mm to 16mm, then each group has 10 circuit boards, and the sum of the dielectric layer thicknesses of the 10 circuit boards in each group needs to be between 13mm and 16mm.

[0046] In this case, if the sum of the dielectric layer thicknesses of the 10 circuit boards in each group needs to be between 13mm and 16mm, the sum of the dielectric layer thicknesses of the 10 circuit boards in each group can be controlled to make the sum of the dielectric layer thicknesses of the 10 circuit boards in each group similar, thereby improving the uniform conduction of heat and improving the subsequent pressing quality.

[0047] Optionally, before pressing each of the N sets of circuit boards together, the method further includes: cleaning each set of circuit boards using a target tool; rinsing each set of circuit boards after cleaning; and heating each set of circuit boards after rinsing to dry them.

[0048] Before each of the N sets of circuit boards is laminated, each set of circuit boards needs to be cleaned to ensure that the surface of the circuit board is clean, thereby ensuring that the normal operation of the circuit board is not affected.

[0049] After cleaning each set of circuit boards individually, each set of circuit boards that requires rinsing is rinsed to remove dust, dirt, grease, and other impurities from the surface. Furthermore, each rinsed set of circuit boards is heated to dry it.

[0050] When heating the circuit board, it is important to heat it evenly and avoid excessively rapid temperature changes or excessively high temperatures to prevent damage to the circuit board.

[0051] Optionally, each of the N groups of circuit boards is pressed together separately, including: obtaining the size of each of the N groups of circuit boards; adjusting the pressing parameters used by the pressing assembly when pressing each of the N groups of circuit boards according to the size of each of the N groups of circuit boards; wherein the pressing parameters include: pressing time, the size of the pressing head of the pressing assembly; and controlling the pressing assembly to press each of the N groups of circuit boards separately according to the parameters corresponding to the size of each of the N groups of circuit boards.

[0052] Each set of circuit boards is pressed together using a pressing assembly. Since the dimensions of each set of circuit boards may differ, the dimensions of each set must be determined separately, and the pressing parameters of the pressing assembly adjusted accordingly. Specifically, the size of the pressing head and the pressing time of the pressing assembly must be determined separately for each set of circuit boards.

[0053] Furthermore, each group of circuit boards is pressed according to the pressing parameters corresponding to each group of circuit boards in the pressing assembly determined above.

[0054] By adjusting the pressing parameters in the pressing device, uneven pressing or over-pressing can be avoided, ensuring that the pressing of each circuit board achieves the expected results.

[0055] Optionally, the patterns at the same positions in N first multilayer circuit boards are spliced ​​together to form N spliced ​​second multilayer circuit boards, including: for the N first multilayer circuit boards, numbering the N patterns in each first multilayer circuit board in the same order; for each numbered first multilayer circuit board, cutting according to the border of the pattern on each first multilayer circuit board to determine multiple numbered multilayer circuit boards corresponding to each first multilayer circuit board, wherein the first multilayer circuit board includes multiple multilayer circuit boards; determining multiple multilayer circuit boards with the same number from the multiple multilayer circuit boards corresponding to the N first multilayer circuit boards; obtaining the wire layout corresponding to each of the multiple multilayer circuit boards with the same number; determining the splicing order of the multiple multilayer circuit boards with the same number according to the wire layout corresponding to each of the multilayer circuit boards; and splicing the multiple multilayer circuit boards with the same number according to the splicing order to form N spliced ​​second multilayer circuit boards.

[0056] Understandable Figure 6 This is a PCB board splicing diagram according to an exemplary embodiment of this application, such as... Figure 6 As shown, Figure 6 Displaying only the pattern from one first-layer circuit board allows for the numbering of patterns in each first-layer circuit board in the same order, meaning that the patterns in each first-layer circuit board can be displayed in the same order. Figure 6 The L1 in the upper left corner is numbered 1, which can be used to identify each first multilayer circuit board in... Figure 6 The pattern in the upper right corner is numbered 2; this can be used to designate each first multilayer circuit board in... Figure 6 The pattern in the lower left corner is numbered 3; this can be used to designate each first multilayer circuit board in... Figure 6The patterns in the lower right corner are all numbered 4. After cutting the pattern on each first multilayer circuit board into multiple multilayer circuit boards according to the border, the patterns at the same position in N first multilayer circuit boards can also be determined according to the number. Furthermore, after determining multiple multilayer circuit boards with the same number, the multiple multilayer circuit boards with the same number are spliced ​​together according to the wire layout of the multiple multilayer circuit boards with the same number.

[0057] In other words, there is a specific order to splicing multilayer circuit boards. It's necessary to determine the number of multilayer circuit boards that can be spliced ​​together in a certain sequence. Furthermore, the splicing method and order of these multilayer circuit boards must be determined based on their wiring layout. Only in this way can the splicing of the multilayer circuit boards be completed, forming N spliced ​​second multilayer circuit boards.

[0058] Furthermore, by splicing the first multilayer circuit board after lamination to form N second multilayer circuit boards, the consistency of the layer offset of the circuit boards can be ensured.

[0059] Optionally, after splicing the patterns at the same positions in N first multilayer circuit boards to form N spliced ​​second multilayer circuit boards, the method further includes: performing reliability tests on the N spliced ​​second multilayer circuit boards respectively; providing feedback on the second multilayer circuit boards that failed the reliability test; and repairing the second multilayer circuit boards that failed the reliability test based on the information.

[0060] Understandably, after splicing the patterns at the same positions in N first multilayer circuit boards to obtain a second multilayer circuit board, it is necessary to conduct a reliability test on the second multilayer circuit board in order to effectively evaluate and verify its reliability and improve its reliability and durability during use.

[0061] Optionally, soldering N second multilayer circuit boards to fabricate a multilayer circuit board includes: determining a plurality of through-holes in each of the N second multilayer circuit boards; determining a plurality of solder points in each second multilayer circuit board based on the plurality of through-holes; and soldering the N second multilayer circuit boards based on the plurality of solder points to fabricate the multilayer circuit board.

[0062] The above solution only requires soldering N second-layer circuit boards, reducing drilling difficulty and thus significantly reducing the number of vias on multiple circuit boards, improving drilling efficiency and increasing trace area.

[0063] To better understand the process of the above-mentioned fabrication method of multilayer circuit boards, the implementation flow of the above-mentioned fabrication method of multilayer circuit boards will be described below in conjunction with optional embodiments, but this is not intended to limit the technical solution of the embodiments of this application.

[0064] This application provides an exemplary embodiment of a method for reducing layer misalignment in a multilayer PCB. Before defining the method for reducing layer misalignment in a multilayer PCB, it is necessary to understand the PCB lamination process. Figure 3 This is a diagram (a) illustrating the PCB board lamination process according to an exemplary embodiment of this application. Figure 4 This is a second diagram illustrating the PCB board lamination process according to an exemplary embodiment of this application. Figure 5 This is a PCB board lamination process diagram (III) according to an exemplary embodiment of this application, as shown below. Figure 3 , 4 As shown in Figure 5:

[0065] A PCB board consists of two parts: copper foil and dielectric (equivalent to the dielectric layer mentioned above). The dielectric is an insulator. The internal traces and external boundaries of the PCB board are as follows... Figure 4 As shown.

[0066] like Figure 5 As shown, in multiple Figure 3 , 4 During the PCB lamination process described, multiple dielectric materials and copper foils are pressed together, with the dielectric materials and copper foils in close contact to complete the lamination of the PCB board.

[0067] The exemplary embodiment of this application solves the problem that using through holes to achieve interconnection between layers on a 10-layer PCB board, i.e., the interconnect holes between every two layers only occupy the trace space of the other 8 layers, and in general, the number of vias on each segment of the PCB board is reduced by about 4 times compared to the processing method of a 40-layer board, thereby increasing the trace area.

[0068] Based on the above analysis, the main causes of layer misalignment during PCB lamination can be identified as follows:

[0069] 1. Causes of inner layer misalignment: The inner layer is mainly the process of transferring the pattern from the film to the inner layer core board. Therefore, inner layer misalignment will only occur during the pattern transfer production process. The main causes of misalignment may be inconsistent expansion and contraction of the inner layer film, misalignment of the exposure machine, improper operation by personnel during the alignment and exposure process, etc.

[0070] The expansion and contraction of the various layers inside the PCB board occurs in three stages: from the process of cutting the material to baking the board; during the process of pattern transfer; and during the process of lamination.

[0071] 2. Reasons for PCB lamination layer misalignment: This may be due to factors such as inconsistent expansion and contraction of the core layers, poor punching of positioning holes, fusion misalignment, and slippage during lamination. These factors result in PCBs typically having 2 to 18 layers. PCBs with more than 18 layers may have a high scrap rate or be unprocessable due to layer misalignment.

[0072] Because each layer expands and contracts differently, their combined expansion and contraction can cause excessive layer misalignment, making it impossible to process boards with multiple layers. Therefore, it is necessary to address the issue of the continuous accumulation of expansion and contraction values ​​across layers during PCB manufacturing and to maintain a consistent processing environment for all layers of the PCB.

[0073] In existing technologies, PCB layer misalignment is mainly reduced through two methods:

[0074] The first method involves adding a set of concentric circles at each of the four corners of the production board. The distance between the concentric circles is set according to the layer offset requirements of the production board. During the production process, the offset of the concentric circles is checked by an X-ray inspection machine (also known as an X-ray inspection machine) or an X-ray drilling machine to confirm the layer offset and determine whether the board is a good product.

[0075] The second method involves creating target holes on both the long and short sides of the multilayer PCB board, measuring the expansion and contraction values ​​between each layer, and adjusting the inner layer compensation coefficient of the PCB board based on these values. This inner layer compensation coefficient can adjust the layer misalignment of the multilayer PCB board, thereby reducing the layer misalignment and preventing the board from being scrapped due to expansion and contraction between the core boards.

[0076] The two methods mentioned above can reduce the layer misalignment of PCB boards, but they cannot solve the problem of the continuous accumulation of expansion and contraction values ​​of each layer during PCB board manufacturing.

[0077] The exemplary embodiments of this application employ a method of segmenting and simultaneously processing the PCB board to ensure that the layer offset of a high-layer PCB board is within the normal range. The method will now be described using a 40-layer PCB board as an example.

[0078] 1) Four graphics are pieced together on a single raw material;

[0079] Figure 6 This is a PCB board splicing diagram according to an exemplary embodiment of this application, such as... Figure 6 As shown:

[0080] Since the raw materials used in the factory are several times larger than the designed PCB boards, the PCB boards are usually spliced ​​together for processing. Four L1 layer patterns can be made on a single raw material (equivalent to each of the multiple circuit boards mentioned above), and similarly, L2, L3, and so on can be made to form 40 PCB boards.

[0081] 2) Divide the 40-layer PCB into four 10-layer PCBs, that is, segment and control the 40 PCBs and laminate them together;

[0082] Figure 7 This is a schematic diagram of segmented control of a PCB board according to an exemplary embodiment of this application, such as... Figure 7 As shown:

[0083] By segmenting and controlling the layer offset, the layer offset value cannot be continuously accumulated. That is, the 40-layer pattern is divided into 4 groups in sequence, and the layer offset value of the 10-layer PCB board is about 1 / 4 of that of the 40-layer board.

[0084] 3) Splice the L1 layer of each segment PCB onto the raw material, and press the L1 to L10 layers together to obtain 4 segment PCBs, that is, splice the graphics of each segment.

[0085] Figure 8 This is a schematic diagram illustrating the splicing of various segmented graphics according to an exemplary embodiment of this application, such as... Figure 8 As shown:

[0086] Will Figure 7 One of the patterns from L1 layer of segment A, L1 layer of segment B, L1 layer of segment C, and L1 layer of segment D is spliced ​​onto a single raw material, and layers L2, L3...L10 are made sequentially. Through the above technical solution, four segments consisting of 10 layers of raw material, each with 4 patterns, can be formed. By pressing the 10 layers of raw material from the four segments together, four PCB boards A, B, C, and D can be obtained, thus ensuring the consistency of layer offset in each segment.

[0087] 4) Solder the contact points of the four PCB segments with solder and fix them with screws through the three fixing holes to connect the segments;

[0088] Figure 9 This is a schematic diagram of the connection between segments according to an exemplary embodiment of this application, such as... Figure 9 As shown:

[0089] Multiple contact points are designed on each PCB segment to connect with other PCB segments. These contact points can be categorized into ABCD connected areas, AB connected areas, AC connected areas, AD connected areas, etc. The specific connected areas are not limited and can be designed according to the actual situation. The contact points between the layers are soldered together, and screws are tightened into the mounting holes to secure the four PCB segments.

[0090] It should be noted that the thickness of the 40-layer board is approximately four times the thickness of each segmented PCB. The deeper the hole is drilled, the more difficult it becomes. Therefore, the segmented PCB board processing method of the exemplary embodiment of this application can also solve the problem of high drilling difficulty.

[0091] The above methods enable the processing of high-layer-count PCBs, resolving the issue of continuously accumulating layer offsets and significantly reducing these offset values. This also significantly reduces the number of vias on segmented PCBs, improving drilling efficiency and increasing trace area. Furthermore, it lowers drilling difficulty and effectively reduces via stub length. These technical solutions improve the yield of high-layer-count PCBs, reduce costs, increase production efficiency, and lower processing difficulty.

[0092] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0093] This embodiment also provides a fabrication apparatus for a multilayer circuit board, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0094] Figure 10 This is a structural block diagram of a multilayer circuit board fabrication apparatus according to an embodiment of this application, such as... Figure 10As shown, the device includes: a determining module 102, used to determine N groups of circuit boards corresponding to multiple circuit boards, wherein the N groups of circuit boards are N groups of circuit boards evenly divided according to a preset rule, each of the multiple circuit boards includes a pattern, the number of patterns on the multiple circuit boards and the position of the patterns on the circuit boards are the same, the number of patterns is N, and N is a positive integer; a pressing module 104, used to press each group of circuit boards in the N groups of circuit boards separately to obtain N pressed first multilayer circuit boards; a splicing module 106, used to splice the patterns at the same position in the N first multilayer circuit boards to form N spliced ​​second multilayer circuit boards; and a welding module 108, used to weld the N second multilayer circuit boards to prepare a multilayer circuit board.

[0095] In an exemplary embodiment, the determining module 102 is further configured to determine the thickness of the dielectric layer of each of the plurality of circuit boards; and to determine the allowable range of the dielectric layer thickness of each group of circuit boards in the N groups of circuit boards; and to determine the N groups of circuit boards corresponding to the plurality of circuit boards based on the thickness of the dielectric layer of each circuit board and the allowable range of the thickness.

[0096] It is understandable that multiple circuit boards can be grouped based on the thickness of the dielectric layer of each circuit board in the multiple circuit boards. Specifically, before grouping, the range of dielectric layer thickness in each group in the preset group is determined, and the multiple circuit boards are grouped based on the range of dielectric layer thickness in each group in the preset group and the thickness of the dielectric layer of each circuit board in the multiple circuit boards.

[0097] In one exemplary embodiment, the apparatus further includes: a cleaning module for cleaning each group of circuit boards using a target tool; rinsing each group of circuit boards after cleaning; and heating each group of circuit boards after rinsing to dry them.

[0098] In other words, the sum of the thicknesses of the dielectric layers of each of the N groups of circuit boards must be within the allowable range of the dielectric layer thicknesses of each group in the preset grouping.

[0099] For example, if 40 circuit boards are divided into 4 groups, and the allowable range of dielectric layer thickness for each group of circuit boards is 13mm to 16mm, then each group has 10 circuit boards, and the sum of the dielectric layer thicknesses of the 10 circuit boards in each group needs to be between 13mm and 16mm.

[0100] In this case, if the sum of the dielectric layer thicknesses of the 10 circuit boards in each group needs to be between 13mm and 16mm, the sum of the dielectric layer thicknesses of the 10 circuit boards in each group can be controlled to make the sum of the dielectric layer thicknesses of the 10 circuit boards in each group similar, thereby improving the uniform conduction of heat and improving the subsequent pressing quality.

[0101] In an exemplary embodiment, the pressing module 104 is further configured to acquire the size of each of the N groups of circuit boards; adjust the parameters corresponding to the size of each of the N groups of circuit boards in the pressing assembly according to the size of each of the N groups of circuit boards, wherein the pressing parameters of the pressing assembly include: pressing time and the size of the pressing head of the pressing assembly; and control the pressing assembly to press each of the N groups of circuit boards according to the parameters corresponding to the size of each of the N groups of circuit boards.

[0102] In an exemplary embodiment, the splicing module 106 is further configured to: number the N patterns in each of the N first multilayer circuit boards in the same order; for each numbered first multilayer circuit board, cut according to the border of the pattern on each first multilayer circuit board to determine a plurality of numbered multilayer circuit boards corresponding to each first multilayer circuit board, wherein the first multilayer circuit board includes a plurality of multilayer circuit boards; determine a plurality of multilayer circuit boards with the same number from the plurality of multilayer circuit boards corresponding to the N first multilayer circuit boards; obtain the wire layout corresponding to each of the plurality of multilayer circuit boards with the same number; determine the splicing order of the plurality of multilayer circuit boards with the same number according to the wire layout corresponding to each of the multilayer circuit boards; and splice the plurality of multilayer circuit boards with the same number according to the splicing order to form N spliced ​​second multilayer circuit boards.

[0103] In one exemplary embodiment, the apparatus further includes: an inspection module, configured to perform reliability inspection on the N spliced ​​second multilayer circuit boards respectively; provide feedback on the second multilayer circuit boards that failed the reliability inspection; and repair the second multilayer circuit boards that failed the reliability inspection based on the information.

[0104] In an exemplary embodiment, the welding module 108 is further configured to determine a plurality of through holes in each of the N second multilayer circuit boards; determine a plurality of welding points in each second multilayer circuit board based on the plurality of through holes; and weld the N second multilayer circuit boards based on the plurality of welding points to fabricate the multilayer circuit board.

[0105] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0106] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0107] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0108] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0109] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0110] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0111] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0112] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a multilayer circuit board, characterized in that, include: N groups of circuit boards are determined corresponding to multiple circuit boards. The N groups of circuit boards are N groups of circuit boards that are evenly divided into the multiple circuit boards according to a preset rule. Each of the multiple circuit boards includes a pattern. The number of patterns on the multiple circuit boards and the position of the patterns on the circuit boards are the same. The number of patterns is N, where N is a positive integer. Each of the N sets of circuit boards is pressed together to obtain N pressed first multilayer circuit boards. The patterns at the same position in N first multilayer circuit boards are spliced ​​together to form N spliced ​​second multilayer circuit boards; N second multilayer circuit boards are soldered together to prepare a multilayer circuit board; The method of splicing patterns at the same position in N first multilayer circuit boards to form N spliced ​​second multilayer circuit boards includes: for the N first multilayer circuit boards, numbering the N patterns in each first multilayer circuit board in the same order; for each numbered first multilayer circuit board, cutting according to the border of the pattern on each first multilayer circuit board to determine multiple numbered multilayer circuit boards corresponding to each first multilayer circuit board, wherein the first multilayer circuit board includes multiple multilayer circuit boards; determining multiple multilayer circuit boards with the same number from the multiple multilayer circuit boards corresponding to the N first multilayer circuit boards; obtaining the wire layout corresponding to each of the multiple multilayer circuit boards with the same number; determining the splicing order of the multiple multilayer circuit boards with the same number according to the wire layout corresponding to each of the multilayer circuit boards; and splicing the multiple multilayer circuit boards with the same number according to the splicing order to form N spliced ​​second multilayer circuit boards.

2. The method according to claim 1, characterized in that, Identify N groups of circuit boards corresponding to multiple circuit boards, including: Determine the thickness of the dielectric layer of each of the plurality of circuit boards; and Determine the allowable range of dielectric layer thickness for each of the N groups of circuit boards; The N groups of circuit boards corresponding to the plurality of circuit boards are determined based on the thickness of the dielectric layer of each circuit board and the allowable thickness range.

3. The method according to claim 1, characterized in that, Before laminating each of the N groups of circuit boards separately, the method further includes: Each set of circuit boards was cleaned using the target tool. Rinse each group of circuit boards after the cleaning process; Each set of circuit boards is then heated to dry it.

4. The method according to claim 1, characterized in that, Each of the N groups of circuit boards is laminated separately, including: Obtain the dimensions of each of the N groups of circuit boards; The pressing parameters used by the pressing assembly when pressing each group of circuit boards are adjusted according to the size of each group of circuit boards in the N groups of circuit boards; wherein, the pressing parameters include: pressing time and the size of the pressing head of the pressing assembly; The pressing assembly is controlled to press each of the N groups of circuit boards according to the parameters corresponding to the size of each group of circuit boards.

5. The method according to claim 1, characterized in that, After splicing the patterns at the same positions in N first multilayer circuit boards to form N spliced ​​second multilayer circuit boards, the method further includes: The reliability of each of the N spliced ​​second multilayer circuit boards is tested. Feedback on the second multilayer circuit board that failed the reliability test; The second multilayer circuit board that failed the reliability test was repaired based on the information provided.

6. The method according to claim 1, characterized in that, Soldering N second multilayer circuit boards to fabricate a multilayer circuit board includes: Determine multiple vias in each of the N second multilayer circuit boards; Multiple solder joints are determined for each of the second multilayer circuit boards based on the plurality of through holes; N second multilayer circuit boards are soldered together according to the plurality of solder points to prepare the multilayer circuit board.

7. An apparatus for fabricating a multilayer circuit board, characterized in that, include: The determining module is used to determine N groups of circuit boards corresponding to multiple circuit boards, wherein the N groups of circuit boards are N groups of circuit boards that are evenly divided according to a preset rule, each of the multiple circuit boards includes a pattern, the number of patterns set on the multiple circuit boards and the position of the patterns on the circuit boards are the same, and the number of patterns is N, where N is a positive integer; The lamination module is used to laminate each of the N sets of circuit boards to obtain N laminated first multilayer circuit boards. The splicing module is used to splice the patterns at the same position in N first multilayer circuit boards to form N spliced ​​second multilayer circuit boards; A welding module is used to weld N second-layer circuit boards to prepare a multilayer circuit board; The splicing module is further configured to: number the N patterns in each of the N first multilayer circuit boards in the same order; for each numbered first multilayer circuit board, cut according to the border of the pattern on each first multilayer circuit board to determine multiple numbered multilayer circuit boards corresponding to each first multilayer circuit board, wherein the first multilayer circuit board includes multiple multilayer circuit boards; determine multiple multilayer circuit boards with the same number from the multiple multilayer circuit boards corresponding to the N first multilayer circuit boards; obtain the wire layout corresponding to each of the multiple multilayer circuit boards with the same number; determine the splicing order of the multiple multilayer circuit boards with the same number according to the wire layout corresponding to each of the multilayer circuit boards; and splice the multiple multilayer circuit boards with the same number according to the splicing order to form N spliced ​​second multilayer circuit boards.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 6.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 6.

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