A hardware tracking circuit, method, apparatus and medium

Abstract

This invention discloses a hardware tracing circuit, method, apparatus, and medium, relating to the field of electronic circuit technology. It is used to trace subsystems and addresses the problems of complex structures and large areas in current hardware tracing schemes. This invention provides a hardware tracing circuit where a filtering unit performs initial filtering of the traced information; a caching unit temporarily stores the traced information; and a protocol interface unit sends it to an external storage device for persistent storage of the traced information. This provides a hardware circuit design scheme suitable for tracing specific subsystems. Furthermore, this scheme reduces the amount of traced information by filtering the traced information through the filtering unit, improving analysis efficiency while increasing tracing time. It also reduces the requirements for subsequent transmission and storage of traced information, thus helping to reduce circuit area and cost.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits, and in particular to a hardware tracking circuit, method, apparatus, and medium. Background Technology

[0002] As the chip industry continues to develop and chips become increasingly larger, users' demands for system-on-chip (SoC) visibility are also increasing. To ensure the visibility of the entire on-chip system hardware, it is necessary to record the on-chip system's operating status, program execution paths, and data read / write operations in real time. This is typically achieved through on-chip hardware design, using a non-intrusive approach to monitor the system.

[0003] Currently, there is a lack of effective hardware design solutions for on-chip system trace tracing in some application scenarios where trace tracing is required only for specific subsystems within the on-chip system.

[0004] Trace: A computer term referring to a method used to debug Hypertext Transfer Protocol (HTTP) connections to network servers.

[0005] Therefore, those skilled in the art urgently need a hardware tracking circuit to provide a design scheme for on-chip system tracking hardware in scenarios where there is a need to track specific subsystems. Summary of the Invention

[0006] The purpose of this invention is to provide a hardware tracing circuit, method, apparatus, and medium to provide a design scheme for on-chip system tracing hardware in scenarios where there is a need to trace specific subsystems, so as to solve the tracing problem of on-chip systems.

[0007] To solve the above technical problems, the present invention provides a hardware tracking circuit, including: a filtering unit, a register configuration unit, a buffer unit, and a protocol interface unit;

[0008] The filtering unit is connected to the subsystem to be tracked, the register configuration unit, and the cache unit. It is used to filter the data and / or events sent by the subsystem to be tracked according to the preset filtering logic in the configuration information stored in the register configuration unit and send them to the cache unit.

[0009] The register configuration unit is connected to the filtering unit and the protocol interface unit, and is used to store configuration information;

[0010] The caching unit is also connected to the protocol interface unit to cache data and / or events sent by the filtering unit;

[0011] The protocol interface unit is also connected to the register configuration unit and the external storage device, and is used to transmit data to the external storage device based on the configuration information stored in the register configuration unit and a preset protocol.

[0012] On the other hand, the filtering unit includes: a control module, a masking module, and a comparison module;

[0013] The control module is connected to the register configuration unit, the masking module, and the comparison module, and is used to control the working mode of the masking module and the comparison module according to the configuration information stored in the register configuration unit.

[0014] The masking module is connected to the register configuration unit and the comparison module. It is used to mask data and / or events according to the preset masking logic in the configuration information stored in the register configuration unit and send them to the comparison module.

[0015] The comparison module is connected to the register configuration unit and is used to compare data and / or events according to the preset comparison logic in the configuration information stored in the register configuration unit, so as to determine whether to output data and / or events;

[0016] Accordingly, the filtering logic includes masking logic and / or comparison logic.

[0017] On the other hand, the control module also includes: a data buffer;

[0018] The control module is connected to the subsystem to be tracked and is also used to cache the data and / or events sent by the subsystem to be tracked through a data buffer for further filtering by the masking module and the comparison module.

[0019] On the other hand, it also includes: information packaging units;

[0020] The information packaging unit is located between the filtering unit and the caching unit, and is also connected to the register configuration unit. It is used to package the data and / or events filtered by the filtering unit according to the preset bit width in the configuration information stored in the register configuration unit, and send them to the caching unit.

[0021] On the other hand, it also includes: a timestamp generation unit;

[0022] The timestamp generation unit is connected to the information packaging unit and is used to generate timestamps;

[0023] The information packaging unit is also used to obtain the timestamp corresponding to the current system time from the timestamp generation unit when it receives data and / or events sent by the filtering unit, and to concatenate the timestamp with the data and / or events.

[0024] On the other hand, the filtering unit includes a data filtering module and an event filtering module;

[0025] The data filtering module is used to filter the data sent by the tracking subsystem according to the filtering logic stored in the register configuration unit; the event filtering module is used to filter the events sent by the tracking subsystem according to the filtering logic stored in the register configuration unit.

[0026] Accordingly, the information packaging unit includes: a data packaging module, an event packaging module, and an error message packaging module;

[0027] The data packaging module is located between the data filtering module and the caching unit. It is used to package the data filtered by the data filtering module and send it to the caching unit.

[0028] The event packaging module is located between the event filtering module and the caching unit. It is used to package the events filtered by the event filtering module and send them to the caching unit.

[0029] The error message packaging module is connected to the cache unit and the timestamp generation unit. It is used to receive the full signal sent by the cache unit when the cache unit is full, and to obtain the timestamp corresponding to the current system time from the timestamp generation unit; and to concatenate the full signal and the timestamp to generate the error message.

[0030] Accordingly, the caching unit includes: a data caching module, an event caching module, and an error message caching module;

[0031] The data caching module is connected to the data packaging module and is used to cache the packaged data.

[0032] The event caching module is connected to the event packaging module and is used to cache the packaged events.

[0033] The error message storage module is connected to the error message packaging module and is used to cache error messages.

[0034] On the other hand, it also includes: arbitrators;

[0035] The arbitrator is located between the cache unit and the protocol interface unit, and is also connected to the register configuration unit. It is used to select any one, several, or all of the cache modules from the data cache module, event cache module, and error information cache module according to the preset arbitration logic in the configuration information stored in the register configuration unit, and allow the cached data and / or events, as well as error information, to be transmitted to the protocol interface unit.

[0036] To address the aforementioned technical problems, the present invention also provides a hardware tracing method applied to a hardware tracing circuit comprising: a filtering unit, a register configuration unit, a cache unit, and a protocol interface unit; wherein, the filtering unit is connected to the subsystem to be traced, the register configuration unit, and the cache unit; the register configuration unit is connected to the filtering unit and the protocol interface unit, and stores configuration information in the register configuration unit; the cache unit is also connected to the protocol interface unit; and the protocol interface unit is also connected to the register configuration unit and an external storage device.

[0037] The methods include:

[0038] Track the subsystem to be tracked and obtain the corresponding data and / or events;

[0039] Data and / or events are filtered according to preset filtering logic;

[0040] Store the filtered data and / or events to an external storage device.

[0041] On the other hand, the configuration information includes: masking logic and comparison logic; the filtering unit includes: control module, masking module and comparison module;

[0042] Accordingly, filtering data and / or events according to preset filtering logic includes:

[0043] Compare the data and / or events acquired in this cycle with those acquired in the previous cycle. If they match, then prevent the output of the data and / or events acquired in this cycle.

[0044] Based on masking logic, specific bits in data and / or events are masked;

[0045] Based on comparison logic, the comparison is performed between specific parameters in the data and preset reference values. If the comparison conditions are not met, the corresponding data is not output.

[0046] Based on comparison logic, it is determined whether the number of times a specific signal combination occurs in an event reaches a preset threshold. If not, the corresponding event is prohibited from being output.

[0047] On the other hand, the hardware tracking circuit also includes: an arbitrator, which is located between the cache unit and the protocol interface unit and is also connected to the register configuration unit; the cache unit includes: a data cache module, an event cache module, and an error information cache module; the configuration information includes the arbitration mode, as well as the arbitration order or arbitration target;

[0048] Correspondingly, the methods also include:

[0049] The arbitrator is determined to operate in either polling arbitration mode or priority arbitration mode based on the arbitration mode.

[0050] The polling arbitration mode includes: according to the arbitration order, sequentially retrieving and outputting the data, events, and error information stored in the data cache module, event cache module, and error information cache module;

[0051] The priority arbitration mode includes: selecting any one of the data caching module, event caching module, and error information caching module according to the arbitration objective, retrieving the stored data, events, or error information, and outputting it.

[0052] To address the aforementioned technical problems, the present invention also provides a hardware tracking device applied to a hardware tracking circuit comprising: a filtering unit, a register configuration unit, a cache unit, and a protocol interface unit; wherein, the filtering unit is connected to the subsystem to be tracked, the register configuration unit, and the cache unit; the register configuration unit is connected to the filtering unit and the protocol interface unit, and stores configuration information in the register configuration unit; the cache unit is also connected to the protocol interface unit; and the protocol interface unit is also connected to the register configuration unit and an external storage device.

[0053] The device includes:

[0054] The subsystem tracking module is used to track the subsystem to be tracked and obtain the corresponding data and / or events;

[0055] The information filtering module is used to filter data and / or events according to preset filtering logic;

[0056] The information storage module is used to store filtered data and / or events to an external storage device.

[0057] To address the aforementioned technical problems, the present invention also provides a hardware tracking device, comprising:

[0058] Memory, used to store computer programs;

[0059] A processor is used to implement the hardware tracing method described above when executing a computer program.

[0060] To address the aforementioned technical problems, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the hardware tracing method described above.

[0061] This invention provides a hardware tracing circuit, offering a hardware circuit solution for tracing a specific subsystem. Subsystem designers send planned tracing data and / or events to a filtering unit, which performs initial filtering of the tracing information. A caching unit then temporarily stores the tracing information, and a protocol interface unit sends it to an external storage device for persistent storage, providing data support for subsequent analysis. Thus, this solution completes the tracing of a specific subsystem, providing a hardware circuit design suitable for tracing specific subsystems. Furthermore, the filtering of tracing information by the filtering unit reduces the amount of tracing information, increasing tracing time while improving analysis efficiency. This reduction also minimizes the requirements for subsequent transmission and storage of tracing information, thus reducing circuit footprint and cost.

[0062] The hardware tracking method, apparatus, and computer-readable storage medium provided by this invention correspond to the circuit described above and have the same effect. Attached Figure Description

[0063] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0064] Figure 1 This is a structural diagram of the simplest hardware implementation circuit for Trace;

[0065] Figure 2 A structural diagram of a hardware tracking circuit provided by the present invention;

[0066] Figure 3 A structural diagram of a screening unit provided by the present invention;

[0067] Figure 4 A data flow transmission path diagram for a hardware tracking circuit provided by the present invention;

[0068] Figure 5 A flowchart of a hardware tracking method provided by the present invention;

[0069] Figure 6 A structural diagram of a hardware tracking device provided by the present invention;

[0070] Figure 7 A structural diagram of another hardware tracking device provided by the present invention. Detailed Implementation

[0071] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0072] The core of this invention is to provide a hardware tracking circuit, method, device, and medium.

[0073] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0074] Currently, to meet the visibility requirements of system-on-chips (SoCs), non-intrusive solutions are often used to monitor the system. A common hardware solution for implementing non-intrusive trace tracing is the use of CoreSight IP for System-on-Chip (SoC) trace tracing.

[0075] CoreSight: An industry term referring to on-chip debugging and tracing.

[0076] IP: Intellectual Property, a reusable integrated circuit design module with a specific function.

[0077] When implementing system-on-a-chip (SoC) tracing using CoreSight IP, the simplest tracing hardware implementation circuit is as follows: Figure 1 As shown, it includes: an interconnect bus (which may be an AXI interconnect bus; Advanced eXtensible Interface, AXI, a bus protocol), a System Trace Macrocel (STM), an Embedded Trace Router (ETR), a Cross Trigger Interface (CTI), a Debug Access Port (DAP), and an Advanced Peripheral Bus (APB) interconnect module; among which, STM, ETR, CTI, and DAP are all components of CoreSight IP.

[0078] The subsystem sends information to the STM via the AXI (Advanced eXtensible Interface, a bus protocol) interconnect bus; the STM packages the data, generates fixed-format data, and saves the data to the storage device via ETR. To implement this trace flow path, CTI is added to receive and send trigger signals to the STM and ETR, and DAP and APB interconnect modules are also needed to configure and access the corresponding components. Since each CoreSight component can be configured as needed, the pursuit of versatility leads to redundant logic and unnecessary configurations, resulting in a loss of operational flexibility and increased unnecessary power consumption and area.

[0079] Therefore, the aforementioned tracing schemes typically require a large circuit area and high system power consumption. For scenarios where tracing is only required for a specific subsystem, such a large circuit area and high system power consumption are usually unacceptable to users. Therefore, there is an urgent need for another hardware tracing scheme that can achieve tracing of a specific subsystem while having a smaller circuit area and lower system power consumption.

[0080] Therefore, the present invention provides a hardware tracking circuit, such as Figure 2 As shown, it includes: a filtering unit 11, a register configuration unit 12, a buffer unit 13, and a protocol interface unit 14;

[0081] The filtering unit 11 is connected to the subsystem to be tracked 20, the register configuration unit 12 and the cache unit 13, and is used to filter the data and / or events sent by the subsystem to be tracked 20 according to the preset filtering logic in the configuration information stored in the register configuration unit 12 and send them to the cache unit 13.

[0082] Register configuration unit 12 is connected to filtering unit 11 and protocol interface unit 14, and is used to store configuration information;

[0083] The caching unit 13 is also connected to the protocol interface unit 14 and is used to cache the data and / or events sent by the filtering unit 11;

[0084] The protocol interface unit 14 is also connected to the register configuration unit 12 and the external storage device 30, and is used to transmit data to the external storage device 30 based on the configuration information stored in the register configuration unit 12 and a preset protocol.

[0085] The filtering unit 11 is a hardware unit that further filters the trace information obtained from a specific subsystem 20 to be traced. Specifically, it can filter key data and / or key events of the subsystem, where key events are key data from multiple cycles. Based on the scenarios and data that the subsystem designers want to observe, corresponding filtering logic can be pre-designed and stored in the register configuration unit 12 as configuration information. This allows the filtering unit 11 to read the configuration information from the register configuration unit 12 during operation and filter the trace information of the subsystem 20 to be traced based on the preset filtering logic.

[0086] It should be noted that the filtering unit 11 provided by this invention can be a hardware module for filtering data, which can be implemented by a digital signal processor (DSP), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), etc. This embodiment does not limit this. However, it should be noted that at the hardware circuit level, the filtering module does not distinguish between data and events. Therefore, whether the filtering unit 11 is used to filter data or events, or data and events, is mainly determined by the actual engineering needs. The data and / or events to be filtered can be input into the filtering unit 11.

[0087] For example Figure 2 As shown, this embodiment provides a possible implementation scheme, wherein the above-mentioned filtering unit 11 includes a data filtering module and an event filtering module;

[0088] The data filtering module is used to filter the data sent by the tracking subsystem 20 according to the filtering logic stored in the register configuration unit 12; the event filtering module is used to filter the events sent by the tracking subsystem 20 according to the filtering logic stored in the register configuration unit 12.

[0089] It is readily apparent that both the data filtering module and the event filtering module are data filters, distinguished only from an application perspective: the filter for filtering data is the data filtering module, and the filter for filtering events is the event filtering module. The data filtering module and the event filtering module can be based on the exact same filtering logic, or, depending on actual needs, the filtering logic for data and events can be designed separately to obtain the corresponding data filtering module and event filtering module. This embodiment does not impose any restrictions on this.

[0090] Furthermore, this embodiment also provides a possible implementation scheme for the specific structure of the screening unit 11 and the actual implementation of the screening logic, such as... Figure 3 As shown, the filtering unit 11 mentioned above includes: a control module 111, a masking module 112, and a comparison module 113;

[0091] The control module 111 is connected to the register configuration unit 12, the masking module 112 and the comparison module 113, and is used to control the working mode of the masking module 112 and the comparison module 113 according to the configuration information stored in the register configuration unit 12.

[0092] The masking module 112 is connected to the register configuration unit 12 and the comparison module 113, and is used to mask data and / or events according to the preset masking logic in the configuration information stored in the register configuration unit 12, and send them to the comparison module 113.

[0093] The comparison module 113 is connected to the register configuration unit 12 and is used to compare data and / or events according to the preset comparison logic in the configuration information stored in the register configuration unit 12, so as to determine whether to output data and / or events;

[0094] Accordingly, the filtering logic of the above-mentioned filtering unit 11 includes masking logic and / or comparison logic.

[0095] As can be seen from the above, in this embodiment, the filtering logic that the filtering unit 11 can execute on data and / or events includes: data masking and comparison output.

[0096] Data masking refers to a situation where subsystem personnel determine that only specific bits in the obtained trace information have changed or are valid, while other bits remain unchanged or are ignored. In this case, the bits that need to be masked or not can be configured in the register configuration unit 12, and the masking module 112 performs the appropriate masking operation, retaining only the specific bits in the data / events that the subsystem personnel need. This enables personalized filtering of trace information, reducing the amount of trace information and alleviating the pressure on subsequent storage and analysis.

[0097] The comparison output can be divided into two cases: comparing trace information between different periods to determine whether to output, and comparing data in the trace information of the same period with preset conditions to determine whether to output. The following examples illustrate these two cases:

[0098] 1. The data or events tracked in the subsystem remain unchanged for multiple cycles (at least two cycles);

[0099] At this point, storing and analyzing the trace information received in each cycle would undoubtedly lead to ineffective operations and wasted resources. Therefore, for trace information that remains unchanged across multiple cycles, only the trace information from one cycle can be output to reduce the pressure on subsequent data storage and analysis.

[0100] The specific screening logic for implementing the above objectives can be:

[0101] For the data, compare whether the data received in each cycle is completely consistent with the data received in the previous cycle. If they are consistent, then the data received in the current cycle is not output; otherwise, the data received in the current cycle is output.

[0102] For an event, which consists of multiple sets of data that meet a certain condition (time, parameter), all data within the same event are compared, and identical data is output only once. Specifically, if data is received over multiple periods, the data from each period is compared; if the data received in each period is identical, only the data from that period is output.

[0103] Second, relevant personnel pay attention to trace information that matches a certain characteristic;

[0104] At this point, the following filtering logic can be used: when a parameter in the Trace information meets a certain condition (a specific size relationship with the reference value, a specific combination that meets a preset number of times, etc.), or when the continuously acquired Trace information is intercepted and output based on a certain specific condition (starting condition, ending condition, etc.), etc., this embodiment does not impose any restrictions on this.

[0105] In summary, the comparisons and filtering of trace information described above are all based on the design of corresponding comparison conditions by the designers according to actual needs. The specific data in the received trace information is compared and judged based on the comparison conditions. If the comparison conditions are met, specific data is extracted (if there are corresponding extraction conditions) and output.

[0106] More specifically, the control module 111 controls the overall operating mode of the filtering unit 11, such as whether the comparison module 113 and the masking module 112 are working. It can also be used to perform simple processing on the trace information to facilitate subsequent comparison and filtering. The specific conditions used for comparison and filtering are stored in the register configuration unit 12 as configuration information. When the comparison module 113 or the filtering module is working normally, the corresponding conditions are read from the register configuration unit 12 to filter the trace information.

[0107] In another possible implementation scenario, the control module 111 can also be used to perform certain preprocessing operations on the data / events to be filtered. The aforementioned preprocessing operations can be common data processing operations, so that the masking module 112 and the comparison module 113 can subsequently execute the corresponding filtering logic. This embodiment does not limit the preprocessing operations. However, in this implementation scheme, such as... Figure 3 As shown, the data / events sent to the filtering unit 11 should first be preprocessed by the control module 111 before being sent to the masking module 112 and the comparison module 113 for subsequent filtering.

[0108] On the other hand, this embodiment also provides another possible implementation scheme. The control module 111 described above may further include a data buffer to provide a data / event caching function, caching the data and / or events sent by the subsystem to be tracked 20, so that the filtering unit 11 can filter the trace information sent by the subsystem to be tracked 20. In this embodiment, the control module 111 also needs to directly receive and cache the trace information sent by the subsystem to be tracked 20 as the filtering unit 11, so that the masking module 112 and the comparison module 113 can perform the next step of filtering.

[0109] It should also be noted that the above-mentioned further details regarding the filtering unit 11 are as follows: Figure 3 In the specific implementation scheme shown, if data and events are traced separately in practical applications, the multiple filtering units 11 used for filtering data and events can all adopt the methods provided in the above embodiments. Figure 3 The implementation scheme shown is not limited in this embodiment.

[0110] On the other hand, this embodiment also provides a possible implementation scheme for hardware tracking circuits, such as... Figure 2 As shown, the hardware tracking circuit also includes: an information packaging unit 15;

[0111] The information packaging unit 15 is located between the filtering unit 11 and the buffer unit 13, and is also connected to the register configuration unit 12. It is used to package the data and / or events filtered by the filtering unit 11 based on a preset bit width, according to the configuration information stored in the register configuration unit 12, and then send it to the buffer unit 13. The information packaging unit 15 enables information to be saved according to a fixed bit width and format, thus allowing for rapid data transfer using advanced protocols and real-time data saving.

[0112] It is readily apparent that the aforementioned information packaging unit 15 is primarily used to process trace information into data of a specific width for subsequent transmission and storage. Similarly, the information packaging unit 15 corresponds to the aforementioned filtering unit 11. If the filtering unit 11 is divided into a data filtering module and an event filtering module based on the different data or events being filtered, then the information packaging unit 15 can be correspondingly divided into a data packaging module and an event packaging module. The data packaging module is connected to the data filtering module and is used to package the filtered data. Likewise, the event packaging module is connected to the event filtering module and is used to package the filtered events.

[0113] On the other hand, such as Figure 2 As shown, this embodiment also provides a possible implementation scheme, wherein the above-mentioned hardware tracking circuit further includes: a timestamp generation unit 16;

[0114] The timestamp generation unit 16 is connected to the information packaging unit 15 and is used to generate timestamps. The logic and configuration of the timestamp generation unit 16 can also be configured through the register configuration unit 12, i.e., as... Figure 2 As shown, the timestamp generation unit 16 is connected to the sea area register configuration unit 12.

[0115] Accordingly, in this embodiment, the information packaging unit 15 is also used to obtain the timestamp corresponding to the current system time from the timestamp generation unit 16 when it receives the data and / or events sent by the filtering unit 11, and to concatenate the timestamp with the data and / or events.

[0116] In this embodiment, the information packaging unit 15 is used to concatenate Trace tracking information with timestamps to generate data with a specific width. The main function of the timestamp is to identify the time when the current information was generated, so as to facilitate the analysis of the data after it is offline. The order in which the data was generated can be determined by the time information, thereby analyzing the running status of the relevant logic.

[0117] On the other hand, for the specific implementation of the cache unit 13 described above, one possible implementation is a FIFO memory.

[0118] FIFO Memory: FIFO stands for First Input First Output. A FIFO memory is a first-in, first-out dual-port buffer, meaning that the first piece of data to enter is the first piece to be removed. One port is the memory's input port, and the other is its output port.

[0119] The FIFO memory can return a full signal when its space is full, thus informing relevant personnel that the cache unit 13 is running out of space. Correspondingly, one possible implementation of the information packaging unit 15 at this time, in addition to the aforementioned data packaging module and event packaging module, also includes an error information packaging module.

[0120] The error message packaging module is connected to the cache unit 13 and the timestamp generation unit 16. It is used to receive the full signal sent by the cache unit 13 when the cache unit 13 is full, and obtain the timestamp corresponding to the current system time from the timestamp generation unit 16; and concatenate the full signal and the timestamp to generate error message.

[0121] Similarly, cache unit 13 also corresponds to a cache module for error information. Combining the above implementation schemes for tracing data and events, one possible implementation scheme for cache unit 13 is as follows: Figure 2 As shown, it includes: a data caching module, an event caching module, and an error message caching module;

[0122] The data caching module is connected to the data packaging module and is used to cache the packaged data; the event caching module is connected to the event packaging module and is used to cache the packaged events; the error information storage module is connected to the error information packaging module and is used to cache error information.

[0123] In this embodiment, the cache unit 13 is specifically implemented using a FIFO memory, utilizing the characteristic that a FIFO memory generates a full signal when it is full. Because a FIFO cannot be infinitely large, and if the trace information time is relatively long, only a portion of the data may be stored, potentially leading to a full FIFO. In this case, a full signal is generated. The information packaging unit 15 concatenates the full signal with a timestamp to generate corresponding error information, which is then cached by the cache unit 13 and sent to the subsequent storage device. This allows relevant personnel to be aware of the insufficient space in the cache unit 13 and take actions such as replacing it with a larger cache unit 13 or adjusting the filtering logic.

[0124] On the other hand, in the above embodiments, the data and events obtained from trace tracking are filtered, cached, and transmitted separately. Furthermore, in a further embodiment, error information is introduced into the hardware tracing circuit, which may result in a large amount of data appearing at a certain moment, putting significant pressure on backend data transmission and storage. Therefore, to further reduce the data volume, this embodiment also provides a possible implementation scheme, such as... Figure 2 As shown, the aforementioned hardware tracking circuit also includes: an arbitrator 17;

[0125] Arbitrator 17 is located between cache unit 13 and protocol interface unit 14, and is also connected to register configuration unit 12. It is used to select any one, several, or all of the cache modules from the data cache module, event cache module, and error information cache module according to the preset arbitration logic in the configuration information stored in register configuration unit 12, allowing the cached data and / or events, as well as error information, to be transmitted to protocol interface unit 14. Furthermore, after arbitration is selected, protocol interface unit 14 is used to save the data in cache unit 13 to external storage device 30 using the corresponding protocol interface.

[0126] The present invention does not limit the data communication protocol used by the protocol interface unit 14. In practical applications, it can be determined comprehensively based on factors such as data transmission rate and the communication interface protocol format supported by the external storage device 30. Furthermore, other requirements can also be considered. For example, in one possible implementation scheme provided in this embodiment, the above-mentioned protocol interface unit 14 specifically adopts the AXI (Advanced eXtensible Interface, a bus protocol) protocol.

[0127] The advantages of the AXI protocol are: firstly, its data transmission rate is relatively fast, which can meet the needs of general trace tracing scenarios; secondly, the structure of the information packaging unit 15 required to implement the AXI protocol is relatively simple (compared to...). Figure 1 (Referring to CoreSight IP, which is commonly used in traditional solutions); Thirdly, the AXI protocol has burst transmission characteristics, which can quickly save the data in the cache unit 13 to the storage device, reducing data loss.

[0128] It is easy to understand that using the AXI protocol as the communication protocol of the protocol interface unit 14 is not a necessary requirement; other interface protocols can also be used, such as the AHB interface protocol or the APB interface protocol.

[0129] To further illustrate how the hardware tracing circuit provided by this invention implements trace tracking, based on the embodiments provided above, this embodiment also provides a data stream transmission path and process for trace tracking information, such as... Figure 4 As shown:

[0130] The data and events obtained by the subsystem Trace are transmitted from two independent paths. In each path, the data / events are first cached in the data buffer of the control module 111 in the filtering unit 11. The comparison module 113 determines whether the data / events meet the corresponding filtering requirements. If they do not meet the requirements, they are temporarily stored in the data buffer. If they do meet the requirements, the data in the specific location is covered by the masking module 112. The data / events are then output to the information packaging unit 15 for packaging. When packaging data / events, the timestamp generation unit 16 provides the timestamp of the current moment in real time so that the packaged data / events can reflect the corresponding generation time. The packaged data / events are cached in the corresponding data FIFO and event FIFO. If any FIFO determines that the storage space is full, a corresponding full signal is generated and sent to the information packaging unit 15. Combined with the timestamp, the corresponding error information is generated and sent to the corresponding error information FIFO. After that, the arbitrator 17 selects data output from the data FIFO, event FIFO and error information FIFO based on the preset arbitration logic and sends it to the external storage device 30 for persistent storage via the protocol interface unit 14.

[0131] The hardware tracing circuit provided by this invention has a simple structure and smaller area. Furthermore, it achieves preliminary screening of trace information through a filtering unit based on filtering logic pre-configured in the register configuration unit. After the subsystem outputs corresponding data and events, the filtering unit can automatically filter the trace information. This allows the hardware tracing circuit to output only the trace information needed by technicians, reducing data volume to facilitate subsequent data transmission and storage, further simplifying the circuit structure and reducing costs. Simultaneously, this solution also improves the targeting and flexibility of trace tracing through custom filtering of trace information, better meeting the trace tracing needs of subsystem designers for specific subsystems.

[0132] On the other hand, the present invention also provides a hardware tracking method corresponding to the above-described hardware tracking circuit, applied to the above-described hardware tracking circuit, such as... Figure 5 As shown, it includes:

[0133] S11: Track the subsystem to be tracked and obtain the corresponding data and / or events;

[0134] S12: Filter data and / or events according to preset filtering logic;

[0135] S13: Store the filtered data and / or events to an external storage device.

[0136] The specific implementation methods for each of the above steps have been described in detail in the embodiments of the hardware tracking circuit section above, so they will not be repeated here. This embodiment provides a further application method for the hardware tracking circuit above.

[0137] In the embodiments of the hardware tracking circuit section described above, some possible implementation schemes for the filtering logic of the filtering unit are given, but no strict restrictions are imposed. That is, depending on the actual needs, any filtering logic can be configured in the register configuration unit. The present invention does not restrict the specific implementation scheme of the filtering logic.

[0138] However, in one possible implementation, the configuration information stored in the register configuration unit includes: masking logic and comparison logic; the filtering unit includes: a control module, a masking module, and a comparison module.

[0139] Accordingly, step S12 above specifically includes:

[0140] S121: Compare the data and / or events obtained in the current cycle with those obtained in the previous cycle. If they are consistent, then prevent the output of the data and / or events obtained in the current cycle.

[0141] S122: Based on masking logic, mask specific bits in data and / or events;

[0142] S123: Based on comparison logic, compare the size relationship between a specific parameter in the data and a preset reference value. If the comparison condition is not met, the corresponding data output is prohibited.

[0143] S124: Based on comparison logic, determine whether the number of times a specific signal combination occurs in the event reaches a preset threshold. If not, prohibit the output of the corresponding event.

[0144] In other words, this embodiment provides an implementation scheme for how to filter data and / or events according to a preset filtering logic in step S12, with four different implementation schemes from steps S121 to S124. It is readily apparent that steps S121-S124 are independent steps or schemes, with no sequential restriction between them, and no interdependence or obstruction in their implementation. They are four independent and parallel filtering and comparison schemes used for customized filtering of trace information. Therefore, depending on the actual filtering needs, any one, any few, or all of the four different implementation schemes from steps S121-S124 can be selected for implementation; this embodiment does not impose any restrictions on this.

[0145] In addition to the filtering logic implementation schemes of the filtering units provided in the above embodiments, this embodiment also provides a possible implementation scheme for the arbitration logic of the arbitrator in the above hardware tracking circuit:

[0146] The following method is applied to a hardware tracking circuit including an arbitrator, which is positioned between a cache unit and a protocol interface unit, and is also connected to a register configuration unit. The cache unit includes a data cache module, an event cache module, and an error information cache module. The configuration information includes the arbitration mode, and the arbitration order or arbitration target. Accordingly, the method further includes:

[0147] S14: Determine whether the arbitrator operates in polling arbitration mode or priority arbitration mode based on the arbitration mode;

[0148] The polling arbitration mode includes: according to the arbitration order, sequentially retrieving and outputting the data, events, and error information stored in the data cache module, event cache module, and error information cache module;

[0149] The priority arbitration mode includes: selecting any one of the data caching module, event caching module, and error information caching module according to the arbitration objective, retrieving the stored data, events, or error information, and outputting it.

[0150] As can be seen from the above embodiment of the hardware tracking circuit, the arbitration process of the arbitrator occurs after the information is packaged and before it is transmitted to the external storage device through the protocol interface unit. Therefore, step S14 in this embodiment generally occurs after step S12 and before step S13. Furthermore, the data and / or events stored to the external storage device in step S13 are further filtered and arbitrated data and / or events.

[0151] In this embodiment, two arbitration logics are provided for the arbitrator, implemented by a polling arbitration mode and a priority arbitration mode, respectively. The two arbitration modes are pre-configured in the register configuration unit. During subsequent trace tracing, the arbitration logic can be quickly switched by changing the mode, eliminating the need for repeated configuration and making it more flexible and convenient to use.

[0152] Regarding the two arbitration logics provided in this embodiment, the polling arbitration mode saves the data in the three FIFOs (data FIFO, event FIFO, and error information FIFO) sequentially (the order can also be configured and stored in the register configuration unit) to the external storage device. The polling arbitration mode can save the data in each FIFO, ensuring that all information is persistently stored in the external storage device. The priority arbitration mode, on the other hand, saves only the data in one of the three FIFOs, omitting data from the other FIFOs from the external storage device, even if the corresponding FIFO memory is full and an error signal is generated. This allows for arbitration of the trace information that needs to be saved based on user requirements, thereby reducing the data volume.

[0153] The hardware tracing method provided in this embodiment is a further tracing scheme based on the aforementioned hardware tracing circuit. It mainly involves filtering and arbitration logic for tracing information, enabling flexible and personalized filtering and arbitration of tracing information for subsystems according to different user tracing needs. On the one hand, this makes the transmission and persistent storage of tracing information more targeted, avoiding irrelevant or unnecessary information from interfering with subsequent analysis. On the other hand, it effectively reduces the amount of data involved in the tracing process, lowers the requirements on various hardware components in the hardware tracing circuit, and helps improve the overall efficiency of the tracing process. This results in faster and more accurate positioning, debugging, and analysis, better meeting the tracing needs of specific subsystems in practical application scenarios.

[0154] In the above embodiments, a hardware tracking method has been described in detail. The present invention also provides an embodiment corresponding to a hardware tracking device. It should be noted that the present invention describes the device embodiment from two perspectives: one based on functional modules, and the other based on hardware.

[0155] From the perspective of functional modules, this embodiment provides a hardware tracking device, such as... Figure 6 As shown, it includes:

[0156] Subsystem tracking module 41 is used to track the subsystem to be tracked and obtain the corresponding data and / or events;

[0157] The information filtering module 42 is used to filter data and / or events according to preset filtering logic;

[0158] Information storage module 43 is used to store filtered data and / or events to an external storage device.

[0159] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0160] Figure 7 A structural diagram of a hardware tracking device provided in another embodiment of the present invention is shown below. Figure 7 As shown, a hardware tracking device includes: a memory 50 for storing computer programs;

[0161] The processor 51 is used to implement the steps of a hardware tracing method as described in the above embodiment when executing a computer program.

[0162] The processor 51 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 51 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 51 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 51 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 51 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0163] The memory 50 may include one or more computer-readable storage media, which may be non-transitory. The memory 50 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 50 is used to store at least the following computer program 501, which, after being loaded and executed by the processor 51, is capable of implementing the relevant steps of a hardware tracing method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 50 may also include an operating system 502 and data 503, etc., and the storage method may be temporary storage or permanent storage. The operating system 502 may include Windows, Unix, Linux, etc. The data 503 may include, but is not limited to, a hardware tracing method.

[0164] In some embodiments, a hardware tracking device may further include a display screen 52, an input / output interface 53, a communication interface 54, a power supply 55, and a communication bus 56.

[0165] Those skilled in the art will understand that Figure 7 The structure shown does not constitute a limitation on a hardware tracking device and may include more or fewer components than illustrated.

[0166] The present invention provides a hardware tracking device, including a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method: a hardware tracking method.

[0167] Finally, the present invention also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, performs the steps described in the above method embodiments.

[0168] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0169] The hardware tracking circuit, method, apparatus, and medium provided by the present invention have been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0170] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A hardware tracking circuit, characterized in that, include: Filtering unit, register configuration unit, buffer unit, and protocol interface unit; The filtering unit is connected to the subsystem to be tracked, the register configuration unit, and the cache unit, and is used to filter the data and / or events sent by the subsystem to be tracked according to the preset filtering logic in the configuration information stored in the register configuration unit and send them to the cache unit. The register configuration unit is connected to the filtering unit and the protocol interface unit, and is used to store the configuration information; The caching unit is also connected to the protocol interface unit and is used to cache the data and / or events sent by the filtering unit; The protocol interface unit is also connected to the register configuration unit and the external storage device, and is used to transmit data to the external storage device based on the configuration information stored in the register configuration unit and a preset protocol. The filtering unit includes: a control module, a masking module, and a comparison module; The control module is connected to the register configuration unit, the masking module, and the comparison module, and is used to control the working mode of the masking module and the comparison module according to the configuration information stored in the register configuration unit; The masking module is connected to the register configuration unit and the comparison module, and is used to mask data and / or events according to the masking logic preset in the configuration information stored in the register configuration unit, and send them to the comparison module; The comparison module is connected to the register configuration unit and is used to compare data and / or events according to the preset comparison logic in the configuration information stored in the register configuration unit, so as to determine whether to output data and / or events; Accordingly, the filtering logic includes the masking logic and / or the comparison logic.

2. The hardware tracking circuit according to claim 1, characterized in that, The control module further includes: a data buffer; The control module is connected to the subsystem to be tracked and is also used to cache the data and / or events sent by the subsystem to be tracked through the data buffer, so that the masking module and the comparison module can perform further filtering.

3. The hardware tracking circuit according to claim 1, characterized in that, Also includes: Information packaging unit; The information packaging unit is located between the filtering unit and the caching unit, and is also connected to the register configuration unit. It is used to package the data and / or events filtered by the filtering unit according to the preset bit width in the configuration information stored in the register configuration unit, and send them to the caching unit.

4. The hardware tracking circuit according to claim 3, characterized in that, Also includes: Timestamp generation unit; The timestamp generation unit is connected to the information packaging unit and is used to generate timestamps; The information packaging unit is further configured to, when receiving data and / or events sent by the filtering unit, obtain the timestamp corresponding to the current system time from the timestamp generation unit, and concatenate the timestamp with the data and / or events.

5. The hardware tracking circuit according to claim 4, characterized in that, The filtering unit includes a data filtering module and an event filtering module; The data filtering module is used to filter the data sent by the subsystem to be tracked according to the filtering logic stored in the register configuration unit; the event filtering module is used to filter the events sent by the subsystem to be tracked according to the filtering logic stored in the register configuration unit. Accordingly, the information packaging unit includes: a data packaging module, an event packaging module, and an error information packaging module; The data packaging module is located between the data filtering module and the caching unit, and is used to package the data filtered by the data filtering module and send it to the caching unit. The event packaging module is located between the event filtering module and the caching unit, and is used to package the events filtered by the event filtering module and send them to the caching unit. The error message packaging module is connected to the cache unit and the timestamp generation unit. It is used to receive a full signal sent by the cache unit when the cache unit is full, and to obtain the timestamp corresponding to the current system time from the timestamp generation unit; and to concatenate the full signal and the timestamp to generate error message. Accordingly, the caching unit includes: a data caching module, an event caching module, and an error information caching module; The data caching module is connected to the data packaging module and is used to cache the packaged data. The event caching module is connected to the event packaging module and is used to cache the packaged events; The error information storage module is connected to the error information packaging module and is used to cache the error information.

6. The hardware tracking circuit according to claim 5, characterized in that, Also includes: Arbitrator; The arbitrator is located between the cache unit and the protocol interface unit, and is also connected to the register configuration unit. It is used to select any one, several, or all of the cache modules from the data cache module, the event cache module, and the error information cache module according to the arbitration logic preset in the configuration information stored in the register configuration unit, and to allow the cached data and / or events, as well as error information, to be transmitted to the protocol interface unit.

7. A hardware tracking method, characterized in that, The method is applied to a hardware tracing circuit comprising a filtering unit, a register configuration unit, a cache unit, and a protocol interface unit; wherein the filtering unit is connected to the subsystem to be traced, the register configuration unit, and the cache unit; the register configuration unit is connected to the filtering unit and the protocol interface unit, and stores configuration information; the cache unit is also connected to the protocol interface unit; the protocol interface unit is also connected to the register configuration unit and an external storage device; the configuration information includes masking logic and comparison logic; the filtering unit comprises a control module, a masking module, and a comparison module. The methods include: The subsystem to be tracked is tracked to obtain the corresponding data and / or events; Data and / or events are filtered according to a preset filtering logic; specifically, the data and / or events acquired in the current cycle are compared with those acquired in the previous cycle, and if they match, the output of the data and / or events acquired in the current cycle is prohibited; based on the masking logic, specific bits in the data and / or events are masked; based on the comparison logic, the magnitude relationship between specific parameters in the data and preset reference values ​​is compared, and if the comparison conditions are not met, the corresponding data is prohibited from being output; based on the comparison logic, it is determined whether the number of times a specific signal combination occurs in the event reaches a preset threshold, and if not, the corresponding event is prohibited from being output. The filtered data and / or events are stored to the external storage device.

8. The hardware tracking method according to claim 7, characterized in that, The hardware tracking circuit further includes an arbitrator, which is disposed between the cache unit and the protocol interface unit and is also connected to the register configuration unit; the cache unit includes a data cache module, an event cache module, and an error information cache module; the configuration information includes the arbitration mode and the arbitration order or arbitration target; Correspondingly, the methods also include: The arbitrator is determined to operate in either polling arbitration mode or priority arbitration mode based on the arbitration mode described above. The polling arbitration mode includes: according to the arbitration order, sequentially obtaining and outputting the data, events, and error information stored in the data cache module, the event cache module, and the error information cache module; The priority arbitration mode includes: selecting any one of the data caching module, the event caching module, and the error information caching module according to the arbitration objective, obtaining the stored data, events, or error information therein, and outputting them.

9. A hardware tracking device, characterized in that, The method is applied to a hardware tracing circuit comprising a filtering unit, a register configuration unit, a cache unit, and a protocol interface unit; wherein the filtering unit is connected to the subsystem to be traced, the register configuration unit, and the cache unit; the register configuration unit is connected to the filtering unit and the protocol interface unit, and stores configuration information; the cache unit is also connected to the protocol interface unit; the protocol interface unit is also connected to the register configuration unit and an external storage device; the configuration information includes masking logic and comparison logic; the filtering unit comprises a control module, a masking module, and a comparison module. The device includes: The subsystem tracking module is used to track the subsystem to be tracked and acquire corresponding data and / or events; An information filtering module is used to filter data and / or events according to preset filtering logic; wherein, it compares the data and / or events acquired in the current cycle with those acquired in the previous cycle, and if they are consistent, it prohibits the output of the data and / or events acquired in the current cycle; based on the masking logic, it masks specific bits in the data and / or events; based on the comparison logic, it compares the magnitude relationship between specific parameters in the data and preset reference values, and if the comparison conditions are not met, it prohibits the output of the corresponding data; based on the comparison logic, it determines whether the number of times a specific signal combination occurs in the event reaches a preset number threshold, and if not, it prohibits the output of the corresponding event. An information storage module is used to store filtered data and / or events to the external storage device.

10. A hardware tracking device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the hardware tracing method as described in claim 7 or 8 when executing the computer program.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the hardware tracing method as described in claim 7 or 8.

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