Quantum chip quantum bit layout method, storage medium and electronic device

Abstract

The application discloses a quantum chip qubit layout method, a storage medium and an electronic device. The method comprises the following steps: acquiring the number of two-bit logic gates between each qubit of a first chip and each qubit of a second chip, denoted as a first number; determining a first lattice array for laying out qubits on the first chip and a second lattice array of laid-out qubits of the second chip, wherein the number of columns of the first lattice array and the second lattice array is equal, each lattice point in the first lattice array and the second lattice array is coupled to adjacent lattice points, the lattice points in the same column in adjacent rows of the first lattice array and the second lattice array are coupled, and the number of columns N of the first lattice array is greater than or equal to 3; and starting from the first row of the first lattice array, selecting the first number of the most qubits from the un-laid-out qubits to be laid out in each lattice point of the current row. The application can realize automatic layout of qubits of a quantum chip.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a quantum chip qubit layout method, storage medium, and electronic device. Background Technology

[0002] Currently, with the significant increase in qubit integration on quantum chips, the number of qubits that can be carried on a single chip has reached its limit. To further increase the number of qubits on quantum chips, the industry has proposed a multi-chip module (MCM) technology. This technology allows multiple chips to be assembled on the same substrate, with the chips coupled together through coupling structures, thereby achieving qubit interconnection between chips. Considering the current level of technology, a two-module chip is the easiest solution to implement.

[0003] After chip coupling, the qubit layout on the chip needs to be considered. Qubit layout is a complex and time-consuming engineering process, and manual layout design is extremely laborious and time-consuming. Therefore, there is an urgent need for a qubit layout scheme suitable for two-module chips. Summary of the Invention

[0004] The purpose of this invention is to provide a qubit layout method, storage medium, and electronic device for a two-module chip, in order to solve the problem of the lack of a qubit layout scheme for a two-module chip in the prior art. This invention enables automatic qubit layout of quantum chips, which is beneficial to the optimization of the yield and performance of quantum chips.

[0005] To address the aforementioned technical problems, this invention provides a method for qubit layout in a quantum chip, comprising:

[0006] The number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip is obtained and denoted as the first quantity;

[0007] A first lattice array for laying out qubits on the first chip and a second lattice array for laying out qubits on the second chip are determined, wherein the number of columns in the first lattice array and the second lattice array are equal, each lattice point in the first lattice array and the second lattice array is coupled to its adjacent lattice points, the lattice points in the same column in the adjacent row of the first lattice array and the second lattice array are coupled to each other, and the number of columns N of the first lattice array is ≥3.

[0008] Starting from the first row of the first lattice array, the N qubits with the largest number of unlaid qubits are selected and laid out at each lattice point in the current row, wherein the first row of the first lattice array is the row closest to the second chip.

[0009] Preferably, the step of obtaining the number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip, denoted as the first number, further includes:

[0010] Each qubit is sorted according to the first quantity order, wherein each qubit of the first chip has a unique serial number, and among multiple qubits with the same first quantity, the qubit with the smaller serial number is sorted first.

[0011] Preferably, the distance between each lattice point of the first lattice array and its adjacent lattice points, and the distance between each lattice point of the second lattice array and its adjacent lattice points, are both first preset values.

[0012] Preferably, the distance between lattice points in the same column of adjacent rows of the second lattice array and the first lattice array is a second preset value.

[0013] Preferably, the step of selecting the N largest number of qubits from the unlaid qubits and laying them out at each lattice point in the current row includes:

[0014] Determine whether N is odd or even.

[0015] If N is odd, then select the largest number of 1 qubits from the unlaid qubits and place them at the center lattice point of the current row;

[0016] Select the two lattice points closest to the center lattice point from the lattice points of the current row that do not have qubits, as the first target lattice point and the second target lattice point, wherein the first target lattice point is close to the first edge of the current row and the second target lattice point is close to the second edge of the current row;

[0017] Select the two qubits with the largest number of unlaid qubits and lay them at the first target lattice point and the second target lattice point;

[0018] Repeat the step of selecting the two lattice points closest to the center lattice point from the lattice points in the current row that are not yet filled with qubits as the first target lattice point and the second target lattice point, until all lattice points in the current row are filled with qubits.

[0019] If N is even, then select the two most central and symmetrical lattice points from the lattice points of the current row of unlaid qubits as the first target lattice point and the second target lattice point.

[0020] Repeat the steps of selecting the two largest qubits from the unlaid qubits and laying them at the first target lattice point and the second target lattice point;

[0021] Repeat the steps of selecting the two most central and symmetrical lattice points from the lattice points of the current row that have not been laid out with qubits as the first target lattice point and the second target lattice point, until all lattice points of the current row are laid out with qubits.

[0022] Preferably, the step of selecting the two qubits with the largest number from the unlaid qubits and laying them at the first target lattice point and the second target lattice point includes:

[0023] From the unplaced qubits, select the two qubits with the largest number of the first competition qubits, and denote them as the first competition qubit and the second competition qubit;

[0024] Calculate the coupling degree of the first competing qubit when it is deployed at the first target lattice point and the coupling degree when it is deployed at the second target lattice point, and calculate the coupling degree of the second competing qubit when it is deployed at the first target lattice point and the coupling degree when it is deployed at the second target lattice point.

[0025] Calculate the absolute value of the difference between the two coupling degrees of the first competing qubit and the absolute value of the difference between the two coupling degrees of the second competing qubit;

[0026] Compare the absolute value of the difference between the first competing qubit and the second competing qubit;

[0027] If the absolute value of the difference between the first competing qubits is greater than or equal to the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the first target lattice point and the second target lattice point according to the two coupling degrees of the first competing qubits.

[0028] If the absolute value of the difference between the first competing qubits is less than the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the first target lattice point and the second target lattice point according to the two coupling degrees of the second competing qubits.

[0029] The formula for calculating the coupling degree is as follows:

[0030] F = ∑ i,j f ij L ij

[0031]

[0032] Where i represents the index of the first or second competing qubit, j represents the index of the already deployed qubit, and f ij Represents the first competing qubit or the second competing qubit q i With the already deployed qubit qj The number of two-bit logic gates between them, l ij Represents the first competing qubit or the second competing qubit q i The lattice point and the already arranged qubit q j The shortest distance between the lattice points, where K2 represents the second preset value and K1 represents the first preset value.

[0033] Preferably, the step of deploying the first competing qubit and the second competing qubit at the first target lattice point and the second target lattice point according to the two coupling degrees of the first competing qubit includes:

[0034] Compare the two coupling degrees of the first competing qubit;

[0035] If the coupling degree of the first competing qubit is greater when it is deployed at the first target lattice point than when it is deployed at the second target lattice point, then the first competing qubit is deployed at the second target lattice point and the second competing qubit is deployed at the first target lattice point.

[0036] If the coupling degree of the first competing qubit when it is deployed at the first target lattice point is less than or equal to the coupling degree when it is deployed at the second target lattice point, then the first competing qubit is deployed at the first target lattice point and the second competing qubit is deployed at the second target lattice point.

[0037] Preferably, the step of deploying the first competing qubit and the second competing qubit at the first target lattice point and the second target lattice point according to the two coupling degrees of the second competing qubit includes:

[0038] Compare the two coupling degrees of the second competing qubit;

[0039] If the coupling degree of the second competing qubit is greater when it is deployed at the first target lattice point than when it is deployed at the second target lattice point, then the second competing qubit is deployed at the second target lattice point and the first competing qubit is deployed at the first target lattice point.

[0040] If the coupling degree of the second competing qubit when it is deployed at the first target lattice point is less than or equal to the coupling degree when it is deployed at the second target lattice point, then the second competing qubit is deployed at the first target lattice point and the first competing qubit is deployed at the second target lattice point.

[0041] To address the aforementioned technical problems, the present invention also provides a storage medium storing a computer program configured to execute the qubit layout method of the quantum chip described in any of the preceding claims when running.

[0042] To address the aforementioned technical problems, the present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the qubit layout method of the quantum chip described in any of the preceding claims.

[0043] Unlike existing technologies, the quantum chip qubit layout method provided by this invention obtains the number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip, denoted as the first quantity. Then, it determines the first lattice array on the first chip used for qubit layout and the second lattice array on the second chip where qubits have already been laid out. Finally, in each row of the first lattice array, it selects the N qubits with the largest first quantity from the unlaid qubits and lays them out at each lattice point in the current row. The layout process takes into account the coupling of qubits between different chips, thereby enabling automatic qubit layout of the quantum chip, which is beneficial to the optimization of the yield and performance of the quantum chip.

[0044] The storage medium and electronic device provided by this invention belong to the same inventive concept as the qubit layout method of quantum chips, and therefore have the same beneficial effects, which will not be repeated here. Attached Figure Description

[0045] Figure 1 This is a flowchart illustrating the qubit layout method for a quantum chip provided in the first embodiment of the present invention.

[0046] Figure 2 A quantum circuit diagram with 4 qubits.

[0047] Figure 3 This is a schematic diagram of the coupling strength matrix obtained from a 4-qubit quantum circuit diagram.

[0048] Figure 4 This is a schematic diagram of the physical layer of the first lattice array.

[0049] Figure 5 This is a schematic diagram of the coupling strength matrix obtained from an 18-qubit quantum circuit diagram.

[0050] Figure 6 A schematic diagram showing the arrangement of qubits in the first lattice array.

[0051] Figure 7 This is a schematic diagram of the specific process of step S3 in the quantum bit layout method of the quantum chip provided in the second embodiment of the present invention.

[0052] Figure 8 for Figure 7 The flowchart shown illustrates the specific process of step S34 in the process diagram.

[0053] Figure 9 for Figure 8 The flowchart shown is a detailed diagram of step S345 in the process.

[0054] Figure 10 for Figure 8 The flowchart shown illustrates the specific process of step S346 in the process diagram. Detailed Implementation

[0055] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0056] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0058] Please refer to Figure 1 The first embodiment of the present invention provides a method for qubit layout of a quantum chip, the method comprising the following steps:

[0059] S1: Obtain the number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip, denoted as the first number.

[0060] The first quantity can be obtained through a quantum circuit diagram composed of qubits on the first chip and qubits on the second chip. For example... Figure 2The diagram shown is a 4-qubit quantum circuit diagram. Qubits q1 and q2 are on the first chip, and qubits q3 and q4 are on the second chip. From the quantum circuit diagram, the number of two-bit logic gates (for ease of description, all two-bit logic gates in the diagram are CNOT gates) between each qubit (q1, q2, q3, q4) can be obtained, thus constructing a coupling strength matrix. This matrix is ​​as follows: Figure 3 As shown, this matrix is ​​a symmetric matrix that reflects the number of two-bit logic gates between different qubits. By summing the columns of the matrix, we can obtain the number of two-bit logic gates between each qubit and all other qubits, including the number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip. For example, the number of two-bit gates between qubit q1 and qubits q3 and q4 is 0, and the number of two-bit gates between qubit q2 and qubits q3 and q4 is also 0.

[0061] S2: Determine the first lattice array on the first chip for laying out qubits and the second lattice array on the second chip for laying out qubits, wherein the number of columns in the first lattice array and the second lattice array are equal, each lattice point in the first lattice array and the second lattice array is coupled to its adjacent lattice points, the lattice points in the same column in the adjacent rows of the first lattice array and the second lattice array are coupled to each other, and the number of columns N of the first lattice array is ≥3.

[0062] Among them, such as Figure 4 As shown, the first lattice array includes 9 lattice points arranged in 3 rows × 3 columns. Circles in the figure represent lattice points, and dashed lines represent coupling connections.

[0063] S3: Starting from the first row of the first lattice array, select the N qubits with the largest number of unlaid qubits and lay them out in each lattice point of the current row, where the first row of the first lattice array is the row closest to the second chip.

[0064] For example, such as Figure 5 The figure shows the coupling strength matrix obtained from an 18-qubit quantum circuit diagram. q10 to q18 are the qubits on the first chip, and q1 to q9 are the qubits on the second chip. Based on the coupling strength matrix, the first number of qubits on the first chip is shown in Table 1.

[0065] Table 1. First number of qubits on the first chip.

[0066] q13 16 q10 10 q11 7 q12 6 q15 6 q18 6 q14 4 q17 4 q16 2

[0067] Both the first and second lattice arrays are 3×3 arrays. The three most numerous qubits, q10, q11, and q13, are placed in the first row of the first lattice array; q12, q15, and q18 are placed in the second row; and q14, q17, and q16 are placed in the third row. After placement, the qubit arrangement of the first lattice array is as follows: Figure 6 As shown, for ease of description, the first lattice array is represented by a grid, and the dashed lines in the figure represent the coupling connection between the wafers. It can be seen from the figure that only the lattice points in the same column of adjacent rows of the first and second lattice arrays are coupled.

[0068] In this embodiment, the step of obtaining the number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip, denoted as the first number, i.e., step S1 further includes:

[0069] Each qubit is sorted according to the first quantity order, wherein each qubit of the first chip has a unique serial number, and among multiple qubits with the same first quantity, the qubit with the smaller serial number is sorted first.

[0070] in, Figure 5 The qubits of the first chip shown are numbered from 10 to 18. In Table 1, among the qubits of the same number, the qubits with smaller numbers are ranked earlier, for example, qubit q12 is ranked before qubit q15, and qubit q14 is ranked before qubit q17.

[0071] Please refer to Figure 7 The second embodiment of the present invention provides a qubit layout method for a quantum chip. This qubit layout method is based on the first embodiment and includes all the technical features of the first embodiment. In addition, in this embodiment, the distance between each lattice point in the first lattice array and its adjacent lattice points, and the distance between each lattice point in the second lattice array and its adjacent lattice points, are both first preset values. If the first lattice array is a 3×3 array, then the distance between the center lattice point of the middle row and any other lattice point is both the first preset value, and the shortest distance between any two lattice points in the first and third rows is both the first preset value × 2.

[0072] The distances between lattice points in the same column of adjacent rows of the second lattice array and the first lattice array are both set to a second preset value. This second preset value is determined by the inter-chip coupling structure between the first and second chips.

[0073] In this embodiment, the step of selecting the largest number of N qubits from the unlaid qubits and laying them out at each lattice point in the current row, i.e., step S3, includes:

[0074] S31: Determine whether N is odd or even.

[0075] S32: If N is odd, select the largest number of 1 qubit from the unlaid qubits and place it at the center lattice point of the current row.

[0076] S33: Select the two lattice points closest to the center lattice point from the lattice points of the current row that are not laid out with qubits as the first target lattice point and the second target lattice point, wherein the first target lattice point is close to the first edge of the current row and the second target lattice point is close to the second edge of the current row.

[0077] S34: Select the two qubits with the largest number of unlaid qubits and place them at the first target lattice point and the second target lattice point.

[0078] S35: Repeat the step of selecting the two lattice points closest to the center lattice point from the lattice points of the current row that have not been laid out with qubits as the first target lattice point and the second target lattice point, until all lattice points of the current row are laid out with qubits.

[0079] For example, when N is 3, the qubit with the largest number of qubits is placed at the center lattice point of the current row of the first lattice array. In this example, the first target lattice point is the lattice point on the left edge of the current row, and the second target lattice point is the lattice point on the right edge of the current row. The two qubits with the largest number of qubits from the unplaced qubits are then placed at the first target lattice point and the second target lattice point. At this point, all lattice points in the current row are filled with qubits.

[0080] For example, when N is 5, the most numerous qubit is placed at the center lattice point of the current row of the first lattice array. The first target lattice point is the lattice point to the left of the center lattice point, and the second target lattice point is the lattice point to the right of the center lattice point. The two most numerous qubits from the unplaced qubits are then selected and placed at the first and second target lattice points. This process is repeated, selecting new first and second target lattice points, with the new first target lattice point being the lattice point at the left edge of the current row and the new second target lattice point at the right edge of the current row. This process is repeated again, selecting the two most numerous qubits from the unplaced qubits and placing them at the first and second target lattice points. At this point, all lattice points in the current row are filled with qubits. For example, if the five qubits with the largest number of qubits are q12, q15, q14, q18, and q11, then q12 is located at the center lattice point in the first row, q15 and q14 are located at the lattice points on the left and right sides of the center lattice point, and q18 and q11 are located at the outermost lattice points on the left and right sides.

[0081] S36: If N is even, select the two most central and symmetrical lattice points from the lattice points of the current row that are not laid out with qubits as the first target lattice point and the second target lattice point.

[0082] S37: Repeat the steps of selecting the two largest qubits from the unlaid qubits and laying them at the first target lattice point and the second target lattice point.

[0083] S38: Repeat the step of selecting the two most central and symmetrical lattice points from the lattice points of the current row that have not been laid out with qubits as the first target lattice point and the second target lattice point, until all lattice points of the current row are laid out with qubits.

[0084] For example, when N is 4, the first target lattice point and the second target lattice point are the two middle lattice points in the current row of the second lattice array. The two qubits with the highest number of qubits are placed on the first target lattice point and the second target lattice point. Then, new first target lattice points and second target lattice points are selected, with the new first target lattice point being the lattice point on the left edge of the current row and the new second target lattice point being the lattice point on the right edge of the current row. This process is repeated, selecting the two qubits with the highest number of qubits from the unplaced qubits and placing them on the first target lattice point and the second target lattice point. At this point, all lattice points in the current row are filled with qubits.

[0085] Please refer to Figure 8 The third embodiment of the present invention provides a qubit layout method for a quantum chip. This qubit layout method is based on the qubit layout method of the second embodiment and includes all the technical features of the second embodiment. In addition, in this embodiment, the step of selecting the two qubits with the largest number from the un-laid-out qubits and placing them at the first target lattice point and the second target lattice point, i.e., step S34, includes:

[0086] S341: Select the two qubits with the largest number of unplaced qubits, and denot them as the first competing qubit and the second competing qubit.

[0087] Among them, with Figure 5 The coupling strength matrix shown is illustrated using a 3×3 lattice array as an example. The arrangement of qubits in the second lattice array is as follows: Figure 6 As shown, the center lattice point of the first row of the first lattice array is positioned with qubit q13. The two qubits with the highest number of unpositioned qubits are q10 and q11. Here, q10 is designated as the first competing qubit, and q11 as the second competing qubit. The lattice point to the left of the center lattice point in the first row of the first lattice array is the first target lattice point, and the lattice point to the right of the center lattice point is the second target lattice point.

[0088] S342: Calculate the coupling degree of the first competing qubit when positioned at the first target lattice point and the coupling degree when positioned at the second target lattice point, as well as the coupling degree of the second competing qubit when positioned at the first target lattice point and the coupling degree when positioned at the second target lattice point. The formula for calculating the coupling degree is:

[0089] F = ∑ i,j f ij L ij

[0090]

[0091] Where i represents the index of the first or second competing qubit, j represents the index of the already deployed qubit, and f ij Represents the first competing qubit or the second competing qubit q i With the already deployed qubit q j The number of two-bit logic gates between them, l ij Represents the first competing qubit or the second competing qubit q i The lattice point and the already arranged qubit q j The shortest distance between the lattice points, where K2 represents the second preset value and K1 represents the first preset value.

[0092] In this example, for ease of calculation, let the first preset value be 1 and the second preset value be 2.

[0093] The formula for calculating the coupling degree when the first competing qubit q10 is positioned at the first target lattice point is: Except for the first competing qubit q10 and qubit q13, which are located on the first chip, the first competing qubit q10 is located on a different chip than qubits q1 to q9. Therefore, the shortest distance between the first competing qubit q10 and qubits q1 to q9 is l. ij +K2-K1, i.e., l ij +1, in calculating l ij When the first lattice array and the second lattice array are equivalent to a single array, that is, when the first lattice array and the second lattice array are joined together to form a single array, for example, when calculating L... 10,1 At that time, L 10,1 =l 10,1 +1, In the equivalent array, the shortest distance between the first competing qubit q10 and qubit q2 is 1, and the shortest distance between qubit q2 and qubit q1 is 2. Therefore, l 10,1 =3, then L 10,1 =l 10,1 +1 = 4.

[0094] The coupling degree of the first competing qubit q10 when positioned at the first target lattice point

[0095] The second coupling degree when the first competing quantum bit q10 is positioned at the second target lattice point

[0096] The second coupling degree when the second competing quantum bit q11 is deployed at the first target lattice point

[0097] The second coupling degree when the second competing quantum bit q11 is deployed at the second target lattice point

[0098] S343: Calculate the absolute value of the difference between the two coupling degrees of the first competing qubit and the absolute value of the difference between the two coupling degrees of the second competing qubit.

[0099] The absolute value of the difference between the two coupling degrees of the first competing qubit q10 is |F L -F R |=|36-35|=1, the absolute value of the difference between the two first coupling degrees of the second competing qubit q9 is |F L -F R |=|22-27|=5.

[0100] S344: Compare the absolute value of the difference between the first competing qubit and the second competing qubit.

[0101] Among them, the absolute value of the difference between the first competing qubit q10 and q11 is 1, which is less than the absolute value of the difference between the second competing qubit q11 and q11.

[0102] S345: If the absolute value of the difference between the first competing qubits is greater than or equal to the absolute value of the difference between the second competing qubits, then the first competing qubit and the second competing qubit are arranged at the first target lattice point and the second target lattice point according to the two coupling degrees of the first competing qubit.

[0103] S346: If the absolute value of the difference between the first competing qubits is less than the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the first target lattice point and the second target lattice point according to the two coupling degrees of the second competing qubits.

[0104] Since the absolute value of the difference between the first competing qubit q10 and the second competing qubit q11 is smaller than the absolute value of the difference between the two competing qubits q11, the qubit layout of the lattice points at the two edges of the current row will be determined according to the magnitude of the two coupling degrees of the second competing qubit q11.

[0105] Specifically, please refer to Figure 9 The step of deploying the first competing qubit and the second competing qubit at the first target lattice point and the second target lattice point according to the two coupling degrees of the first competing qubit, i.e., step S345, includes:

[0106] S3451: Compare the two coupling degrees of the first competing qubit.

[0107] S3452: If the coupling degree of the first competing qubit when it is laid out at the first target lattice point is greater than that when it is laid out at the second target lattice point, then the first competing qubit is laid out at the second target lattice point and the second competing qubit is laid out at the first target lattice point.

[0108] S3453: If the coupling degree of the first competing qubit when it is laid out at the first target lattice point is less than or equal to the coupling degree when it is laid out at the second target lattice point, then the first competing qubit is laid out at the first target lattice point and the second competing qubit is laid out at the second target lattice point.

[0109] If the absolute value of the difference between the first competing qubit q10 and the second competing qubit q11 is greater than or equal to the absolute value of the difference between the two competing qubits q10, then the two coupling degrees of the first competing qubit q10 are compared. If the coupling degree of the first competing qubit q10 when it is placed at the first target lattice point is greater than the coupling degree when it is placed at the second target lattice point, the first competing qubit q10 is placed at the second target lattice point (i.e., the right edge lattice point), and the second competing qubit q11 is placed at the first target lattice point (i.e., the left edge lattice point).

[0110] If the coupling degree of the first competing qubit q10 when it is placed at the first target lattice point is less than or equal to the coupling degree when it is placed at the second target lattice point, the first competing qubit q10 is placed at the first target lattice point (i.e., the left edge lattice point), and the second competing qubit q11 is placed at the second target lattice point (i.e., the right edge lattice point).

[0111] Please refer to Figure 10 The step of deploying the first and second competing qubits at the first and second target lattice points according to the two coupling degrees of the second competing qubit, i.e., step S346, includes:

[0112] S3461: Compare the two coupling degrees of the second competing qubit;

[0113] S3462: If the coupling degree of the second competing qubit when it is laid out at the first target lattice point is greater than that when it is laid out at the second target lattice point, then the second competing qubit is laid out at the second target lattice point and the first competing qubit is laid out at the first target lattice point.

[0114] S3463: If the coupling degree of the second competing qubit when it is laid out at the first target lattice point is less than or equal to the coupling degree when it is laid out at the second target lattice point, then the second competing qubit is laid out at the first target lattice point and the first competing qubit is laid out at the second target lattice point.

[0115] In this example, the coupling degree F when the second competing qubit q11 is positioned at the first target lattice point is calculated as follows: L =22 is less than the coupling degree F when it is arranged at the second target lattice point. R =27, the second competing qubit q11 is placed at the first target lattice point (i.e., the left edge lattice point), and the first competing qubit q10 is placed at the second target lattice point (i.e., the right edge lattice point).

[0116] If the coupling degree of the second competing qubit q11 when it is placed at the first target lattice point is greater than that when it is placed at the second target lattice point, the second competing qubit q11 is placed at the second target lattice point (i.e., the right edge lattice point), and the first competing qubit q10 is placed at the first target lattice point (i.e., the left edge lattice point).

[0117] The second and third rows of the first lattice array are also arranged with qubits according to the above process. The final qubit arrangement of the first lattice array is as follows: Figure 6 As shown.

[0118] The present invention also provides a storage medium storing a computer program configured to execute, when running, the qubit layout method of the quantum chip of the first embodiment, the second embodiment, or the third embodiment.

[0119] Specifically, in this embodiment, the storage medium may include, but is not limited to, USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks, and other media capable of storing computer programs.

[0120] The present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to execute a quantum bit layout method of a quantum chip according to a first embodiment, a second embodiment, or a third embodiment.

[0121] Specifically, the memory and processor can be connected via a data bus. Furthermore, the aforementioned electronic device may also include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0122] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0123] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for qubit layout in a quantum chip, characterized in that, include: The number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip is obtained and denoted as the first quantity; A first lattice array for laying out qubits on the first chip and a second lattice array for laying out qubits on the second chip are determined, wherein the number of columns in the first lattice array and the second lattice array are equal, each lattice point in the first lattice array and the second lattice array is coupled to its adjacent lattice points, the lattice points in the same column in the adjacent row of the first lattice array and the second lattice array are coupled to each other, and the number of columns N of the first lattice array is ≥3. Starting from the first row of the first lattice array, the N qubits with the largest number of unlaid qubits are selected and laid out at each lattice point in the current row, wherein the first row of the first lattice array is the row closest to the second chip.

2. The qubit layout method according to claim 1, characterized in that, The step of obtaining the number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip, denoted as the first number, further includes: Each qubit is sorted according to the first quantity order, wherein each qubit of the first chip has a unique serial number, and among multiple qubits with the same first quantity, the qubit with the smaller serial number is sorted first.

3. The qubit layout method according to claim 2, characterized in that, The distance between each lattice point of the first lattice array and its adjacent lattice points, and the distance between each lattice point of the second lattice array and its adjacent lattice points, are both first preset values.

4. The qubit layout method according to claim 3, characterized in that, The distances between lattice points in the same column of adjacent rows of the second lattice array and the first lattice array are all second preset values.

5. The qubit layout method according to claim 4, characterized in that, The step of selecting the N qubits with the largest number from the unlaid qubits and laying them out at each lattice point in the current row includes: Determine whether N is odd or even. If N is odd, then select the largest number of 1 qubits from the unlaid qubits and place them at the center lattice point of the current row; Select the two lattice points closest to the center lattice point from the lattice points of the current row that do not have qubits, as the first target lattice point and the second target lattice point, wherein the first target lattice point is close to the first edge of the current row and the second target lattice point is close to the second edge of the current row; Select the two qubits with the largest number of unlaid qubits and lay them at the first target lattice point and the second target lattice point; Repeat the step of selecting the two lattice points closest to the center lattice point from the lattice points in the current row that are not yet filled with qubits as the first target lattice point and the second target lattice point, until all lattice points in the current row are filled with qubits. If N is even, then select the two most central and symmetrical lattice points from the lattice points of the current row of unlaid qubits as the first target lattice point and the second target lattice point. Repeat the steps of selecting the two largest qubits from the unlaid qubits and laying them at the first target lattice point and the second target lattice point; Repeat the steps of selecting the two most central and symmetrical lattice points from the lattice points of the current row that have not been laid out with qubits as the first target lattice point and the second target lattice point, until all lattice points of the current row are laid out with qubits.

6. The qubit layout method according to claim 5, characterized in that, The step of selecting the two qubits with the largest number from the unlaid qubits and laying them at the first target lattice point and the second target lattice point includes: Select the two qubits with the largest number of unplaced qubits and denote them as the first competing qubit and the second competing qubit. Calculate the coupling degree of the first competing qubit when it is deployed at the first target lattice point and the coupling degree when it is deployed at the second target lattice point, and calculate the coupling degree of the second competing qubit when it is deployed at the first target lattice point and the coupling degree when it is deployed at the second target lattice point. Calculate the absolute value of the difference between the two coupling degrees of the first competing qubit and the absolute value of the difference between the two coupling degrees of the second competing qubit; Compare the absolute value of the difference between the first competing qubit and the second competing qubit; If the absolute value of the difference between the first competing qubits is greater than or equal to the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the first target lattice point and the second target lattice point according to the two coupling degrees of the first competing qubits. If the absolute value of the difference between the first competing qubits is less than the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the first target lattice point and the second target lattice point according to the two coupling degrees of the second competing qubits. The formula for calculating the coupling degree is as follows: Where i represents the index of the first or second competing qubit, j represents the index of the already deployed qubit, and f ij Represents the first competing qubit or the second competing qubit q i With the already deployed qubit q j The number of two-bit logic gates between them, l ij Represents the first competing qubit or the second competing qubit q i The lattice point and the already arranged qubits q j The shortest distance between the lattice points, where K2 represents the second preset value and K1 represents the first preset value.

7. The qubit layout method according to claim 6, characterized in that, The step of deploying the first competing qubit and the second competing qubit at the first target lattice point and the second target lattice point according to the two coupling degrees of the first competing qubit includes: Compare the two coupling degrees of the first competing qubit; If the coupling degree of the first competing qubit is greater when it is deployed at the first target lattice point than when it is deployed at the second target lattice point, then the first competing qubit is deployed at the second target lattice point and the second competing qubit is deployed at the first target lattice point. If the coupling degree of the first competing qubit when it is deployed at the first target lattice point is less than or equal to the coupling degree when it is deployed at the second target lattice point, then the first competing qubit is deployed at the first target lattice point and the second competing qubit is deployed at the second target lattice point.

8. The qubit layout method according to claim 7, characterized in that, The step of deploying the first competing qubit and the second competing qubit at the first target lattice point and the second target lattice point according to the two coupling degrees of the second competing qubit includes: Compare the two coupling degrees of the second competing qubit; If the coupling degree of the second competing qubit is greater when it is deployed at the first target lattice point than when it is deployed at the second target lattice point, then the second competing qubit is deployed at the second target lattice point and the first competing qubit is deployed at the first target lattice point. If the coupling degree of the second competing qubit when it is deployed at the first target lattice point is less than or equal to the coupling degree when it is deployed at the second target lattice point, then the second competing qubit is deployed at the first target lattice point and the first competing qubit is deployed at the second target lattice point.

9. A storage medium, characterized in that, The storage medium stores a computer program, which is configured to execute the qubit layout method of the quantum chip according to any one of claims 1 to 8 when it runs.

10. An electronic device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the qubit layout method of the quantum chip according to any one of claims 1 to 8.

Images