Quantum bit layout method for two-module chip, storage medium and electronic device

Abstract

The application discloses a kind of quantum bit layout method of two module chips, storage medium and electronic equipment.The method comprises: determining the first lattice array on the first chip and the quantum bit to be laid out;Obtain the number of two-bit logic gates between each quantum bit and other quantum bits of the first chip, denoted as the first number, and obtain the number of two-bit logic gates between each quantum bit of the first chip and each quantum bit of the second chip, denoted as the second number;Select the N quantum bits with the most second number and layout in the first row of the first lattice array;In the current row after the first row, select the N-2 quantum bits with the most first number from the un-laid quantum bits and layout in other lattice points except the two edge lattice points in the current row;Select the 2 quantum bits with the most second number from the un-laid quantum bits and layout in the two edge lattice points of the current row.The application can realize the automatic layout of quantum bits of two module chips.

Description

Technical Field

[0001] This invention relates to the field of computer information technology, and in particular to a method for qubit layout of a two-module chip, a storage medium, and an electronic device. Background Technology

[0002] Currently, with the significant increase in qubit integration on quantum chips, the number of qubits that can be carried on a single chip has reached its limit. To further increase the number of qubits on quantum chips, the industry has proposed a multi-chip module (MCM) technology. This technology allows multiple chips to be assembled on the same substrate, with the chips coupled together through coupling structures, thereby achieving qubit interconnection between chips. Considering the current level of technology, a two-module chip is the easiest solution to implement.

[0003] After chip coupling, the qubit layout on the chip needs to be considered. Qubit layout is a complex and time-consuming engineering process, and manual layout design is extremely laborious and time-consuming. Therefore, there is an urgent need for a qubit layout scheme suitable for two-module chips. Summary of the Invention

[0004] The purpose of this invention is to provide a qubit layout method, storage medium, and electronic device for two-module chips, so as to solve the problem of the lack of qubit layout schemes for two-module chips in the prior art. It can realize automatic qubit layout of two-module chips, which is beneficial to the optimization of the yield and performance of two-module chips.

[0005] To address the aforementioned technical problems, this invention provides a qubit layout method for a two-module chip, wherein the two-module chip includes a first chip and a second chip coupled to each other, and the qubit layout method includes:

[0006] The first lattice array on the first chip for laying out qubits and the qubits to be laid out on the first chip are determined. The first lattice array includes multiple lattice points arranged in M ​​rows × N columns, and each lattice point of the first lattice array is coupled to its adjacent lattice points, N≥3, M≥2.

[0007] The number of two-bit logic gates between each qubit of the first chip and other qubits is obtained, denoted as the first number; and the number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip is obtained, denoted as the second number.

[0008] The N qubits with the largest second quantity are selected and arranged in the first row of the first lattice array, wherein the first row of the first lattice array is the row closest to the second chip;

[0009] In the current row following the first row, select the N-2 qubits with the largest number of unlaid qubits and lay them out in the current row except for the lattice points at the two edges;

[0010] Select the two qubits with the highest second number from the unplaced qubits and place them at the lattice points on both edges of the current row.

[0011] Preferably, the steps of obtaining the number of two-bit logic gates between each qubit of the first chip and other qubits, denoted as the first number, and obtaining the number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip, denoted as the second number, further include:

[0012] Each qubit is sorted according to the first quantity order and the second quantity order, wherein each qubit of the first chip has a unique serial number, and among multiple qubits with the same first or second quantity, the qubit with the smaller serial number is sorted first.

[0013] Preferably, the step of selecting the N qubits with the largest second quantity to be arranged in the first row of the first lattice array includes:

[0014] Determine whether N is odd or even.

[0015] If N is odd, then select the 1 qubit with the largest second number and place it at the center lattice point of the first row of the first lattice array. Also, select N-1 qubits with the largest second number from the unplaced qubits and place them at the other lattice points of the first row in sequence. The closer the qubit is to the center lattice point, the greater the second number of qubits.

[0016] If N is even, the two qubits with the largest second number are selected and placed in the two middle lattice points of the first row of the first lattice array. The N-2 qubits with the largest second number are selected from the unplaced qubits and placed in the other lattice points of the first row. The closer the lattice point is to the middle, the greater the second number of qubits.

[0017] Preferably, the step of selecting the largest number of N-2 qubits from the unlaid qubits and laying them out at the lattice points in the current row, excluding the two edge lattice points, includes:

[0018] When N is odd, the 1 qubit with the largest number of the first type is selected from the unplaced qubits and placed at the center lattice point of the current row, and N-3 qubits with the largest number of the first type are selected from the unplaced qubits and placed at the other lattice points in the current row except for the two edge lattice points. The number of qubits is greater closer to the center lattice point.

[0019] When N is even, the two qubits with the largest number of the first type selected from the unplaced qubits are placed at the two middle lattice points of the current row, and the N-4 qubits with the largest number of the first type selected from the unplaced qubits are sequentially placed at the other lattice points in the current row except for the two edge lattice points, wherein the number of qubits is greater the closer to the middle lattice point.

[0020] Preferably, the distance between each lattice point of the first lattice array and its adjacent lattice points is a first preset value.

[0021] Preferably, the step of selecting the two qubits with the largest number from the unlaid qubits and laying them at the lattice points on both edges of the current row includes:

[0022] From the unplaced qubits, select the two qubits with the largest second number, and denot them as the first competing qubit and the second competing qubit;

[0023] Calculate the first coupling degree when the first competing qubit is arranged at the first edge lattice point of the current row and the first coupling degree when it is arranged at the second edge lattice point of the current row, and calculate the first coupling degree when the second competing qubit is arranged at the first edge lattice point and the first coupling degree when it is arranged at the second edge lattice point;

[0024] Calculate the absolute value of the difference between the two first coupling degrees of the first competing qubit and the absolute value of the difference between the two first coupling degrees of the second competing qubit;

[0025] Compare the absolute value of the difference between the first competing qubit and the second competing qubit;

[0026] If the absolute value of the difference between the first competing qubits is greater than or equal to the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the lattice points on the two edges of the current row according to the magnitude of the two first coupling degrees of the first competing qubits.

[0027] If the absolute value of the difference between the first competing qubits is less than the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the lattice points on the two edges of the current row according to the magnitude of the two first coupling degrees of the second competing qubits.

[0028] The formula for calculating the first coupling degree is as follows:

[0029] F1=∑ i,j f ij l ij

[0030] Where i represents the index of the first or second competing qubit, j represents the index of the already deployed qubit, and f ij Represents the first competing qubit or the second competing qubit q i With the already deployed qubit q j The number of two-bit logic gates between them, l ij Represents the first competing qubit or the second competing qubit q i The lattice point and the already arranged qubit q j The shortest distance between the points in the lattice.

[0031] Preferably, the step of arranging the first competing qubit and the second competing qubit at the lattice points on both edges of the current row according to the two first coupling degrees of the first competing qubit includes:

[0032] Compare the first coupling degrees of the two competing qubits;

[0033] If the first coupling degree when the first competing qubit is disposed at the first edge lattice point is greater than the first coupling degree when it is disposed at the second edge lattice point, then the first competing qubit is disposed at the second edge lattice point and the second competing qubit is disposed at the first edge lattice point.

[0034] If the first coupling degree when the first competing qubit is disposed at the first edge lattice point is less than or equal to the first coupling degree when disposed at the second edge lattice point, then the first competing qubit is disposed at the first edge lattice point and the second competing qubit is disposed at the second edge lattice point.

[0035] Preferably, the step of arranging the first competing qubit and the second competing qubit at the lattice points on both edges of the current row according to the two first coupling degrees of the second competing qubit includes:

[0036] Compare the two first coupling degrees of the second competing qubit;

[0037] If the first coupling degree when the second competing qubit is disposed at the first edge lattice point is greater than the first coupling degree when disposed at the second edge lattice point, then the second competing qubit is disposed at the second edge lattice point and the first competing qubit is disposed at the first edge lattice point.

[0038] If the first coupling degree of the second competing qubit when it is disposed at the first edge lattice point is less than or equal to the first coupling degree when it is disposed at the second edge lattice point, then the second competing qubit is disposed at the first edge lattice point and the first competing qubit is disposed at the second edge lattice point.

[0039] Preferably, the qubit layout method further includes:

[0040] The second lattice array for laying out qubits on the second chip and the qubits to be laid out on the second chip are determined. The second lattice array includes multiple lattice points arranged in L rows × N columns, and each lattice point of the second lattice array is coupled to its adjacent lattice points. The second lattice array is coupled to the lattice points in the same column of the adjacent row of the first lattice array, where L≥1.

[0041] The number of two-bit logic gates between each quantum bit of the second chip and each quantum bit of the first chip is obtained and denoted as the third number.

[0042] Starting from the first row of the second lattice array, the N qubits with the largest number of unplaced qubits are selected and placed at each lattice point in the current row, wherein the first row of the second lattice array is the row closest to the first chip.

[0043] Preferably, the step of obtaining the number of two-bit logic gates between each qubit of the second chip and each qubit of the first chip, denoted as the third number, further includes:

[0044] Each qubit is sorted according to the third order of quantity, wherein each qubit of the second chip has a unique serial number, and among multiple qubits with the same third quantity, the qubit with the smaller serial number is sorted first.

[0045] Preferably, the distance between each lattice point of the second lattice array and its adjacent lattice points is the first preset value, and the distance between lattice points in the same column of adjacent rows of the second lattice array and the first lattice array is the second preset value.

[0046] Preferably, the step of selecting the N qubits with the largest number from the unlaid qubits and laying them out at each lattice point in the current row includes:

[0047] When N is odd, the third largest number of 1 qubit is selected from the unplaced qubits and placed at the center lattice point of the current row.

[0048] Select the two lattice points closest to the center lattice point from the lattice points of the current row that do not have qubits, as the first target lattice point and the second target lattice point, wherein the first target lattice point is close to the first edge of the current row and the second target lattice point is close to the second edge of the current row;

[0049] Select the two qubits with the largest number of unplaced qubits and place them on the first target lattice point and the second target lattice point. Repeat the step of selecting the two lattice points closest to the center lattice point from the lattice points of the current row that have no qubits placed as the first target lattice point and the second target lattice point, until all lattice points of the current row have qubits placed.

[0050] When N is even, select two lattice points that are close to the center and symmetrical to the center of the current row from the lattice points of the unlaid qubits in the current row as the first target lattice point and the second target lattice point.

[0051] Repeat the step of selecting the two largest qubits from the unlaid qubits and laying them on the first target lattice point and the second target lattice point, and repeat the step of selecting two lattice points that are close to the middle and relatively symmetrical to the center of the current row from the lattice points of the unlaid qubits in the current row as the first target lattice point and the second target lattice point, until all lattice points in the current row are laid with qubits.

[0052] Preferably, the step of selecting the two qubits with the largest number from the unlaid qubits and laying them at the first target lattice point and the second target lattice point includes:

[0053] Select the two qubits with the largest number of the third type from the qubits that have not been deployed, and denote them as the new first and second competing qubits.

[0054] Calculate the second coupling degree when the first competing qubit is deployed at the first target lattice point and the second coupling degree when it is deployed at the second target lattice point, and calculate the second coupling degree when the second competing qubit is deployed at the first target lattice point and the second coupling degree when it is deployed at the second target lattice point;

[0055] Calculate the absolute value of the difference between the two second coupling degrees of the first competing qubit and the absolute value of the difference between the two second coupling degrees of the second competing qubit;

[0056] Compare the absolute value of the difference between the first competing qubit and the second competing qubit;

[0057] If the absolute value of the difference between the first competing qubits is greater than or equal to the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the first target lattice point and the second target lattice point according to the magnitude of the two second coupling degrees of the first competing qubits.

[0058] If the absolute value of the difference between the first competing qubits is less than the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the first target lattice point and the second target lattice point according to the magnitude of the two second coupling degrees of the second competing qubits.

[0059] The formula for calculating the second degree of coupling is as follows:

[0060] F2=∑ i,j f ij L ij

[0061]

[0062] Where K2 represents the second preset value and K1 represents the first preset value.

[0063] Preferably, the step of deploying the first competing qubit and the second competing qubit at the first target lattice point and the second target lattice point according to the magnitude of the two second coupling degrees of the first competing qubit includes:

[0064] Compare the two second coupling degrees of the first competing qubit;

[0065] If the second coupling degree when the first competing qubit is deployed at the first target lattice point is greater than the second coupling degree when deployed at the second target lattice point, then the first competing qubit is deployed at the second target lattice point and the second competing qubit is deployed at the first target lattice point.

[0066] If the second coupling degree of the first competing qubit when it is deployed at the first target lattice point is less than or equal to the second coupling degree when it is deployed at the second target lattice point, then the first competing qubit is deployed at the first target lattice point and the second competing qubit is deployed at the second target lattice point.

[0067] Preferably, the step of deploying the first competing qubit and the second competing qubit at the first target lattice point and the second target lattice point according to the two second coupling degrees of the second competing qubit includes:

[0068] Compare the two second coupling degrees of the second competing qubit;

[0069] If the second coupling degree when the second competing qubit is disposed at the first target lattice point is greater than the second coupling degree when disposed at the second target lattice point, then the second competing qubit is disposed at the second target lattice point and the first competing qubit is disposed at the first target lattice point.

[0070] If the second coupling degree when the second competing qubit is disposed at the first target lattice point is less than or equal to the second coupling degree when disposed at the second target lattice point, then the second competing qubit is disposed at the first target lattice point and the second competing qubit is disposed at the second target lattice point.

[0071] To address the aforementioned technical problems, the present invention also provides a storage medium storing a computer program configured to execute the qubit layout method for the two-module chip described in any of the preceding claims during runtime.

[0072] To address the aforementioned technical problems, the present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the qubit layout method of the two-module chip described in any of the preceding claims.

[0073] Unlike existing technologies, the qubit layout method for two-module chips provided by this invention determines the first lattice array (M rows × N columns) on the first chip and the qubits to be laid out on the first chip. It obtains the number of two-bit logic gates between each qubit of the first chip and other qubits, and the number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip, denoted as the first quantity and the second quantity, respectively. When laying out the qubits, firstly, the N qubits with the largest second quantity are selected and placed in the first row of the first lattice array closest to the second chip. Then, the N-2 qubits with the largest first quantity are selected from the unlaid qubits and placed in the other rows after the first row, except for the lattice points on the two edges. Finally, the 2 qubits with the largest second quantity are selected from the unlaid qubits and placed in the lattice points on the two edges. The layout process takes into account both the coupling of qubits between different chips and the coupling between different qubits within the chip, thereby enabling automatic qubit layout of two-module chips, which is beneficial to the optimization of the yield and performance of the two-module chips.

[0074] The storage medium and electronic device provided by this invention belong to the same inventive concept as the quantum bit layout method of the two-module chip, and therefore have the same beneficial effects, which will not be repeated here. Attached Figure Description

[0075] Figure 1This is a flowchart illustrating the quantum bit layout method for a two-module chip provided in the first embodiment of the present invention.

[0076] Figure 2 This is a schematic diagram of the physical layer of the first lattice array.

[0077] Figure 3 A quantum circuit diagram with 4 qubits.

[0078] Figure 4 This is a schematic diagram of the coupling strength matrix obtained from a 4-qubit quantum circuit diagram.

[0079] Figure 5 This is a schematic diagram of the coupling strength matrix obtained from an 18-qubit quantum circuit diagram.

[0080] Figure 6 A schematic diagram showing the arrangement of qubits in the first lattice array.

[0081] Figure 7 for Figure 1 The diagram shows the specific process flow of step S3 in the qubit layout method.

[0082] Figure 8 for Figure 1 The diagram shows the specific process flow of step S4 in the qubit layout method.

[0083] Figure 9 This is a schematic diagram of the specific process of step S5 in the two-module chip qubit layout method provided in the second embodiment of the present invention.

[0084] Figure 10 for Figure 9 The diagram shows the specific process flow of step S55 in the qubit layout method.

[0085] Figure 11 for Figure 9 The diagram shows the specific process flow of step S56 in the qubit layout method.

[0086] Figure 12 This is a flowchart illustrating the quantum bit layout method for a two-module chip provided in the third embodiment of the present invention.

[0087] Figure 13 This is a schematic diagram of the specific process of step S9 in the quantum bit layout method of the two-module chip provided in the fourth embodiment of the present invention.

[0088] Figure 14 for Figure 13 The flowchart shown illustrates the specific process of step S93 in the process diagram.

[0089] Figure 15 for Figure 14The flowchart shown is a detailed diagram of step S935 in the process.

[0090] Figure 16 for Figure 14 The flowchart shown is a detailed diagram of step S936 in the process.

[0091] Figure 17 A schematic diagram showing the arrangement of qubits in the first and second lattice arrays. Detailed Implementation

[0092] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0093] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0094] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0095] Please refer to Figure 1 The first embodiment of the present invention provides a qubit layout method for a two-module chip. The two-module chip includes a first chip and a second chip coupled to each other. The qubit layout method includes the following steps:

[0096] S1: Determine the first lattice array on the first chip for laying out qubits and the qubits to be laid out on the first chip. The first lattice array includes multiple lattice points arranged in M ​​rows × N columns, and each lattice point of the first lattice array is coupled to its adjacent lattice points, N≥3, M≥2.

[0097] Among them, such as Figure 2 As shown, the first lattice array includes 9 lattice points arranged in 3 rows × 3 columns. Circles in the figure represent lattice points, and dashed lines represent coupling connections.

[0098] S2: Obtain the number of two-bit logic gates between each qubit of the first chip and other qubits, denoted as the first number, and obtain the number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip, denoted as the second number.

[0099] The first and second quantities can be obtained through a quantum circuit diagram composed of qubits on the first chip and qubits on the second chip. For example... Figure 3 The diagram shown is a 4-qubit quantum circuit diagram. From this diagram, the number of two-bit logic gates (all two-bit logic gates in the diagram are CNOT gates for ease of description) between each qubit (q1, q2, q3, q4) can be obtained, thus constructing a coupling strength matrix. This matrix is ​​as follows: Figure 4 As shown, this matrix is ​​a symmetric matrix that reflects the number of two-bit logic gates between different qubits. By summing the columns of the matrix, the number of two-bit logic gates between each qubit and all other qubits can be obtained.

[0100] If q1, q2, q3, and q4 in the quantum circuit diagram are all qubits on the first chip, then the summation of the columns will yield the first quantity, and the first quantities of q1, q2, q3, and q4 are 1, 2, 5, and 2, respectively.

[0101] If q1 and q2 are qubits on the first chip and q3 and q4 are qubits on the second chip in the quantum circuit diagram, then the first quantity of q1 and q2 is 0 and 0 respectively, and the second quantity of q1 and q2 is 1 and 2 respectively.

[0102] S3: Select the N qubits with the second largest number and arrange them in the first row of the first lattice array, where the first row is the row closest to the second chip.

[0103] For example, such as Figure 5 The figure shows the coupling strength matrix obtained from an 18-qubit quantum circuit diagram. q1 to q9 are the qubits on the first chip, and q10 to q18 are the qubits on the second chip. Based on the coupling strength matrix, the first number of qubits on the first chip is shown in Table 1, and the second number of qubits on the first chip is shown in Table 2.

[0104] Table 1. First number of qubits on the first chip.

[0105] q6 13 q1 11 q4 11 q2 9 q5 9 q9 8 q3 7 q7 7 q8 7

[0106] Table 2. Second number of qubits on the first chip.

[0107] q3 12 q2 8 q8 8 q9 7 q1 6 q4 6 q6 6 q5 5 q7 3

[0108] The three qubits with the second largest number, namely q3, q2 and q8, will be arranged in the first row of the first lattice array.

[0109] S4: In the current row after the first row, select the N-2 qubits with the largest number of unlaid qubits and lay them out on the lattice points in the current row, excluding the two edge lattice points.

[0110] Among them, q3, q2 and q8 are arranged after the first row of the first lattice array. When qubits are arranged in the second row, the qubit with the largest number of unarranged qubits is q6. q6 is arranged in the lattice points in the current row except for the two edge lattice points. Since the first lattice array has only 3 columns, q6 will be arranged in the middle lattice point of the second row.

[0111] S5: Select the two qubits with the second largest number of unlaid qubits and place them at the lattice points on both edges of the current row.

[0112] Among them, after q6 is laid out, the two qubits with the second largest number of unlaid qubits are q1 and q9. Therefore, q1 and q9 are laid out at the lattice points on the two edges of the second row.

[0113] The third row of the first lattice array is laid out according to the above process. After the final layout is completed, the qubits of the first lattice array are as follows: Figure 6 As shown, for ease of description, the first lattice array is represented by a square grid.

[0114] In this embodiment, the steps of obtaining the number of two-bit logic gates between each qubit of the first chip and other qubits, denoted as the first number, and obtaining the number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip, denoted as the second number, i.e., step S2 further includes:

[0115] Each qubit is sorted according to a first quantity order and a second quantity order. Each qubit in the first chip has a unique serial number. Among multiple qubits with the same first or second quantity, the qubit with the smaller serial number is sorted first.

[0116] in, Figure 5 The qubits of the first chip shown are numbered from 1 to 9. In Table 1, among the same number of qubits, the qubits with smaller numbers are ranked earlier; for example, qubit q1 is ranked before qubit q4, and qubit q2 is ranked before qubit q5. In Table 2, among the same number of qubits, the qubits with smaller numbers are ranked earlier; for example, qubit q2 is ranked before qubit q8, and qubit q4 is ranked before qubit q6.

[0117] The number of columns N in the first lattice array can be either even or odd. In this embodiment, such as... Figure 7 As shown, the step of selecting the second most numerous N qubits to arrange in the first row of the first lattice array, i.e., step S3, includes:

[0118] S31: Determine whether N is odd or even.

[0119] S32: If N is odd, select the second most numerous 1 qubit and place it at the center lattice point of the first row of the first lattice array. Also, select the second most numerous N-1 qubits from the unplaced qubits and place them at the other lattice points in the first row in sequence. The closer the qubits are to the center lattice point, the more numerous the second qubits are.

[0120] For example, when N is 3, the second most numerous qubit is placed at the center lattice point of the first row of the first lattice array. Then, the two most numerous qubits are selected from the unplaced qubits and placed at the two edge lattice points of the first row. There are no restrictions on which of these two qubits is to the left or right of the center lattice point. The final qubit layout of the first row is as follows. Figure 6 As shown.

[0121] For another example, when N is 5, the second most numerous qubit is placed at the center lattice point of the first row of the first lattice array. Then, the four second most numerous qubits are selected from the unplaced qubits and placed at the other lattice points in the first row. For example, if the five second most numerous qubits are q2, q5, q4, q8, and q1, then q2 is placed at the center lattice point of the first row, q5 and q4 are placed at the lattice points to the left and right of the center lattice point, and q8 and q1 are placed at the outermost lattice points on the left and right sides.

[0122] S33: If N is even, select the two qubits with the second largest number to be placed in the two middle lattice points of the first row of the first lattice array, and select the N-2 qubits with the second largest number from the unplaced qubits to be placed in the other lattice points of the first row in sequence. The closer the lattice point is to the middle, the greater the second number of qubits.

[0123] For example, when N is 4, the two qubits with the second largest number are arranged at the two middle lattice points of the first row of the first lattice array, and then the two qubits with the second largest number are selected from the unarranged qubits and arranged at the outermost lattice points on the left and right sides of the first row.

[0124] Furthermore, in this embodiment, as Figure 8As shown, step S4, which involves selecting the largest number of N-2 qubits from the unlaid qubits and laying them out at all other lattice points in the current row except for the two edge points, includes:

[0125] S41: When N is odd, select the 1 qubit with the largest number of qubits from the unplaced qubits and place it at the center lattice point of the current row. Also, select N-3 qubits with the largest number of qubits from the unplaced qubits and place them sequentially at the other lattice points in the current row, excluding the two edge lattice points. The closer the qubit is to the center lattice point, the larger the number of qubits.

[0126] For example, when N is 5, the most numerous qubit is placed at the center lattice point of the current row. Then, the two most numerous qubits selected from the unplaced qubits are placed at the lattice points to the left and right of the center lattice point. There is no restriction on whether these two qubits are placed to the left or right of the center lattice point. Finally, the two edge lattice points of the current row remain unplaced. It should be noted that if N is 3, the two lattice points to the left and right of the center lattice point are exactly the two edge lattice points. Therefore, selecting the most numerous 0 qubits from the unplaced qubits and placing them sequentially at the two edge lattice points to the left and right of the center lattice point is equivalent to this step not being performed.

[0127] S42: When N is even, select the two qubits with the largest number of first-order qubits from the unplaced qubits and place them at the two middle lattice points of the current row. Also, select the N-4 qubits with the largest number of first-order qubits from the unplaced qubits and place them sequentially at the other lattice points in the current row, excluding the two edge lattice points. The closer the lattice point is to the middle, the greater the number of first-order qubits.

[0128] For example, when N is 6, the two most numerous qubits are selected and placed on the two middle lattice points of the current row. Then, the two most numerous qubits from the unplaced qubits are selected and placed on the left and right lattice points of the two middle lattice points. Finally, the two edge lattice points of the current row are left unplaced. It should be noted that if N is 4, the left and right lattice points of the two middle lattice points are exactly the two edge lattice points. Therefore, selecting the 0 most numerous qubits from the unplaced qubits and placing them on the left and right lattice points of the two middle lattice points is equivalent to not performing this step.

[0129] Please refer to Figure 9The second embodiment of the present invention provides a qubit layout method for a two-module chip. This qubit layout method is based on the qubit layout method of the first embodiment and includes all the technical features of the first embodiment. The difference lies in that, in this embodiment, the distance between each lattice point of the first lattice array and its adjacent lattice points is a first preset value. If the first lattice array is a 3×3 array, then the distance between the center lattice point of the middle row and any other lattice point is the first preset value, and the shortest distance between any two lattice points in the first row and the third row is the first preset value × 2.

[0130] The step of selecting the two qubits with the second largest number from the unlaid qubits and placing them at the lattice points on both edges of the current row, i.e., step S5, includes:

[0131] S51: Select the two qubits with the second largest number of unplaced qubits, and denot them as the first competing qubit and the second competing qubit.

[0132] Among them, with Figure 5 The coupling strength matrix shown is exemplified by a 3×3 lattice array. In the first row of the first lattice array, q2, q3, and q8 are arranged from left to right. In the second row, q6 is arranged at the center lattice point. The two qubits with the highest number of unarranged qubits are q1 and q9. Here, q1 is denoted as the first competing qubit and q9 is denoted as the second competing qubit.

[0133] S52: Calculate the first coupling degree of the first competing qubit layout at the first edge lattice point of the current row and the first coupling degree of the layout at the second edge lattice point of the current row, and the first coupling degree of the second competing qubit layout at the first edge lattice point and the first coupling degree of the layout at the second edge lattice point.

[0134] The formula for calculating the first degree of coupling is:

[0135] F1=Σ i,j f ij l ij

[0136] Where i represents the index of the first or second competing qubit, j represents the index of the already deployed qubit, and f ij Represents the first competing qubit or the second competing qubit q i With the already deployed qubit q j The number of two-bit logic gates between them, l ij Represents the first competing qubit or the second competing qubit q i The lattice point and the already arranged qubit q j The shortest distance between the points in the lattice.

[0137] For ease of explanation, the first preset value is set to 1 in this example.

[0138] The first coupling degree F when the first competing qubit q1 is positioned at the first edge lattice point of the current row (in this example, the left edge is taken as the first edge and the right edge as the second edge) is... 1_L =f 12 l 12 +f 13 l 13 +f 16 l 16 +f 18 l 18 =1×1+0×1+2×1+1×2=5, the first coupling degree F when the first competing qubit q1 is positioned at the second edge lattice point of the current row. 1_R =f 12 l 12 +f 13 l 13 +f 16 l 16 +f 18 l 18 =1×2+0×1+2×1+1×1=5.

[0139] The first coupling degree F when the second competing qubit q9 is arranged at the first edge lattice point of the current row is... 1_L =f 92 l 92 +f 93 l 93 +f 96 l 96 +f 98 l 98 =3×1+1×1+1×1+2×2=9, the first coupling degree F when the second competing qubit q9 is positioned at the second edge lattice point of the current row. 1_R =f 92 l 92 +f 93 l 93 +f 96 l 96 +f 98 l 98 =3×2+1×1+2×1+2×1=11.

[0140] S53: Calculate the absolute value of the difference between the two first coupling degrees of the first competing qubit and the absolute value of the difference between the two first coupling degrees of the second competing qubit.

[0141] Among them, the absolute value of the difference between the two first coupling degrees of the first competing qubit q1 is |F 1_L -F 1_R|=|5-5|=0, the absolute value of the difference between the two first coupling degrees of the second competing qubit q9 is |F 1_L -F 1_R |=|9-11|=2.

[0142] S54: Compare the absolute value of the difference between the first competing qubit and the second competing qubit.

[0143] Among them, the absolute value of the difference between the first competing qubit q1 and q9 is 0, which is less than the absolute value of the difference between the second competing qubit q9 and q9 is 2.

[0144] S55: If the absolute value of the difference between the first competing qubits is greater than or equal to the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the lattice points on the two edges of the current row according to the magnitude of the two first coupling degrees of the first competing qubits.

[0145] S56: If the absolute value of the difference between the first competing qubits is less than the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the lattice points on the two edges of the current row according to the magnitude of the two first coupling degrees of the second competing qubits.

[0146] Since the absolute value of the difference between the first competing qubit q1 and the second competing qubit q9 is less than the absolute value of the difference between the two competing qubits q9, the qubit layout of the lattice points at the two edges of the current row will be determined according to the magnitude of the two first coupling degrees of the second competing qubit q9.

[0147] Specifically, please refer to Figure 10 The step of arranging the first and second competing qubits at the lattice points on the two edges of the current row according to the magnitude of the two first coupling degrees of the first competing qubit, i.e., step S55, includes:

[0148] S551: Compare the first coupling degrees of the two first competing qubits.

[0149] S552: If the first coupling degree of the first competing qubit when it is placed at the first edge lattice point is greater than the first coupling degree when it is placed at the second edge lattice point, then the first competing qubit is placed at the second edge lattice point and the second competing qubit is placed at the first edge lattice point.

[0150] S553: ​​If the first coupling degree of the first competing qubit when it is disposed at the first edge lattice point is less than or equal to the first coupling degree when it is disposed at the second edge lattice point, then the first competing qubit is disposed at the first edge lattice point and the second competing qubit is disposed at the second edge lattice point.

[0151] If the absolute value of the difference between the first competing qubit q1 and the second competing qubit q9 is greater than or equal to the absolute value of the difference between the two first coupling degrees of the first competing qubit q1, then the two first coupling degrees of the first competing qubit q1 are compared. If the first coupling degree of the first competing qubit q1 when it is placed at the first edge lattice point is greater than the first coupling degree when it is placed at the second edge lattice point, the first competing qubit q1 is placed at the second edge lattice point (i.e., the right edge lattice point), and the second competing qubit q9 is placed at the first edge lattice point (i.e., the left edge lattice point).

[0152] If the first coupling degree of the first competing quantum bit q1 when it is placed at the first edge lattice point is less than or equal to the first coupling degree when it is placed at the second edge lattice point, the first competing quantum bit q1 is placed at the first edge lattice point (i.e., the left edge lattice point), and the second competing quantum bit q9 is placed at the second edge lattice point (i.e., the right edge lattice point).

[0153] Please refer to Figure 11 The step of arranging the first and second competing qubits at the lattice points on both edges of the current row according to the magnitude of the two first coupling degrees of the second competing qubit, i.e., step S56, includes:

[0154] S561: Compare the first coupling degrees of the two competing qubits.

[0155] S562: If the first coupling degree of the second competing qubit when it is laid out at the first edge lattice point is greater than the first coupling degree when it is laid out at the second edge lattice point, then the second competing qubit is laid out at the second edge lattice point and the first competing qubit is laid out at the first edge lattice point.

[0156] S563: If the first coupling degree of the second competing qubit when it is disposed at the first edge lattice point is less than or equal to the first coupling degree when it is disposed at the second edge lattice point, then the second competing qubit is disposed at the first edge lattice point and the first competing qubit is disposed at the second edge lattice point.

[0157] In this example, the first coupling degree F when the second competing qubit q9 is positioned at the first edge lattice point is... 1_L =9 is less than the first coupling degree F when the lattice point is located at the second edge. 1_R =11, the second competing quantum bit q9 is placed at the first edge lattice point (i.e., the left edge lattice point), and the first competing quantum bit q1 is placed at the second edge lattice point (i.e., the right edge lattice point).

[0158] If the first coupling degree of the second competing qubit q9 when it is placed at the first edge lattice point is greater than that when it is placed at the second edge lattice point, then the second competing qubit q9 is placed at the second edge lattice point (i.e., the right edge lattice point), and the first competing qubit q1 is placed at the first edge lattice point (i.e., the left edge lattice point).

[0159] Following the example above, the third row of the first lattice array is also arranged with qubits according to the above process, and the final qubit arrangement is as follows. Figure 6 As shown.

[0160] Please refer to Figure 12 The third embodiment of the present invention provides a qubit layout method for a two-module chip. This qubit layout method is based on the qubit layout method of the second embodiment, and includes all the technical features of the qubit layout method of the second embodiment. In addition, the qubit layout method of this embodiment further includes:

[0161] S7: Determine the second lattice array on the second chip for laying out qubits and the qubits to be laid out on the second chip. The second lattice array includes multiple lattice points arranged in L rows × N columns, and each lattice point of the second lattice array is coupled to its adjacent lattice points. The second lattice array is coupled to the lattice points in the same column of the adjacent row of the first lattice array, and L≥1.

[0162] The second lattice array, like the first lattice array, also includes, for example, Figure 2 The diagram shows nine lattice points arranged in a 3x3 grid. Circles represent lattice points, and dashed lines represent coupling connections.

[0163] S8: Obtain the number of two-bit logic gates between each qubit of the second chip and each qubit of the first chip, denoted as the third number.

[0164] The third quantity can be obtained through a quantum circuit diagram composed of qubits on the first chip and qubits on the second chip. For example, Figure 3 In the quantum circuit diagram shown, q1 and q2 are qubits on the first chip, and q3 and q4 are qubits on the second chip. Therefore, the third quantities of q3 and q4 are 3 and 0, respectively. In this embodiment, step S8 further includes: sorting each qubit according to the order of its third quantity.

[0165] S9: Starting from the first row of the second lattice array, select the N qubits with the largest number of unlaid qubits and lay them out at each lattice point in the current row, where the first row of the second lattice array is the row closest to the first chip.

[0166] by Figure 5For example, based on the coupling strength matrix, the third number of qubits on the second chip is shown in Table 3.

[0167] Table 3. Third number of qubits on the second chip

[0168] q13 16 q10 10 q11 7 q12 6 q15 6 q18 6 q14 4 q17 4 q16 2

[0169] The three largest qubits, q10, q11 and q13, will be arranged in the first row of the second lattice array.

[0170] In this embodiment, the step of obtaining the number of two-bit logic gates between each qubit of the second chip and each qubit of the first chip, denoted as the third number, i.e., step S8 further includes:

[0171] Each qubit is sorted according to the third order of quantity, where each qubit in the second chip has a unique serial number, and among multiple qubits with the same third quantity, the qubit with the smaller serial number is sorted first.

[0172] in, Figure 5 The qubits of the second chip shown are numbered from 10 to 18. In Table 3, among the qubits of the same number, the qubits with smaller numbers are ranked earlier, for example, qubit q12 is ranked before qubit q15, and qubit q14 is ranked before qubit q17.

[0173] Please refer to Figure 13 The fourth embodiment of this invention provides a qubit layout method for a two-module chip. This qubit layout method is based on the qubit layout method of the third embodiment and includes all the technical features of the third embodiment. The difference lies in that, in this embodiment, the distance between each lattice point of the second lattice array and its adjacent lattice points is a first preset value, and the distance between lattice points in the same column of adjacent rows of the second lattice array and the first lattice array is also a second preset value. If the second lattice array is a 3×3 array, then the distance between the center lattice point of the middle row and any other lattice point is the first preset value, and the shortest distance between any two lattice points in the first row and the third row is the first preset value × 2. The second preset value is determined by the inter-chip coupling structure between the first chip and the second chip.

[0174] In this embodiment, the step of selecting the N qubits with the largest third number from the unlaid qubits and laying them out at each lattice point in the current row, i.e., step S9, includes:

[0175] S91: When N is odd, select the third largest number of qubits from the unplaced qubits and place them at the center lattice point of the current row.

[0176] S92: Select the two lattice points closest to the center lattice point from the lattice points of the current row that are not laid out with qubits as the first target lattice point and the second target lattice point, wherein the first target lattice point is close to the first edge of the current row and the second target lattice point is close to the second edge of the current row.

[0177] S93: Select the two qubits with the largest number of unplaced qubits and place them at the first target lattice point and the second target lattice point. Repeat the step of selecting the two lattice points closest to the center lattice point from the lattice points of the current row that have not placed qubits as the first target lattice point and the second target lattice point, until all lattice points in the current row have placed qubits.

[0178] For example, when N is 3, the qubit with the largest number of qubits is placed at the center lattice point of the current row of the second lattice array. The first target lattice point is the lattice point on the left edge of the current row, and the second target lattice point is the lattice point on the right edge of the current row. From the unplaced qubits, the two qubits with the largest number of qubits are selected and placed at the first and second target lattice points. At this point, all lattice points in the current row are filled with qubits.

[0179] For example, when N is 5, the qubit with the largest number of qubits is placed at the center lattice point of the current row of the second lattice array. The first target lattice point is the lattice point to the left of the center lattice point, and the second target lattice point is the lattice point to the right of the center lattice point. The two qubits with the largest number of qubits of the third type are selected from the unplaced qubits and placed at the first and second target lattice points. Then, a new first target lattice point and a new second target lattice point are selected, with the new first target lattice point being the lattice point on the left edge of the current row and the new second target lattice point being the lattice point on the right edge of the current row. This process is repeated again, selecting the two qubits with the largest number of qubits of the third type from the unplaced qubits and placing them at the first and second target lattice points. At this point, all lattice points in the current row are filled with qubits. For example, if the five qubits with the largest number of qubits are q12, q15, q14, q18, and q11, then q12 is located at the center lattice point in the first row, q15 and q14 are located at the lattice points on the left and right sides of the center lattice point, and q18 and q11 are located at the outermost lattice points on the left and right sides.

[0180] S94: When N is even, select two lattice points from the lattice points of the current row that are close to the center and are symmetrical about the center of the current row as the first target lattice point and the second target lattice point.

[0181] S95: Repeat the step of selecting the two qubits with the largest number of unlaid qubits and laying them on the first target lattice point and the second target lattice point, and repeat the step of selecting two lattice points that are close to the middle and relatively symmetrical to the center of the current row from the lattice points of the unlaid qubits in the current row as the first target lattice point and the second target lattice point, until all lattice points in the current row are laid with qubits.

[0182] For example, when N is 4, the first and second target lattice points are the two middle lattice points in the current row of the second lattice array. The two qubits with the largest number of qubits are then placed on the first and second target lattice points. Then, new first and second target lattice points are selected, with the new first target lattice point being the lattice point on the left edge of the current row and the new second target lattice point being the lattice point on the right edge of the current row. This process is repeated, selecting the two qubits with the largest number of qubits from the unplaced qubits and placing them on the first and second target lattice points. At this point, all lattice points in the current row are filled with qubits.

[0183] Further, see Figure 14 The step of selecting the two qubits with the largest number of unlaid qubits and laying them at the first and second target lattice points, i.e., step S93, includes:

[0184] S931: Select the two qubits with the largest number of qubits from the unlaid qubits, and denote them as the new first and second competing qubits.

[0185] Among them, with Figure 5 Taking the coupling strength matrix shown as an example, with the second lattice array being a 3×3 array, if the center lattice point of the first row of the second lattice array has qubit q13, then the two qubits with the highest number of third-order qubits selected from the unplaced qubits are q10 and q11. Here, q10 is designated as the new first competing qubit, and q11 as the new second competing qubit. The lattice point to the left of the center lattice point in the first row of the second lattice array is the first target lattice point, and the lattice point to the right of the center lattice point is the second target lattice point.

[0186] S932: Calculate the second coupling degree when the first competing qubit is positioned at the first target lattice point and the second coupling degree when it is positioned at the second target lattice point, as well as the second coupling degree when the second competing qubit is positioned at the first target lattice point and the second coupling degree when it is positioned at the second target lattice point. The formula for calculating the second coupling degree is:

[0187] F2=∑ i,j f ij L ij

[0188]

[0189] Wherein, K2 represents the second preset value and K1 represents the first preset value.

[0190] The formula for calculating the second coupling degree when the first competing qubit q10 is positioned at the first target lattice point is: Except for the first competing qubit q10 and qubit q13, which are located on the second chip, the first competing qubit q10 is located on a different chip than qubits q1 to q9. Therefore, the shortest distance between the first competing qubit q10 and qubits q1 to q9 is l. ij +K2-K1, i.e., l ij +K2-1, in calculating l ij When the first lattice array and the second lattice array are equivalent to a single array, that is, when the first lattice array and the second lattice array are joined together to form a single array, for example, when calculating L... 10,1 At that time, L 10,1 =l 10,1 +K2-1, in the equivalent array, the shortest distance between the first competing qubit q10 and qubit q2 is 1, and the shortest distance between qubit q2 and qubit q1 is 2. Therefore, l 10,1 =3, then L 10,1 =l 10,1 +K2-1=K2+2.

[0191] The second coupling degree when the first competing qubit q10 is positioned at the first target lattice point.

[0192] The second coupling degree when the first competing quantum bit q10 is positioned at the second target lattice point

[0193] The second coupling degree when the second competing quantum bit q11 is deployed at the first target lattice point

[0194] The second coupling degree when the second competing quantum bit q11 is deployed at the second target lattice point

[0195] S933: Calculate the absolute value of the difference between the two second coupling degrees of the first competing qubit and the absolute value of the difference between the two second coupling degrees of the second competing qubit.

[0196] Among them, the absolute value of the difference between the two first coupling degrees of the first competing qubit q10 is |F 2_L -F 2_R |=|10K2+14-10K2-13|=1, the absolute value of the difference between the two first coupling degrees of the second competing qubit q9 is |F 2_L -F 2_R |=|7K2+8-7K2-13|=5.

[0197] S934: Compare the absolute value of the difference between the first competing qubit and the second competing qubit.

[0198] Among them, the absolute value of the difference between the first competing qubit q10 and q11 is 1, which is less than the absolute value of the difference between the second competing qubit q11 and q11.

[0199] S935: If the absolute value of the difference between the first competing qubits is greater than or equal to the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the first target lattice point and the second target lattice point according to the magnitude of the two second coupling degrees of the first competing qubits.

[0200] S936: If the absolute value of the difference between the first competing qubits is less than the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the first target lattice point and the second target lattice point according to the magnitude of the two second coupling degrees of the second competing qubits.

[0201] Since the absolute value of the difference between the first competing qubit q10 and the second competing qubit q11 is smaller than the absolute value of the difference between the second competing qubit q11, the qubit layout of the lattice points at the two edges of the current row will be determined according to the magnitude of the two second coupling degrees of the second competing qubit q11.

[0202] Specifically, please refer to Figure 15 The step of deploying the first competing qubit and the second competing qubit at the first target lattice point and the second target lattice point according to the magnitude of the two second coupling degrees of the first competing qubit, i.e., step S935, includes:

[0203] S9351: Compare the two second coupling degrees of the first competing qubit.

[0204] S9352: If the second coupling degree of the first competing qubit when it is laid out at the first target lattice point is greater than the second coupling degree when it is laid out at the second target lattice point, then the first competing qubit is laid out at the second target lattice point and the second competing qubit is laid out at the first target lattice point.

[0205] S9353: If the second coupling degree of the first competing qubit when it is laid out at the first target lattice point is less than or equal to the second coupling degree when it is laid out at the second target lattice point, then the first competing qubit is laid out at the first target lattice point and the second competing qubit is laid out at the second target lattice point.

[0206] If the absolute value of the difference between the first competing qubits q10 and q11 is greater than or equal to the absolute value of the difference between the second competing qubits q11, then the two second coupling degrees of the first competing qubits q10 are compared. If the second coupling degree of the first competing qubits q10 when it is placed at the first target lattice point is greater than the second coupling degree when it is placed at the second target lattice point, then the first competing qubits q10 are placed at the second target lattice point (i.e., the right edge lattice point), and the second competing qubits q11 are placed at the first target lattice point (i.e., the left edge lattice point).

[0207] If the second coupling degree of the first competing qubit q10 when it is placed at the first target lattice point is less than or equal to the second coupling degree when it is placed at the second target lattice point, the first competing qubit q10 is placed at the first target lattice point (i.e., the left edge lattice point), and the second competing qubit q11 is placed at the second target lattice point (i.e., the right edge lattice point).

[0208] Please refer to Figure 16 The step of deploying the first competing qubit and the second competing qubit at the first target lattice point and the second target lattice point according to the magnitude of the two second coupling degrees of the second competing qubit, i.e., step S936, includes:

[0209] S9361: Compare the two second coupling degrees of the second competing qubit;

[0210] S9362: If the second coupling degree of the second competing qubit when it is laid out at the first target lattice point is greater than the second coupling degree when it is laid out at the second target lattice point, then the second competing qubit is laid out at the second target lattice point and the first competing qubit is laid out at the first target lattice point.

[0211] S9363: If the second coupling degree of the second competing qubit when it is laid out at the first target lattice point is less than or equal to the second coupling degree when it is laid out at the second target lattice point, then the second competing qubit is laid out at the first target lattice point and the second competing qubit is laid out at the second target lattice point.

[0212] In this example, the second coupling degree F when the second competing qubit q11 is positioned at the first target lattice point is calculated as follows: 2_L =7K2+8 is less than the second coupling degree F when it is positioned at the second target lattice point. 2_R =7K2+13, the second competing qubit q11 is placed at the first target lattice point (i.e., the left edge lattice point), and the first competing qubit q10 is placed at the second target lattice point (i.e., the right edge lattice point).

[0213] If the second coupling degree of the second competing qubit q11 when it is placed at the first target lattice point is greater than that when it is placed at the second target lattice point, the second competing qubit q11 is placed at the second target lattice point (i.e., the right edge lattice point), and the first competing qubit q10 is placed at the first target lattice point (i.e., the left edge lattice point).

[0214] Following the example above, the second and third rows of the second lattice array are also arranged with qubits according to the above process, and the final qubit arrangement is as follows. Figure 17 As shown in the figure, the dashed lines represent the coupling connections between wafers. It can be seen from the figure that only the lattice points in the same column of adjacent rows of the first and second lattice arrays are coupled together.

[0215] The present invention also provides a storage medium storing a computer program, which is configured to execute the qubit layout method of the two-module chip of the first embodiment, the second embodiment, the third embodiment, or the fourth embodiment when running.

[0216] Specifically, in this embodiment, the storage medium may include, but is not limited to, USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks, and other media capable of storing computer programs.

[0217] The present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to execute the qubit layout method of a two-module chip according to the first embodiment, the second embodiment, the third embodiment, or the fourth embodiment.

[0218] Specifically, the memory and processor can be connected via a data bus. Furthermore, the aforementioned electronic device may also include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0219] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0220] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for qubit layout in a two-module chip, wherein the two-module chip comprises a first chip and a second chip coupled to each other, characterized in that, The qubit layout method includes: The first lattice array on the first chip for laying out qubits and the qubits to be laid out on the first chip are determined. The first lattice array includes multiple lattice points arranged in M ​​rows × N columns, and each lattice point of the first lattice array is coupled to its adjacent lattice points, N≥3, M≥2. The number of two-bit logic gates between each qubit of the first chip and other qubits is obtained, denoted as the first number; and the number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip is obtained, denoted as the second number. The N qubits with the largest second quantity are selected and arranged in the first row of the first lattice array, wherein the first row of the first lattice array is the row closest to the second chip; In the current row following the first row, select the N-2 qubits with the largest number of unlaid qubits and lay them out in the current row except for the lattice points at the two edges; Select the two qubits with the largest number of qubits from the unlaid qubits and place them at the lattice points on both edges of the current row.

2. The qubit layout method according to claim 1, characterized in that, The steps of obtaining the number of two-bit logic gates between each qubit of the first chip and other qubits, denoted as the first number, and obtaining the number of two-bit logic gates between each qubit of the first chip and each qubit of the second chip, denoted as the second number, further include: Each qubit is sorted according to the first quantity order and the second quantity order, wherein each qubit of the first chip has a unique serial number, and among multiple qubits with the same first or second quantity, the qubit with the smaller serial number is sorted first.

3. The qubit layout method according to claim 1, characterized in that, The step of selecting the N qubits with the largest second quantity to be arranged in the first row of the first lattice array includes: Determine whether N is odd or even. If N is odd, then select the 1 qubit with the largest second number and place it at the center lattice point of the first row of the first lattice array. Also, select N-1 qubits with the largest second number from the unplaced qubits and place them at the other lattice points of the first row in sequence. The closer the qubit is to the center lattice point, the greater the second number of qubits. If N is even, the two qubits with the largest second number are selected and placed in the two middle lattice points of the first row of the first lattice array. The N-2 qubits with the largest second number are selected from the unplaced qubits and placed in the other lattice points of the first row. The closer the lattice point is to the middle, the greater the second number of qubits.

4. The qubit layout method according to claim 3, characterized in that, The step of selecting the largest number of N-2 qubits from the unplaced qubits and placing them on the lattice points in the current row, excluding the two edge lattice points, includes: When N is odd, the 1 qubit with the largest number of the first type is selected from the unplaced qubits and placed at the center lattice point of the current row, and N-3 qubits with the largest number of the first type are selected from the unplaced qubits and placed at the other lattice points in the current row except for the two edge lattice points. The number of qubits is greater closer to the center lattice point. When N is even, the two qubits with the largest number of the first type selected from the unplaced qubits are placed at the two middle lattice points of the current row, and the N-4 qubits with the largest number of the first type selected from the unplaced qubits are sequentially placed at the other lattice points in the current row except for the two edge lattice points, wherein the number of qubits is greater the closer to the middle lattice point.

5. The qubit layout method according to claim 3 or 4, characterized in that, The distance between each lattice point of the first lattice array and its adjacent lattice points is a first preset value.

6. The qubit layout method according to claim 5, characterized in that, The step of selecting the two qubits with the largest number from the unlaid qubits and laying them out at the lattice points on both edges of the current row includes: From the unplaced qubits, select the two qubits with the largest second number, and denot them as the first competing qubit and the second competing qubit; Calculate the first coupling degree when the first competing qubit is arranged at the first edge lattice point of the current row and the first coupling degree when it is arranged at the second edge lattice point of the current row, and calculate the first coupling degree when the second competing qubit is arranged at the first edge lattice point and the first coupling degree when it is arranged at the second edge lattice point; Calculate the absolute value of the difference between the two first coupling degrees of the first competing qubit and the absolute value of the difference between the two first coupling degrees of the second competing qubit; Compare the absolute value of the difference between the first competing qubit and the second competing qubit; If the absolute value of the difference between the first competing qubits is greater than or equal to the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the lattice points on the two edges of the current row according to the magnitude of the two first coupling degrees of the first competing qubits. If the absolute value of the difference between the first competing qubits is less than the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the lattice points on the two edges of the current row according to the magnitude of the two first coupling degrees of the second competing qubits. The formula for calculating the first coupling degree is as follows: F1=∑ i,j in ij the ij Where i represents the index of the first or second competing qubit, j represents the index of the already deployed qubit, and f ij Represents the first competing qubit or the second competing qubit q i With the already deployed qubit q j The number of two-bit logic gates between them, l ij Represents the first competing qubit or the second competing qubit q i The lattice point and the already arranged qubit q j The shortest distance between the points in the lattice.

7. The qubit layout method according to claim 6, characterized in that, The step of arranging the first competing qubit and the second competing qubit at the lattice points on both edges of the current row according to the magnitude of the two first coupling degrees of the first competing qubit includes: Compare the first coupling degrees of the two competing qubits; If the first coupling degree when the first competing qubit is disposed at the first edge lattice point is greater than the first coupling degree when it is disposed at the second edge lattice point, then the first competing qubit is disposed at the second edge lattice point and the second competing qubit is disposed at the first edge lattice point. If the first coupling degree when the first competing qubit is disposed at the first edge lattice point is less than or equal to the first coupling degree when disposed at the second edge lattice point, then the first competing qubit is disposed at the first edge lattice point and the second competing qubit is disposed at the second edge lattice point.

8. The qubit layout method according to claim 7, characterized in that, The step of arranging the first competing qubit and the second competing qubit at the lattice points on both edges of the current row according to the magnitude of the two first coupling degrees of the second competing qubit includes: Compare the two coupling degrees of the second competing qubit; If the first coupling degree when the second competing qubit is disposed at the first edge lattice point is greater than the first coupling degree when disposed at the second edge lattice point, then the second competing qubit is disposed at the second edge lattice point and the first competing qubit is disposed at the first edge lattice point. If the first coupling degree of the second competing qubit when it is disposed at the first edge lattice point is less than or equal to the first coupling degree when it is disposed at the second edge lattice point, then the second competing qubit is disposed at the first edge lattice point and the first competing qubit is disposed at the second edge lattice point.

9. The qubit layout method according to claim 8, characterized in that, The qubit layout method further includes: The second lattice array for laying out qubits on the second chip and the qubits to be laid out on the second chip are determined. The second lattice array includes multiple lattice points arranged in L rows × N columns, and each lattice point of the second lattice array is coupled to its adjacent lattice points. The second lattice array is coupled to the lattice points in the same column of the adjacent row of the first lattice array, where L≥1. The number of two-bit logic gates between each quantum bit of the second chip and each quantum bit of the first chip is obtained and denoted as the third number. Starting from the first row of the second lattice array, the N qubits with the largest number of unplaced qubits are selected and placed at each lattice point in the current row, wherein the first row of the second lattice array is the row closest to the first chip.

10. The qubit layout method according to claim 9, characterized in that, The step of obtaining the number of two-bit logic gates between each quantum bit of the second chip and each quantum bit of the first chip, denoted as the third number, further includes: Each qubit is sorted according to the third order of quantity, wherein each qubit of the second chip has a unique serial number, and among multiple qubits with the same third quantity, the qubit with the smaller serial number is sorted first.

11. The qubit layout method according to claim 10, characterized in that, The distance between each lattice point of the second lattice array and its adjacent lattice points is the first preset value, and the distance between lattice points in the same column of adjacent rows of the second lattice array and the first lattice array is the second preset value.

12. The qubit layout method according to claim 11, characterized in that, The step of selecting the N qubits with the largest number from the unplaced qubits and placing them at each lattice point in the current row includes: When N is odd, the third largest number of 1 qubit is selected from the unplaced qubits and placed at the center lattice point of the current row. Select the two lattice points closest to the center lattice point from the lattice points of the current row that do not have qubits, as the first target lattice point and the second target lattice point, wherein the first target lattice point is close to the first edge of the current row and the second target lattice point is close to the second edge of the current row; Select the two qubits with the largest number of unplaced qubits and place them on the first target lattice point and the second target lattice point. Repeat the step of selecting the two lattice points closest to the center lattice point from the lattice points of the current row that have no qubits placed as the first target lattice point and the second target lattice point, until all lattice points of the current row have qubits placed. When N is even, select two lattice points that are close to the center and symmetrical to the center of the current row from the lattice points of the unlaid qubits in the current row as the first target lattice point and the second target lattice point. Repeat the step of selecting the two largest qubits from the unlaid qubits and laying them on the first target lattice point and the second target lattice point, and repeat the step of selecting two lattice points that are close to the middle and relatively symmetrical to the center of the current row from the lattice points of the unlaid qubits in the current row as the first target lattice point and the second target lattice point, until all lattice points in the current row are laid with qubits.

13. The qubit layout method according to claim 12, characterized in that, The step of selecting the two largest qubits from the unplaced qubits and placing them at the first target lattice point and the second target lattice point includes: Select the two qubits with the largest number of the third type from the qubits that have not been deployed, and denote them as the new first and second competing qubits. Calculate the second coupling degree when the first competing qubit is deployed at the first target lattice point and the second coupling degree when it is deployed at the second target lattice point, and calculate the second coupling degree when the second competing qubit is deployed at the first target lattice point and the second coupling degree when it is deployed at the second target lattice point; Calculate the absolute value of the difference between the two second coupling degrees of the first competing qubit and the absolute value of the difference between the two second coupling degrees of the second competing qubit; Compare the absolute value of the difference between the first competing qubit and the second competing qubit; If the absolute value of the difference between the first competing qubits is greater than or equal to the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the first target lattice point and the second target lattice point according to the magnitude of the two second coupling degrees of the first competing qubits. If the absolute value of the difference between the first competing qubits is less than the absolute value of the difference between the second competing qubits, then the first competing qubits and the second competing qubits are arranged at the first target lattice point and the second target lattice point according to the magnitude of the two second coupling degrees of the second competing qubits. The formula for calculating the second degree of coupling is as follows: F2=∑ i,j f ij L ij Wherein, K2 represents the second preset value and K1 represents the first preset value.

14. The qubit layout method according to claim 13, characterized in that, The step of deploying the first competing qubit and the second competing qubit at the first target lattice point and the second target lattice point according to the magnitude of the two second coupling degrees of the first competing qubit includes: Compare the two second coupling degrees of the first competing qubit; If the second coupling degree when the first competing qubit is deployed at the first target lattice point is greater than the second coupling degree when deployed at the second target lattice point, then the first competing qubit is deployed at the second target lattice point and the second competing qubit is deployed at the first target lattice point. If the second coupling degree of the first competing qubit when it is deployed at the first target lattice point is less than or equal to the second coupling degree when it is deployed at the second target lattice point, then the first competing qubit is deployed at the first target lattice point and the second competing qubit is deployed at the second target lattice point.

15. The qubit layout method according to claim 14, characterized in that, The step of deploying the first competing qubit and the second competing qubit at the first target lattice point and the second target lattice point according to the two second coupling degrees of the second competing qubit includes: Compare the two second coupling degrees of the second competing qubit; If the second coupling degree when the second competing qubit is disposed at the first target lattice point is greater than the second coupling degree when disposed at the second target lattice point, then the second competing qubit is disposed at the second target lattice point and the first competing qubit is disposed at the first target lattice point. If the second coupling degree when the second competing qubit is disposed at the first target lattice point is less than or equal to the second coupling degree when disposed at the second target lattice point, then the second competing qubit is disposed at the first target lattice point and the second competing qubit is disposed at the second target lattice point.

16. A storage medium, characterized in that, The storage medium stores a computer program, which is configured to execute the quantum bit layout method of the two-module chip according to any one of claims 1 to 15 when it runs.

17. An electronic device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the qubit layout method for a two-module chip according to any one of claims 1 to 15.

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