A vertical super-junction diode structure based on selective-area growth and a preparation method thereof
By using selective region growth to form a vertical superjunction structure with alternating n-type and p-type regions on the substrate surface, the reliability problem of GaN superjunction devices in etching and regeneration processes is solved, and the device performance is improved with high reliability and high consistency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2023-11-14
- Publication Date
- 2026-07-31
AI Technical Summary
Existing technologies require complex etching and regrowth processes to manufacture GaN superjunction devices, which leads to etching defects and material inhomogeneities, affecting device reliability.
By employing a selective region growth method, a heavily doped n+-GaN layer, an n-GaN layer, and a p-GaN cladding layer are sequentially grown on the substrate surface to form alternating n-type and p-type regions, avoiding the re-etching step. By controlling the epitaxial growth conditions, the material thickness is controlled, forming a charge-balanced vertical superjunction structure.
It simplifies the fabrication process, improves the reliability and consistency of the device, breaks the limitation of the square relationship between on-resistance and breakdown voltage, and enhances breakdown characteristics, forward conduction characteristics, and reverse withstand voltage characteristics.
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Figure CN117497406B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, specifically relating to a vertical superjunction diode structure based on selected area growth and its fabrication method. Background Technology
[0002] Gallium nitride (GaN), as a third-generation wide-bandgap semiconductor, possesses advantages such as high breakdown voltage, high electron mobility, and high frequency. GaN-based power electronic devices have broad prospects in power electronic systems applications such as mobile consumer electronics, electric vehicles, photovoltaics, data centers, and drones. Among them, GaN-based diodes have many advantages, including high switching frequency, high operating junction temperature, and low on-resistance.
[0003] Currently, existing technologies have been used to conduct extensive research and fabrication of GaN-based devices to meet the growing demand for high-power electronic devices. In particular, compared with parallel GaN devices, GaN vertical diodes have a smaller area, better heat dissipation, and higher voltage withstand capability.
[0004] To further reduce on-resistance and increase breakdown voltage, the concept of GaN superjunction structures was proposed. However, fabricating GaN superjunction devices often requires complex etching and regrowth processes, which introduce numerous etching defects and material inhomogeneities, leading to serious reliability issues. Summary of the Invention
[0005] To address the aforementioned problems in the prior art, this invention provides a vertical superjunction diode structure based on selected region growth and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:
[0006] In a first aspect, the present invention provides a method for fabricating a vertical superjunction diode structure based on selected region growth, comprising:
[0007] A substrate is provided, and an epitaxial barrier layer is grown on the surface of the substrate;
[0008] At least a portion of the dielectric material of the epitaxial barrier layer is etched until the substrate is exposed, and selective epitaxy is performed on the exposed substrate surface to sequentially grow heavily doped n-type substrates. + A GaN layer, an n-GaN layer, and a p-GaN encapsulation layer, wherein the n-GaN layer is located within the heavily doped n-GaN layer. + -The GaN layer is located on the side away from the substrate, and the p-GaN wrapping layer is situated on the heavily doped n-side. + -GaN layer and the outer surface of the n-GaN layer;
[0009] A SiO2 layer is grown on the surface of the epitaxial barrier layer and the p-GaN coating layer;
[0010] An anode is fabricated on the side of the SiO2 layer away from the substrate;
[0011] A cathode is fabricated on the substrate away from the epitaxial barrier layer to obtain the vertical superjunction diode structure based on selective growth.
[0012] In one embodiment of the present invention, the step of providing a substrate and growing an epitaxial barrier layer on the surface of the substrate includes:
[0013] A heavily doped p-type Si substrate with a crystal plane of (111) is provided;
[0014] A dielectric material is deposited on the surface of the p-Si substrate using a low-pressure chemical vapor deposition (LPCVD) process to form an epitaxial barrier layer. The epitaxial material is one of SiO2, SiN, AlON, or Al2O3.
[0015] In one embodiment of the present invention, at least a portion of the dielectric material of the epitaxial barrier layer is etched until the substrate is exposed, and selective epitaxy is performed on the exposed substrate surface to sequentially grow heavily doped n-type substrates. + The steps of forming a GaN layer, an n-GaN layer, and a p-GaN wrapping layer include:
[0016] The dielectric material in a predetermined region of the epitaxial barrier layer is etched away until the substrate is exposed.
[0017] Si element doping concentration of 1×10⁻⁶ is epitaxially grown on the exposed substrate surface. 18 ~1×10 21 cm -3 Heavy doping n + -GaN layer;
[0018] In the heavily doped n + The surface growth of the GaN layer has a Si element doping concentration of 1×10⁻⁶. 15 cm -3 ~1×10 18 cm -3 n-GaN layer;
[0019] In the heavily doped n + The outer surface of the -GaN layer and the n-GaN layer is grown with a Mg element doping concentration of 10. 18 cm -3 ~10 20 cm -3 p-GaN wrapping layer.
[0020] In one embodiment of the present invention, the heavily doped n +The thickness of the n-GaN layer is 0.1µm to 5µm, the thickness of the n-GaN layer is 1µm to 10µm, and the thickness of the p-GaN coating layer is 5nm to 500nm.
[0021] In one embodiment of the present invention, the step of growing a SiO2 layer on the surface of the epitaxial barrier layer and the p-GaN coating layer includes:
[0022] High-resolution electron beam (HSQ) photoresist is spin-coated or deposited on the side of the epitaxial barrier layer away from the substrate, so that the HSQ photoresist covers the surface of the p-GaN layer and the epitaxial barrier layer. A SiO2 layer is formed by high-temperature annealing or electron beam bombardment. The height of the SiO2 layer is greater than the height of the p-GaN coating layer in a direction perpendicular to the plane of the substrate.
[0023] In one embodiment of the present invention, the step of fabricating an anode on the side of the SiO2 layer away from the substrate includes:
[0024] Using photolithography, an anode region is formed on the surface of the SiO2 layer using photoresist as a mask layer.
[0025] The SiO2 in the anode region is etched away using image etching until the p-GaN coating layer is exposed;
[0026] An anode metal is deposited on the exposed p-GaN coating surface and forms an ohmic contact with the p-GaN coating. The anode metal includes Al, Ni, Pt / Au, Ni / Au, or Ni / Ag / Ti / Au.
[0027] In one embodiment of the present invention, prior to the step of fabricating a cathode away from the epitaxial barrier layer on the substrate, the method further includes:
[0028] Reduce the thickness of the substrate;
[0029] The step of fabricating a cathode on the substrate away from the epitaxial barrier layer to obtain the vertical superjunction diode structure based on selective growth includes:
[0030] The substrate is subjected to back hole etching;
[0031] Cathode metal is deposited in the back hole and then reacted with the heavily doped n. + - The GaN layer forms an ohmic contact, and the cathode metal includes Al or Ti / Al or Ti / Al / Au or Ti / Al / Ni / Au or Ti / Al / Pt / Au.
[0032] In one embodiment of the present invention, the step of back-hole etching of the substrate includes:
[0033] Using photolithography, the HSQ photoresist is used as a mask layer to etch the substrate of the cathode ohmic contact area, forming a back hole that penetrates the substrate to the lower surface of the heavily doped n-type GaN layer.
[0034] In a second aspect, the present invention provides a vertical superjunction diode structure based on selected region growth, which is prepared by the method described in the first aspect, comprising:
[0035] Substrate;
[0036] An epitaxial barrier layer located on one side of the substrate, the epitaxial barrier layer including vias;
[0037] Heavily doped n located on one side of the substrate + -GaN layer;
[0038] Located in the heavily doped n + - An n-GaN layer on the side of the GaN layer away from the substrate, wherein n-GaN layers are heavily doped along a direction perpendicular to the plane of the substrate. + The orthogonal projections of the -GaN layer and the n-GaN layer are located within the via;
[0039] Located in the heavily doped n + -GaN layer and p-GaN wrapping layer on the outer surface of the n-GaN layer;
[0040] The SiO2 layer located on the outer surface of the epitaxial barrier layer and the p-GaN coating layer;
[0041] The anode is located on the side of the SiO2 layer furthest from the substrate;
[0042] The cathode is located on the side of the substrate away from the epitaxial barrier layer.
[0043] In one embodiment of the present invention, the anode forms an ohmic contact with the p-GaN cladding layer, and the cathode connects to the heavily doped n-type substrate through a back via in the substrate. + - The GaN layer forms an ohmic contact.
[0044] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0045] This invention provides a vertical superjunction diode structure based on selected region growth and its fabrication method. The fabrication process involves selective epitaxy on a substrate surface, sequentially growing heavily doped n-type diodes. +The GaN superjunction is formed by alternating n-type and p-type regions, consisting of GaN layers, n-GaN layers, and p-GaN encapsulation layers. This process does not require re-etching, making the fabrication method simple and resulting in devices with high reliability and consistency. Furthermore, the thickness of the growth material can be controlled by adjusting epitaxial growth conditions such as the V / III ratio during selective epitaxy. The superjunction formed by the p-type and n-type regions is beneficial for achieving charge balance.
[0046] Furthermore, theoretically, one-dimensional unipolar power devices are subject to a trade-off where the on-resistance increases squarely with the breakdown voltage. The diode provided by this invention adopts a vertical superjunction structure. Since the vertical superjunction structure device is based on the two-dimensional Poisson theory, the on-resistance and breakdown voltage are linearly related, which can reduce the on-resistance and thus break the above-mentioned limitation. This effectively improves the breakdown characteristics, forward conduction characteristics, and reverse withstand voltage characteristics of the device.
[0047] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0048] Figure 1 This is a flowchart of a method for fabricating a vertical superjunction diode structure based on selective growth, provided in an embodiment of the present invention.
[0049] Figure 2-10 This is a schematic diagram illustrating the fabrication process of the vertical superjunction diode structure based on selective growth provided in an embodiment of the present invention;
[0050] Figure 11a This is a forward characteristic curve of the vertical superjunction diode structure based on selective growth provided in an embodiment of the present invention;
[0051] Figure 11b This is the reverse breakdown characteristic curve of the vertical superjunction diode structure based on selective growth provided in the embodiments of the present invention. Detailed Implementation
[0052] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0053] Figure 1 This is a flowchart of a method for fabricating a vertical superjunction diode structure based on selected region growth, provided in an embodiment of the present invention. Figure 2-10 This is a schematic diagram illustrating the fabrication process of the vertical superjunction diode structure based on selected region growth provided in an embodiment of the present invention. Figure 1-10 As shown, this embodiment of the invention provides a method for fabricating a vertical superjunction diode structure based on selected region growth, comprising:
[0054] S1. Provide a substrate 1, and grow an epitaxial barrier layer 2 on the surface of the substrate 1;
[0055] S2. Etch at least a portion of the dielectric material of the epitaxial barrier layer 2 until the substrate 1 is exposed, and perform selective epitaxy on the exposed substrate 1 surface to sequentially grow a heavily doped n+-GaN layer 3, an n-GaN layer 4 and a p-GaN encapsulation layer 5. The n-GaN layer 4 is located on the side of the heavily doped n+-GaN layer 3 away from the substrate 1, and the p-GaN encapsulation layer 5 is located on the outer surface of the heavily doped n+-GaN layer 3 and the n-GaN layer 4.
[0056] S3. A SiO2 layer 6 is grown on the surface of the epitaxial barrier layer 2 and the p-GaN coating layer 5;
[0057] S4. Fabricate an anode 7 on the side of the SiO2 layer 6 away from the substrate 1;
[0058] S5. A cathode 8 is fabricated on substrate 1 away from epitaxial barrier layer 2 to obtain a vertical superjunction diode structure based on selected area growth.
[0059] Please see Figure 1-2 Step S1, which involves providing a substrate 1 and growing an epitaxial barrier layer 2 on the surface of the substrate 1, includes:
[0060] S101, Provide a heavily doped p-type Si substrate 1 with a crystal plane of (111);
[0061] S102. A dielectric material is deposited on the surface of a p-Si substrate 1 using a low-pressure chemical vapor deposition (LPCVD) process to form an epitaxial barrier layer 2. The epitaxial material is one of SiO2, SiN, AlON, or Al2O3.
[0062] Specifically, in the process of preparing gallium nitride superjunction diodes, a substrate 1 is first provided, such as a heavily doped p-type Si substrate 1, the crystal plane of which is (111). Then, a dielectric material is deposited on the upper surface of the substrate 1 using LPCVD (Low Pressure Chemical Vapor Deposition) process to form an epitaxial barrier layer 2 with a thickness of 10nm to 1000nm. The deposited dielectric material can be selected from SiO2, SiN, AlON or Al2O3.
[0063] Step S2, which involves etching at least a portion of the dielectric material of the epitaxial barrier layer 2 until the substrate 1 is exposed, and performing selective epitaxy on the exposed substrate 1 surface to sequentially grow a heavily doped n+-GaN layer 3, an n-GaN layer 4, and a p-GaN encapsulation layer 5, includes:
[0064] S201. Etch away the dielectric material in the preset area of the epitaxial barrier layer 2 until the substrate 1 is exposed;
[0065] S202, Si element doping concentration of 1×10⁻⁶ is epitaxially grown on the exposed substrate 1 surface. 18 ~1×10 21 cm -3 3. Heavily doped n+-GaN layer;
[0066] S203, Si element doping concentration of 1×10⁻⁶ is grown on the surface of heavily doped n+-GaN layer 3. 15 cm -3 ~1×10 18 cm -3 n-GaN layer 4;
[0067] S204, Mg element doping concentration of 10 is grown on the outer surface of heavily doped n+-GaN layer 3 and n-GaN layer 4. 18 cm -3 ~10 20 cm -3 5. p-GaN wrapping layer.
[0068] Specifically, in step S201, the dielectric material in a predetermined region of the epitaxial layer is etched away in a graphical manner, and the epitaxial barrier layer 2 is etched through in a direction perpendicular to the plane of the substrate 1. In other words, all the epitaxial material in the predetermined region needs to be etched away to expose the upper surface of the substrate 1. Obviously, the exposed upper surface of the substrate 1 is the selected epitaxial region.
[0069] Next, as Figure 4 As shown, in steps S202 to S204, a heavily doped n+-GaN layer 3, an n-GaN layer 4, and a p-GaN encapsulation layer 5 are sequentially grown on the exposed surface of the substrate 1. Specifically, Si-doped elements with a doping concentration of 1×10⁻⁶ are epitaxially grown on the exposed surface of the substrate 1. 18 ~1×10 21 cm -3 A heavily doped n+-GaN layer 3 is formed, and Si element is grown on the upper surface of the heavily doped n+-GaN layer 3 with a doping concentration of 1×10⁻⁶. 15 cm -3 ~1×10 18 cm -3 The n-GaN layer 4 is then formed, and finally, Mg-doped elements with a doping concentration of 10 are grown on the surface of the n-GaN layer 4. 18 cm -3 ~10 20 cm -3 As shown in the figure, the p-GaN encapsulation layer 5 covers the top surface of the n-GaN layer 4 and the outer surface of the n-GaN layer 4 and the heavily doped n+-GaN layer 3.
[0070] In this embodiment, a superjunction is formed by the heavily doped n+-GaN layer 3, the n-GaN layer 4, and the p-GaN encapsulation layer 5. During the growth process, the lateral and longitudinal growth of the material can be controlled by adjusting the V / III ratio to obtain the desired heavily doped n+-GaN layer. + The width and height of the GaN layer are then determined, and then an n-GaN layer 4 and a p-GaN wrapping layer 5 are grown based on the heavily doped n+-GaN layer 3. The resulting n-region and p-region are conducive to achieving charge balance.
[0071] In one optional embodiment, the thickness of the heavily doped n+-GaN layer 3 is 0.1 μm to 5 μm, the thickness of the n-GaN layer 4 is 1 μm to 10 μm, and the thickness of the p-GaN coating layer 5 is 5 nm to 500 nm.
[0072] like Figure 5 As shown, step S4, the step of growing a SiO2 layer 6 on the surface of the epitaxial barrier layer 2 and the p-GaN coating layer, includes:
[0073] HSQ photoresist is spin-coated or deposited on the side of the epitaxial barrier layer 2 away from the substrate 1, so that the HSQ photoresist covers the surface of the p-GaN layer and the epitaxial barrier layer 2, and SiO2 layer 6 is formed by high-temperature annealing or electron beam bombardment. The height of SiO2 layer 6 is greater than the height of p-GaN coating layer 5 in the direction perpendicular to the plane of substrate 1.
[0074] It should be noted that when performing spin coating or deposition of HSQ photoresist, the HSQ photoresist should fill the outer surface area of the p-GaN coating layer 5 and the epitaxial barrier layer 2, and then form amorphous SiO2 after high-temperature annealing or electron beam bombardment.
[0075] like Figure 6-7 As shown, step S4, the step of fabricating the anode 7 on the side of the SiO2 layer 6 away from the substrate 1, includes:
[0076] S401. Using photolithography, an anode region 7 is formed on the surface of SiO2 layer 6 using photoresist as a mask layer.
[0077] S402, Image etching away SiO2 in the anode 7 region until the p-GaN coating layer 5 is exposed;
[0078] S403. An anode 7 metal is deposited on the exposed p-GaN coating layer 5 and forms an ohmic contact with the p-GaN coating layer 5. The anode 7 metal includes Al, Ni, Pt / Au, Ni / Au, or Ni / Ag / Ti / Au.
[0079] like Figure 8 As shown, it should be noted that before the step of fabricating the cathode 8 away from the epitaxial barrier layer 2 on the substrate 1, the following steps are also included:
[0080] Reduce the thickness of substrate 1.
[0081] It should be understood that reducing the thickness of substrate 1 is beneficial for heat dissipation of the device and reduces thermal resistance and parasitic resistance, etc. However, the thickness of substrate 1 should not be reduced too much in this step, otherwise it may break during the fabrication process.
[0082] like Figure 9-10 As shown, step S5, which involves fabricating a cathode 8 on the substrate 1 away from the epitaxial barrier layer 2 to obtain a vertical superjunction diode structure based on selected area growth, includes:
[0083] S501, perform back hole etching on substrate 1;
[0084] S502. Deposit cathode 8 metal in the back hole and form an ohmic contact with the heavily doped n+-GaN layer 3. The cathode 8 metal includes Al or Ti / Al or Ti / Al / Au or Ti / Al / Ni / Au or Ti / Al / Pt / Au.
[0085] Step S501, the step of etching the back hole of substrate 1, includes:
[0086] Using photolithography, HSQ photoresist is used as a mask layer to etch the substrate 1 of the cathode ohmic contact area, forming a back hole that penetrates the substrate 1 all the way to the lower surface of the heavily doped n-type GaN layer.
[0087] This invention also provides a vertical superjunction diode structure based on selected region growth, prepared using the above method, comprising:
[0088] Substrate 1;
[0089] An epitaxial barrier layer 2 is located on one side of the substrate 1, and the epitaxial barrier layer 2 includes a via;
[0090] A heavily doped n+-GaN layer 3 located on one side of substrate 1;
[0091] The n-GaN layer 4 is located on the side of the heavily doped n+-GaN layer 3 away from the substrate 1, wherein, along the direction perpendicular to the plane where the substrate 1 is located, the orthogonal projection of the heavily doped n+-GaN layer 3 and the n-GaN layer 4 is located in the via.
[0092] A p-GaN encapsulation layer 5 is located on the outer surface of the heavily doped n+-GaN layer 3 and the n-GaN layer 4;
[0093] A SiO2 layer located on the outer surface of the epitaxial barrier layer 2 and the p-GaN encapsulation layer 5;
[0094] Anode 7 is located on the side of the SiO2 layer away from substrate 1;
[0095] The cathode 8 is located on the side of the substrate 1 away from the epitaxial barrier layer 2.
[0096] Optionally, the anode 7 forms an ohmic contact with the p-GaN coating layer 5, and the cathode 8 forms an ohmic contact with the heavily doped n+-GaN layer 3 through a back hole in the substrate 1.
[0097] Figure 11a This is a forward characteristic curve of the vertical superjunction diode structure based on selective growth provided in an embodiment of the present invention. Figure 11b This is the reverse breakdown characteristic curve of the vertical superjunction diode structure based on selective growth provided in this embodiment of the invention. Please refer to... Figure 11a As can be seen from the forward characteristic curves of the fabricated GaN vertical superjunction diode, it exhibits good forward turn-on voltage and current density characteristics, and low on-resistance. Please refer to [link to relevant documentation]. Figure 11b As can be seen from the reverse breakdown characteristic curve, the GaN vertical superjunction diode exhibits excellent reverse breakdown voltage characteristics, with a reverse breakdown voltage exceeding 1400V, which is higher than that of ordinary GaN vertical diodes. Therefore, the aforementioned GaN vertical superjunction diode combines low turn-on voltage, low reverse leakage current, and high breakdown voltage, and also possesses advantages such as low off-state loss.
[0098] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows:
[0099] This invention provides a vertical superjunction diode structure based on selected region growth and its fabrication method. The fabrication process involves selective epitaxy on a substrate surface, sequentially growing heavily doped n-type diodes. + The GaN superjunction is formed by alternating n-type and p-type regions, consisting of GaN layers, n-GaN layers, and p-GaN encapsulation layers. This process does not require re-etching, making the fabrication method simple and resulting in devices with high reliability and consistency. Furthermore, the thickness of the growth material can be controlled by adjusting epitaxial growth conditions such as the V / III ratio during selective epitaxy. The superjunction formed by the p-type and n-type regions is beneficial for achieving charge balance.
[0100] Furthermore, theoretically, one-dimensional unipolar power devices are subject to a trade-off where the on-resistance increases squarely with the breakdown voltage. The diode provided by this invention adopts a vertical superjunction structure. Since the vertical superjunction structure device is based on the two-dimensional Poisson theory, the on-resistance and breakdown voltage are linearly related, which can reduce the on-resistance and thus break the above-mentioned limitation. This effectively improves the breakdown characteristics, forward conduction characteristics, and reverse withstand voltage characteristics of the device.
[0101] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0102] The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0103] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A method for fabricating a vertical superjunction diode structure based on selected region growth, characterized in that, include: A substrate is provided, and an epitaxial barrier layer is grown on the surface of the substrate; At least a portion of the dielectric material of the epitaxial barrier layer is etched until the substrate is exposed, and selective epitaxy is performed on the exposed substrate surface to sequentially grow heavily doped n-type substrates. + A GaN layer, an n-GaN layer, and a p-GaN encapsulation layer, wherein the n-GaN layer is located within the heavily doped n-GaN layer. + -The GaN layer is located on the side away from the substrate, and the p-GaN wrapping layer is situated on the heavily doped n-side. + -GaN layer and the outer surface of the n-GaN layer; A SiO2 layer is grown on the surface of the epitaxial barrier layer and the p-GaN coating layer; An anode is fabricated on the side of the SiO2 layer away from the substrate; A cathode is fabricated on the substrate away from the epitaxial barrier layer to obtain the vertical superjunction diode structure based on selective growth; At least a portion of the dielectric material of the epitaxial barrier layer is etched until the substrate is exposed, and selective epitaxy is performed on the exposed substrate surface to sequentially grow heavily doped n-type substrates. + The steps of forming a GaN layer, an n-GaN layer, and a p-GaN wrapping layer include: The dielectric material in a predetermined region of the epitaxial barrier layer is etched away until the substrate is exposed. Si element doping concentration of 1×10⁻⁶ is epitaxially grown on the exposed substrate surface. 18 ~1×10 21 cm -3 Heavy doping n + -GaN layer; In the heavily doped n + The surface growth of the GaN layer has a Si element doping concentration of 1×10⁻⁶. 15 cm -3 ~1×10 18 cm -3 n-GaN layer; In the heavily doped n + The outer surface of the -GaN layer and the n-GaN layer is grown with a Mg element doping concentration of 10. 18 cm -3 ~10 20 cm -3 p-GaN encapsulation layer; Wherein, the heavily doped n + The thickness of the -GaN layer is 0.1um to 5um, the thickness of the n-GaN layer is 1um to 10um, and the thickness of the p-GaN coating layer is 5nm to 500nm.
2. The method for fabricating a vertical superjunction diode structure based on selected region growth according to claim 1, characterized in that, The step of providing a substrate and growing an epitaxial barrier layer on the surface of the substrate includes: A heavily doped p-type Si substrate with a crystal plane of (111) is provided; A dielectric material is deposited on the surface of a p-Si substrate using a low-pressure chemical vapor deposition (LPCVD) process to form an epitaxial barrier layer. The epitaxial material is one of SiO2, SiN, AlON, or Al2O3.
3. The method for fabricating a vertical superjunction diode structure based on selected region growth according to claim 1, characterized in that, The step of growing a SiO2 layer on the surface of the epitaxial barrier layer and the p-GaN coating layer includes: High-resolution electron beam (HSQ) photoresist is spin-coated or deposited on the side of the epitaxial barrier layer away from the substrate, so that the HSQ photoresist covers the surface of the p-GaN cladding layer and the epitaxial barrier layer. A SiO2 layer is formed by high-temperature annealing or electron beam bombardment. The height of the SiO2 layer is greater than the height of the p-GaN cladding layer in a direction perpendicular to the plane of the substrate.
4. The method for fabricating a vertical superjunction diode structure based on selected region growth according to claim 3, characterized in that, The step of fabricating the anode on the side of the SiO2 layer away from the substrate includes: Using photolithography, an anode region is formed on the surface of the SiO2 layer using photoresist as a mask layer. The SiO2 in the anode region is etched away using image etching until the p-GaN coating layer is exposed; An anode metal is deposited on the exposed p-GaN coating surface and forms an ohmic contact with the p-GaN coating. The anode metal includes Al, Ni, Pt / Au, Ni / Au, or Ni / Ag / Ti / Au.
5. The method for fabricating a vertical superjunction diode structure based on selected region growth according to claim 4, characterized in that, Prior to the step of fabricating a cathode away from the epitaxial barrier layer on the substrate, the method further includes: Reduce the thickness of the substrate; The step of fabricating a cathode on the substrate away from the epitaxial barrier layer to obtain the vertical superjunction diode structure based on selective growth includes: The substrate is subjected to back hole etching; Cathode metal is deposited in the back hole and then reacted with the heavily doped n. + - The GaN layer forms an ohmic contact, and the cathode metal includes Al or Ti / Al or Ti / Al / Au or Ti / Al / Ni / Au or Ti / Al / Pt / Au.
6. The method for fabricating a vertical superjunction diode structure based on selected region growth according to claim 5, characterized in that, The step of performing back-hole etching on the substrate includes: Using photolithography, the HSQ photoresist is used as a mask layer to etch the substrate of the cathode ohmic contact area, forming a back hole that penetrates the substrate to the lower surface of the heavily doped n-type GaN layer.
7. A vertical superjunction diode structure based on selective region growth, characterized in that, Prepared using the method described in any one of claims 1 to 6, comprising: Substrate; An epitaxial barrier layer located on one side of the substrate, the epitaxial barrier layer including vias; Heavily doped n located on one side of the substrate + -GaN layer; Located in the heavily doped n + - An n-GaN layer on the side of the GaN layer away from the substrate, wherein n-GaN layers are heavily doped along a direction perpendicular to the plane of the substrate. + The orthogonal projections of the -GaN layer and the n-GaN layer are located within the via; Located in the heavily doped n + -GaN layer and p-GaN wrapping layer on the outer surface of the n-GaN layer; The SiO2 layer located on the outer surface of the epitaxial barrier layer and the p-GaN coating layer; The anode is located on the side of the SiO2 layer furthest from the substrate; The cathode is located on the side of the substrate away from the epitaxial barrier layer.
8. The vertical superjunction diode structure based on selective growth according to claim 7, characterized in that, The anode forms an ohmic contact with the p-GaN coating layer, and the cathode connects to the heavily doped n-type substrate through a back via in the substrate. + - The GaN layer forms an ohmic contact.