An AOI detection method for appearance defects in MPW wafers

Abstract

This invention discloses an AOI (Audiometric Inspector) method for detecting appearance defects in MPW (Multi-Layer Wafer) wafers, belonging to the field of wafer inspection technology. The method includes: selecting and defining an AOI inspection model within the wafer, particularly a strategy for selecting and defining an AOI inspection model for MPW wafers; locating and aligning dies within the wafer, particularly a strategy for locating and aligning MPW wafer dies; generating a MAP (Map Image) to form the area to be inspected on the wafer, particularly a strategy for arranging MAPs for MPW wafers composed of dies of non-uniform sizes; comparative calculation to generate an AOI inspection standard model; AOI scanning the entire wafer to complete the appearance inspection judgment; and outputting the inspection judgment results: a strategy for outputting MAP_image and MAP_BIN code. This invention can obtain the overall yield data of the wafer through a single scan, achieving the goal of using AOI to detect appearance defects in MPW wafers, improving the AOI detection efficiency of MPW wafer appearance defects, reaching the same technical level as AOI detection of full-mask wafer appearance defects, improving wafer production efficiency, and reducing semiconductor manufacturing costs.

Description

Technical Field

[0001] This invention relates to the field of wafer inspection technology, and more particularly to an AOI method for detecting appearance defects in MPW wafers. Background Technology

[0002] With the rapid development of the semiconductor industry, AOI (Automated Optical Inspection) has become increasingly popular. Compared with traditional manual inspection methods, it can detect and determine wafer appearance defects more quickly and accurately, and provide real-time specific yield data for production. It is widely used in quality control at all stages of Full Mask (all masks in the chip manufacturing process serve the same design, and only one type of chip is contained on the same wafer, usually mass-produced chips) wafer fabrication. It plays a positive role in improving product quality, increasing production efficiency, and controlling production costs.

[0003] However, chips in the R&D stage, and even some mass-produced chips, are often manufactured as MPW (Multi-Project Wafer, meaning a single chip manufacturing process can handle multiple design services, with two or more chip models on the same wafer) wafers due to cost control and other factors. In existing AOI technology, typically one inspection model corresponds to one chip model. Therefore, MPW wafers require multiple scans to obtain overall wafer yield data, thus reducing the efficiency of wafer appearance defect detection. If a single wafer contains a sufficient number of chip models arranged with non-uniform dimensions (different chip models have different length and width dimensions), AOI will completely lose its detection capability. Therefore, AOI detection technology based on MPW wafer appearance defects urgently needs improvement. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of existing AOI inspection technology when applied to MPW wafers, and to provide an AOI inspection method for appearance defects in MPW wafers.

[0005] The objective of this invention is achieved through the following technical solution: This paper mainly provides an AOI inspection method for appearance defects of MPW wafers, including the following steps: (a) Selecting and defining the AOI inspection model within the wafer, this step includes: (i) Selection and definition of the parent model; (ii) Selection and definition of sub-models; (b) Locating and aligning the chip die within the wafer, this step includes: (i) One-time search and alignment; (ii) Secondary search and alignment; (c) Generate a MAP map to form the area to be inspected on the wafer, so that the MAP map corresponds one-to-one with the chips on the wafer. This step is divided into the following two cases: (i) Generation of MPW wafer MAP composed of chips of equal size; (ii) Generation of MPW wafer MAP composed of non-uniform sized chip dies; (d) Compare and calculate to generate the AOI test standard model; (e) AOI scan the entire wafer to complete the appearance inspection and judgment.

[0006] In some possible embodiments, an AOI method for detecting appearance defects in an MPW wafer also includes the following steps: (f) Output the verification result, wherein the output method of the verification result includes MAP_graphic and MAP_BIN code output.

[0007] In an AOI detection method for appearance defects of MPW wafers provided in some possible embodiments, in step (a) and (i), the smallest repeating unit within the wafer is defined as the AOI inspection master model; in step (a) and (ii), each chip in the master model is defined as a sub-model.

[0008] In an AOI detection method for MPW wafer appearance defects provided in some possible embodiments, when defining sub-models, the sub-models are grouped according to the category to which the sub-models belong in the chip model area contained in the parent model.

[0009] In an AOI detection method for appearance defects in an MPW wafer provided in some possible embodiments, the first search and alignment includes: Align the chip in the wafer with the master model; The secondary search and alignment includes: Align the chips in the wafer with the sub-model.

[0010] In an AOI inspection method for appearance defects on an MPW wafer provided in some possible embodiments, aligning the chips in the wafer with the master model includes: Based on the size and appearance characteristics of the master model, each block in the wafer that is similar to the master model is located by size calculation and wafer appearance scanning. The alignment of the chip in the wafer with the sub-model includes: Based on the arrangement, size, and appearance of the sub-model in the parent model, locate each chip in the positioning block that is similar to the sub-model.

[0011] In an AOI detection method for MPW wafer appearance defects provided in some possible embodiments, the generation of a MAP map includes: Based on the category to which the sub-model belongs, different colors are assigned to the points on the wafer_MAP to distinguish the current chip model.

[0012] In an AOI detection method for MPW wafer appearance defects provided in some possible embodiments, in step (c) and (ii), the chips that are not arranged in a two-dimensional matrix are output as a wafer_MAP diagram arranged in a two-dimensional matrix through a certain strategy, so that the MAP diagram corresponds one-to-one with the chips on the wafer.

[0013] In an AOI detection method for MPW wafer appearance defects provided in some possible embodiments, the MAP_illustration includes: The color of the points on the MAP map is used to distinguish the current chip model and the result of the appearance inspection.

[0014] In an AOI detection method for MPW wafer appearance defects provided in some possible embodiments, the MAP_BIN code output includes: Grouping sub-models according to their category and assigning different first codes to distinguish the current chip model; Based on the appearance inspection result in step (e), different second codes are assigned to distinguish the current chip inspection Fail / Pass; The first code and the second code are combined to form the MAP_BIN code output.

[0015] It should be further noted that the technical features corresponding to the above options can be combined or substituted to form new technical solutions if there is no conflict.

[0016] Compared with the prior art, the beneficial effects of the present invention are: (1) The present invention adopts a technical solution of matching the sub-model and the mother model and secondary search alignment, which realizes the AOI detection technology of appearance defects of MPW wafer in one scan, making the AOI detection of appearance defects of MPW wafer feasible and improving the detection efficiency of appearance defects of MPW wafer.

[0017] (2) In one example, the sub-model of the present invention uses the chip model contained in the parent model as a distinction to determine the category group to which the sub-model belongs. In the generation of the wafer MAP map and the output of the inspection judgment results, the purpose of classifying according to the chip model is achieved, making the inspection process more intuitive and the inspection data statistics more accurate, which helps to promote the optimization of the semiconductor manufacturing process.

[0018] (3) In one example, the present invention uses a dual-code technical solution to output the MPW wafer inspection and judgment result MAP_BIN code. The MAP_BIN code contains dual information of chip model classification and appearance inspection and judgment result. The MAP_BIN code is input to the automatic sorting equipment, making the automatic sorting of MPW wafers (sorting: after wafer cutting, qualified chips are picked out according to classification. In the industry, manual sorting and automatic sorting by equipment are usually used to perform the sorting) technically feasible, and further improving the production efficiency of semiconductor manufacturing. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating an AOI detection method for appearance defects in an MPW wafer according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating an AOI detection method including the step of outputting verification and judgment results, as shown in an embodiment of the present invention. Figure 3 This is a schematic diagram of the AOI detection process for appearance defects in an MPW wafer composed of laterally arranged equal-sized dies, as shown in an embodiment of the present invention. Figure 4 This is a schematic diagram of the AOI detection process for appearance defects in an MPW wafer composed of vertically aligned dies of equal size, as shown in an embodiment of the present invention. Figure 5 This is a schematic diagram of the AOI detection process for appearance defects in an MPW wafer composed of non-uniformly sized dies, as shown in an embodiment of the present invention. Detailed Implementation

[0020] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0022] This invention is mainly based on the matching of parent and child models, secondary search alignment, sub-model model classification, and dual-code BIN output, which effectively solves the related problems of MPW wafer appearance defect detection, improves wafer production efficiency and reduces semiconductor manufacturing costs.

[0023] Reference Figure 1 In one exemplary embodiment, an AOI detection method for appearance defects in an MPW wafer is provided, comprising the following steps: (a) Selecting and defining the AOI verification model within the wafer. This step includes selecting and defining the parent model and selecting and defining the sub-models. Specifically, as follows: Figure 3 (1) Figure 4 (1) Figure 5 As shown in (1), the smallest repeating unit within the wafer is selected based on the wafer layout and defined as the AOI inspection mother model, usually in the form of "a column in a shot", such as Figure 3 (1, ⑥) "A line in a shot" such as Figure 4 (1, ⑥) or “a complete shot”, such as Figure 5 (1, ⑦), as the parent model. For example... Figure 3 (1, ⑥) Figure 4 (1, ⑥) Figure 5 As shown in (1, ⑦), each chip is defined as a sub-model in the parent model, distinguished by chip model.

[0024] (b) Locating and aligning the chip die within the wafer, this step includes: (i) One-time search and alignment; (ii) Secondary search and alignment.

[0025] Specifically, based on the size and appearance characteristics of the master model, each block in the positioning wafer that is similar to the master model is located and aligned with the master model through size calculation and wafer appearance scanning. Then, based on the arrangement position, size, and appearance characteristics of the sub-model in the master model, each chip in the positioning block that is similar to the sub-model is located and aligned with the sub-model.

[0026] (c) Generate a MAP map to form the areas to be inspected on the wafer, ensuring a one-to-one correspondence between the MAP map and the chips on the wafer. Specifically, based on the dies found within the wafer in step (b), generate a MAP map, such as... Figure 3 (2) Figure 4 (2) Figure 5 (2) forms the inspection area of ​​the wafer, so that the MAP map corresponds one-to-one with the chip on the wafer; and according to the category of the sub-model determined in step (a), the color of the point on the wafer_MAP map is used to distinguish the model of the current chip.

[0027] This step is divided into two cases: generating the MPW wafer MAP map composed of dies of equal size and generating the MPW wafer MAP map composed of dies of non-equal size. The generation of the MPW wafer MAP map composed of dies of equal size is as follows: Figure 3 (2) Figure 4 As shown in (2), the chips are originally arranged in a two-dimensional matrix, and the MAP diagram can be generated one-to-one according to their relative positions. The generation of the MAP diagram for an MPW wafer composed of non-uniform sized dies is as follows: Figure 5 As shown in (2), its chips are not arranged in a two-dimensional matrix, but rather using a MAP (map-based) array. Figure 2 2D matrix arrangement strategy: Generate 2D matrix points using the smallest chip size in the X / Y directions, and position the remaining chips at the current matrix point with the relative position of the upper left corner. The remaining matrix points are defined as empty matrix points, and if an entire row or column of empty matrix points appears, they are deleted.

[0028] (d) Comparative calculation to generate an AOI inspection standard model. Specifically, multiple parent model regions are randomly selected in the MAP diagram, scanned, compared, and calculated to generate an AOI inspection standard model that does not contain appearance defects.

[0029] (e) AOI scans the entire wafer to complete the appearance inspection judgment. Specifically, the appearance information of each scanned chip is compared with the corresponding sub-model in the standard model. If there is an appearance difference, the current chip is judged as Fail, and if there is no appearance difference, the current chip is judged as Pass. In this way, the appearance inspection judgment of each chip in the wafer is completed.

[0030] Furthermore, referring to Figure 2 An AOI inspection method for appearance defects in MPW wafers further includes the following steps: (f) Output the verification result, wherein the output method of the verification result includes MAP_graphic and MAP_BIN code output.

[0031] Specifically, such as Figure 3 (3) Figure 4 (3) Figure 5 As shown in (3), the category grouping of the sub-model in step (a) and the appearance inspection judgment result in step (e) are displayed together on the MAP diagram. The color of the point on the MAP diagram is used to distinguish the current chip model and the appearance inspection judgment result, and the MAP diagram result is obtained.

[0032] like Figure 3 (4) Figure 4 (4) Figure 5 As shown in (4), different first codes are assigned to distinguish the current chip model according to the category grouping of the sub-model in step (a); different second codes are assigned to distinguish the current chip Fail / Pass according to the appearance inspection judgment result in step (e); the first and second codes are merged to form the MAP_BIN code, and the MAP_BIN code output display is completed.

[0033] This invention combines strategies for selecting and defining MPW wafer AOI inspection models based on parent and child models, secondary search and alignment strategies for MPW wafer dies, MAP diagram arrangement strategies for MPW wafers composed of non-uniform sized dies, and output strategies for dual-code MPW wafer MAP_BIN codes. These related strategies achieve the goal of AOI detection of MPW wafer appearance defects, improving the efficiency of MPW wafer appearance defect AOI detection and reaching the same technical level as AOI detection of full-mask wafer appearance defects. It provides an efficient and accurate solution for AOI detection of MPW wafer appearance defects and offers an innovative technical solution for the semiconductor manufacturing industry.

[0034] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. An AOI method for detecting surface defects in MPW wafers, characterized in that, Includes the following steps: (a) Selecting and defining the AOI inspection model within the wafer, this step includes: (i) Selection and definition of the parent model; (ii) Selection and definition of sub-models; In steps (a) and (i), the smallest repeating unit within the wafer is defined as the AOI inspection master model; in steps (a) and (ii), each chip in the master model is defined as a sub-model. When defining sub-models, the sub-models are grouped according to the chip model type contained in the parent model. (b) Locating and aligning the chip die within the wafer, this step includes: (i) One-time search and alignment; (ii) Secondary search and alignment; (c) Generate a MAP map to form the area to be inspected on the wafer, so that the MAP map corresponds one-to-one with the chips on the wafer. This step is divided into the following two cases: (i) Generation of MPW wafer MAP composed of chips of equal size; (ii) Generation of MPW wafer MAP composed of non-uniform sized chip dies; The generation of the MAP map includes: Based on the category to which the sub-model belongs, different colors are assigned to the points on the wafer_MAP map to distinguish the current chip model; wherein, MPW wafers composed of equal-sized chip dies are arranged in a two-dimensional matrix, and the MAP map is generated one-to-one according to the relative positions; in steps (c) and (ii), non-equal-sized chip dies that are not arranged in a two-dimensional matrix are output as wafer_MAP maps with a two-dimensional matrix arrangement strategy through the MAP map two-dimensional matrix arrangement strategy, so that the MAP map corresponds one-to-one with the chips on the wafer; The MAP diagram two-dimensional matrix arrangement strategy includes: generating two-dimensional matrix points with the smallest chip size in the X / Y directions, positioning the remaining chips at the current matrix point with the relative position of the upper left corner, defining the remaining matrix points as empty matrix points, and deleting any empty matrix points in a row or column. (d) Compare and calculate to generate the AOI test standard model; (e) AOI scan the entire wafer to complete the appearance inspection and judgment; (f) Output the verification result, wherein the output method of the verification result includes MAP_graphic and MAP_BIN code output; The MAP diagram includes: The color of the points on the MAP map is used to distinguish the current chip model and the result of the appearance inspection.

2. The AOI detection method for appearance defects of an MPW wafer according to claim 1, characterized in that, The search and alignment process includes: Align the chip in the wafer with the master model; The secondary search and alignment includes: Align the chips in the wafer with the sub-model.

3. The AOI detection method for appearance defects of an MPW wafer according to claim 2, characterized in that, The process of aligning the chip in the wafer with the master model includes: Based on the size and appearance characteristics of the master model, each block in the wafer that is similar to the master model is located by size calculation and wafer appearance scanning. The alignment of the chip in the wafer with the sub-model includes: Based on the arrangement, size, and appearance of the sub-model in the parent model, locate each chip in the positioning block that is similar to the sub-model.

4. The AOI detection method for appearance defects of an MPW wafer according to claim 1, characterized in that, The MAP_BIN code output includes: Grouping sub-models according to their category and assigning different first codes to distinguish the current chip model; Based on the appearance inspection result in step (e), different second codes are assigned to distinguish the current chip inspection Fail / Pass; The first code and the second code are combined to form the MAP_BIN code output.

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