Vertical cavity surface emitting laser array chip and method for manufacturing the same

Abstract

Embodiments of the present application relate to a vertical cavity surface emitting laser array chip and a preparation method thereof. The method comprises: forming a water-soluble material layer and a photoresist layer on a semiconductor material layer; performing exposure and first development on the photoresist layer to form at least two first openings, and the water-soluble material layer exposed through the first openings is partially removed to form second openings; wherein the line width of the second openings is greater than the line width of the first openings; forming an electrode structure layer on the semiconductor material layer; wherein the thickness of the electrode structure layer is less than the thickness of the water-soluble material layer, so that the second openings are not filled and have a gap; performing second development to remove the water-soluble material layer between the two adjacent second openings through the gap, and removing the photoresist layer on the water-soluble material layer to expose the upper surface of part of the semiconductor material layer; and etching the semiconductor material layer to form a groove in the semiconductor material layer by taking the remaining photoresist layer as a mask.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a vertical cavity surface-emitting laser array chip and its fabrication method. Background Technology

[0002] Photolithography is a commonly used process in the fabrication of semiconductor devices. The general photolithography process is quite complex and requires many steps to complete one photolithography step, resulting in long fabrication time and low fabrication efficiency for semiconductor devices.

[0003] The existing manufacturing process for Vertical Cavity Surface Emitting Laser (VCSEL) array chips requires at least two photolithography and resist removal processes to complete chip manufacturing, which is quite complicated. Summary of the Invention

[0004] In view of this, the present application provides a vertical cavity surface emission laser array chip and its fabrication method to solve at least one problem existing in the background art.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a vertical-cavity surface-emitting laser array chip, the method comprising:

[0006] Provides a semiconductor material layer;

[0007] A water-soluble material layer and a photoresist layer are sequentially formed on the upper surface of the semiconductor material layer;

[0008] The photoresist layer is exposed and first developed to form at least two first openings in the photoresist layer, and the water-soluble material layer exposed through the first openings is partially removed in the first development to form at least two second openings in the water-soluble material layer corresponding to the at least two first openings; wherein the linewidth of the second opening is greater than the linewidth of the first opening.

[0009] An electrode structure layer is formed on the semiconductor material layer exposed through the second opening, the electrode structure layer including an upper electrode; wherein the thickness of the electrode structure layer is less than the thickness of the water-soluble material layer, so that the second opening is not filled and a gap is retained;

[0010] A second development is performed to remove the water-soluble material layer between two adjacent second openings through the gap, and to detach the photoresist layer on the removed water-soluble material layer from the semiconductor material layer, exposing part of the upper surface of the semiconductor material layer.

[0011] Using the remaining photoresist layer as a mask, the semiconductor material layer is etched to form trenches in the semiconductor material layer.

[0012] In conjunction with the first aspect of this application, in an optional embodiment, the electrode structure layer includes only the upper electrode, the thickness of which is 3 / 5 to 4 / 5 of the thickness of the water-soluble material layer.

[0013] In conjunction with the first aspect of this application, in an optional embodiment, the electrode structure layer further includes: a dielectric film covering the upper electrode; the total thickness of the upper electrode and the dielectric film is 3 / 5 to 4 / 5 of the thickness of the water-soluble material layer.

[0014] In conjunction with the first aspect of this application, in an optional embodiment, forming an electrode structure layer on the semiconductor material layer exposed through the second opening includes:

[0015] An upper electrode is formed on the semiconductor material layer exposed through the second opening;

[0016] A dielectric film is formed on the upper electrode; wherein the dielectric film is formed by a sputtering process.

[0017] In conjunction with the first aspect of this application, in an alternative embodiment, the material of the water-soluble material layer comprises a non-photosensitive release adhesive.

[0018] In conjunction with the first aspect of this application, in an optional embodiment, the semiconductor material layer includes at least a substrate, a first Bragg reflector layer, an active layer, a confinement layer, and a second Bragg reflector layer stacked sequentially; wherein the depth of the trench is greater than the distance between the upper surface of the semiconductor material layer and the confinement layer.

[0019] In conjunction with the first aspect of this application, in an alternative embodiment, after forming trenches in the semiconductor material layer, the fabrication method further includes: performing a wet oxidation process to oxidize at least a portion of the confinement layer into an oxide confinement layer.

[0020] In conjunction with the first aspect of this application, in an optional embodiment, the preparation method further includes:

[0021] A lower electrode is formed on the lower surface of the semiconductor material layer.

[0022] Secondly, embodiments of this application provide a vertical-cavity surface-emitting laser array chip, which is fabricated using any of the fabrication methods for vertical-cavity surface-emitting laser array chips described in the foregoing embodiments.

[0023] The vertical-cavity surface-emitting laser array chip and its fabrication method provided in this application embodiment involve providing a semiconductor material layer; sequentially forming a water-soluble material layer and a photoresist layer on the upper surface of the semiconductor material layer; exposing and first developing the photoresist layer to form at least two first openings in the photoresist layer, wherein the water-soluble material layer exposed through the first openings is partially removed in the first development to form at least two second openings corresponding to the at least two first openings in the water-soluble material layer; wherein the linewidth of the second opening is greater than the linewidth of the first opening; forming an electrode structure layer on the semiconductor material layer exposed through the second openings, the electrode structure layer including an upper electrode; wherein the thickness of the electrode structure layer is less than the thickness of the water-soluble material layer, so that the second openings are not filled and gaps are retained; performing a second development to remove the water-soluble material layer between two adjacent second openings through the gaps, and causing the photoresist layer on the removed water-soluble material layer to detach from the semiconductor material layer, exposing part of the upper surface of the semiconductor material layer; using the remaining photoresist layer as a mask, etching the semiconductor material layer to form trenches in the semiconductor material layer. This reduces the number of photolithography steps required in fabricating vertical-cavity surface-emitting laser (VCSEL) array chips, simplifies the manufacturing process, saves manufacturing costs, and improves manufacturing efficiency.

[0024] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0025] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0026] Figure 1 A schematic flowchart illustrating the fabrication method of a vertical-cavity surface-emitting laser array chip for related technologies;

[0027] Figures 2 to 12 A cross-sectional structural diagram of a vertical cavity surface-emitting laser array chip during its fabrication process, provided for related technologies;

[0028] Figure 13 A schematic flowchart illustrating a method for fabricating a vertical-cavity surface-emitting laser array chip according to an embodiment of this application;

[0029] Figures 14 to 23 A cross-sectional structural diagram of the vertical cavity surface-emitting laser array chip provided in the embodiments of this application during the fabrication process;

[0030] Figure 24A schematic flowchart illustrating the fabrication method of a vertical-cavity surface-emitting laser array chip provided as a specific example of this application;

[0031] Figure 25 This is another cross-sectional structural diagram of the vertical cavity surface-emitting laser array chip provided in an embodiment of this application. Detailed Implementation

[0032] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0033] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0034] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0038] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0039] Figure 1 A schematic flowchart illustrating the fabrication method of a vertical-cavity surface-emitting laser array chip for related technologies; Figures 2 to 12 A cross-sectional structural diagram of a vertical cavity surface-emitting laser array chip during its fabrication process, provided for related technologies.

[0040] First, please refer to Figure 1 Manufacturing a vertical cavity surface-emitting laser array chip requires multiple process steps, including providing wafers, photolithography (first photolithography), metal evaporation, resist removal, dielectric film deposition, photolithography (second photolithography), etching, resist removal, oxidation, dielectric film removal, and back metal evaporation.

[0041] Next, please refer to Figures 2 to 12The specific steps for manufacturing a vertical cavity surface-emitting laser array chip include: providing a wafer 100, forming a first photoresist layer 101' on the wafer 100; exposing and developing the first photoresist layer 101' to form a patterned first photoresist layer 101; then forming a first electrode 110 on the wafer 100 exposed by the patterned first photoresist layer 101; then removing the patterned first photoresist layer 101, and sequentially forming a dielectric layer 120 and a patterned second photoresist layer 102 on the first electrode 110; next, using the patterned second photoresist layer 102 as a mask, etching the wafer 100 to form a groove 130; finally, removing the patterned second photoresist layer 102, and performing a wet oxidation process on the wafer 100 to oxidize the confinement layer in the wafer 100 into a high-alumina oxide layer 140, then removing the dielectric layer 120, and forming a second electrode 150 on the lower surface of the wafer 100. In this way, the fabrication of a vertical cavity surface-emitting laser array chip can be completed.

[0042] It is evident that in related technologies, the manufacturing process of vertical-cavity surface-emitting laser array chips requires multiple photolithography processes, resulting in problems such as long manufacturing time, complex manufacturing process, and easy damage to the wafers of vertical-cavity surface-emitting laser array chips during manufacturing.

[0043] In addition, due to the long manufacturing time of vertical-cavity surface-emitting laser array chips, technicians cannot test the optoelectronic performance of vertical-cavity surface-emitting laser array chips in a timely manner, and therefore cannot complete the rapid verification of the epitaxy (EPI) structure of vertical-cavity surface-emitting laser array chips.

[0044] Based on this, this application provides a method for fabricating a vertical cavity surface-emitting laser array chip. Figure 13 A schematic flowchart illustrating the fabrication method of a vertical-cavity surface-emitting laser array chip provided in this application embodiment; as shown in the figure, the method includes:

[0045] Step S101: Provide a semiconductor material layer;

[0046] Step S102: A water-soluble material layer and a photoresist layer are sequentially formed on the upper surface of the semiconductor material layer;

[0047] Step S103: Expose the photoresist layer and perform a first development to form at least two first openings in the photoresist layer, and the water-soluble material layer exposed through the first openings is partially removed in the first development to form at least two second openings corresponding to the at least two first openings in the water-soluble material layer; wherein the linewidth of the second opening is greater than the linewidth of the first opening.

[0048] Step S104: An electrode structure layer is formed on the semiconductor material layer exposed through the second opening. The electrode structure layer includes an upper electrode. The thickness of the electrode structure layer is less than the thickness of the water-soluble material layer so that the second opening is not filled and a gap is retained.

[0049] Step S105: Perform a second development to remove the water-soluble material layer between two adjacent second openings through the gap, and cause the photoresist layer on the removed water-soluble material layer to detach from the semiconductor material layer, exposing part of the upper surface of the semiconductor material layer.

[0050] Step S106: Using the remaining photoresist layer as a mask, etch the semiconductor material layer to form trenches in the semiconductor material layer.

[0051] It is understood that the embodiments of this application can reduce the number of photolithography processes required in the fabrication of vertical-cavity surface-emitting laser array chips, simplify the manufacturing process of vertical-cavity surface-emitting laser array chips, save manufacturing costs, and improve manufacturing efficiency.

[0052] Furthermore, simplifying the manufacturing process of vertical-cavity surface-emitting laser (VCSEL) array chips allows for timely optoelectronic testing of the fabricated chips. In other words, the fabrication method provided in this application enables rapid verification of the CCSEL array chip's optoelectronic characteristics and facilitates quick detection of problems in the manufacturing process. Additionally, it allows for rapid verification of the performance of the semiconductor material layers used in fabricating the CCSEL array chip, improving verification efficiency.

[0053] It should also be understood that although the steps in the above flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Moreover, at least some of the steps in the above flowchart may include multiple steps or stages, and these steps or stages are not necessarily completed at the same time, nor are they necessarily performed sequentially.

[0054] Below, in conjunction with Figures 14 to 23 The fabrication method of the vertical cavity surface-emitting laser array chip provided in the embodiments of this application and its beneficial effects are further described in detail.

[0055] First, please refer to Figure 14 Step S101 is executed to provide a semiconductor material layer 200.

[0056] In some embodiments, the semiconductor material layer 200 includes at least a substrate, a first Bragg reflector layer, an active layer, a confinement layer, and a second Bragg reflector layer stacked sequentially. The semiconductor material layer 200 may also be referred to as a "wafer".

[0057] For example, the substrate can be a semiconductor substrate, and the material of the substrate can be at least one of gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), etc.

[0058] For example, the first Bragg reflector layer and the second Bragg reflector layer can be epitaxial layers grown on a substrate. The first and second Bragg reflector layers each have a first conductivity type and a second conductivity type, which can be P-type or N-type. This conductivity type can be formed by doping the Bragg reflector layer with P-type or N-type impurities. Specifically, when the first Bragg reflector layer is an N-type Bragg reflector layer, the second Bragg reflector layer can be a P-type Bragg reflector layer. Specifically, the first and / or second Bragg reflector layers may contain multiple epitaxial layers, such as a periodic structure formed from high- and low-refractive-index materials.

[0059] For example, the active layer can be a quantum well layer. The active layer is disposed between the first and second Bragg reflector layers to form a resonant cavity, in which photons, after being excited, are repeatedly amplified by reflecting back and forth within the resonant cavity to form laser oscillations, thereby generating a laser beam. Those skilled in the art will understand that the emission direction of the laser beam can be selectively controlled through the configuration and design of the first and second Bragg reflector layers.

[0060] For example, the confinement layer is a high-aluminum-content material layer disposed between the active layer and the second Bragg reflector layer. Specifically, the high-aluminum-content material layer may be Al x Ga 1-x As (x≥0.95) material.

[0061] In practical applications, the substrate can be a growth substrate, and the first Bragg reflector layer, active layer, confinement layer, and second Bragg reflector layer can be epitaxial layers grown on the substrate. Thus, the first Bragg reflector layer, active layer, confinement layer, and second Bragg reflector layer can be collectively referred to as an "epitaxy structure"; the semiconductor material layer 200 can also be referred to as an "epitaxy wafer." It should be understood that this application obviously does not exclude the possibility that the semiconductor material layer may have other structures.

[0062] Next, please continue to refer to... Figure 14 In step S102, a water-soluble material layer 201 and a photoresist layer 202 are sequentially formed on the upper surface of the semiconductor material layer 200.

[0063] For example, the water-soluble material layer 201 can be any material layer that is water-soluble. For instance, the water-soluble material layer 201 can be a water-soluble organic layer, and more specifically, the material of the water-soluble material layer 201 includes a water-soluble non-photosensitive resin.

[0064] In practice, the water-soluble material layer 201 can be a lift-off photoresist used in photolithography. For example, the material of the water-soluble material layer 201 includes a non-photosensitive lift-off photoresist (LOR photoresist). It should be noted that the LOR photoresist used in this embodiment is only an example, and the water-soluble material layer 201 can also be made of other materials that are soluble in the developer. For example, the water-soluble material layer 201 can be a negative photoresist that is soluble in the developer when not exposed.

[0065] For example, the photoresist layer 202 can be either a positive or negative photoresist. The main components of the photoresist layer 202 are resin and photosensitizer. The resin has adhesive properties; for positive photoresist, the resin is relatively insoluble before exposure, but undergoes a chemical reaction after exposure, changing from insoluble to soluble. The photosensitizer acts as a dissolution inhibitor before exposure, reducing the dissolution rate of the resin, and as a dissolution enhancer after exposure, increasing the photoresist's solubility in the developer. Here, the method of coating the photoresist includes spin coating, in which centrifugal force causes the solvent to continuously evaporate, thereby forming a uniformly coated photoresist layer.

[0066] For example, after coating the water-soluble material layer 201, the preparation method may further include high-temperature curing of the water-soluble material layer 201 for a preset time to prevent the water-soluble material layer 201 from dissolving too quickly. Specifically, the curing time and curing temperature can be determined according to the water solubility of the water-soluble material layer 201. For example, the higher the water solubility of the water-soluble material layer 201, the higher the high-temperature curing temperature and the longer the time; conversely, the lower the water solubility of the water-soluble material layer 201, the lower the high-temperature curing temperature and the shorter the time.

[0067] Next, please refer to Figure 15 Step S103 is executed to expose and first develop the photoresist layer 202 to form at least two first openings T1 in the photoresist layer 202, and the water-soluble material layer 201 exposed through the first openings T1 is partially removed in the first development to form at least two second openings T2 in the water-soluble material layer 201 corresponding to the at least two first openings T1; wherein the linewidth D2 of the second opening T2 is greater than the linewidth D1 of the first opening T1.

[0068] For example, a developing solution can be used to partially dissolve the water-soluble material layer 201 through the first opening T1. Since the degree of dissolution of the water-soluble material layer 201 increases with increasing development time, by controlling the development time, the water-soluble material layer 201 can be dissolved in the developing solution to obtain a pattern with a second opening T2 in the water-soluble material layer 201, and the linewidth D2 of the second opening T2 is greater than the linewidth D1 of the first opening T1, forming a pattern on the semiconductor material layer 200 as shown in the example. Figure 15 The structure shown.

[0069] For example, the linewidth D2 of the second opening T2 is greater than the linewidth D1 of the first opening T1, and the projection of the first opening T1 onto the upper surface of the semiconductor material layer 200 falls into the projection of the corresponding second opening T2 onto the upper surface of the semiconductor material layer 200.

[0070] For example, both the first opening T1 and the second opening T2 are annular structures. It should be noted that... Figure 15 The partial cross-sections of two first openings T1 and two corresponding second openings T2 adjacent to a predetermined formation position of a groove 230 are shown only schematically. For practical applications, please refer to... Figure 25 The two upper electrodes 210 subsequently formed in the two adjacent second openings T2 are respectively located in Figure 25 The two dashed box regions shown (i.e., the two adjacent first openings T1 / second openings T2 are also located in) Figure 25 (In the two dashed box areas shown). Thus, it can be understood that the two subsequently formed upper electrodes 210 are also ring-shaped structures.

[0071] For example, the first opening T1 and the second opening T2 can be any one of a circular, rectangular, or hexagonal ring structure. For instance, the first opening T1 and the second opening T2 formed on the semiconductor material layer 200 can be a plurality of circular ring structures arranged in an array.

[0072] For example, please refer to Figure 15 The water-soluble material layer 201 includes a first portion located between two adjacent second openings T2, and a second portion other than the first portion; specifically, in an example where the second opening T2 is a ring-shaped structure, the second portion is the portion surrounding the area of ​​the second opening T2. The distance between the two farthest points on the boundary of the first portion is less than the distance between the two farthest points on the boundary of the second portion. Thus, in the subsequent second development process, the water-soluble material layer 201 located between the two adjacent second openings T2 can be completely removed, while the water-soluble material layer 201 located within the area surrounding the second opening T2 is not removed.

[0073] Next, please refer to Figure 16In step S104, an electrode structure layer is formed on the semiconductor material layer 200 exposed through the second opening T2. The electrode structure layer includes an upper electrode 210. The thickness of the electrode structure layer is less than the thickness of the water-soluble material layer 201, so that the second opening T2 is not filled and a gap is retained.

[0074] For example, the upper electrode 210 is located in the second opening T2, and the upper electrode 210 can be a circular annular electrode. The upper electrode 210 can be formed by vapor deposition or sputtering processes, and this application does not impose specific limitations on this. Specifically, during the formation of the upper electrode 210, the upper electrode material also covers the upper surface of the photoresist layer 202.

[0075] The material of the upper electrode 210 may include a conductive metal. For example, the upper electrode 210 may be a single-layer metal design, and the metal material includes, but is not limited to, any one of gold (Au), titanium (Ti), and platinum (Pt). The upper electrode 210 may also be a multi-layer metal design, for example, it may include a titanium layer, a platinum layer, and a gold layer stacked sequentially.

[0076] Next, please refer to Figure 17 and Figure 18 Step S105 is executed to perform a second development, removing the water-soluble material layer 201 between two adjacent second openings T2 through the gap, and causing the photoresist layer 202 on the removed water-soluble material layer 201 to detach from the semiconductor material layer 200, exposing part of the upper surface of the semiconductor material layer 200.

[0077] It should be noted that the water-soluble material layer 201 removed in this step is located between two adjacent second openings T2 (i.e., Figure 17 The area within the dashed box shown is 230'.

[0078] Specifically, when the water-soluble material layer 201 located in the dashed box region 230' is removed by the developing solution, the water-soluble material layer 201 located in the dashed box region 230' can be completely dissolved by controlling the developing time, while the water-soluble material layer 201 surrounding the second opening T2 is only partially dissolved by the developing solution. In addition, the photoresist layer 202 is insoluble in the developing solution, but after the water-soluble material layer 201 located in the dashed box region 230' is completely dissolved, the photoresist layer 202 located on the removed water-soluble material layer 201 can be completely detached from the semiconductor material layer 200 and also removed.

[0079] For example, a wet stripping process can be used to remove the water-soluble material layer 201 and the photoresist layer 202 located in the dashed box region 230'.

[0080] In some embodiments, the electrode structure layer includes only the upper electrode 210, and the thickness of the upper electrode 210 is 3 / 5 to 4 / 5 of the thickness of the water-soluble material layer 201.

[0081] Here, during the second development, the developer can flow into the second opening T2 through the gap between the photoresist layer 202 and the upper electrode 210.

[0082] In other embodiments, the electrode structure layer further includes a dielectric film 220 covering the upper electrode 210, the total thickness of the upper electrode 210 and the dielectric film 220 being 3 / 5 to 4 / 5 of the thickness of the water-soluble material layer 201.

[0083] Here, during the second development, the developer can flow into the second opening T2 through the gap between the photoresist layer 202 and the dielectric film 220.

[0084] In some embodiments, please refer to Figure 16 and Figure 17 An electrode structure layer is formed on the semiconductor material layer 200 exposed through the second opening T2, comprising:

[0085] An upper electrode 210 is formed on the semiconductor material layer 200 exposed through the second opening T2;

[0086] A dielectric film 220 is formed on the upper electrode 210; wherein the dielectric film 220 is formed by a sputtering process.

[0087] For example, when a dielectric film 220 is formed on the upper electrode 210, the dielectric film material also covers the upper surface of the upper electrode material covering the photoresist layer 202.

[0088] For example, the dielectric film 220 may be made of silicon nitride. Here, the dielectric film 220 covers the top and sidewalls of the upper electrode 210, and can protect the upper electrode 210 in subsequent fabrication processes.

[0089] It is understood that in the above embodiments, the thickness of the electrode structure layer is less than the thickness of the water-soluble material layer 201. This ensures that the developing solution can flow into the second opening T2 and contact the water-soluble material layer 201, thereby partially removing the water-soluble material layer 201. Furthermore, the thickness of the electrode structure layer is 3 / 5 to 4 / 5 of the thickness of the water-soluble material layer 201. This improves the fabrication efficiency of the vertical-cavity surface-emitting laser array chip while ensuring the optoelectronic performance of the formed vertical-cavity surface-emitting laser array chip.

[0090] It should be noted that in the above steps, the developer flows into the second opening T2 through the gap between the photoresist layer 202 and the dielectric film 220 or the upper electrode 210, thereby dissolving and removing the water-soluble material layer 201 located between two adjacent second openings T2. However, this application does not exclude the possibility that the developer may flow into the second opening T2 through other locations.

[0091] Finally, please refer to Figure 19 In step S106, the remaining photoresist layer 202 is used as a mask to etch the semiconductor material layer 200, forming trenches 230 in the semiconductor material layer 200.

[0092] In some embodiments, the depth of the trench 230 is greater than the distance from the upper surface of the semiconductor material layer 200 to the confinement layer. Figure 19 The spacing between (not shown).

[0093] For example, the etching of the semiconductor material layer 200 can be performed using dry etching processes such as reactive ion etching (RIE), ion beam etching, or plasma etching. During the etching process, the etching depth can be controlled so that the depth of the etched trench 230 is greater than the distance between the upper surface of the semiconductor material layer 200 and the confinement layer. Here, the depth of the trench 230 is greater than the distance between the upper surface of the semiconductor material layer 200 and the confinement layer (…). Figure 19 The spacing between (not shown). Thus, after the trench 230 is formed in the semiconductor material layer 200, the sidewalls of the trench 230 can expose the confinement layer in the semiconductor material layer 200, which can then be oxidized into an oxide confinement layer in subsequent processes.

[0094] For example, please refer to Figure 20 After forming the trench 230 in the semiconductor material layer 200, the method further includes: removing the remaining photoresist layer 202 and water-soluble material layer 201 on the surface of the semiconductor material layer 200. Simultaneously, the upper electrode material and dielectric film material covering the remaining photoresist layer 202 can also be completely removed from the semiconductor material layer 200.

[0095] In some embodiments, please refer to Figure 21 After forming trench 230 in semiconductor material layer 200, the fabrication method further includes performing a wet oxidation process to oxidize at least a portion of the confinement layer into an oxide confinement layer 240.

[0096] Here, the confinement layer undergoes a wet oxidation process. When the confinement layer is a high-alumina content material layer, the exposed sidewalls of the high-alumina content material layer are oxidized from the surface inwards to form aluminum oxide, while a portion of the high-alumina content material layer remains unoxidized, forming an oxide confinement layer 240, thereby obtaining an annular circular current channel. Here, the oxide confinement layer 240 is a compound layer closely attached to the active layer. This compound layer undergoes oxidation to form a ring of non-conductive oxide, which is used to improve the convergence of the current injected into the active layer.

[0097] For example, please refer to Figure 22When a dielectric film 220 is formed on the upper electrode 210, after oxidizing the confinement layer to form an oxide confinement layer 240, the preparation method may further include: placing the semiconductor material layer 200 into an etching apparatus and removing the dielectric film 220 by dry etching processes such as reactive ion etching, ion beam etching, and plasma etching.

[0098] In some embodiments, please refer to Figure 23 The fabrication method of the vertical cavity surface-emitting laser array chip also includes forming a lower electrode 250 on the lower surface of the semiconductor material layer 200.

[0099] For example, the lower electrode 250 can be formed by vapor deposition or sputtering processes, and this application does not impose specific limitations on this. The lower electrode 250 may contain a conductive metal. For example, the lower electrode 250 may be a single-layer metal design, and the metal material includes, but is not limited to, any one of gold (Au), titanium (Ti), and platinum (Pt). The lower electrode 250 may also be a multi-layer metal design, for example, it may contain a titanium layer, a platinum layer, and a gold layer stacked sequentially.

[0100] Figure 24 This is a schematic flowchart illustrating a specific example of the fabrication method of a vertical-cavity surface-emitting laser array chip provided in this application.

[0101] In one embodiment, please refer to Figure 24 The fabrication of a vertical-cavity surface-emitting laser (VCSEL) array chip can be accomplished through a series of processes including wafer fabrication, photolithography, metal evaporation, dielectric film deposition, development, etching, resist removal, oxidation, dielectric film etching, and back-side metal evaporation. Compared to the process steps provided by related technologies, this embodiment can complete the fabrication of the VCSEL array chip in a single photolithography step.

[0102] For example, the fabrication method of the vertical-cavity surface-emitting laser array chip in this application embodiment may include the following steps:

[0103] Step 1: First, apply a layer of LOR adhesive to the surface of the wafer, and then apply a layer of positive photoresist or negative photoresist;

[0104] Step 2: Expose the wafer using a photolithography machine, followed by a first development. After development, the desired pattern is left. Here, the pattern left after development can refer to the above embodiment, where at least two first openings are formed in the photoresist layer, and at least two second openings corresponding to the at least two first openings are formed in the water-soluble material layer.

[0105] Step 3: Sequentially deposit three metal layers of Ti / Pt / Au on the wafer surface; here, the total thickness of the metal is less than the thickness of the LOR photoresist, and the metal deposition can be carried out by evaporation or sputtering;

[0106] Step 4: Continue to deposit a dielectric film on the wafer surface;

[0107] Step 5: Place the wafer into the developing equipment for a second development, to remove the photoresist in certain areas (please refer to...). Figure 17 The area within the dashed box shown (230') was completely developed, exposing the surface of the wafer.

[0108] Step 6: Dry etching is performed on the wafer. The areas exposed on the wafer surface will be etched, and the high-aluminum layer will be exposed after etching.

[0109] Step 7: Place the wafer into the photoresist stripping equipment to remove any remaining photoresist from the surface;

[0110] Step 8: Place the wafer into an oxidation apparatus for wet oxidation, where the high-alumina layer will be oxidized. This step can refer to the above embodiment, performing a wet oxidation process to oxidize at least a portion of the confinement layer into an oxide confinement layer 240.

[0111] Step 9: Place the wafer into the etching equipment to remove the dielectric film;

[0112] Step 10: Deposit metal on the back of the wafer. After the metal deposition is complete, testing can be performed.

[0113] It is understood that the wafer in this embodiment can refer to the semiconductor material layer in the above embodiments, the Ti / Pt / Au three-layer metal in this embodiment can refer to the upper electrode in the above embodiments, and the metal deposited on the back of the wafer in this embodiment can refer to the lower electrode in the above embodiments.

[0114] In this way, the fabrication of a vertical-cavity surface-emitting laser array chip can be completed in just one photolithography step, simplifying the manufacturing process of the vertical-cavity surface-emitting laser array chip, saving manufacturing costs, and improving manufacturing efficiency.

[0115] Based on this, this application also provides a vertical cavity surface-emitting laser array chip, which is prepared by the steps in the preparation method of the vertical cavity surface-emitting laser array chip provided in any of the foregoing embodiments.

[0116] It should be noted that the embodiments of vertical cavity surface-emitting laser array chips provided in this application and the embodiments of the fabrication method of vertical cavity surface-emitting laser array chips belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0117] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A method for fabricating a vertical-cavity surface-emitting laser array chip, characterized in that, The preparation method includes: Provides a semiconductor material layer; A water-soluble material layer and a photoresist layer are sequentially formed on the upper surface of the semiconductor material layer; The photoresist layer is exposed and first developed to form at least two first openings in the photoresist layer, and the water-soluble material layer exposed through the first openings is partially removed in the first development to form at least two second openings in the water-soluble material layer corresponding to the at least two first openings; wherein the linewidth of the second opening is greater than the linewidth of the first opening. An electrode structure layer is formed on the semiconductor material layer exposed through the second opening, the electrode structure layer including an upper electrode; wherein the thickness of the electrode structure layer is less than the thickness of the water-soluble material layer, so that the second opening is not filled and a gap is retained; A second development is performed to remove the water-soluble material layer between two adjacent second openings through the gap, and to detach the photoresist layer on the removed water-soluble material layer from the semiconductor material layer, exposing part of the upper surface of the semiconductor material layer. Using the remaining photoresist layer as a mask, the semiconductor material layer is etched to form trenches in the semiconductor material layer.

2. The method for fabricating a vertical-cavity surface-emitting laser array chip according to claim 1, characterized in that, The electrode structure layer includes only the upper electrode, and the thickness of the upper electrode is 3 / 5 to 4 / 5 of the thickness of the water-soluble material layer.

3. The method for fabricating a vertical-cavity surface-emitting laser array chip according to claim 1, characterized in that, The electrode structure layer further includes a dielectric film covering the upper electrode; the total thickness of the upper electrode and the dielectric film is 3 / 5 to 4 / 5 of the thickness of the water-soluble material layer.

4. The method for fabricating a vertical-cavity surface-emitting laser array chip according to claim 1, characterized in that, The formation of an electrode structure layer on the semiconductor material layer exposed through the second opening includes: An upper electrode is formed on the semiconductor material layer exposed through the second opening; A dielectric film is formed on the upper electrode; wherein the dielectric film is formed by a sputtering process.

5. The method for fabricating a vertical-cavity surface-emitting laser array chip according to any one of claims 1-4, characterized in that, The material of the water-soluble material layer includes a non-photosensitive release adhesive.

6. The method for fabricating a vertical-cavity surface-emitting laser array chip according to claim 1, characterized in that, The semiconductor material layer includes at least a substrate, a first Bragg reflector layer, an active layer, a confinement layer, and a second Bragg reflector layer stacked sequentially; wherein the depth of the trench is greater than the distance between the upper surface of the semiconductor material layer and the confinement layer.

7. The method for fabricating a vertical-cavity surface-emitting laser array chip according to claim 6, characterized in that, After forming trenches in the semiconductor material layer, the preparation method further includes performing a wet oxidation process to oxidize at least a portion of the confinement layer into an oxide confinement layer.

8. The method for fabricating a vertical-cavity surface-emitting laser array chip according to claim 1, characterized in that, The preparation method further includes: A lower electrode is formed on the lower surface of the semiconductor material layer.

9. A vertical-cavity surface-emitting laser array chip, characterized in that, The vertical cavity surface-emitting laser array chip is prepared using the fabrication method of the vertical cavity surface-emitting laser array chip according to any one of claims 1-8.

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