Charge pump

Abstract

The application discloses a charge pump, each charge pump unit comprising a voltage boosting circuit unit and a transfer unit. The voltage boosting circuit unit comprises a voltage boosting capacitor and a clock input circuit. The input end of the clock input circuit is connected with a clock input signal and the output end outputs a clock output signal to the first plate of the voltage boosting capacitor. The second plate of the voltage boosting capacitor is a voltage boosting node and is connected with the transfer unit. The clock input circuit comprises an output end inverter, the output end of the output end inverter serving as the output end of the clock input circuit; and the power supply end of the output end inverter is connected with an output end power supply voltage. Starting from the kth charge pump unit, the output end power supply voltage is output by a voltage generating circuit with a power supply end connected with a power supply voltage and is fixed by a reference voltage clamp, and the output end power supply voltage is less than the power supply voltage, so as to reduce the voltage stress of the voltage boosting node of each charge pump unit above the kth charge pump unit. The application can avoid voltage stress of the charge pump and prevent damage of the charge pump.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a charge pump (CP). Background Technology

[0002] like Figure 1 The diagram shown is a block diagram of an existing charge pump; as shown... Figure 2 The diagram shown is a circuit diagram of a charge pump unit 101 of an existing charge pump; the existing charge pump includes n-stage charge pump units 101 cascaded together, where n is greater than or equal to 1.

[0003] Each of the charge pump units 101 includes a boost circuit unit 102 and a transmission unit 103.

[0004] The boost circuit unit 102 includes a boost capacitor and a clock input circuit.

[0005] The clock input circuit connects the clock input signal clkin to its input terminal and outputs a clock output signal to the first plate of the boost capacitor.

[0006] The second plate of the boost capacitor is a boost node and is connected to the transmission unit 103.

[0007] Figure 1 The system includes two boost nodes that are inversely related, namely the first boost node A and the second boost node B. The corresponding settings are:

[0008] The boost capacitor is divided into a first boost capacitor 106a and a second boost capacitor 106b, and the clock input circuit is also divided into a first clock input circuit 104a and a second clock input circuit 104b.

[0009] The second plate of the first boost capacitor 106a is the first boost node A, and the second plate of the second boost capacitor 106b is the second boost node B.

[0010] The first clock input circuit 104a includes inverters 105c and 105a connected in sequence, and the output terminal of inverter 105a outputs the first clock output signal clkout.

[0011] The second clock input circuit 104b includes in-phase buffers 105d and 105b connected in sequence, and the output terminal of inverter 105b outputs the second clock output signal clkoutb.

[0012] The input terminals of the first clock input circuit 104a and the second clock input circuit 104b are connected to the clock input signal clkin. The in-phase buffer 105d and the inverter 105c have the same buffer time but opposite phases, thus making clkout and clkoutb exactly out of phase.

[0013] like Figure 2 As shown, the transmission unit 103 includes a voltage input terminal Vin, a voltage output terminal Vout, a first transmission circuit 103a, and a second transmission circuit 103b.

[0014] The first transmission circuit 103a is disposed between the voltage input terminal Vin and the first boost node A and the second boost node B; when the first boost node A is charged, the first transmission circuit 103a connects the voltage input terminal Vin and the first boost node A and disconnects the voltage input terminal Vin and the second boost node B; when the second boost node B is charged, the first transmission circuit 103a connects the voltage input terminal Vin and the second boost node B and disconnects the voltage input terminal Vin and the first boost node A.

[0015] The second part of the transmission circuit 103b is disposed between the voltage output terminal Vout and the first boost node A and the second boost node B; when the first boost node A is fully charged, the second part of the transmission circuit 103b connects the voltage output terminal Vout and the first boost node A and disconnects the voltage output terminal Vout and the second boost node B; when the second boost node B is fully charged, the second part of the transmission circuit 103b connects the voltage output terminal Vout and the second boost node B and disconnects the voltage output terminal Vout and the first boost node A.

[0016] The first part of the transmission circuit 103a includes a first NMOS transistor MN101 and a second NMOS transistor MN102.

[0017] The drain of the first NMOS transistor MN101 and the drain of the second NMOS transistor MN102 are both connected to the voltage input terminal Vin. The source of the first NMOS transistor MN101 and the gate of the second NMOS transistor MN102 are both connected to the first boost node A. The source of the second NMOS transistor MN102 and the gate of the first NMOS transistor MN101 are both connected to the second boost node B.

[0018] Both the first NMOS transistor MN101 and the second NMOS transistor MN102 are native NMOS transistors.

[0019] The second part of the transmission circuit 103b includes a second PMOS transistor MP101 and a third PMOS transistor MP102.

[0020] The drain of the second PMOS transistor MP101 and the drain of the third PMOS transistor MP102 are both connected to the voltage output terminal Vout. The source of the second PMOS transistor MP101 and the gate of the third PMOS transistor MP102 are both connected to the first boost node A. The source of the third PMOS transistor MP102 and the gate of the second PMOS transistor MP101 are both connected to the second boost node B.

[0021] The first boost capacitor 106a uses a third NMOS transistor MN103 with its source and drain connected together, and the second boost capacitor 106b uses a fourth NMOS transistor MN104 with its source and drain connected together.

[0022] Both the third NMOS transistor MN103 and the fourth NMOS transistor MN104 are native NMOS transistors.

[0023] The working principle of the charge pump unit is as follows: Figure 2 As shown, when clkout is low, node A is also low, while node B, which is inversely phase to node A, is high. Thus, MN101 turns on, and the voltage input terminal Vin charges node A. Since Vin is also represented by Vin, after charging, node A is at Vin. After charging, clkout becomes high (Vdd), MN101 turns off, and the voltage level of node A becomes Vdd + Vin. At this point, node B is low, MP101 turns on, and the voltage from node A is transmitted to the voltage output terminal Vout. The charging and discharging of node B is exactly inversely phase to that of node A.

[0024] Depend on Figure 1 As shown, with the increase in the number of charge pump units, the voltage of nodes A and B after charging also increases. The voltage of nodes A and B after charging is Vdd + Vin. Vdd is usually 3.6V or 5.5V. Vdd usually has a large ripple. This ripple will eventually cause the voltage stress of nodes A and B to be large, especially the voltage stress of nodes A and B in the last few stages of the charge pump unit. This may lead to device damage. For example, the MOS transistors connected to nodes A and B are prone to damage. Summary of the Invention

[0025] The technical problem to be solved by the present invention is to provide a charge pump that can reduce the voltage stress at the boost node of the corresponding stage charge pump unit, thereby avoiding large voltage stress caused by power supply voltage fluctuations in the charge pump and thus preventing damage to the charge pump.

[0026] To address the aforementioned technical problems, the present invention provides a charge pump comprising n cascaded charge pump units, where n is greater than or equal to 1.

[0027] Each of the charge pump units includes a boost circuit unit and a transmission unit.

[0028] The boost circuit unit includes a boost capacitor and a clock input circuit.

[0029] The clock input circuit connects the clock input signal to its input terminal and outputs the clock output signal to the first plate of the boost capacitor.

[0030] The second plate of the boost capacitor is a boost node and is connected to the transmission unit.

[0031] The clock input circuit includes an output inverter, the output of which serves as the output of the clock input circuit; the power supply terminal of the output inverter is connected to the output power supply voltage, and the high level of the clock output signal is determined by the output power supply voltage.

[0032] Starting with the charge pump unit at stage k, where k is greater than or equal to 1 and less than or equal to n, the output power supply voltage is output by a voltage generation circuit connected to the power supply terminal and fixed by a reference voltage clamp. The output power supply voltage is less than the power supply voltage to reduce the voltage stress at the boost nodes of the charge pump units at stages k and above.

[0033] A further improvement is that the voltage generating circuit outputs multiple output terminal power supply voltages of different magnitudes. Starting from the kth stage, as the stage number increases, the magnitude of the output terminal power supply voltage of the charge pump unit corresponding to the stage gradually decreases.

[0034] A further improvement is that the voltage generating circuit outputs two different output terminal power supply voltages, namely a first output terminal power supply voltage and a second output terminal power supply voltage, wherein the first output terminal power supply voltage is greater than the second output terminal power supply voltage.

[0035] k equals n-1, the output power supply voltage of the charge pump unit of the (n-1)th stage adopts the first output power supply voltage, and the output power supply voltage of the charge pump unit of the nth stage adopts the second output power supply voltage.

[0036] A further improvement is that when k is greater than 1, the output power supply voltage of the charge pump unit from stage 1 to stage (k-1) is maintained at the power supply voltage.

[0037] A further improvement is that the voltage generation circuit includes: a comparator, a first PMOS transistor, and a resistor string.

[0038] The first input terminal of the comparator is connected to a reference voltage.

[0039] The source of the first PMOS transistor is connected to the power supply voltage.

[0040] The gate of the first PMOS transistor is connected to the output of the comparator.

[0041] The resistor is connected in series between the drain of the first PMOS transistor and ground.

[0042] The resistor string includes three output terminals, which respectively output the power supply voltage of the first output terminal, the power supply voltage of the second output terminal, and the feedback voltage.

[0043] The feedback voltage is connected to the second input terminal of the comparator.

[0044] A further improvement is that the boost capacitor is divided into a first boost capacitor and a second boost capacitor, and the clock input circuit is also divided into a first clock input circuit and a second clock input circuit.

[0045] The second plate of the first boost capacitor is the first boost node, and the second plate of the second boost capacitor is the second boost node. The first boost node and the second boost node are out of phase.

[0046] The inverter at the output terminal of the first clock input circuit is a first output inverter, and the inverter at the output terminal of the second clock input circuit is a second output inverter; the output terminal of the first output inverter outputs a first clock output signal, and the output terminal of the second output inverter outputs a second clock output signal.

[0047] The input terminal of the first clock input circuit is connected to the clock input signal, and a first buffer circuit is connected between the input terminal of the first clock input circuit and the inverter of the first output terminal.

[0048] The input terminal of the second clock input circuit is connected to the clock input signal, and a second buffer circuit is connected between the input terminal of the second clock input circuit and the inverter of the second output terminal.

[0049] The first buffer circuit and the second buffer circuit invert the first clock output signal and the second clock output signal.

[0050] A further improvement is that the first buffer circuit consists of an inverting buffer, and the second buffer circuit consists of a non-inverting buffer.

[0051] A further improvement is that the transmission unit includes a voltage input terminal, a voltage output terminal, a first part of the transmission circuit, and a second part of the transmission circuit.

[0052] The first part of the transmission circuit is disposed between the voltage input terminal and the first boost node and the second boost node; when the first boost node is charged, the first part of the transmission circuit connects the voltage input terminal and the first boost node and disconnects the voltage input terminal and the second boost node; when the second boost node is charged, the first part of the transmission circuit connects the voltage input terminal and the second boost node and disconnects the voltage input terminal and the first boost node.

[0053] The second part of the transmission circuit is disposed between the voltage output terminal and the first boost node and the second boost node; when the first boost node is fully charged, the second part of the transmission circuit connects the voltage output terminal and the first boost node and disconnects the voltage output terminal and the second boost node; when the second boost node is fully charged, the second part of the transmission circuit connects the voltage output terminal and the second boost node and disconnects the voltage output terminal and the first boost node.

[0054] A further improvement is that the first part of the transmission circuit includes a first NMOS transistor and a second NMOS transistor.

[0055] The drains of the first NMOS transistor and the second NMOS transistor are both connected to the voltage input terminal. The source of the first NMOS transistor and the gate of the second NMOS transistor are both connected to the first boost node. The source of the second NMOS transistor and the gate of the first NMOS transistor are both connected to the second boost node.

[0056] A further improvement is that both the first NMOS transistor and the second NMOS transistor are native NMOS transistors.

[0057] A further improvement is that the second part of the transmission circuit includes a second PMOS transistor and a third PMOS transistor.

[0058] The drain of the second PMOS transistor and the drain of the third PMOS transistor are both connected to the voltage output terminal. The source of the second PMOS transistor and the gate of the third PMOS transistor are both connected to the first boost node. The source of the third PMOS transistor and the gate of the second PMOS transistor are both connected to the second boost node.

[0059] A further improvement is that the first boost capacitor is a MOS capacitor with its source and drain connected together, and the second boost capacitor is a MOS capacitor with its source and drain connected together.

[0060] A further improvement is that the first boost capacitor and the second boost capacitor are of equal size.

[0061] A further improvement is that the MOS capacitor constituting the first boost capacitor is formed by connecting the source and drain of a third NMOS transistor, with the source and drain of the third NMOS transistor serving as the first plate of the first boost capacitor and the gate of the third NMOS transistor serving as the second plate of the first boost capacitor.

[0062] The MOS capacitor that makes up the second boost capacitor is formed by connecting the source and drain of the fourth NMOS transistor. The source and drain of the fourth NMOS transistor serve as the first plate of the second boost capacitor, and the gate of the fourth NMOS transistor serves as the second plate of the second boost capacitor.

[0063] A further improvement is that both the third NMOS transistor and the fourth NMOS transistor are native NMOS transistors.

[0064] This invention can set the power supply voltage (i.e., the output power supply voltage) of the inverter at the output terminal of the first plate of the boost capacitor in the corresponding charge pump unit, thereby setting the high level of the clock output signal input to the first plate of the boost capacitor, and thus adjusting the voltage stress of the second plate of the boost capacitor, i.e., the boost node. Through the voltage generation circuit, the output power supply voltage can be made lower than the internal power supply voltage of the chip and can pass through the reference voltage clamp. This avoids the adverse effects of large voltage fluctuations caused by large power supply voltage on the voltage stress of the boost node, thereby reducing the voltage stress of the boost node of the corresponding charge pump unit.

[0065] This invention enables the output power supply voltage of each stage of the charge pump unit to be set progressively. Since the output voltage of each stage of the charge pump unit increases with the number of stages, the output power supply voltage of each stage of the charge pump unit before the voltage stress problem at the boost node is generated can be kept at the power supply voltage. After the voltage stress problem at the boost node is generated, i.e., after the kth stage, the output power supply voltage of each stage of the charge pump unit is set to be fixed with reference voltage clamping, so that the voltage stress problem at the boost node will not occur in the entire charge pump. Attached Figure Description

[0066] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0067] Figure 1 This is a block diagram of an existing charge pump;

[0068] Figure 2 This is a circuit diagram of the charge pump unit of an existing charge pump;

[0069] Figure 3 This is a block diagram of the charge pump according to an embodiment of the present invention;

[0070] Figure 4 This is a circuit diagram of the charge pump unit of the charge pump according to an embodiment of the present invention;

[0071] Figure 5 This is a circuit diagram of the voltage generation circuit used in the charge pump of this invention. Detailed Implementation

[0072] like Figure 3 The diagram shown is a block diagram of a charge pump according to an embodiment of the present invention; as follows: Figure 4 The diagram shown is a circuit diagram of the charge pump unit 201 of the charge pump according to an embodiment of the present invention. Figure 4 yes Figure 3 The circuit diagram of the n-th stage charge pump unit 201201a; as shown. Figure 5 The diagram shown is a circuit diagram of the voltage generation circuit used in the charge pump of this embodiment of the invention. The charge pump of this embodiment of the invention includes n-stage charge pump units 201 cascaded together, where n is greater than or equal to 1.

[0073] Each charge pump unit 201 includes a boost circuit unit 202 and a transmission unit 203. The charge pump unit of the (n-1)th stage is marked with 201a, and the charge pump unit of the nth stage is marked with 201b.

[0074] The boost circuit unit 202 includes a boost capacitor and a clock input circuit.

[0075] The clock input circuit connects the clock input signal clkin to its input terminal and outputs a clock output signal to the first plate of the boost capacitor.

[0076] The second plate of the boost capacitor is a boost node and is connected to the transmission unit 203.

[0077] The clock input circuit includes an output inverter, the output of which serves as the output of the clock input circuit; the power supply terminal of the output inverter is connected to the output power supply voltage, and the high level of the clock output signal is determined by the output power supply voltage.

[0078] In this embodiment of the invention, the boost capacitor is divided into a first boost capacitor 206a and a second boost capacitor 206b, and the clock input circuit is also divided into a first clock input circuit 204a and a second clock input circuit 204b.

[0079] The second plate of the first boost capacitor 206a is the first boost node A, and the second plate of the second boost capacitor 206b is the second boost node B. The first boost node A and the second boost node B are out of phase.

[0080] The inverter at the output terminal of the first clock input circuit is a first output inverter 205a, and the inverter at the output terminal of the second clock input circuit is a second output inverter 205b; the output terminal of the first output inverter 205a outputs a first clock output signal clkout, and the output terminal of the second output inverter 205b outputs a second clock output signal clkoutb.

[0081] The input terminal of the first clock input circuit 204a is connected to the clock input signal clkin, and a first buffer circuit is connected between the input terminal of the first clock input circuit 204a and the first output inverter 205a.

[0082] The input terminal of the second clock input circuit 204b is connected to the clock input signal clkin, and a second buffer circuit is connected between the input terminal of the second clock input circuit 204b and the inverter 205b of the second output terminal.

[0083] The first and second buffer circuits invert the first clock output signal clkout and the second clock output signal clkoutb. In some preferred embodiments, the first buffer circuit consists of an inverting buffer 205c, and the second buffer circuit consists of a non-inverting buffer 205d.

[0084] Starting with the k-th stage of the charge pump unit 201, where k is greater than or equal to 1 and less than or equal to n, the output power supply voltage is output by a voltage generation circuit 301 connected to the power supply voltage Vdd and clamped and fixed by a reference voltage Vref. The output power supply voltage is less than the power supply voltage Vdd to reduce the voltage stress at the boost nodes of the charge pump units 201 in stages above the k-th stage. The voltage generation circuit 301 outputs multiple output power supply voltages of different magnitudes. Starting with the k-th stage, as the stage number increases, the magnitude of the output power supply voltage of the charge pump unit 201 in the corresponding stage gradually decreases.

[0085] like Figure 5 As shown, the voltage generating circuit 301 outputs two different output terminal power supply voltages, namely the first output terminal power supply voltage Vdd1 and the second output terminal power supply voltage Vdd2, wherein the first output terminal power supply voltage Vdd1 is greater than the second output terminal power supply voltage Vdd2.

[0086] k equals n-1, the output power supply voltage of the charge pump unit 201 of the (n-1)th stage adopts the first output power supply voltage Vdd1, and the output power supply voltage of the charge pump unit 201 of the nth stage adopts the second output power supply voltage Vdd2. The charge pump unit 201 of the (n-1)th stage is the charge pump unit 201a, and the charge pump unit 201 of the nth stage is the charge pump unit 201b; Figure 3 and Figure 4 In this context, the power supply voltage at the output terminal of the charge pump unit 201a is represented by Vdd1. Figure 4 In this context, the output power supply voltage of the charge pump unit 201b is represented by Vdd2. Figure 4 It can be seen that the first output power supply voltage Vdd1 is connected to the power supply terminal of the output inverter 205a of the charge pump unit 201 of the (n-1)th stage; the second output power supply voltage Vdd2 is connected to the power supply terminal of the output inverter 205b of the charge pump unit 201 of the nth stage. Other charge pump units 201 and... Figure 4 The difference between the charge pump unit 201b and the other output inverters 205a and 205b is that the voltages connected to the power supply terminals are different. Figure 3 The voltage connected to the power supply terminals of the output inverters 205a and 205b in the last stage, i.e., the nth stage, is Vdd2; the voltage connected to the power supply terminals of the output inverters 205a and 205b in each stage before the n-2th stage is Vdd.

[0087] In this embodiment of the invention, when k is greater than 1, the output power supply voltage of the charge pump unit 201 from the first stage to the (k-1)th stage is maintained at the power supply voltage Vdd.

[0088] like Figure 5 As shown, the voltage generation circuit 301 includes: a comparator 302, a first PMOS transistor MP301, and a resistor string. The resistor string is composed of resistors R101, R102, and R103 connected in series.

[0089] The first input terminal of the comparator 302 is connected to the reference voltage Vref.

[0090] The source of the first PMOS transistor MP301 is connected to the power supply voltage Vdd.

[0091] The gate of the first PMOS transistor MP301 is connected to the output terminal of the comparator 302.

[0092] The resistor is connected in series between the drain of the first PMOS transistor MP301 and ground.

[0093] The resistor string includes three output terminals, which respectively output the power supply voltage Vdd1 of the first output terminal, the power supply voltage Vdd2 of the second output terminal, and the feedback voltage Vfb.

[0094] The feedback voltage Vfb is connected to the second input terminal of the comparator 302.

[0095] In embodiments of the present invention, such as Figure 4 As shown, the transmission unit 203 includes a voltage input terminal Vin, a voltage output terminal Vout, a first transmission circuit 203a, and a second transmission circuit 203b.

[0096] The first transmission circuit 203a is disposed between the voltage input terminal Vin and the first boost node A and the second boost node B; when the first boost node A is charged, the first transmission circuit 203a connects the voltage input terminal Vin and the first boost node A and disconnects the voltage input terminal Vin and the second boost node B; when the second boost node B is charged, the first transmission circuit 203a connects the voltage input terminal Vin and the second boost node B and disconnects the voltage input terminal Vin and the first boost node A.

[0097] The second part of the transmission circuit 203b is disposed between the voltage output terminal Vout and the first boost node A and the second boost node B; when the first boost node A is fully charged, the second part of the transmission circuit 203b connects the voltage output terminal Vout and the first boost node A and disconnects the voltage output terminal Vout and the second boost node B; when the second boost node B is fully charged, the second part of the transmission circuit 203b connects the voltage output terminal Vout and the second boost node B and disconnects the voltage output terminal Vout and the first boost node A.

[0098] More preferably, the first part of the transmission circuit 203a includes a first NMOS transistor MN201 and a second NMOS transistor MN202.

[0099] The drain of the first NMOS transistor MN201 and the drain of the second NMOS transistor MN202 are both connected to the voltage input terminal Vin. The source of the first NMOS transistor MN201 and the gate of the second NMOS transistor MN202 are both connected to the first boost node A. The source of the second NMOS transistor MN202 and the gate of the first NMOS transistor MN201 are both connected to the second boost node B.

[0100] Both the first NMOS transistor MN201 and the second NMOS transistor MN202 are native NMOS transistors.

[0101] The second part of the transmission circuit 203b includes a second PMOS transistor MP201 and a third PMOS transistor MP202.

[0102] The drain of the second PMOS transistor MP201 and the drain of the third PMOS transistor MP202 are both connected to the voltage output terminal Vout. The source of the second PMOS transistor MP201 and the gate of the third PMOS transistor MP202 are both connected to the first boost node A. The source of the third PMOS transistor MP202 and the gate of the second PMOS transistor MP201 are both connected to the second boost node B.

[0103] In this embodiment of the invention, the first boost capacitor 206a is a MOS capacitor with its source and drain connected together, and the second boost capacitor 206b is a MOS capacitor with its source and drain connected together.

[0104] The first boost capacitor 206a and the second boost capacitor 206b are of equal size.

[0105] Preferably, the MOS capacitor constituting the first boost capacitor 206a is formed by connecting the source and drain of a third NMOS transistor MN203, with the source and drain of the third NMOS transistor MN203 serving as the first plate of the first boost capacitor 206a and the gate of the third NMOS transistor MN203 serving as the second plate of the first boost capacitor 206a.

[0106] The MOS capacitor that makes up the second boost capacitor 206b is formed by connecting the source and drain of the fourth NMOS transistor MN204. The source and drain of the fourth NMOS transistor MN204 serve as the first plate of the second boost capacitor 206b, and the gate of the fourth NMOS transistor MN204 serves as the second plate of the second boost capacitor 206b.

[0107] Both the third NMOS transistor MN203 and the fourth NMOS transistor MN204 are native NMOS transistors.

[0108] The working principle of the charge pump unit 201 is as follows: Figure 4As shown, when clkout is low, node A is also low, while node B, which is inversely phase to node A, is high. Thus, MN201 turns on, and the voltage input Vin charges node A. Since the voltage input Vin is also represented by Vin, after charging, node A is at Vin. After charging, clkout becomes high (Vdd1), MN201 turns off, and the voltage level of node A becomes Vdd1 + Vin. At this point, node B is low, MP201 turns on, and the voltage from node A is transmitted to the voltage output Vout. The charging and discharging of node B is exactly inversely phase to that of node A.

[0109] Figure 3 In the first stage, the voltage input terminal of the charge pump unit 201 is Vdd, and the output terminal is connected to the input terminal of the next stage. In subsequent stages, the input terminal is connected to the output terminal of the previous stage, and the output terminal is connected to the input terminal of the next stage. The output terminal Vout of the last stage serves as the output terminal of the charge pump.

[0110] This invention can set the power supply voltage (i.e., the output power supply voltage) of the inverter at the output terminal of the first plate of the boost capacitor in the corresponding charge pump unit 201, thereby setting the high level of the clock output signal input to the first plate of the boost capacitor, and thus adjusting the voltage stress of the second plate of the boost capacitor, i.e., the boost node. Through the voltage generation circuit 301, the output power supply voltage can be made lower than the internal power supply voltage Vdd of the chip and can be clamped by the reference voltage Vref. This avoids the adverse effects of large voltage fluctuations caused by a large power supply voltage Vdd on the voltage stress of the boost node, thereby reducing the voltage stress of the boost node of the corresponding charge pump unit 201.

[0111] This invention allows for step-by-step setting of the output power supply voltage of each stage of the charge pump unit 201. Because the output voltage of each stage of the charge pump unit 201 increases with the number of stages, the output power supply voltage of each stage of the charge pump unit 201 before the voltage stress problem at the boost node is generated can be maintained at the power supply voltage Vdd. After the voltage stress problem at the boost node is generated, i.e., after the kth stage, the output power supply voltage of each stage of the charge pump unit 201 is clamped and fixed with a reference voltage Vref, thereby preventing the voltage stress problem at the boost node from occurring in the entire charge pump.

[0112] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A charge pump, characterized in that, It includes n-stage charge pump units cascaded together, where n is greater than or equal to 1; Each of the charge pump units includes a boost circuit unit and a transmission unit; The boost circuit unit includes a boost capacitor and a clock input circuit; The clock input circuit connects the clock input signal to its input terminal and outputs the clock output signal to the first plate of the boost capacitor. The second plate of the boost capacitor is a boost node and is connected to the transmission unit; The clock input circuit includes an output inverter, the output of which serves as the output of the clock input circuit; the power supply terminal of the output inverter is connected to the output power supply voltage, and the high level of the clock output signal is determined by the output power supply voltage. Starting with the charge pump unit at stage k, where k is greater than or equal to 1 and less than or equal to n, the output power supply voltage is output by a voltage generation circuit connected to the power supply voltage and fixed by a reference voltage clamp. The output power supply voltage is less than the power supply voltage to reduce the voltage stress at the boost node of the charge pump units at stages k and above. The voltage generating circuit outputs multiple power supply voltages of different magnitudes at the output terminals. Starting from the kth stage, as the stage number increases, the magnitude of the power supply voltage at the output terminal of the charge pump unit at the corresponding stage gradually decreases.

2. The charge pump as claimed in claim 1, characterized in that: The voltage generating circuit outputs two output terminal power supply voltages of different magnitudes, namely the first output terminal power supply voltage and the second output terminal power supply voltage, wherein the first output terminal power supply voltage is greater than the second output terminal power supply voltage. k equals n-1, the output power supply voltage of the charge pump unit of the (n-1)th stage adopts the first output power supply voltage, and the output power supply voltage of the charge pump unit of the nth stage adopts the second output power supply voltage.

3. The charge pump as described in claim 1 or 2, characterized in that: When k is greater than 1, the output power supply voltage of the charge pump unit from stage 1 to stage (k-1) remains the same as the power supply voltage.

4. The charge pump as described in claim 2, characterized in that: The voltage generation circuit includes: a comparator, a first PMOS transistor, and a resistor string; The first input terminal of the comparator is connected to a reference voltage; The source of the first PMOS transistor is connected to the power supply voltage; The gate of the first PMOS transistor is connected to the output terminal of the comparator; The resistor is connected in series between the drain of the first PMOS transistor and ground; The resistor string includes three output terminals, which respectively output the power supply voltage of the first output terminal, the power supply voltage of the second output terminal, and the feedback voltage; The feedback voltage is connected to the second input terminal of the comparator.

5. The charge pump as claimed in claim 1, characterized in that: The boost capacitor is divided into a first boost capacitor and a second boost capacitor, and the clock input circuit is also divided into a first clock input circuit and a second clock input circuit. The second plate of the first boost capacitor is the first boost node, and the second plate of the second boost capacitor is the second boost node. The first boost node and the second boost node are out of phase. The inverter at the output terminal of the first clock input circuit is a first output inverter, and the inverter at the output terminal of the second clock input circuit is a second output inverter; the output terminal of the first output inverter outputs a first clock output signal, and the output terminal of the second output inverter outputs a second clock output signal. The input terminal of the first clock input circuit is connected to the clock input signal, and a first buffer circuit is connected between the input terminal of the first clock input circuit and the inverter of the first output terminal. The input terminal of the second clock input circuit is connected to the clock input signal, and a second buffer circuit is connected between the input terminal and the inverter of the second output terminal of the second clock input circuit. The first buffer circuit and the second buffer circuit invert the first clock output signal and the second clock output signal.

6. The charge pump as described in claim 5, characterized in that: The first buffer circuit consists of an inverting buffer, and the second buffer circuit consists of a non-inverting buffer.

7. The charge pump as claimed in claim 6, characterized in that: The transmission unit includes a voltage input terminal, a voltage output terminal, a first part of the transmission circuit, and a second part of the transmission circuit. The first part of the transmission circuit is disposed between the voltage input terminal and the first boost node and the second boost node; when the first boost node is charged, the first part of the transmission circuit enables the voltage input terminal and the first boost node to conduct and enables the voltage input terminal and the second boost node to disconnect. When the second boost node is charged, the first part of the transmission circuit connects the voltage input terminal and the second boost node and disconnects the voltage input terminal from the first boost node. The second part of the transmission circuit is disposed between the voltage output terminal and the first boost node and the second boost node; When the first boost node is fully charged, the second part of the transmission circuit connects the voltage output terminal to the first boost node and disconnects the voltage output terminal from the second boost node. When the second boost node is fully charged, the second part of the transmission circuit connects the voltage output terminal and the second boost node and disconnects the voltage output terminal from the first boost node.

8. The charge pump as claimed in claim 7, characterized in that: The first part of the transmission circuit includes a first NMOS transistor and a second NMOS transistor; The drains of the first NMOS transistor and the second NMOS transistor are both connected to the voltage input terminal. The source of the first NMOS transistor and the gate of the second NMOS transistor are both connected to the first boost node. The source of the second NMOS transistor and the gate of the first NMOS transistor are both connected to the second boost node.

9. The charge pump as claimed in claim 8, characterized in that: Both the first NMOS transistor and the second NMOS transistor are native NMOS transistors.

10. The charge pump as claimed in claim 7, characterized in that: The second part of the transmission circuit includes a second PMOS transistor and a third PMOS transistor; The drain of the second PMOS transistor and the drain of the third PMOS transistor are both connected to the voltage output terminal. The source of the second PMOS transistor and the gate of the third PMOS transistor are both connected to the first boost node. The source of the third PMOS transistor and the gate of the second PMOS transistor are both connected to the second boost node.

11. The charge pump as claimed in claim 5, characterized in that: The first boost capacitor is a MOS capacitor with its source and drain connected together, and the second boost capacitor is a MOS capacitor with its source and drain connected together.

12. The charge pump as claimed in claim 11, characterized in that: The first boost capacitor and the second boost capacitor are of equal size.

13. The charge pump as claimed in claim 12, characterized in that: The MOS capacitor that makes up the first boost capacitor is formed by connecting the source and drain of a third NMOS transistor. The source and drain of the third NMOS transistor serve as the first plate of the first boost capacitor, and the gate of the third NMOS transistor serves as the second plate of the first boost capacitor. The MOS capacitor that makes up the second boost capacitor is formed by connecting the source and drain of the fourth NMOS transistor. The source and drain of the fourth NMOS transistor serve as the first plate of the second boost capacitor, and the gate of the fourth NMOS transistor serves as the second plate of the second boost capacitor.

14. The charge pump as claimed in claim 13, characterized in that: Both the third NMOS transistor and the fourth NMOS transistor are native NMOS transistors.

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