Signal conversion circuit

Abstract

The application relates to a signal conversion circuit. The circuit comprises inputting an input signal into internal multiple nodes through an inverter, driving different modules to work, and the modules comprise a signal input and voltage lifting function module, a voltage conversion and latching function module and a voltage bias function module. The circuit can realize corresponding functions through different modules, input the input signal into the internal multiple nodes through the inverter, drive different modules to work, adopt a diode unidirectional charging method and a capacitor coupling method, shorten the signal conversion delay, and transmit the signal from a low voltage end to a high voltage end.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a signal conversion circuit. Background Technology

[0002] Today, integrated circuits typically contain multiple voltage domains, each with different operating voltages. Normally, a simple buffer can convert a signal from a high-voltage domain to a low-voltage domain. However, converting a signal from a low-voltage domain to a high-voltage domain requires more complex circuitry. The current mainstream circuit uses a differential interlock structure, such as... Figure 1 As shown, however, when using this structure to switch from one voltage state to another, it is necessary to overcome the previous latch state to reverse it, which results in a long delay. Summary of the Invention

[0003] Therefore, it is necessary to provide a voltage signal conversion circuit with a shorter delay to address the aforementioned technical problems.

[0004] In a first aspect, this application provides a signal conversion circuit, the circuit comprising:

[0005] The input signal is introduced into multiple internal nodes by an inverter to drive different modules of the circuit. The modules include a signal input and voltage boosting module, a voltage conversion and latching module, and a voltage biasing module.

[0006] The signal input and voltage boosting function module includes: a signal input terminal, a low-voltage power input terminal, a first output terminal and a second output terminal. The first output terminal is connected to the voltage bias function module, and the second output terminal is connected to the voltage conversion and latching function module.

[0007] The voltage conversion and latching function module includes: a high-voltage power input terminal, a signal output terminal, a first input terminal, and a second input terminal. The signal output terminal is connected to the second input terminal of the voltage bias function module, the first input terminal is connected to the output terminal of the voltage bias function module, and the second input terminal is connected to the second output terminal of the signal input and voltage boost function module.

[0008] The voltage biasing function module includes: a high-voltage power input terminal, a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to the first output terminal of the signal input and voltage boosting function module, and the second input terminal and the output terminal are connected to the voltage conversion and latching function module.

[0009] In one embodiment, the signal input and voltage boosting function module includes:

[0010] First inverter, second inverter, third inverter, first capacitor, zeroth PMOS transistor, zeroth NOMS transistor, Zener diode;

[0011] The first inverter, the second inverter, and the third inverter are connected in series.

[0012] The input terminal of the first inverter is the signal input terminal, and the output terminal of the first inverter is the first output terminal of the signal input and voltage boosting function module.

[0013] The output terminal of the second inverter is connected to the first terminal of the zeroth POMS transistor through the first capacitor, and is also connected to the cathode terminal of the Zener diode;

[0014] The output terminal of the third inverter is simultaneously connected to the third terminal of the zeroth PMOS transistor and the zeroth NOMS transistor.

[0015] The first end of the zeroth NOMS transistor is connected to ground, and the second end is connected to the second end of the zeroth POMS transistor, serving as the second output terminal of the signal input and voltage boosting function module.

[0016] The anode of the Zener diode is connected to a low-voltage power supply, serving as the low-voltage power input terminal of the signal input and voltage boosting function module.

[0017] In one embodiment, the voltage conversion and latching function module includes:

[0018] The first NOMS transistor, the fourth NOMS transistor, the third PMOS transistor, the fourth PMOS transistor, the second capacitor, and the sixth inverter;

[0019] The first terminal of the first NOMS transistor is connected to ground, the second terminal is connected to the input terminal of the sixth inverter, the third terminal serves as the second input terminal of the voltage conversion and latching function module, and is connected to the third terminal of the third PMOS transistor through the second capacitor;

[0020] The first terminal of the fourth NMOS transistor is connected to the high-voltage power supply as the high-voltage power supply input terminal, the second terminal is connected to the third terminal of the third PMOS transistor, and the third terminal is connected to the output terminal of the sixth inverter.

[0021] The first terminal of the third PMOS transistor is connected to the high-voltage power supply as the high-voltage power supply input terminal, the second terminal is connected to the input terminal of the sixth inverter, and the third terminal serves as the first input terminal of the voltage conversion and latching function module.

[0022] The first terminal of the fourth PMOS transistor is connected to the high-voltage power supply as the high-voltage power supply input terminal, the second terminal is connected to the input terminal of the sixth inverter, and the third terminal is connected to the output terminal of the sixth inverter.

[0023] In one embodiment, the voltage biasing function module includes:

[0024] Fourth inverter, fifth inverter, first PMOS transistor, second PMOS transistor, second NOMS transistor, third NOMS transistor;

[0025] The input terminal of the fourth inverter serves as the second input terminal of the voltage biasing function module, and its output terminal is connected to the third terminal of the second PMOS transistor and the input terminal of the fifth inverter.

[0026] The output terminal of the fifth inverter is connected to the third terminal of the second NMOS transistor;

[0027] The first terminal of the first PMOS transistor is connected to the high-voltage power supply as the high-voltage power supply input terminal, and the second terminal is connected to the third terminal, the second terminal of the third NMOS transistor, and the second terminal of the second PMOS transistor.

[0028] The first terminal of the second PMOS transistor serves as the output terminal of the voltage biasing function module.

[0029] The first terminal of the second NMOS transistor is connected to ground, and the second terminal is connected to the first terminal of the third NMOS transistor;

[0030] The second terminal of the third NMOS transistor is connected to the second terminal of the first PMOS transistor, and the third terminal serves as the first input terminal of the voltage biasing function module.

[0031] In one embodiment, the circuit includes:

[0032] The first terminal of each NMOS and PMOS transistor is the source, the second terminal is the drain, and the third terminal is the gate.

[0033] In one embodiment, the circuit includes:

[0034] The on-resistance of the fourth PMOS transistor is much smaller than the off-resistance of the first NMOS transistor, and it is used to latch the current signal state.

[0035] In one embodiment, the circuit includes:

[0036] The gate voltage of the first NMOS transistor NM1 varies between 0 voltage and "2LVDD-Vpn", while the voltage operating range of the third PMOS transistor is between the high-voltage power supply HVDD and "HVDD-(2LVDD-Vpn)". The absolute range of both is much larger than the threshold voltage of the high-voltage devices NMOS and PMOS.

[0037] In one embodiment, the circuit includes:

[0038] When the input signal resides at a low voltage for a long time, the second PMOS transistor is in the off state, but its parasitic diode will also experience leakage, affecting other circuits.

[0039] In one embodiment, the circuit includes:

[0040] The first PMOS transistor, the second NMOS transistor, and the third NMOS transistor are used to shorten the signal switching delay during the signal switching process.

[0041] In one embodiment, the circuit includes:

[0042] Each NMOS transistor and PMOS transistor also includes a fourth terminal. The fourth terminal of each NMOS transistor is connected to ground, and the fourth terminal of each PMOS transistor is connected to the first terminal of each PMOS transistor. The fourth terminal of each NMOS transistor and PMOS transistor is the body electrode.

[0043] The above signal conversion circuit has at least the following beneficial effects:

[0044] This application uses inverters to introduce input signals to multiple internal nodes, driving different modules to operate. In the signal input and voltage boosting module, capacitors and Zener diodes are added to boost the voltage and drive the zeroth NMOS transistor NM0. In the voltage conversion and latching module, the first NMOS transistor NM1 and the third PMOS transistor PM3 complete the signal voltage conversion, while the fourth NMOS transistor NM4 and the fourth PMOS transistor PM4 latch the current signal state. The voltage biasing module uses the first PMOS transistor PM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 to bias the gate terminal ld of the first NMOS transistor NM1, shortening the signal conversion delay. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a block diagram of a conventional voltage signal conversion circuit;

[0047] Figure 2 This is a circuit block diagram of a signal conversion circuit in one embodiment;

[0048] Figure 3This is a schematic diagram of the circuit's operating waveform when the input signal in rises from a low voltage to a high voltage in one embodiment;

[0049] Figure 4 This is a schematic diagram of the circuit's operating process when the input signal in drops from a high voltage to a low voltage in one embodiment. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0051] In some embodiments of this application, an inverter is denoted by inv, a P-channel positive metal-oxide-semiconductor field-effect transistor is denoted by PMOS, an N-channel negative metal-oxide-semiconductor field-effect transistor is denoted by PMOS, a low-voltage power supply is denoted by LVDD, and a high-voltage power supply is denoted by HVDD.

[0052] In one embodiment, such as Figure 2 As shown, a signal conversion circuit is provided, the circuit comprising:

[0053] The input signal is introduced into multiple internal nodes by an inverter to drive different modules of the circuit. The modules include a signal input and voltage boosting module, a voltage conversion and latching module, and a voltage biasing module.

[0054] The signal input and voltage boosting function module includes: a signal input terminal, a low-voltage power input terminal, a first output terminal and a second output terminal. The first output terminal is connected to the voltage bias function module, and the second output terminal is connected to the voltage conversion and latching function module.

[0055] The voltage conversion and latching function module includes: a high-voltage power input terminal, a signal output terminal, a first input terminal, and a second input terminal. The signal output terminal is connected to the second input terminal of the voltage bias function module, the first input terminal is connected to the output terminal of the voltage bias function module, and the second input terminal is connected to the second output terminal of the signal input and voltage boost function module.

[0056] The voltage biasing function module includes: a high-voltage power input terminal, a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to the first output terminal of the signal input and voltage boosting function module, and the second input terminal and the output terminal are connected to the voltage conversion and latching function module.

[0057] In this embodiment, after the input signal enters the circuit from the input port, it passes through an inverter, and the converted high or low voltage is input to different modules through a preset circuit. Each module selects an operating or shut-off state according to the input signal, realizing the conversion of a low-voltage high-speed signal into a high-voltage signal. The signal input and voltage boosting function module is responsible for receiving information from field devices or control devices, performing signal level conversion, and then transmitting the conversion result to other modules for processing. The voltage biasing function module shortens the signal conversion time. The voltage conversion and latching function module latches the current signal state to ensure a stable voltage state at the signal output terminal.

[0058] After the voltage signal is input to the voltage boosting module from the signal input terminal, it can be transmitted from the first output terminal to the first input terminal of the voltage biasing module and the second input terminal of the voltage conversion and latching module from the first output terminal and the second output terminal, respectively. The voltage conversion and latching module transmits the signal to the second input terminal of the voltage biasing module through the signal output terminal, and the voltage biasing module transmits the signal to the first input terminal of the voltage biasing module through the output terminal.

[0059] In one embodiment, the signal input and voltage boosting function module includes: a first inverter inv1, a second inverter inv2, a third inverter inv3, a first capacitor C1, a zero-th PMOS transistor PMO, a zero-th NMOS transistor NMO, and a Zener diode; the first inverter inv1, the second inverter inv2, and the third inverter inv3 are connected in series; the input terminal of the first inverter inv1 serves as the signal input terminal in, and the output terminal 1a of the first inverter inv1 serves as the first output terminal of the signal input and voltage boosting function module; the output terminal 1b of the second inverter inv2 is connected through the... The first capacitor C1 is connected to the first terminal of the zeroth PMOS transistor PM0 and to the cathode terminal lv of the Zener diode; the output terminal lc of the third inverter inv3 is connected to the third terminals of both the zeroth PMOS transistor PM0 and the zeroth NOMS transistor NM0; the first terminal of the zeroth NOMS transistor NM0 is connected to ground, and the second terminal is connected to the second terminal of the zeroth PMOS transistor PM0, serving as the second output terminal of the signal input and voltage boosting function module; the anode terminal of the Zener diode is connected to the low-voltage power supply LVDD, serving as the low-voltage power supply input terminal of the signal input and voltage boosting function module.

[0060] Specifically, an inverter can reverse the phase of an input signal by 180 degrees, achieving level conversion. Capacitor C1 serves to boost the voltage in the circuit. The diode maintains unidirectional conduction between nodes LV and LVDD; that is, when the voltage of LV is lower than the voltage of LVDD, the diode charges to raise its voltage to near LVDD. When the voltage of LV is higher than LVDD, the diode does not conduct, preventing charge from discharging to LVDD, thus maintaining the high voltage of LV.

[0061] When the input signal in is a rising edge, the output terminal la of the first inverter inv1 is a falling edge, and the signal is transmitted to the first input terminal of the voltage biasing function module through the first output terminal of the signal input and voltage boosting function module. The output terminal lb of the second inverter inv2 is a rising edge, and through the coupling effect of the first capacitor C1, it raises the voltage at the cathode lv of the Zener diode. The output terminal lc of the third inverter inv3 is a falling edge, the zeroth NMOS transistor NM0 is cut off, and the zeroth PMOS transistor PM0 is turned on. Therefore, the charge on the cathode lv of the Zener diode is transferred to the voltage conversion and latching function module through the zeroth PMOS transistor PM0.

[0062] Before the input signal in rises, the output terminal lb of the second inverter inv2 is at a low voltage, and the output terminal lc of the third inverter inv3 is at a high voltage. The zeroth NMOS transistor NM0 is turned on, and the zeroth PMOS transistor PM0 is turned off. Leakage causes the cathode LV of the Zener diode to not be able to maintain a voltage higher than the low-voltage power supply LVDD for a long time. The maximum voltage can only be equal to the low-voltage power supply LVDD minus the PN junction voltage drop Vpn of the Zener diode, which is "LVDD-Vpn". In advanced processes, the value of Vpn is approximately between 0.3 and 0.4V.

[0063] During the rise of the input signal in, the voltage at the output terminal lb of the second inverter inv2 at node 1 rises from 0 to LVDD. The first capacitor C1 couples the voltage, causing the voltage at the cathode lv of the Zener diode at node 1 to rise from "LVDD-Vpn" to "2LVDD-Vpn". The output terminal lc of the third inverter inv3 is at a low voltage. The zeroth NMOS transistor NM0 is cut off, and the zeroth PMOS transistor PM0 is turned on, transmitting the voltage "2LVDD-Vpn" to the second input terminal of the voltage conversion and latching function module.

[0064] If the input signal in remains at a high voltage for a long time, the voltage at the output terminal lb of the second inverter inv2 will reach node lv through the coupling of the first capacitor C1. Then, the voltage at the cathode terminal lv of the node Zener diode will drop to "LVDD-Vpn" due to leakage.

[0065] When the input signal in drops from a high voltage to a low voltage, the voltage at the output terminal la of the first inverter inv1 rises to LVDD, and the voltage at the output terminal lb of the second inverter inv2 drops. Through the coupling effect of the first capacitor C1, the voltage at the cathode lv of the Zener diode is also pulled to the voltage value of "LVDD-Vpn". At this time, the zeroth NMOS transistor NM0 is turned on, and the zeroth PMOS transistor PM0 is turned off.

[0066] If the input signal in remains at a low voltage for a long time, the voltage at the cathode lv of the Zener diode will always be at the voltage value of "LVDD-Vpn", the zeroth NMOS transistor NM0 will be turned on, and the zeroth PMOS transistor PM0 will be turned off.

[0067] In one embodiment, the voltage conversion and latching function module includes:

[0068] The first NMOS transistor NM1, the fourth NMOS transistor NM4, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the second capacitor C2, and the sixth inverter inv6;

[0069] The first terminal of the first NOMS transistor NM1 is connected to ground, the second terminal is connected to the input terminal of the sixth inverter inv6, the third terminal serves as the second input terminal of the voltage conversion and latching function module, and is connected to the third terminal of the third PMOS transistor PM3 through the second capacitor C2.

[0070] The first terminal of the fourth NMOS transistor NM4 is connected to the high-voltage power supply as the high-voltage power supply input terminal, the second terminal is connected to the third terminal of the third PMOS transistor PM3, and the third terminal is connected to the output terminal of the sixth inverter inv6.

[0071] The first terminal of the third PMOS transistor PM3 is connected to the high-voltage power supply as the high-voltage power supply input terminal, the second terminal is connected to the input terminal of the sixth inverter inv6, and the third terminal serves as the first input terminal of the voltage conversion and latching function module.

[0072] The first terminal of the fourth PMOS transistor PM4 is connected to the high-voltage power supply as the high-voltage power supply input terminal, the second terminal is connected to the input terminal of the sixth inverter inv6, and the third terminal is connected to the output terminal of the sixth inverter inv6.

[0073] Specifically, when the input signal in is a rising edge, the voltage at the gate terminal ld of the first NMOS transistor NM1 is also raised, and the first NMOS transistor NM1 turns on, starting to discharge the charge at the drain terminal he of the first NMOS transistor NM1. At the same time, the coupling effect of the second capacitor C2 raises the voltage at the gate terminal hd of the third PMOS transistor PM3, and the third PMOS transistor PM3 turns off, closing the path to replenish the charge at the drain terminal he of the first NMOS transistor NM1. As a result, the voltage at the drain terminal he of the first NMOS transistor NM1 decreases, and the potential at the signal output terminal out rises. The fourth PMOS transistor PM4 turns off, and the fourth NMOS transistor NM4 turns on, thus locking the high voltage state at the gate terminal hd of the third PMOS transistor.

[0074] Before the input signal in rises, the voltage at the gate terminal hd of the first NMOS transistor NM1 is low, and the first NMOS transistor NM1 is cut off. The voltage signal reaches the gate terminal hd of the third PMOS transistor PM3 through the second capacitor C2, thereby turning on the third PMOS transistor PM3. The voltage at node he rises, and through the sixth inverter inv6, the signal output terminal out is low. Therefore, the fourth PMOS transistor PM4 turns on, locking the high voltage state at the drain terminal he of the first NMOS transistor NM1 at node he.

[0075] During the rise of the input signal in, the voltage at the gate terminal ld of the first NMOS transistor NM1 at node Node 1 rises to "2LVDD-Vpn", which reduces the on-resistance of the first NMOS transistor NM1 and provides stronger discharge capability at the drain terminal he of the first NMOS transistor NM1. Moreover, because it is much smaller than the on-resistance of the fourth PMOS transistor PM4, it will not be affected by the latching effect of the fourth PMOS transistor PM4. Due to the coupling of the second capacitor C2, the voltage at the gate terminal hd of the third PMOS transistor PM3 at node Node 1 will also change by approximately the same magnitude, ensuring that the third PMOS transistor PM3 is turned off.

[0076] The input signal in resides at a high voltage for a long time, the first NMOS transistor NM1 is turned on, and the voltage at node he is low. After passing through the sixth inverter inv6, the signal output terminal out is high voltage, the fourth NMOS transistor NM4 is turned on, and the third NMOS transistor NM3 is turned off, so the voltage at node hc is high voltage, while the voltage at node ha is low voltage. The second PMOS transistor PM2 is turned on, so the voltage at node hd is high voltage, and the third PMOS transistor PM3 is turned off. Therefore, the drain terminal he of the first NMOS transistor NM1 will still remain at a low potential.

[0077] When the input signal in drops from high voltage to low voltage, the first NMOS transistor NM1 is turned off. Due to the coupling effect of the second capacitor C2, the voltage at the gate terminal hd of the third PMOS transistor PM3 is also pulled down. Since the second PMOS transistor PM2 is turned on, the charge at the gate terminal hd of the third PMOS transistor PM3 also begins to be discharged through the path of NM2 and NM3, resulting in a voltage drop. There are two mechanisms that cause the voltage drop at the gate terminal hd of the third PMOS transistor PM3: the third PMOS transistor PM3 is turned on, and the voltage at node he is high. After passing through the sixth inverter inv6, the signal output terminal out is low, ensuring that the fourth PMOS transistor PM4 can be fully turned on and has a sufficiently small on-resistance to charge the drain terminal he of the first NMOS transistor NM1 at node he, locking the drain terminal he of the first NMOS transistor NM1 at a high voltage, and maintaining the low voltage state of the signal output terminal out. The on-resistance of the second NMOS transistor NM2 and the third NMOS transistor NM3 is much smaller than that of the third NMOS transistor NM4. This ensures that when the output terminal 1a of the first inverter inv1 goes high, the charge at the gate terminal hd of the third PMOS transistor at node 3 can be discharged, instead of being compensated by the fourth NMOS transistor NM4 and unable to pull the voltage down.

[0078] If the input signal in remains at a low voltage for a long time, the gate voltage at point hd of the third PMOS transistor PM3 will slowly rise to "HVDD-Vthp-Vpn_par" because the parasitic diode of the second PMOS transistor PM2 will also leak current. Vpn_par is the PN junction voltage of the parasitic diode of the third PMOS transistor PM3. At this time, the on-resistance of the third PMOS transistor PM3 becomes smaller, and its pull-up capability is weakened. However, because of the latching of the fourth PMOS transistor PM4, the signal output terminal out can be maintained at a low voltage for a long time.

[0079] In one embodiment, the voltage biasing function module includes:

[0080] The system comprises a fourth inverter (inv4), a fifth inverter (inv5), a first PMOS transistor (PM1), a second PMOS transistor (PM2), a second NMOS transistor (NM2), and a third NMOS transistor (NM3). The input terminal of the fourth inverter (inv4) serves as the second input terminal of the voltage biasing module, and its output terminal is connected to the third terminal of the second PMOS transistor (PM2) and the input terminal of the fifth inverter (inv5). The output terminal of the fifth inverter (inv5) is connected to the third terminal of the second NMOS transistor (NM2). The first terminal of the first PMOS transistor (PM1) is connected to a high-voltage power supply, serving as its input terminal. Its second terminal is connected to the third terminal, the second terminal of the third NMOS transistor (NM3), and the second terminal of the second PMOS transistor (PM2). The first terminal of the second PMOS transistor (PM2) serves as the output terminal of the voltage biasing module. The first terminal of the second NMOS transistor (NM2) is connected to ground, and its second terminal is connected to the first terminal of the third NMOS transistor (NM3). The second terminal of the third NMOS transistor (NM3) is connected to the second terminal of the first PMOS transistor (PM1), and its third terminal serves as the first input terminal of the voltage biasing module.

[0081] Specifically, when the input signal in is a rising edge, the output terminal la of the first inverter inv1 is a falling edge, the third NMOS transistor NM3 is cut off, and the voltage biasing function module does not function.

[0082] Before the input signal in rises, the signal output terminal out is at a low voltage, the output terminal ha of the fourth inverter inv4 is at a high voltage, the second PMOS transistor PM2 is cut off, and the output terminal hb of the fifth inverter inv5 is at a low voltage. The gate terminal hb of the second NMOS transistor NM2 is also at a low voltage, and the second NMOS transistor NM2 is cut off. Therefore, the path from the first PMOS transistor PM1 to the third NMOS transistor NM3 to the second NMOS transistor NM2 does not consume static current.

[0083] During the rise of the input signal in, the output terminal la of the first inverter inv1 is at a low voltage, the third NMOS transistor NM3 is off, and the path from the first PMOS transistor PM1 to the third NMOS transistor NM3 to the second NMOS transistor NM2 consumes no quiescent current. When the signal output terminal out also rises to a high voltage, after a certain delay, the gate terminal hb of the second NMOS transistor NM2 is also at a high voltage, and the second NMOS transistor NM2 is turned on. However, because the third NMOS transistor NM3 is off, there is still no quiescent DC current consumption in this path. This process can be found in [reference needed]. Figure 3 .

[0084] If the input signal in remains at a high voltage for a long time, the output terminal la of the first inverter inv1 will always be at a low voltage, and the third NMOS transistor NM3 will be cut off. There is still no static DC current consumption on this path.

[0085] When the input signal in drops from a high voltage to a low voltage, the output terminal la of the first inverter inv1, initially at a low voltage, gradually rises to LVDD. The third NMOS transistor NM3 turns on, and current begins to flow through the path from the first PMOS transistor PM1 to the third NMOS transistor NM3 to the second NMOS transistor NM2. After a certain delay, the low voltage state at the signal output terminal out, through the series inverters inv4 and inv5, reaches the gate terminal hb of the second NMOS transistor NM2. The second NMOS transistor NM2 turns off, thus shutting off the quiescent current in the path from the first PMOS transistor PM1 to the third NMOS transistor NM3 to the second NMOS transistor NM2. Furthermore, there is a sufficiently long time between the high voltage at the output terminal la of the first inverter inv1 and the low voltage at the gate terminal hb of the second NMOS transistor NM2, ensuring that the path from the first PMOS transistor PM1 to the third NMOS transistor NM3 to the second NMOS transistor NM2 can fully discharge the charge at the gate terminal hd of the third PMOS transistor. This is because the circuit only turns off after the logic potential at the signal output terminal out becomes low. Please refer to this process Figure 4 .

[0086] If the input signal in remains at a low voltage for a long time, the voltage at the gate (hc) of the first PMOS transistor at node 1 will rise to approximately "HVDD-Vthp", where Vthp is the threshold voltage of the PMOS transistor. At this time, the signal output (out) is at a low voltage. Through the series inverters inv4 and inv5, the second NMOS transistor NM2 is turned off. Therefore, the quiescent current in the path from the first PMOS transistor PM1 to the third NMOS transistor NM3 to the second NMOS transistor NM2 is shut off. Figure 4 The Ids_NM2 in the middle.

[0087] In one embodiment, the first terminal of each NMOS transistor and PMOS transistor is the source, the second terminal of each NMOS transistor and PMOS transistor is the drain, and the third terminal of each NMOS transistor and PMOS transistor is the gate.

[0088] Specifically, when the gate voltage of an NMOS transistor is high, the NMOS transistor is turned on, and current flows from the drain to the source; when the gate voltage of an NMOS transistor is low, the NMOS transistor is turned off. When the gate voltage of a PMOS transistor is high, the PMOS transistor is turned off; when the gate voltage of a PMOS transistor is low, the PMOS transistor is turned on, and current flows from the source to the drain.

[0089] In one embodiment, the on-resistance of the fourth PMOS transistor is much smaller than the off-resistance of the first NMOS transistor, thereby latching the current signal state.

[0090] Specifically, the latching function of the voltage conversion and latching module is mainly completed by the fourth PMOS transistor PM4. Since the NMOS transistor is turned on at high voltage and the PMOS transistor is turned on at low voltage, when the on-resistance of the fourth PMOS transistor PM4 is much smaller than the off-resistance of the first NMOS transistor NM1, the fourth PMOS transistor PM4 stabilizes the voltage of node he, thus latching the current signal state.

[0091] In one embodiment, the circuit further includes:

[0092] The gate voltage of the first NMOS transistor varies between 0 voltage and "2LVDD-Vpn", while the voltage operating range of the third PMOS transistor is between the high voltage power supply HVDD and "HVDD-(2LVDD-Vpn)". The absolute range of both is much larger than the threshold voltage of the high voltage devices NMOS and PMOS.

[0093] Specifically, when the input signal in is low voltage, the output terminal lc of the third inverter inv3 is high voltage, the zeroth PMOS transistor PM0 is off, and the zeroth NMOS transistor NM0 is on. At this time, the gate voltage ld of the first NMOS transistor NM1 is 0. When the input signal in rises from low voltage to high voltage, the output terminal lc of the second inverter inv2 is high voltage. Through the coupling effect of the first capacitor C1, the voltage lv at the cathode of the node Zener diode rises from "LVDD-Vpn" to "2LVDD-Vpn". With the voltage at the output terminal lc of the third inverter inv3 low, the zeroth PMOS transistor PM0 is turned on, and the zeroth NMOS transistor NM0 is turned off. This raises the voltage at the gate terminal ld of the first NMOS transistor NM1 to "2LVDD-Vpn". Since the gate terminal ld voltage of the first NMOS transistor NM1 varies between 0 and "2LVDD-Vpn", the operating voltage range of the third PMOS transistor PM3 is between the high-voltage power supply HVDD and "HVDD-(2LVDD-Vpn)". Both the gate terminal ld voltage of the first NMOS transistor NM1 and the operating voltage range of the third PMOS transistor PM3 are higher than the threshold voltages of the NMOS and PMOS transistors, ensuring that the first NMOS transistor NM1 and the third PMOS transistor PM3 can conduct normally within this voltage transition range.

[0094] In one embodiment, the circuit further includes:

[0095] When the input signal resides at a low voltage for a long time, the second PMOS transistor PM2 is in the off state, but its parasitic diode will also experience leakage, affecting other circuits.

[0096] Specifically, the voltage at the gate terminal hc of the first PMOS transistor at the node will first rise to approximately "HVDD-Vthp", where Vthp is the threshold voltage of the PMOS transistor. Although the first PMOS transistor PM1 is in an off state, its parasitic diode will also leak current, causing the voltage at the gate terminal hd of the third PMOS transistor at the node to slowly rise to "HVDD-Vthp-Vpn_par", where Vpn_par is the PN junction voltage of the parasitic diode of PM1. The third PMOS transistor PM3 is turned on, and the voltage at the node he rises. Due to the latching of the fourth PMOS transistor PM4, the signal output terminal out can be maintained at a low voltage for a long time.

[0097] In one embodiment, the circuit further comprises:

[0098] The first PMOS transistor, the second NMOS transistor, and the third NMOS transistor are configured to reduce signal transition delay during the signal switching process.

[0099] Specifically, the first PMOS transistor PM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 function to apply a bias voltage to the gate terminal ld of the first NMOS transistor NM1 at the node during the signal switching process, which can shorten the transition time of the gate terminal ld of the first NMOS transistor NM1.

[0100] In one embodiment, the circuit further comprises:

[0101] Each of the NMOS transistors and PMOS transistors further includes a fourth terminal, the fourth terminal of each NMOS transistor is connected to ground, the fourth terminal of each PMOS transistor is connected to the first terminal of the corresponding PMOS transistor, and the fourth terminal of each of the NMOS transistors and PMOS transistors is a body terminal.

[0102] In this embodiment, the MOS transistor includes a gate, a source, a drain and a body terminal. Vth is an important parameter of the MOS transistor, which is the turn-on voltage. Vgs is the gate-source voltage. When Vgs<Vth, the MOS transistor is in a cut-off region. When Vgs>Vth and Vds<Vgs-Vth, the MOS transistor enters a linear region, and the MOS transistor is equivalent to a variable resistor controlled by Vgs. When Vgs>Vth and Vds>Vgs-Vth, the MOS transistor enters a saturation region.

[0103] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, all such combinations shall be regarded as the scope recorded in this specification.

[0104] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A signal conversion circuit, characterized in that, The circuit includes: The input signal is introduced into multiple nodes inside the circuit by an inverter, driving different modules of the circuit to work. The modules include a signal input and voltage boosting module, a voltage conversion and latching module, and a voltage biasing module. The signal input and voltage boosting function module includes: a signal input terminal, a low-voltage power input terminal, a first output terminal and a second output terminal. The first output terminal is connected to the voltage bias function module, and the second output terminal is connected to the voltage conversion and latching function module. The voltage conversion and latching function module includes: a high-voltage power input terminal, a signal output terminal, a first input terminal, and a second input terminal. The signal output terminal is connected to the second input terminal of the voltage bias function module, the first input terminal is connected to the output terminal of the voltage bias function module, and the second input terminal is connected to the second output terminal of the signal input and voltage boost function module. The voltage conversion and latching function module also includes: The first NMOS transistor, the fourth NMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the second capacitor, and the sixth inverter; The first terminal of the first NMOS transistor is connected to ground, the second terminal is connected to the input terminal of the sixth inverter, and the third terminal serves as the second input terminal of the voltage conversion and latching function module, and is connected to the third terminal of the third PMOS transistor through the second capacitor. The first terminal of the fourth NMOS transistor is connected to the high-voltage power supply as the high-voltage power supply input terminal, the second terminal is connected to the third terminal of the third PMOS transistor, and the third terminal is connected to the output terminal of the sixth inverter. The first terminal of the third PMOS transistor is connected to the high-voltage power supply as the high-voltage power supply input terminal, the second terminal is connected to the input terminal of the sixth inverter, and the third terminal serves as the first input terminal of the voltage conversion and latching function module. The first terminal of the fourth PMOS transistor is connected to the high-voltage power supply as the high-voltage power supply input terminal, the second terminal is connected to the input terminal of the sixth inverter, and the third terminal is connected to the output terminal of the sixth inverter. The voltage biasing function module includes: a high-voltage power input terminal, a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to the first output terminal of the signal input and voltage boosting function module, and the second input terminal and the output terminal are connected to the voltage conversion and latching function module.

2. The circuit according to claim 1, characterized in that, The signal input and voltage boosting function module includes: First inverter, second inverter, third inverter, first capacitor, zeroth PMOS transistor, zeroth NMOS transistor, Zener diode; The first inverter, the second inverter, and the third inverter are connected in series. The input terminal of the first inverter is the signal input terminal, and the output terminal of the first inverter is the first output terminal of the signal input and voltage boosting function module. The output terminal of the second inverter is connected to the first terminal of the zeroth PMOS transistor through the first capacitor, and is also connected to the cathode terminal of the Zener diode; The output terminal of the third inverter is simultaneously connected to the third terminal of both the zeroth PMOS transistor and the zeroth NMOS transistor. The first terminal of the zeroth NMOS transistor is connected to ground, and the second terminal is connected to the second terminal of the zeroth PMOS transistor, serving as the second output terminal of the signal input and voltage boosting function module. The anode of the Zener diode is connected to a low-voltage power supply, serving as the low-voltage power input terminal of the signal input and voltage boosting function module.

3. The circuit according to claim 1, characterized in that, The voltage biasing function module includes: Fourth inverter, fifth inverter, first PMOS transistor, second PMOS transistor, second NMOS transistor, third NMOS transistor; The input terminal of the fourth inverter serves as the second input terminal of the voltage biasing function module, and its output terminal is connected to the third terminal of the second PMOS transistor and the input terminal of the fifth inverter. The output terminal of the fifth inverter is connected to the third terminal of the second NMOS transistor; The first terminal of the first PMOS transistor is connected to the high-voltage power supply as the high-voltage power supply input terminal, and the second terminal is connected to the third terminal, the second terminal of the third NMOS transistor, and the second terminal of the second PMOS transistor. The first terminal of the second PMOS transistor serves as the output terminal of the voltage biasing function module. The first terminal of the second NMOS transistor is connected to ground, and the second terminal is connected to the first terminal of the third NMOS transistor; The second terminal of the third NMOS transistor is connected to the second terminal of the first PMOS transistor, and the third terminal serves as the first input terminal of the voltage biasing function module.

4. The circuit according to any one of claims 2 to 3, characterized in that, The first terminal of each NMOS and PMOS transistor is the source, the second terminal is the drain, and the third terminal is the gate.

5. The circuit according to claim 1, characterized in that, The circuit also includes: The on-resistance of the fourth PMOS transistor is much smaller than the off-resistance of the first NMOS transistor, and it is used to latch the current signal state.

6. The circuit according to claim 1, characterized in that, The gate voltage of the first NMOS transistor varies between 0 and "2LVDD-Vpn", while the operating voltage range of the third PMOS transistor is between the high-voltage power supply HVDD and "HVDD-(2LVDD-Vpn)". The absolute range of both is much larger than the threshold voltage of the high-voltage devices NMOS and PMOS. LVDD is the voltage of the low-voltage power supply, and Vpn is the PN junction voltage drop of the Zener diode.

7. The circuit according to claim 3, characterized in that, When the input signal resides at a low voltage for a long time, the second PMOS transistor is in the off state, but its parasitic diode will also experience leakage, affecting other circuits.

8. The circuit according to claim 3, characterized in that... The first PMOS transistor, the second NMOS transistor, and the third NMOS transistor are used to shorten the signal switching delay during the signal switching process.

9. The circuit according to claim 4, characterized in that, Each NMOS transistor and PMOS transistor also includes a fourth terminal. The fourth terminal of each NMOS transistor is connected to ground, and the fourth terminal of each PMOS transistor is connected to the first terminal of each PMOS transistor. The fourth terminal of each NMOS transistor and PMOS transistor is the body electrode.

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