Receiving circuit for adaptive impedance matching and method of operation thereof

Abstract

The present disclosure provides a receiving circuit for adaptive impedance matching and an operating method thereof. The receiving circuit comprises: a first amplification module configured to amplify an input signal input from an input end of the first amplification module to generate a first amplified signal; a mixing module, an input end of which is connected to an output end of the first amplification module, and which is configured to down-convert the first amplified signal to generate a down-converted signal; and a second amplification module, an input end of which is connected to an output end of the mixing module, and which is configured to amplify the down-converted signal to generate an output signal, wherein the first amplification module comprises an active negative feedback structure for providing adaptive impedance matching within a first bandwidth range.

Description

Technical Field

[0001] This disclosure relates to the field of circuit system technology, and more specifically, to a receiving circuit for adaptive impedance matching and its operation method. Background Technology

[0002] With the rapid development of mobile communication technology, people's demands for wireless applications are increasing, especially with the growing application of the Internet of Things (IoT). Impedance matching is an indispensable component for wireless applications. However, different application scenarios place different requirements on the matching circuit and performance of the RF receiver, such as operating frequency and effective bandwidth. Currently, the common matching circuit usually uses discrete passive components outside the chip, but using discrete passive components increases costs and also limits the effective bandwidth to some extent. Summary of the Invention

[0003] Technical issues

[0004] Currently, conventional RF receivers require external discrete passive components for impedance matching. When the application requires an effective bandwidth that equals 10% of the operating bandwidth (in this paper, taking the 470MHz–510MHz frequency range as an example, the effective bandwidth is the width of this frequency range, 40MHz, while the operating bandwidth is the center frequency of this frequency range, 490MHz), a single-stage LC matching circuit cannot cover this 10% ratio of effective to operating bandwidth due to the limitations of the quality factor (e.g., Q value) of the external discrete passive components. In this case, a pi-type network or a two-stage LC circuit is needed, but this increases the number of external components and noise, thus reducing receiver performance.

[0005] In addition, wideband matching may result in an inability to properly distinguish between blocking and useful signals. Both blocking and useful signals may be received simultaneously by the receiver, which increases the burden on the subsequent baseband circuitry of the receiver, such as the need to separate the useful and blocking signals.

[0006] Conventional receivers require modifications to the matching circuitry to accommodate different operating frequencies and bandwidths. This can be achieved by altering multiple sets of matching circuits, either internally or externally within the package or chip, to switch between different operating frequencies and bandwidths. For blocking, conventional receivers typically use surface acoustic wave (SAW) filters to isolate the blocking signal, thereby improving blocking performance. Another effective method for blocking is to use an N-path filter, but this design significantly increases power consumption.

[0007] Solution to the problem

[0008] Embodiments of this disclosure provide a receiver circuit for adaptive impedance matching, comprising: a first amplification module configured to amplify an input signal input from an input terminal of the first amplification module to generate a first amplified signal; a mixer module having its input terminal connected to the output terminal of the first amplification module and configured to down-convert the first amplified signal to generate a down-converted signal; and a second amplification module having its input terminal connected to the output terminal of the mixer module and configured to amplify the down-converted signal to generate an output signal, wherein the first amplification module includes an active negative feedback structure for providing adaptive impedance matching over a first bandwidth.

[0009] According to embodiments of this disclosure, the active negative feedback structure includes an active negative feedback low-noise amplifier, wherein the active negative feedback low-noise amplifier includes a feedback transistor, a bias transistor, a first amplifying transistor, and a second amplifying transistor. The source of the first amplifying transistor is connected to a power supply voltage, its gate is connected to the input terminal of the first amplifying module, and its drain is connected to the output terminal of the first amplifying module. The drain of the second amplifying transistor is connected to the output terminal of the first amplifying module, its gate is connected to the input terminal of the first amplifying module, and its source is connected to ground. The drain of the feedback transistor is connected to a power supply voltage, its gate is connected to the output terminal of the first amplifying module, and its source is connected to the input terminal of the first amplifying module. Furthermore, the drain of the bias transistor is connected to the input terminal of the first amplifying module, its gate is connected to a bias voltage, and its source is connected to ground.

[0010] According to embodiments of this disclosure, the transconductance of the feedback transistor is regulated via the bias voltage.

[0011] According to an embodiment of this disclosure, the mixing module includes an orthogonal passive mixer, which includes a local oscillator and a first to a fourth switching transistor. The local oscillator generates a first to a fourth local oscillator signal with phases increasing by 90 degrees sequentially to control the switching states of the first to the fourth switching transistors.

[0012] According to embodiments of this disclosure, the sources of the first to fourth switching transistors are respectively connected to the output terminal of the first amplification module; the gate of the first switching transistor is connected to the first local oscillator signal, and its drain is connected to the first output path of the mixing module; the gate of the second switching transistor is connected to the third local oscillator signal, and its drain is connected to the first output path of the mixing module; the gate of the third switching transistor is connected to the second local oscillator signal, and its drain is connected to the second output path of the mixing module; and the gate of the fourth switching transistor is connected to the fourth local oscillator signal, and its drain is connected to the second output path of the mixing module.

[0013] According to an embodiment of this disclosure, the second amplification module includes one or more transimpedance amplifiers, the input terminals of which are respectively connected to one or more output paths of the mixer module, and amplify the signals output via the one or more output paths of the mixer module.

[0014] According to embodiments of this disclosure, the active negative feedback structure includes a feedback transistor, wherein the first bandwidth range is determined at least in part based on the transconductance of the feedback transistor.

[0015] According to embodiments of this disclosure, the first bandwidth range is any one or more of 220MHz to 240MHz, 433.05MHz to 433.79MHz, 902MHz to 928MHz, 240MHz to 470MHz, 470MHz to 510MHz, and 220MHz to 510MHz.

[0016] According to an embodiment of this disclosure, the input signal is a radio frequency voltage signal, and the first amplified signal is a radio frequency current signal.

[0017] According to embodiments of this disclosure, the down-conversion signal is one or more intermediate frequency or baseband current signals, and the output signal is one or more intermediate frequency or baseband voltage signals.

[0018] Embodiments of this disclosure provide an operating method for a receiver circuit for adaptive impedance matching, the receiver circuit including a first amplification module, a mixing module, and a second amplification module. The method includes: amplifying an input signal input from an input terminal of the first amplification module to generate a first amplified signal by the first amplification module; down-converting the first amplified signal by the mixing module to generate a down-converted signal; and amplifying the down-converted signal by the second amplification module to generate an output signal, wherein the first amplification module includes an active negative feedback structure for providing adaptive impedance matching within a first bandwidth range.

[0019] Beneficial effects of the invention

[0020] Embodiments of this disclosure provide a receiver circuit for adaptive impedance matching. By employing an active negative feedback structure, it effectively solves the problem of requiring external discrete passive components for impedance matching. The receiver circuit according to embodiments of this disclosure can adaptively perform impedance matching for different channels within the effective bandwidth and isolate blocking signals without requiring external discrete passive components, while also without increasing power consumption, thereby improving receiver performance. Attached Figure Description

[0021] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0022] Figure 1 A schematic diagram of a receiver circuit for adaptive impedance matching according to an embodiment of the present disclosure is shown;

[0023] Figure 2 An example circuit diagram of a receiver circuit for adaptive impedance matching according to an embodiment of the present disclosure is shown;

[0024] Figure 3 A view showing the equivalent impedance of the mixer and transimpedance amplifier as seen from the input of the quadrature mixer according to an embodiment of the present disclosure;

[0025] Figure 4 This diagram shows a view of the equivalent impedance of the mixer and transimpedance amplifier, taken into account, from the input of the quadrature mixer according to an embodiment of the present disclosure; and

[0026] Figure 5 A flowchart illustrating an operation method of a receiver circuit for adaptive impedance matching according to an embodiment of the present disclosure is shown. Detailed Implementation

[0027] Before proceeding with the detailed description below, it may be advantageous to define certain words and phrases used throughout this patent document. The terms “coupled,” “connected,” and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are physically in contact with each other. The terms “transmit,” “receive,” and “communicate,” and their derivatives cover both direct and indirect communication. The terms “comprise,” “include,” and their derivatives refer to, but are not limited to, those including, those including, those including, those including, those including. The term “or” is inclusive, meaning and / or. The phrases “associated with,” “corresponding to,” and their derivatives refer to, including, being contained within, interconnected, containing, being included in, connected or connected to, coupled or coupled to, communicating with, cooperating, intertwined, juxtaposed, proximate, bound or bound to, having, having attributes, having a relationship or being related to, etc. The term “controller” refers to any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, local or remote. The phrase "at least one" when used with a list of items means that different combinations of one or more of the listed items may be used, and that only one item from the list may be required. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0028] Definitions of other specific words and phrases are provided throughout this patent document. Those skilled in the art will understand that, in many, if not most, cases, these definitions apply to the prior and future use of the words and phrases thus defined.

[0029] In this patent document, the application combinations of modules and the hierarchical division of submodules are for illustrative purposes only. Without departing from the scope of this disclosure, the application combinations of modules and the hierarchical division of submodules can be implemented in different ways. The embodiments of this disclosure can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey exemplary implementation methods to those skilled in the art. Embodiments of this disclosure can be combined to form other embodiments.

[0030] The present disclosure will now be described in detail with reference to exemplary embodiments thereof. However, the present disclosure is not limited to the embodiments described herein, which may be implemented in many different forms. The described embodiments are provided only to make the present disclosure thorough and complete, and to fully convey the concept of the present disclosure to those skilled in the art. Features of the various embodiments described may be combined with or substituted for each other, unless expressly excluded or should be excluded based on the context.

[0031] Figure 1 A schematic diagram of a receiver circuit 100 for adaptive impedance matching according to an embodiment of the present disclosure is shown.

[0032] like Figure 1 As shown, the receiver circuit 100 for adaptive impedance matching according to an embodiment of the present disclosure may include a first amplification module 101, a mixer module 102, and a second amplification module 103. In some embodiments, the first amplification module 101 may be configured to amplify an input signal INPUT (e.g., a radio frequency (RF) voltage signal) input from the input terminal of the first amplification module 101 to generate a first amplified signal. The input terminal of the mixer module 102 may be connected to the output terminal of the first amplification module 101 and may be configured to down-convert the first amplified signal output by the first amplification module 101 to generate a down-converted signal. The input terminal of the second amplification module 103 may be connected to the output terminal of the mixer module 102 and may be configured to amplify the down-converted signal output by the mixer module 102 to generate the output signal OUTPUT of the receiver circuit 100. According to an embodiment of the present disclosure, the first amplification module 101 may include an active negative feedback structure 104 for providing adaptive impedance matching within a first bandwidth (e.g., a specific effective bandwidth), the configuration of which will be described in detail below.

[0033] More specifically, Figure 2 An example circuit diagram of a receiver circuit 100 for adaptive impedance matching according to an embodiment of the present disclosure is shown.

[0034] like Figure 2 As shown, the active negative feedback structure 104 included in the first amplification module 101 can be an active negative feedback low noise amplifier (LNA). In some embodiments, the active negative feedback low noise amplifier (LNA) may include a feedback transistor MN. fb Bias transistor MN bias The first amplifying transistor MP1 and the second amplifying transistor MN1. It should be understood that, depending on the specific circuit configuration, each of these transistors can be one of any type of transistor, such as a P-type transistor (e.g., a PMOS transistor), an N-type transistor (e.g., an NMOS transistor), etc., without any limitation.

[0035] In some embodiments, such as Figure 2 As shown, the first amplifying transistor MP1 can be a P-type transistor, and the feedback transistor MN fb Bias transistor MN bias The first and second amplifying transistors, MN1, can be N-type transistors. For example... Figure 2As shown, the source of the first amplifying transistor MP1 can be connected to the power supply voltage VDD, its gate can be connected to the input terminal P1 of the first amplifying module 101, and its drain can be connected to the output terminal P2 of the first amplifying module 101. The drain of the second amplifying transistor MN1 can be connected to the output terminal P2 of the first amplifying module 101, its gate can be connected to the input terminal P1 of the first amplifying module 101, and its source can be connected to ground voltage GND. In some embodiments, a feedback resistor Rf can optionally be connected between the gate of the second amplifying transistor MN1 and the input terminal P1 of the first amplifying module 101 to adjust the gate voltage of the second amplifying transistor MN1. Feedback transistor MN fb The drain of the transistor can be connected to the power supply voltage VDD, its gate can be connected to the output terminal P2 of the first amplification module 101, and its source can be connected to the input terminal P1 of the first amplification module 101. Bias transistor MN bias The drain of the amplification module can be connected to the input terminal P1 of the first amplification module 101, and its gate can be connected to the bias voltage V. bias It is connected, and its source can be connected to ground voltage GND.

[0036] In some embodiments, the effective bandwidth (e.g., a first bandwidth range) for adaptive impedance matching of the receiver circuit 100 having an example structure according to embodiments of this disclosure can be at least partially based on the feedback transistor MN. fb transconductance gm fb To determine. Feedback transistors MN with different transconductance values. fb This can correspond to different effective bandwidths and / or operating bandwidths. For example, when selecting a feedback transistor MN with a first transconductance value... fb When the receiver circuit 100 is selected, the effective bandwidth for adaptive impedance matching can be 470MHz to 510MHz; when the feedback transistor MN with a second transconductance value is selected... fb At that time, the effective bandwidth for adaptive impedance matching in the receiving circuit 100 can be 220MHz to 240MHz; and so on. Furthermore, the feedback transistor MN... fb transconductance gm fb It can also be achieved through bias voltage V bias For bias transistor MN bias The gate voltage is adjusted for further regulation. Therefore, without changing the circuit structure or the connection or on / off state of circuit elements, the bias voltage V can be adjusted simply by adjusting the bias voltage V. bias The bandwidth range in which the receiver circuit 100, according to an example structure of an embodiment of the present disclosure, is capable of adaptive impedance matching can be changed, for example, switching between 220MHz to 240MHz and 470MHz to 510MHz.

[0037] More generally, in some embodiments, the bandwidth range within which the receiver circuit 100 of the example structure according to embodiments of this disclosure can perform adaptive impedance matching may depend on the frequency range of the local oscillator signal supported by the local oscillator included in the mixer module 102 described below. For example, the first bandwidth range described herein may be any bandwidth range below 3 GHz. More specifically, the first bandwidth range described herein may include, but is not limited to: 220 MHz to 240 MHz, 433 MHz (e.g., 433.05 MHz to 433.79 MHz) and 915 MHz (e.g., 902 MHz to 928 MHz) in the ISM band, 470 MHz to 510 MHz, 240 MHz to 470 MHz, 220 MHz to 510 MHz, etc.

[0038] Back Figure 2 In some embodiments, the mixing module 102 may be an orthogonal passive mixer (e.g., a switching mixer), which may include a local oscillator (not shown) and a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, and a fourth switching transistor M4. The local oscillator may generate a first local oscillator signal LO_I+, a second local oscillator signal LO_Q+, a third local oscillator signal LO_I-, and a fourth local oscillator signal LO_Q- with phases increasing sequentially by 90 degrees. For example, the first local oscillator signal LO_I+ may have a 0-degree phase shift, the second local oscillator signal LO_Q+ may have a 90-degree phase shift, the third local oscillator signal LO_I- may have a 180-degree phase shift, and the fourth local oscillator signal LO_Q- may have a 360-degree phase shift. In some embodiments, except for the different phase shifts, other aspects of the first to fourth local oscillator signals (e.g., frequency, amplitude, etc.) may be exactly the same. The first local oscillator signal LO_I+, the second local oscillator signal LO_Q+, the third local oscillator signal LO_I-, and the fourth local oscillator signal LO_Q- can be connected (for example, directly connected or connected through a corresponding capacitor) to the gate of a corresponding one of the first switching transistors M1, the second switching transistor M2, the third switching transistor M3, and the fourth switching transistor M4 to control their switching states. In this case, the switching frequency of each switch is controlled by the local oscillator signals, thereby enabling the mixing of the input signal.

[0039] Each of the first switching transistor M1, the second switching transistor M2, the third switching transistor M3, and the fourth switching transistor M4 can be any type of transistor, such as a P-type transistor or an N-type transistor; there are no restrictions here.

[0040] In such Figure 2In the illustrated embodiment, the first switching transistor M1 to the fourth switching transistor M4 can be N-type transistors. The sources of the first switching transistor M1 to the fourth switching transistor M4 can be connected to the output terminal P2 of the first amplification module 101, respectively. Furthermore, the gate of the first switching transistor M1 can be connected to the first local oscillator signal LO_I+, and its drain can be connected to the first output path PATH_I of the mixer module 102, for example, via the first path output point P4. The gate of the second switching transistor M2 can be connected to the third local oscillator signal LO_I-, and its drain can be connected to the first output path PATH_I of the mixer module 102, for example, via the first path output point P4. The gate of the third switching transistor M3 can be connected to the second local oscillator signal LO_Q+, and its drain can be connected to the second output path PATH_Q of the mixer module 102. The gate of the fourth switching transistor M4 can be connected to the fourth local oscillator signal LO_Q-, and its drain can be connected to the second output path PATH_Q of the mixer module 102. In this embodiment, the mixer module 102 can output two down-converted signals, one in phase and one quadrature, through two output paths, PATH_I and PATH_Q.

[0041] In some embodiments, specific control signals may also be connected, for example, to the gate of a corresponding one of the first switching transistor M1, the second switching transistor M2, the third switching transistor M3, and the fourth switching transistor M4 via corresponding resistors (not shown in the figures for simplicity), thereby allowing for smoother switching of the individual transistors, while the mixer conversion gain can be optimized by adjusting the appropriate value of the control signals.

[0042] In some embodiments, an isolation capacitor may be connected between the output terminal P2 of the first amplification module 101 and the input terminal P3 of the mixer module 102 to isolate the DC component in the circuit.

[0043] In some embodiments, the second amplification module 103 may include one or more transimpedance amplifiers (e.g., such as...). Figure 2 (as shown in TIA1 and TIA2). The inputs of one or more transimpedance amplifiers can be connected to one or more output paths of mixer module 102, respectively, and amplify the signals output via one or more output paths of mixer module 102. For example, the input of TIA1 can be connected to the first output path PATH_I of mixer module 102, and the input of TIA2 can be connected to the second output path PATH_Q of mixer module 102.

[0044] The working principle of the receiver circuit 100 for adaptive impedance matching according to an embodiment of the present disclosure is further described below with reference to specific examples.

[0045] The following explanation will use a scenario involving radio frequency signal reception and impedance matching as an example. Figure 2 As shown, the input signal INPUT can be an RF voltage signal. Generally, when the input signal is transmitted over the air, it needs to be received using an antenna, and the characteristic impedance of the antenna end is 50 ohms. In order to transmit the energy received by the antenna to the chip with minimal attenuation, the receiving end of the chip (e.g., receiving circuit 100) also needs to be impedance matched to 50 ohms.

[0046] The active negative feedback low-noise amplifier (LNA) in the receiving circuit 100 according to an embodiment of this disclosure can convert the received radio frequency (RF) voltage signal from a voltage signal to a current signal (e.g., an RF current signal) and amplify it. The amplified RF current signal can then be input to the next stage quadrature mixer. The quadrature mixer can down-convert the RF current signal to one or more intermediate frequency (IF) or baseband current signals, and then a transimpedance amplifier (TIA) converts one or more IF or baseband current signals to one or more IF or baseband voltage signals and amplifies them.

[0047] The active negative feedback structure (e.g., a feedback transistor structure) included in the active negative feedback low-noise amplifier (LNA) according to embodiments of the present disclosure can provide impedance matching over an ultra-wide bandwidth range (e.g., 230MHz to 510MHz). Furthermore, the current multiplexing structure (e.g., a structure of a first amplifying transistor MP1 plus a second amplifying transistor MN1) in the active negative feedback low-noise amplifier (LNA) according to embodiments of the present disclosure requires only half the current to achieve the same performance, such as the same equivalent transconductance, compared to a single amplifying transistor structure.

[0048] refer to Figure 2 The equivalent impedance Z at the input of the active negative feedback low noise amplifier (LNA) in the receiving circuit 100 according to an embodiment of this disclosure. in,LNA Mainly composed of feedback transistor MN fb The effective equivalent impedance Z is determined by the transconductance of the first amplifying transistor MP1 and the second amplifying transistor MN1, as well as the effective equivalent impedance of the mixer and transimpedance amplifiers (e.g., TIA1 and TIA2) as seen from the input of the quadrature mixer. For example, the equivalent impedance Z is determined by neglecting the feedback resistor Rf. in,LNA It can be defined by the following equation (1):

[0049]

[0050] Among them, gm fb For feedback transistor MN fb transconductance, gm n,pThe equivalent transconductance of the first amplifying transistor MP1 and the second amplifying transistor MN1 (for example, it can be the transconductance gm of the first amplifying transistor MP1) p The transconductance gm of the second amplifying transistor MN1 n (the sum of C) gs Let be the equivalent parasitic capacitance of the first amplifying transistor MP1 and the second amplifying transistor MN1, s be a parameter corresponding to a specific frequency range, and Z be the equivalent parasitic capacitance of the first amplifying transistor MP1 and the second amplifying transistor MN1. in,mixer For example Figure 3 The effective equivalent impedance of the mixer and transimpedance amplifiers (e.g., TIA1 and TIA2) as seen from the input of the quadrature mixer is shown.

[0051] Due to the transconductance of the feedback transistor and / or amplifying transistor of the receiving circuit 100 according to the embodiment of this disclosure, and the effective equivalent impedance Z at the mixer input, in,mixer It can maintain the same value over a very wide bandwidth range (e.g., 470MHz to 510MHz), so it can be seen from the above equation (1) that the transconductance of a specific feedback transistor and / or amplifying transistor and the effective equivalent impedance Z of a specific mixer input are related. in,mixer This enables the receiving circuit 100 to maintain its equivalent impedance at a specific value (e.g., 50 ohms) over a very wide bandwidth range (e.g., 470MHz to 510MHz).

[0052] On the other hand, when the transconductance of the feedback transistor and / or amplification transistor of the receiving circuit 100 is a fixed value, it can be seen from the above equation (1) (for ease of description, sC is not considered). gs According to an embodiment of the present disclosure, the equivalent impedance Z at the input of the active negative feedback low noise amplifier (LNA) in the receiving circuit 100 is... in,LNA The effective equivalent impedance Z at the mixer input terminal will be... in,mixer Change with change.

[0053] Furthermore, Figure 4 A view showing the equivalent impedance of the mixer and transimpedance amplifier, taken into account, from the input of the quadrature mixer according to an embodiment of the present disclosure.

[0054] Considering the load, the effective equivalent impedance Z at the mixer input is... in,mixer It can be defined by the following equation (2):

[0055]

[0056] Among them, R sw ω is the equivalent reactance of the switches (e.g., switching transistors M1 to M4) in the mixer. loZ is the frequency of the switches in the mixer (e.g., the frequency of the local oscillator signal), ω is the frequency of the input signal INPUT, and Z BB This is the equivalent impedance of the load.

[0057] As shown in equation (2) above, the effective equivalent impedance Z at the mixer input is... in,mixer It is positively correlated with the equivalent reactance of the switches in the mixer and the frequency of the local oscillator signal LO. Combined with the above, derived from equation (1): Z in,LNA The effective equivalent impedance Z at the mixer input terminal will be... in,mixer The overall input equivalent impedance Z in the receiving circuit 100 according to embodiments of this disclosure changes with the change in [the specific condition]. in,LNA It can change with the frequency of the local oscillator signal LO. For example, when the frequency of the local oscillator signal LO is 490MHz, the overall input equivalent impedance Z in the receiving circuit 100 according to the embodiment of this disclosure is... in,LNA It can have an effective equivalent impedance of, for example, 50 ohms within a specific bandwidth range centered at 490 MHz, and a high impedance within other bandwidth ranges; when the frequency of the local oscillator signal LO is 500 MHz, the overall input equivalent impedance Z in the receiving circuit 100 according to the embodiments of this disclosure is... in,LNA The receiver circuit 100 according to embodiments of this disclosure can have an effective equivalent impedance of, for example, 50 ohms within a specific bandwidth range centered at 500 MHz, and a high impedance in other bandwidth ranges. Therefore, the receiver circuit 100 also has frequency selectivity, which can isolate blocking signals while ensuring impedance matching, thereby improving receiver performance.

[0058] More generally, assuming there are 40 available signal transmission channels within an effective bandwidth of 40MHz (470MHz to 510MHz), each transmission channel has a bandwidth of 1MHz. The RF transceiver can select a specific channel from these 40 channels for current data transmission. The baseband and software can select the corresponding frequency local oscillator (LO) signal based on the selected channel. Simultaneously, the impedance matching of the receiving circuit 100 according to this embodiment is automatically adjusted to the corresponding frequency channel without the need for additional circuitry.

[0059] Next, Figure 5 A flowchart of an operation method 500 for an adaptive impedance matching receiver circuit 100 according to an embodiment of the present disclosure is shown.

[0060] As described above, the receiver circuit 100 for adaptive impedance matching according to embodiments of this disclosure may include a first amplification module 101, a mixer module 102, and a second amplification module 103. In step S501, the first amplification module 101 may amplify the input signal INPUT input from its input terminal to generate a first amplified signal. In some embodiments, the first amplification module 101 may include an active negative feedback structure to provide adaptive impedance matching over a first bandwidth. In step S502, the mixer module 102 may down-convert the first amplified signal to generate a down-converted signal. In step S503, the second amplification module 103 may amplify the down-converted signal to generate an output signal OUTPUT.

[0061] It should be understood that the operating method 500 may also include any operating methods and steps related to the receiving circuit 100 described herein.

[0062] The hardware computing device or its components described in this disclosure can be implemented by a variety of suitable hardware means, including but not limited to FPGA, ASIC, SoC, discrete gate or transistor logic, discrete hardware components, or any combination thereof.

[0063] The block diagrams of circuits, devices, apparatuses, equipment, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that connections, arrangements, or configurations must be made in the manner shown in the block diagrams. As those skilled in the art will recognize, these circuits, devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner that achieves the desired purpose.

[0064] Although this disclosure has been described with reference to exemplary embodiments, various changes and modifications may be suggested to those skilled in the art. This disclosure is intended to cover such changes and modifications that fall within the scope of the appended claims.

[0065] Nothing described in this disclosure should be construed as implying that any particular element, step, or function is essential and must be included within the scope of the claims. The scope of the patent subject matter is defined solely by the claims.

[0066] Exemplary embodiments according to this disclosure have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise stated. Therefore, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of the claims.

Claims

1. A receiver circuit for adaptive impedance matching, comprising: The first amplification module is configured to amplify an input signal input from the input terminal of the first amplification module to generate a first amplified signal; A mixer module, the input of which is connected to the output of the first amplification module, is configured to downconvert the first amplified signal to generate a downconverted signal; as well as The second amplification module has its input connected to the output of the mixer module and is configured to amplify the down-converted signal to generate an output signal. The first amplification module includes an active negative feedback structure to provide adaptive impedance matching within a first bandwidth range. The active negative feedback structure includes a feedback transistor, a bias transistor, a first amplifying transistor, and a second amplifying transistor. The source of the first amplifying transistor is connected to the power supply voltage, the gate is connected to the input terminal of the first amplifying module, and the drain is connected to the output terminal of the first amplifying module. The drain of the second amplifying transistor is connected to the output terminal of the first amplifying module, the gate is connected to the input terminal of the first amplifying module, and the source is connected to ground voltage. The drain of the feedback transistor is connected to the power supply voltage, the gate is connected to the output terminal of the first amplification module, and the source is connected to the input terminal of the first amplification module; and The drain of the bias transistor is connected to the input terminal of the first amplification module, the gate is connected to the bias voltage, and the source is connected to the ground voltage.

2. The receiving circuit according to claim 1, wherein, The transconductance of the feedback transistor is regulated by the bias voltage.

3. The receiving circuit according to claim 1, wherein, The mixing module includes an orthogonal passive mixer, which includes a local oscillator and a first to a fourth switching transistor. The local oscillator generates a first to a fourth local oscillator signal with phases increasing by 90 degrees sequentially to control the switching states of the first to fourth switching transistors.

4. The receiving circuit according to claim 3, wherein, The sources of the first to fourth switching transistors are respectively connected to the output terminal of the first amplification module; The gate of the first switching transistor is connected to the first local oscillator signal, and the drain is connected to the first output path of the mixer module; The gate of the second switching transistor is connected to the third local oscillator signal, and the drain is connected to the first output path of the mixer module; The gate of the third switching transistor is connected to the second local oscillator signal, and the drain is connected to the second output path of the mixer module; and The gate of the fourth switching transistor is connected to the fourth local oscillator signal, and the drain is connected to the second output path of the mixer module.

5. The receiving circuit according to claim 1, wherein, The second amplification module includes one or more transimpedance amplifiers, the input terminals of which are respectively connected to one or more output paths of the mixer module, and amplify the signals output through one or more output paths of the mixer module.

6. The receiving circuit according to claim 1, wherein, The first bandwidth range is determined at least in part based on the transconductance of the feedback transistor.

7. The receiving circuit according to claim 1, wherein, The first bandwidth range is any one or more of 220MHz to 240MHz, 433.05MHz to 433.79MHz, 902MHz to 928MHz, 240MHz to 470MHz, 470MHz to 510MHz, and 220MHz to 510MHz.

8. The receiving circuit according to claim 1, wherein, The input signal is a radio frequency voltage signal, and the first amplified signal is a radio frequency current signal.

9. The receiving circuit according to claim 1, wherein, The down-conversion signal is one or more intermediate frequency or baseband current signals, and the output signal is one or more intermediate frequency or baseband voltage signals.

10. A method of operating a receiver circuit for adaptive impedance matching, the receiver circuit comprising a first amplification module, a mixer module, and a second amplification module, the method comprising: The first amplification module amplifies the input signal input from the input terminal of the first amplification module to generate a first amplified signal; The mixing module down-converts the first amplified signal to generate a down-converted signal. as well as The second amplification module amplifies the down-converted signal to generate an output signal. The first amplification module includes an active negative feedback structure to provide adaptive impedance matching within a first bandwidth range. The active negative feedback structure includes a feedback transistor, a bias transistor, a first amplifying transistor, and a second amplifying transistor. The source of the first amplifying transistor is connected to the power supply voltage, the gate is connected to the input terminal of the first amplifying module, and the drain is connected to the output terminal of the first amplifying module. The drain of the second amplifying transistor is connected to the output terminal of the first amplifying module, the gate is connected to the input terminal of the first amplifying module, and the source is connected to ground voltage. The drain of the feedback transistor is connected to the power supply voltage, the gate is connected to the output terminal of the first amplification module, and the source is connected to the input terminal of the first amplification module; and The drain of the bias transistor is connected to the input terminal of the first amplification module, the gate is connected to the bias voltage, and the source is connected to the ground voltage.

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