Memory device and method of manufacturing the same

Abstract

A memory device and a method of manufacturing the same are disclosed. The method includes providing a substrate. A stack layer and a hard mask layer are sequentially formed on the substrate. A first patterned mandrel and a plurality of second patterned mandrels are formed on the hard mask layer, wherein the first patterned mandrel is disposed adjacent to and separated from ends of the second patterned mandrels in a first direction. The hard mask layer and the stack layer are sequentially patterned using the first patterned mandrel and the second patterned mandrels as masks to form a dummy structure and a plurality of word lines separated from each other on the substrate, wherein portions of the stack layer corresponding to the first patterned mandrel are formed as the dummy structure, and portions of the stack layer corresponding to the second patterned mandrels are formed as the word lines.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor process technology, and in particular to a method for manufacturing a memory device. Background Technology

[0002] As the critical dimensions of memory elements continue to shrink, photolithography becomes increasingly difficult. With the resolution of conventional photolithography processes approaching their theoretical limits, manufacturers have begun to turn to methods such as double patterning to overcome optical limitations and improve the integration density of memory elements. However, in current patterning methods, word lines may bridge with dummy structures at their ends, affecting the electrical performance of the memory device. Summary of the Invention

[0003] This invention provides a method for manufacturing a memory device, comprising: providing a substrate; sequentially forming a stacked layer and a hard mask layer on the substrate; forming a first patterned mandrel and a plurality of second patterned mandrels on the hard mask layer, wherein the first patterned mandrel is adjacent to and separated from the ends of the second patterned mandrels in a first direction; and using the first patterned mandrel and the second patterned mandrels as masks, sequentially patterning the hard mask layer and the stacked layer to form mutually separated dummy structures and a plurality of word lines on the substrate, wherein the portion of the stacked layer corresponding to the first patterned mandrel is formed as a dummy structure, and the portion of the stacked layer corresponding to the second patterned mandrel is formed as the word lines.

[0004] This invention provides a memory device comprising a substrate; a plurality of word lines disposed on the substrate, wherein the word lines extend along a first direction and are arranged along a second direction, and the first direction intersects the second direction; and a dummy structure disposed on the substrate, adjacent to and separated from the ends of the word lines in the first direction, wherein the dummy structure is a block extending along the second direction and has a plurality of closed holes arranged along the second direction.

[0005] The beneficial effect of this invention is that the formed word lines are not affected by subsequent optical proximity effects, nor do they bridge with dummy structures, increasing the process margin of pattern transfer and thus maintaining the yield of memory devices. Attached Figure Description

[0006] To make the features and advantages of the present invention more apparent and understandable, different embodiments are described below in detail with reference to the accompanying drawings: Figure 1 This is a partial top view schematic diagram of a memory device according to an embodiment of the present invention.

[0007] Figure 2 , Figure 4 , Figure 6 , Figure 8, Figure 10 , Figure 12 , Figure 14 , Figure 16 as well as Figure 18 This is a top view schematic diagram illustrating an intermediate stage in the formation of a memory device according to an embodiment of the present invention.

[0008] Figure 3A , Figure 3B , Figure 3C , Figure 5A , Figure 5B , Figure 5C , Figure 7A , Figure 7B , Figure 7C , Figure 9A , Figure 9B , Figure 9C , Figure 11A , Figure 11B , Figure 11C , Figure 13A , Figure 13B , Figure 13C , Figure 15A , Figure 15B , Figure 15C , Figure 17A , Figure 17B , Figure 17C , Figure 19A , Figure 19B as well as Figure 19C This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a memory device according to an embodiment of the present invention.

[0009] Attached symbols

[0010] 10: Memory devices

[0011] 100: Substrate

[0012] 105: Stacked Layers

[0013] 110: Sacrificial Layer

[0014] 115: Hard mask layer

[0015] 115a: Hard mask layer

[0016] 115b1: Hard mask layer

[0017] 115b2: Hard mask layer

[0018] 120: First patterned mandrel

[0019] 122: Closed aperture

[0020] 125: Second patterned mandrel

[0021] 129: End

[0022] 130: Spacer material layer

[0023] 135: Spacer

[0024] 135a: Spacer

[0025] 135b: Spacer

[0026] 137: Depression area

[0027] 140: First patterned photoresist

[0028] 145: Second patterned photoresist

[0029] 147: Corner

[0030] 150: Closed aperture

[0031] 200: Word line

[0032] 300: Virtual Structure

[0033] 400: Selector gate

[0034] 500: Landing mat

[0035] AA: Section line

[0036] BB: Section

[0037] CC: Section

[0038] R: Region

[0039] X: Coordinate axis

[0040] Y: Coordinate axis

[0041] Z: Coordinate axis Detailed Implementation

[0042] In semiconductor optical lithography, different light source wavelengths can affect the exposure accuracy at the edges of the photomask. For example, choosing a longer wavelength laser source may affect the diffraction and imaging of light at the corners of the photomask, i.e., it will be affected by the optical proximity effect (OPE), causing the corners of the photoresist pattern to become rounded. This can prevent the lithography process from forming the correct mask, leading to short circuits in subsequently formed components. This invention reduces the impact of the OPE by using layout decomposition, thereby forming components unaffected by the OPE.

[0043] Figure 1This is a partial top view schematic diagram of a memory device 10 according to an embodiment of the present invention. The memory device 10 includes a plurality of word lines 200. The word lines 200 are disposed on a substrate 100. The word lines 200 extend along a first direction (e.g., along the X-axis) and are arranged along a second direction (e.g., along the Y-axis), and the first direction intersects the second direction. In some embodiments, the first direction is perpendicular to the second direction. In some embodiments, the pitch of the word lines 200 is approximately 1:1 to the width of the word lines 200.

[0044] The memory device 10 further includes a dummy structure 300. The dummy structure 300 is disposed on the substrate 100. The dummy structure 300 is adjacent to and separated from the end of the word line 200 in a first direction (e.g., adjacent to and separated from the end of the word line 200 in the X-axis direction). The dummy structure 300 can prevent the end portion of the word line 200 from being affected by the etching load effect, resulting in uneven width. The dummy structure 300 is a block extending along a second direction and has a plurality of closed vias 150 arranged along the second direction. In this document, "closed via" refers to a via that, in the top view, is completely surrounded by solid material (as opposed to an "open via" which is open to the outside on at least one side). In conventional processes, longer wavelength light sources may cause rounded corners at the corners of the photoresist pattern due to the optical proximity effect. After the etching process, the dummy structure 300 and the word line 200 may bridge due to the small separation distance between them. However, in this embodiment of the invention, since the dummy structure 300 and the word line 200 are separated from each other during the patterning phase of the layout definition, bridging between the word line 200 and the dummy structure 300 in subsequent forming processes can be avoided, and the distance between the word line 200 and the dummy structure 300 can be adjusted according to design requirements. In some embodiments, the dummy structure 300 is in the shape of a railroad track. In some embodiments, the dummy structure 300 is a floating structure and is not connected to an external circuit. In some embodiments, the distance between the dummy structure 300 and the word line 200 is approximately 50 nanometers to approximately 110 nanometers.

[0045] The memory device 10 includes two select gates 400, respectively disposed on both sides of the word line 200 in a second direction (e.g., on both sides of the Y-axis). The select gates 400 extend along a first direction (e.g., along the X-axis), and the dummy structure 300 is located between the two select gates 400 in the second direction (e.g., between the two select gates 400 in the Y-axis). It should be understood that... Figure 1This is only a partial top view of the memory device 10; therefore, the number of selectors 400 is not limited to two. The number of selectors 400 depends on the number of groups of word lines 200 and dummy structures 300, and each group of word lines 200 and dummy structures 300 may have two corresponding selectors 400. In some embodiments, the memory device 10 includes a plurality of landing pads 500, which can serve as pick-ups for word lines 200. The landing pads 500 extend along a second direction (e.g., along the Y-axis) and are arranged along a first direction (e.g., along the X-axis), and are respectively connected to a plurality of other word lines 200 (not shown). The dummy structures 300 are located between the landing pads 500 and the word lines 200.

[0046] Figure 2 , Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 as well as Figure 18 This is a top view schematic diagram illustrating an intermediate stage in the formation of a memory device according to an embodiment of the present invention.

[0047] First see Figure 2 The top view diagram, along with... Figure 3A , Figure 3B as well as Figure 3C A cross-sectional schematic diagram illustrating the steps involved in forming a patterned mandrel. Figure 2 According to an embodiment of the present invention, the corresponding diagram is shown. Figure 1 A magnified top view of region R of the memory device 10. Figure 3A , Figure 3B as well as Figure 3C According to embodiments of the present invention, corresponding figures are drawn respectively. Figure 2The diagram shows cross-sectional views of sections AA, BB, and CC. A substrate 100 is provided. In some embodiments, the substrate 100 may be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; a compound semiconductor substrate, such as a silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP) substrate; or an alloy semiconductor substrate, such as SiGe, SiGeC, GaAsP, or GaInP. A stacked layer 105, a sacrificial layer 110, and a hard mask layer 115 are sequentially formed on the substrate 100. First, the stacked layer 105 is formed on the substrate 100. The stacked layer 105 is a film layer stacked in a third direction (e.g., the Z-axis), and the third direction intersects with the first direction and the second direction. In some embodiments, the third direction is perpendicular to the first direction and the second direction. In some embodiments, the stacked layer 105 may sequentially include, from bottom to top in a third direction, a tunneling dielectric layer, a floating gate layer, an inter-gate dielectric layer, a control gate layer, a metal layer, and a capping layer. For simplicity, the above layers are not shown in detail, but only schematically illustrated using the stacked layer 105. In some embodiments, the material of the tunneling dielectric layer may be silicon oxide. In some embodiments, the material of the patterned floating gate layer may be a conductive material, such as doped polysilicon, undoped polysilicon, or a combination thereof. In some embodiments, the inter-gate dielectric layer may be a composite layer such as that composed of nitride / oxide / nitride (ONO), but the invention is not limited thereto, and the composite layer may also be a film layer with five or more layers. In some embodiments, the material of the control gate layer may be a conductive material, such as doped polysilicon, undoped polysilicon, or a combination thereof. In some embodiments, the material of the metal layer may be such as W, TiN, or a combination thereof. In some embodiments, the material of the top cover layer may be a dielectric material, such as silicon nitride, silicon oxynitride, or a combination thereof.

[0048] Next, a sacrificial layer 110 and a hard mask layer 115 are sequentially formed on the stacked layer 105. The sacrificial layer 110 can protect the stacked layer 105 from the etching process during the subsequent patterning of the hard mask layer 115. The hard mask layer 115 can serve as a patterning mask for the stacked layer 105 in subsequent process steps to form word lines 200 and dummy structures 300. In some embodiments, the material of the sacrificial layer 110 comprises silicon oxide. In some embodiments, the hard mask layer 115 may be a single-layer or multi-layer structure. In some embodiments, the material of the hard mask layer 115 comprises polysilicon.

[0049] A first patterned mandrel 120 and a plurality of second patterned mandrels 125 are formed on a hard mask layer 115, with the first patterned mandrel 120 adjacent to and separated from the ends of the second patterned mandrels 125 in a first direction (e.g., coordinate axis X). In conventional patterning processes for forming character lines, a plurality of patterned mandrels connected to each other at their ends are typically formed. After the pattern transfer process of the mandrels, another patterning process is used to separate the patterns, so that the part connected at the ends becomes the pattern of the dummy structure, while the remaining part serves as the pattern of the character line. In the step of forming the patterned mandrels, the mandrel patterns corresponding to the subsequent formation of the character line 200 and the dummy structure 300 are separated from each other, i.e., layout decomposition, effectively avoiding incomplete pattern separation that may occur later. The first patterned mandrel 120 extends along a second direction and has a plurality of closed vias 122 arranged along the second direction (e.g., extending along the Y-axis and having a plurality of closed vias 122 arranged along the Y-axis), while the second patterned mandrel 125 extends along a first direction and is arranged along the second direction (e.g., extending along the X-axis and arranged along the Y-axis). In some embodiments, the first patterned mandrel 120 and the second patterned mandrel 125 are formed by first forming a mandrel layer (not shown) on a hard mask layer 115, and then forming a photoresist pattern on the mandrel layer via photolithography and etching processes. In some embodiments, after forming the photoresist pattern, a trimming process may be performed to further reduce the width of the photoresist pattern, followed by an etching process to transfer the photoresist pattern to the mandrel layer, thereby forming the first patterned mandrel 120 and the second patterned mandrel 125. In some embodiments, the materials of the first patterned mandrel 120 and the second patterned mandrel 125 may include carbon, silicon oxynitride (SiON), a bottom anti-reflective coating (BARC), or a combination thereof. In some embodiments, the ratio of the width of the plurality of closed apertures in the second direction to the pitch of the plurality of second patterned mandrels is approximately 1:1, the ratio of the width of the plurality of closed apertures in the second direction to the width of the plurality of second patterned mandrels in the second direction is approximately 3:1, and the distance between the first patterned mandrel 120 and the second patterned mandrel 125 in the first direction is approximately 50 nanometers to approximately 110 nanometers.

[0050] See Figure 4 , 6 and Figure 8 The top view diagram and Figure 5A , Figure 5B , Figure 5C , Figure 7A , Figure 7B , Figure 7C , Figure 9A , Figure 9B and Figure 9C The cross-sectional schematic diagram shows that after forming the first patterned mandrel 120 and the second patterned mandrel 125, a self-alignment double patterning (SADP) process is performed to form multiple spacers 135 on the hard mask layer 115. (See also...) Figure 4 , Figure 5A , Figure 5B as well as Figure 5C A spacer material layer 130 is compliantly formed on the hard mask layer 115, the first patterned mandrel 120, and the second patterned mandrel 125. In some embodiments, the spacer material layer 130 may be formed by means such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). In some embodiments, the material of the spacer material layer 130 may be an oxide such as silicon oxide (SiO).

[0051] See next Figure 6 , Figure 7A , Figure 7B as well as Figure 7C After forming the spacer material layer 130, the self-aligned dual patterning process further includes a back etching process on the spacer material layer 130 until the top surfaces of the first patterned mandrel 120 and the second patterned mandrel 125, as well as part of the top surface of the hard mask layer 115, are exposed, thereby forming spacers 135 on the opposing sidewalls of the first patterned mandrel 120 and the second patterned mandrel 125. The spacers 135 are connected to the end 129 of the second patterned mandrel 125, as shown below. Figure 6 drawn.

[0052] See next Figure 8 , Figure 9A , Figure 9B as well as Figure 9C After forming the spacer 135, the self-aligned dual patterning process further includes transferring the patterns of the first patterned mandrel 120, the second patterned mandrel 125, and the spacer 135 to the hard mask layer 115, thereby forming a patterned hard mask layer 115a. In some embodiments, during the etching process of transferring the patterns of the first patterned mandrel 120, the second patterned mandrel 125, and the spacer 135, the first patterned mandrel 120 and the second patterned mandrel 125 can be removed together, leaving a portion of the spacer 135a. After forming the spacer 135a, a portion of the top surface of the sacrificial layer 110 and a portion of the top surface of the hard mask layer 115a are exposed, such as... Figure 9A , Figure 9B as well as Figure 9C As illustrated. Due to the removal of the first patterned mandrel 120 and the second patterned mandrel 125, the spacer 135a forms a recessed region 137 above the hard mask layer 115a that exposes the top surface of the mask layer 115a. That is, the top surface of the spacer 135a is located above the top surface of the mask layer 115a.

[0053] See next Figure 10 and Figure 12 The top view diagram and Figure 11A , Figure 11B , Figure 11C , Figure 13A , Figure 13B as well as Figure 13C A cross-sectional schematic diagram illustrates a cutting process for spacers 135a to form spacers that are separated from each other. The cutting process includes forming a first patterned photoresist 140 covering a portion of the spacers 135a; that is, covering portions of the spacers 135a formed on opposite sides of the second patterned mandrel 125 in a second direction (e.g., the Y-axis), exposing portions of the spacers 135a connected to the ends 129 of the second patterned mandrel 125. The first patterned photoresist 140 exposes at least a portion of the spacers 135a formed on the first patterned mandrel 120. In some embodiments, the first patterned photoresist 140 exposes the spacers 135a in the regions corresponding to sections AA and BB, but covers the spacers 135a in the region corresponding to section CC, including filling in recessed areas 137, such as... Figure 11A , Figure 11B as well as Figure 11C As illustrated. Subsequently, the spacers 135a not covered by the first patterned photoresist 140 are removed, thereby forming spacers 135b, as shown. Figure 12 As illustrated. The removed portion includes the portion of spacer 135a connected to the end 129 of the second patterned mandrel 125 and the exposed portion formed on the first patterned mandrel 120. After the slitting process, a plurality of spacers 135b that are not connected to each other are formed. These spacers 135b extend along a first direction and are arranged along a second direction. In some embodiments, such as Figure 13A , Figure 13B as well as Figure 13C As illustrated, the spacers 135a in the regions corresponding to sections AA and BB are removed, exposing the hard mask layer 115a that was originally partially covered by the spacers 135a. The region corresponding to section AA further exposes the closed via 150, while the spacers 135b in the region corresponding to section CC are retained and used as a pattern for subsequent letter lines. In some embodiments, the width of the spacers 135b in the second direction is equal to the spacing of the spacers 135b in the second direction.

[0054] See next Figure 14 , Figure 16 and Figure 18 The top view diagram and Figure 15A , Figure 15B , Figure 15C , Figure 17A , Figure 17B , Figure 17C , Figure 19A , Figure 19B and Figure 19C The cross-sectional schematic diagram shows the pattern of spacer 135b being sequentially transferred to hard mask layer 115a, sacrificial layer 110, and stacked layer 105. First, referring to... Figure 14 The pattern transfer process includes forming a second patterned photoresist 145 covering all portions of the hard mask layer 115a corresponding to the first patterned mandrel 120, and exposing spacers 135b corresponding to the second patterned mandrel 125. In some embodiments, the second patterned photoresist 145 covers the hard mask layer 115a of the region corresponding to section AA, while the hard mask layer 115a of the region corresponding to section BB and the hard mask layer 115a and spacers 135b of the region corresponding to section CC are exposed, such as... Figure 15A , Figure 15B as well as Figure 15C drawn.

[0055] It is worth noting that the corners 147 of the photoresist pattern may be affected by the optical proximity effect, forming a second patterned photoresist 145 with rounded corners 147. However, in this embodiment of the invention, since the areas for the subsequent formation of the dummy structure 300 and word line 200 have been defined by the first patterned mandrel 120 and the second patterned mandrel 125, the second patterned photoresist 145 with rounded corners 147 does not cause bridging between the dummy structure 300 and the word line 200, increasing the process margin for pattern transfer.

[0056] See Figure 16 The pattern of the spacer 135b is then transferred to the hard mask layer 115a below the spacer 135b, and the second patterned photoresist 145 and all the spacers 135b are removed, thereby forming a hard mask layer 115b1 corresponding to the first patterned mandrel 120 (which will subsequently form the dummy structure 300) and a hard mask layer 115b2 corresponding to the second patterned mandrel 125 (which will subsequently form the word line 200). In some embodiments, the spacers 135b in the region corresponding to section AA are completely removed, leaving the hard mask layer 115b1 exposing the closed via 150; the hard mask layer 115a in the region corresponding to section BB is completely removed, exposing the top surface of the sacrificial layer 110; and the region corresponding to section CC is left with the patterned hard mask layer 115b2, such as... Figure 17A , Figure 17B as well as Figure 17C As illustrated. In some embodiments, since the closed aperture 150 is the region defined by the closed aperture 122 after the spacer 135 is formed, the closed aperture 122 is larger than the closed aperture 150.

[0057] Next, using hard mask layers 115b1 and 115b2 as masks, the patterns of hard mask layer 115b1 (a pattern double-patterned using the first patterning mandrel 120) and hard mask layer 115b2 (a pattern double-patterned using the second patterning mandrel 125 and a slitting process pattern) are sequentially transferred to sacrificial layer 110 and stacked layer 105. Then, hard mask layers 115b1, 115b2, and sacrificial layer 110 are removed to form dummy structure 300 and word lines 200 on substrate 100, as shown below. Figure 18 As illustrated. The pattern of hard mask layer 115b1 corresponds to the formation of dummy structure 300, while the pattern of hard mask layer 115b2 corresponds to the formation of word lines 200. In some embodiments, the dummy structure 300 is rail-shaped, which is a block extending along a second direction (e.g., a block extending along the Y-axis) and has closed vias 150 arranged along the second direction (e.g., closed vias 150 arranged along the Y-axis). In some embodiments, the region corresponding to section line AA forms a dummy structure 300 exposing the closed vias 150, the region corresponding to section line BB has the sacrificial layer 110 and stacked layer 105 completely removed to expose the top surface of substrate 100, and the region corresponding to section line CC uses hard mask layer 115b2 as a mask to form word lines 200, such as... Figure 17A , Figure 17B as well as Figure 17C As illustrated. In embodiments using self-aligned double patterning, the width of the aperture 150 in the second direction is approximately 1:1 to the pitch of the word line 200. In other embodiments using self-aligned quadruple patterning, the width of the aperture 150 in the second direction is approximately 2:1 to the pitch of the word line 200. In some embodiments, the spacing of the aperture 150 in the second direction is greater than the width of the word line 200.

[0058] After forming word line 200 and dummy structure 300, other semiconductor processes can be carried out to form various components and elements of the memory device, which will not be described in detail here.

[0059] In summary, by defining the word line regions and dummy regions of the memory device separately during the word line pattern definition process, the resulting word lines are not affected by subsequent optical proximity effects and do not bridge with dummy structures. This increases the process margin for pattern transfer, thereby maintaining the yield of the memory device. Furthermore, since the resulting word lines are not affected by optical proximity effects, the photolithography process performed in this embodiment can appropriately select light sources of other wavelengths, thereby reducing the manufacturing cost of the memory device and maintaining its performance.

[0060] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art to which this invention pertains may make modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention shall be determined by the appended claims.

Claims

1. A method for manufacturing a memory device, characterized in that, include: Provide a substrate; A stacked layer and a hard mask layer are sequentially formed on the substrate; A first patterned mandrel and a plurality of second patterned mandrels are formed on the hard mask layer, wherein the first patterned mandrel is adjacent to and spaced apart from one end of the plurality of second patterned mandrels in a first direction; and Using the first patterned mandrel and the plurality of second patterned mandrels as masks, the hard mask layer and the stacked layer are patterned sequentially to form a dummy structure and a plurality of word lines separated from each other on the substrate. The portion of the stacked layer corresponding to the first patterned mandrel is formed as the dummy structure, and the portion of the stacked layer corresponding to the plurality of second patterned mandrels is formed as the plurality of word lines.

2. The method for manufacturing a memory device as claimed in claim 1, characterized in that, The first patterned mandrel extends along a second direction and has a plurality of closed holes arranged along the second direction, while the plurality of second patterned mandrels extend along the first direction and are arranged along the second direction, wherein the first direction intersects the second direction.

3. The method for manufacturing a memory device as described in claim 2, characterized in that, The ratio of the width of the plurality of closed holes in the second direction to the pitch of the plurality of second patterned mandrels is approximately 1:1, and the ratio of the width of the plurality of closed holes in the second direction to the width of the plurality of second patterned mandrels in the second direction is approximately 3:

1.

4. The method for manufacturing a memory device as claimed in claim 1, characterized in that, The steps of sequentially patterning the hard mask layer and the stacked layer to form the plurality of word lines include: Multiple spacers are formed on multiple opposite sidewalls of the multiple second patterned mandrels; The patterns of the plurality of second patterned mandrels and the plurality of spacers are transferred to the hard mask layer and the plurality of second patterned mandrels are removed, leaving the plurality of spacers on the hard mask layer; and The patterns of the plurality of spacers are sequentially transferred to the hard mask layer and the stacked layer to form the plurality of word lines on the substrate.

5. The method for manufacturing a memory device as claimed in claim 4, characterized in that, The step of forming the plurality of spacers further includes forming the portion where the plurality of spacers are connected at the ends of the plurality of second patterned mandrels, and after the step of removing the plurality of second patterned mandrels, the steps include: A first patterned photoresist is formed, covering portions of the plurality of spacers on opposite sides of the plurality of second patterned mandrels, but exposing portions where the plurality of spacers connect at the ends of the plurality of second patterned mandrels; and Remove the portions of the plurality of spacers that are connected at the ends of the plurality of second patterned mandrels, so that the remaining plurality of spacers are not connected to each other.

6. The method for manufacturing a memory device as claimed in claim 5, characterized in that, The remaining spacers are arranged along a second direction, which intersects the first direction, and the width of the spacers in the second direction is equal to the spacing between the spacers in the second direction.

7. The method for manufacturing a memory device as claimed in claim 4, characterized in that, The step of sequentially transferring the pattern of the plurality of spacers to the hard mask layer and the stacked layer includes: A second patterned photoresist is formed, covering the portion of the hard mask layer corresponding to the first patterned mandrel and exposing the plurality of spacers; The pattern of the plurality of spacers is transferred to the hard mask layer below them; Remove the second patterned photoresist and the plurality of spacers; and The pattern of the hard mask layer is transferred to the stacked layer to form the plurality of word lines on the substrate.

8. The method for manufacturing a memory device as claimed in claim 1, characterized in that, Before forming the hard mask layer on the stacked layers, it further includes: A sacrificial layer is formed on the stacked layer, which protects the stacked layer from etching during the patterning of the hard mask layer, wherein the hard mask layer comprises polysilicon and the sacrificial layer comprises silicon oxide.

9. The method for manufacturing a memory device as claimed in claim 1, characterized in that, The virtual structure is shaped like a railway track. It is a block extending along a second direction and has multiple closed holes arranged along the second direction, wherein the first direction intersects the second direction.

10. A memory device, characterized in that, include: One substrate; Multiple character lines are disposed on the substrate, wherein the multiple character lines extend along a first direction and are arranged along a second direction, and the first direction intersects the second direction; as well as A dummy structure is disposed on the substrate, adjacent to and separated from the ends of the plurality of word lines in the first direction, wherein the dummy structure is a block extending along the second direction and has a plurality of closed holes arranged along the second direction.

11. The memory device as claimed in claim 10, characterized in that, The virtual structure is shaped like a railway track.

12. The memory device as claimed in claim 10, characterized in that, Including: Two selector gates are respectively disposed on both sides of the plurality of word lines in the second direction, wherein the two selector gates extend along the first direction, and the dummy structure is located between the two selector gates in the second direction; and Multiple landing pads, extending along the second direction, are respectively connected to multiple other letter lines, wherein the dummy structure is located between the multiple landing pads and the multiple letter lines.

13. The memory device as claimed in claim 10, characterized in that, The ratio of the width of the plurality of closed holes in the second direction to the pitch of the plurality of letter lines is approximately 1:

1.

14. The memory device as claimed in claim 10, characterized in that, The distance between the dummy structure and the plurality of word lines is approximately 50 nanometers to approximately 110 nanometers.

15. The memory device as claimed in claim 10, characterized in that, The spacing between the plurality of closed holes in the second direction is greater than the width of the plurality of letter lines.

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