Magnetoresistive random access memory components and methods of forming the same

Abstract

A magnetic random access memory (MRAM) component and a method of forming the same are disclosed. The MRAM component includes a bottom electrode, a magnetic tunnel junction (MTJ) structure, a first spin orbit torque (SOT) layer, a cap layer, a second SOT layer, an etch stop layer, and an upper metal line layer. The MTJ structure is disposed on the bottom electrode. The first SOT layer is disposed on the MTJ structure. The cap layer is disposed on the first SOT layer. The second SOT layer is disposed on the cap layer. The etch stop layer is disposed on the second SOT layer. The upper metal line layer passes through the etch stop layer and lands on the second SOT layer.

Description

Technical Field

[0001] This invention relates to a semiconductor component and a method for forming the same, and more particularly to a magnetoresistive random access memory (MRAM) component and a method for forming the same. Background Technology

[0002] Many modern electronic devices incorporate memory components. These components can be volatile or non-volatile. Non-volatile memory retains its stored data even without power, while volatile memory loses its stored data when power is lost. Magnetoresistive random access memory (MRAM) is highly anticipated as the next generation of non-volatile memory technology due to its superior characteristics compared to current memory components.

[0003] Magnetoresistive random access memory (MRAM) does not store bit information using traditional electric charge, but rather uses the effect of magnetic impedance to store data. However, existing MRAM technology still has many shortcomings that require further improvement. Summary of the Invention

[0004] This invention provides a magnetoresistive random access memory (MRAM) device in which an upper metal wire is directly landed on a second SOT layer to increase the contact area between the upper metal wire and the second SOT layer, thereby increasing the drive current. Furthermore, directly landing the upper metal wire on the second SOT layer also effectively shortens the electrical path between the second SOT layer and the transistors in the front-end (FEOL) structure, reducing interconnect resistance and thus improving device performance.

[0005] The present invention provides a method for forming a magnetoresistive random access memory (MRAM) component, wherein an etch stop layer is formed on a second SOT layer to avoid damage to the second SOT layer by the formation of trenches or vias in subsequent back-end (BEOL) processes, thereby improving process yield and component reliability.

[0006] This invention provides an MRAM component comprising: a magnetoresistive random access memory (MRAM) component including: a bottom electrode, a magnetic tunneling junction (MTJ) structure, a first spin-orbit torque (SOT) layer, a capping layer, a second SOT layer, an etch stop layer, and an upper metal interconnect layer. The magnetic tunneling junction structure is disposed on the bottom electrode. The first SOT layer is disposed on the MTJ structure. The capping layer is disposed on the first SOT layer. The second SOT layer is disposed on the capping layer. The etch stop layer is disposed on the second SOT layer. The upper metal interconnect layer passes through the etch stop layer and lands on the second SOT layer.

[0007] In one embodiment of the present invention, the material of the etch stop layer includes SiN, and the thickness of the etch stop layer is between 100 angstroms. Between 500 and 500 angstroms.

[0008] In one embodiment of the present invention, the material of the top cover layer includes Ta, TaN, Pt, WN or a combination thereof.

[0009] In one embodiment of the present invention, the material of the first SOT layer includes W, and the material of the second SOT layer includes TiN.

[0010] In one embodiment of the present invention, the MRAM component further includes: a protective layer covering the sidewalls of the MTJ structure, the sidewalls of the first SOT layer, and the sidewalls of the top cover layer; and an interlayer dielectric (ILD) layer disposed on the protective layer and laterally surrounding the MTJ structure, the first SOT layer, the top cover layer, the second SOT layer, the etch stop layer, and the upper metal conductor layer.

[0011] In one embodiment of the present invention, the MRAM component further includes: a first lower metal conductor layer disposed directly below the bottom electrode, wherein the bottom electrode is electrically connected to the first transistor through the first lower metal conductor layer; and a second lower metal conductor layer disposed next to the first lower metal conductor layer, wherein the upper metal conductor layer is electrically connected to the second lower metal conductor layer through a conductive via penetrating the ILD layer and the protective layer, and the second lower metal conductor layer is electrically connected to a second transistor different from the first transistor.

[0012] In one embodiment of the present invention, the material of the above-mentioned protective layer includes SiN.

[0013] In one embodiment of the present invention, the area of ​​the second SOT layer is larger than the area of ​​the first SOT layer.

[0014] The present invention provides a method for forming an MRAM component, comprising: forming a bottom electrode in a first dielectric layer; forming a memory stack structure on the bottom electrode; forming a protective layer to conformally cover the top surface and sidewalls of the memory stack structure; forming a second dielectric layer on the protective layer; performing a planarization process to expose the top surface of the memory stack structure; sequentially forming a SOT material layer and an etch stop material layer on the second dielectric layer and the top surface of the memory stack structure; patterning the etch stop material layer and the SOT material layer to form a second SOT layer and an etch stop layer corresponding to the memory stack structure; forming a third dielectric layer on the etch stop layer and the second dielectric layer; and forming an upper metal interconnect layer in the third dielectric layer, wherein the upper metal interconnect layer passes through the etch stop layer and stops on the second SOT layer.

[0015] In one embodiment of the present invention, the memory stack structure described above includes, from bottom to top, an MTJ structure, a first SOT layer, and a top cover layer.

[0016] In one embodiment of the present invention, the first SOT layer and the second SOT layer are made of different materials, the material of the first SOT layer includes W, and the material of the second SOT layer includes TiN.

[0017] In one embodiment of the present invention, the material of the etch stop layer includes SiN, and the thickness of the etch stop layer is between 100 angstroms and 500 angstroms.

[0018] In one embodiment of the present invention, after the second dielectric layer is formed, the top surface of the second dielectric layer located on the memory stack structure is higher than the top surface of the second dielectric layer located next to the memory stack structure.

[0019] In one embodiment of the invention, after the planarization process, the top surface of the memory stack structure is substantially flush with the top surface of the second dielectric layer.

[0020] In one embodiment of the present invention, after patterning the etch stop material layer and the SOT material layer, the second SOT layer and the etch stop layer are located directly above the memory stack structure, and part of the second dielectric layer is removed, such that the top surface of the second dielectric layer is lower than the bottom surface of the second SOT layer.

[0021] In one embodiment of the present invention, after patterning the etch stop material layer and the SOT material layer, the second SOT layer further extends to cover the top surface of the second dielectric layer.

[0022] In one embodiment of the present invention, the formation of the above-mentioned upper metal conductor layer includes: forming a hard mask layer on a third dielectric layer, wherein the hard mask layer has an opening that partially overlaps with the second SOT layer; using the hard mask layer as a mask, removing a portion of the third dielectric layer to form a trench in the third dielectric layer, wherein the trench stops on an etch stop layer; performing an over-etching process to remove a portion of the etch stop layer so that the trench extends downward and stops on the second SOT layer; and filling the trench with metal material.

[0023] In one embodiment of the invention, after forming the trench, the method further includes forming a via, wherein the via extends from the bottom surface of the trench through a second dielectric layer, a protective layer, and a first dielectric layer to reach a lower metal conductor layer.

[0024] In one embodiment of the invention, prior to forming the trench, the method further includes forming vias in a first dielectric layer and a second dielectric layer adjacent to the memory stack structure, wherein the trench is formed on the via to communicate with the via space.

[0025] In one embodiment of the present invention, the aforementioned metal material is simultaneously filled into the trench and the through hole to form an upper metal conductor layer and a conductive through hole.

[0026] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0027] Figures 1 to 7 This is a cross-sectional schematic diagram of the manufacturing process of an MRAM component according to an embodiment of the present invention. Detailed Implementation

[0028] The invention is described more fully with reference to the accompanying drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar components, which will not be repeated in the following paragraphs.

[0029] Figures 1 to 7 This is a cross-sectional schematic diagram of the manufacturing process of an MRAM component according to an embodiment of the present invention.

[0030] Please refer to Figure 1 An initial structure is provided, including: a lower dielectric layer 100, a lower metal interconnect layer 102, a top cap layer 104, a first dielectric layer 106, a bottom electrode 108, a memory stack structure 110, and a protective layer 118. Specifically, the lower metal interconnect layer 102 may be embedded in the lower dielectric layer 100. The lower metal interconnect layer 102 may include a first lower metal interconnect layer 102A and a second lower metal interconnect layer 102B. In one embodiment, the first lower metal interconnect layer 102A corresponds to the upper bottom electrode 108 and the memory stack structure 110, and is configured to electrically connect the bottom electrode 108 to a first transistor (not shown) in the front-end structure. In one embodiment, the second lower metal interconnect layer 102B is disposed next to the first lower metal interconnect layer 102A, and is configured to connect the subsequently formed upper metal interconnect layer 134 (e.g., ...) to the memory stack structure 110. Figure 7 The transistor (not shown) is electrically connected to a second transistor (different from the first transistor described above) in the front-end structure. In one embodiment, the material of the lower dielectric layer 100 is, for example, silicon oxide or a low-k dielectric material (i.e., a dielectric constant value less than 3.9), while the material of the lower metal conductor layer 102 includes metals such as copper, aluminum, tungsten, and aluminum-copper. Additionally, the lower metal conductor layer 102 also includes a barrier layer (not shown) disposed between the metal material and the lower dielectric layer 100. The barrier layer may be made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0031] The capping layer 104 may cover the lower dielectric layer 100 and the lower metal conductor layer 102. In one embodiment, the material of the capping layer 104 includes silicon nitride (SiN), silicon carbide (SiC), silicon carbide nitride (SiCN), silicon oxynitride (SiON), or a combination thereof.

[0032] A first dielectric layer 106 may be disposed on a capping layer 104. In one embodiment, the material of the first dielectric layer 106 is, for example, silicon oxide or a low-k dielectric material. A bottom electrode 108 may be disposed in the first dielectric layer 106 and pass through the capping layer 104 to contact the first lower metal conductive layer 102A. The bottom electrode 108 may include a barrier layer 108a and a conductor layer 108b. In one embodiment, the material of the barrier layer 108a includes Ti, TiN, Ta, TaN, or combinations thereof, while the conductor layer 108b includes metal materials such as copper, aluminum, tungsten, or aluminum-copper.

[0033] The memory stack structure 110 can be configured on and in contact with the bottom electrode 108. Specifically, the memory stack structure 110 may include, from bottom to top, a magnetic tunneling junction (MTJ) structure 112, a first spin-orbit torque (SOT) layer 114, and a top cap layer 116. Although Figure 1 The illustrated MTJ structure 112 is a single-layer structure, but the invention is not limited thereto. In some embodiments, the MTJ structure 112 includes at least a three-layer structure consisting of a lower ferromagnetic layer, a barrier layer, and an upper ferromagnetic layer. The barrier layer separates the upper ferromagnetic layer from the lower ferromagnetic layer. The materials of the upper and lower ferromagnetic layers may include cobalt (Co), iron (Fe), boron (B), or combinations thereof, while the material of the barrier layer may include magnesium oxide, aluminum oxide, or combinations thereof. In some embodiments, the lower ferromagnetic layer may have a fixed or pinned magnetic orientation, while the upper ferromagnetic layer may have a variable or free magnetic orientation, and may switch between two or more different magnetic polarities, each of which may represent a different data state. In this embodiment, the lower ferromagnetic layer can be considered as a pinned reference layer, while the upper ferromagnetic layer can be considered as a free layer. In an alternative embodiment, the MTJ structure 112 can be flipped vertically, meaning the lower ferromagnetic layer can have a free magnetic orientation, while the upper ferromagnetic layer can have a pinned magnetic orientation. Although the MTJ structure 112 has been described with reference to the above embodiment, the present invention is not limited thereto, and those skilled in the art can adjust the composition of the MTJ structure 112 according to product requirements.

[0034] The first SOT layer 114 may be sandwiched between the MTJ structure 112 and the capping layer 116. In one embodiment, the material of the first SOT layer 114 includes a heavy metal material, such as platinum, palladium, tungsten, tantalum, gold, alloys of the foregoing, or combinations thereof. In this embodiment, the material of the first SOT layer 114 is tungsten (W). In one embodiment, the material of the capping layer 116 includes Ta, TaN, Pt, WN, or combinations thereof. In this embodiment, the capping layer 116 may be considered as a top electrode or an etch stop layer to prevent subsequent processes from damaging the underlying first SOT layer 114.

[0035] Additionally, the method for manufacturing the memory stack structure 110 may include the following steps, but the present invention is not limited thereto. First, a capping layer 104 and a first dielectric layer 106 may be sequentially formed on the lower dielectric layer 100 and the lower metal conductor layer 102. Next, a bottom electrode 108 may be formed in the capping layer 104 and the first dielectric layer 106 by a single damascene process. Then, an MTJ material layer, a SOT material layer, and a capping material layer (not shown) may be sequentially formed on the first dielectric layer 106 and the bottom electrode 108 by a deposition process. The MTJ material layer, the SOT material layer, and the capping material layer may then be patterned by photolithography and etching processes to form the MTJ structure 112, the first SOT layer 114, and the capping layer 116.

[0036] After forming the memory stack structure 110, a protective layer 118 may be formed to conformally cover the top surface and sidewalls of the memory stack structure 110. Specifically, the protective layer 118 extends from the surface of the memory stack structure 110 to cover the top surface of the first dielectric layer 106. In one embodiment, the material of the protective layer 118 is, for example, silicon nitride, and the method for forming the protective layer 118 is, for example, chemical vapor deposition (CVD).

[0037] Please refer to Figure 2 A second dielectric layer 120 is formed on the protective layer 118. In one embodiment, the material of the second dielectric layer 120 is, for example, silicon oxide or a low-k dielectric material, and the method for forming the second dielectric layer 120 is, for example, atomic layer deposition (ALD). After the second dielectric layer 120 is formed, the top surface 120t1 of the second dielectric layer 120 located on the memory stack structure 110 is higher than the top surface 120t2 of the second dielectric layer 120 located beside the memory stack structure 110. That is, the second dielectric layer 120 has an uneven top surface.

[0038] Please refer to Figure 3A planarization process is performed to expose the top surface 110t of the memory stack structure 110. Specifically, the planarization process includes removing a portion of the second dielectric layer 120 and a portion of the protective layer 118 to expose the top cap layer 116. In one embodiment, the planarization process is, for example, a chemical mechanical polishing (CMP) process. Furthermore, after the planarization process, the top surface 110t of the memory stack structure 110 is substantially flush with the top surface 120t of the second dielectric layer 120.

[0039] Please refer to Figure 4 An SOT material layer 122a and an etch stop material layer 124a are sequentially formed on the top surface 120t of the second dielectric layer 120 and the top surface 110t of the memory stack structure 110. The second dielectric layer 120, the memory stack structure 110, and the protective layer 118 are overlying the SOT material layer 122a, while the etch stop material layer 124a is formed on the SOT material layer 122a. In one embodiment, the SOT material layer 122a and the first SOT layer 114 are made of different materials. For example, the material of the first SOT layer 114 is tungsten (W), while the material of the SOT material layer 122a is titanium nitride (TiN). In one embodiment, the material of the etch stop material layer 124a is, for example, silicon nitride (SiN), and the thickness of the etch stop material layer 124a is between 100 angstroms and 500 angstroms. Furthermore, the SOT material layer 122a and the etch stop material layer 124a can be formed, for example, by CVD.

[0040] Please refer to Figure 4 and Figure 5 The etch stop material layer 124a and the SOT material layer 122a are patterned to form a second SOT layer 122 and an etch stop layer 124 corresponding to the memory stack structure 110. Specifically, a mask pattern (e.g., a photoresist pattern) can be formed on the etch stop material layer 124a. Then, using the mask pattern as an etching mask, an etching process is performed to remove a portion of the etch stop material layer 124a and a portion of the SOT material layer 122a, thereby forming the second SOT layer 122 and the etch stop layer 124. After the patterning process, the second SOT layer 122 and the etch stop layer 124 can be located directly above the memory stack structure 110. In one embodiment, the etching process includes a dry etching process, such as reactive ion etching (RIE). Additionally, the etching process also removes a portion of the second dielectric layer 120 to ensure that adjacent second SOT layers 122 are disconnected. In this case, the top surface of the second dielectric layer 120 can be lower than the bottom surface of the second SOT layer 122 to form a groove, such as Figure 5As shown. It is worth noting that the area of ​​the second SOT layer 122 may be larger than the area of ​​the first SOT layer 114 or the area of ​​the memory stack structure 110. That is, the second SOT layer 122 covers the top surface of the memory stack structure 110 and extends to cover part of the top surface of the protective layer 118 and the second dielectric layer 120.

[0041] Please refer to Figures 5 to 7 A third dielectric layer 126 is formed on the etch stop layer 124 and the second dielectric layer 120. In one embodiment, the material of the third dielectric layer 126 is, for example, an ultra-low-k (ULK) dielectric material, i.e., a dielectric material with a dielectric constant value less than 2.6. The method for forming the third dielectric layer 126 includes depositing the ULK dielectric material by CVD and performing a planarization process (e.g., CMP) on the ULK dielectric material. The third dielectric layer 126 and the underlying second dielectric layer 120 can be considered together as an interlayer dielectric (ILD) layer. This ILD layer can be disposed on the protective layer 118 and laterally surround the memory stack structure 110, the second SOT layer 122, the etch stop layer 124, and the subsequently formed upper metal conductor layer 134 and conductive vias 132 (e.g., Figure 7 (As shown).

[0042] Next, an upper metal conductive layer 134 is formed in the third dielectric layer 126. Specifically, the method for manufacturing the upper metal conductive layer 134 may include the following steps, but the present invention is not limited thereto. First, a hard mask layer 128 is formed on the third dielectric layer 126, such as... Figure 6 As shown. The hard mask layer 128 may have an opening 127 that partially overlaps with the second SOT layer 122. The hard mask layer 128 may include a lower hard mask layer 128a and an upper hard mask layer 128b disposed on the lower hard mask layer 128a. In one embodiment, the material of the lower hard mask layer 128a is, for example, TiN, while the material of the upper hard mask layer 128b is, for example, silicon oxide. Next, using the hard mask layer 128 as a mask, an etching process (e.g., RIE process) is performed to remove a portion of the third dielectric layer 126 to form a trench in the third dielectric layer 126, wherein the trench stops on the etch stop layer 124. Then, an over-etching process is performed to remove a portion of the etch stop layer 124 so that the trench 133 extends downward and stops on the second SOT layer 122, as shown. Figure 7As shown. It is worth noting that the etch stop layer 124 is made of silicon nitride, and the third dielectric layer 126 is made of ULK dielectric material. Therefore, the etch stop layer 124 and the third dielectric layer 126 have high etch selectivity. That is, in the above etching process, the etching rate of the third dielectric layer 126 is greater than the etching rate of the etch stop layer 124. In this case, the trench will stop on the etch stop layer 124 without damaging the underlying second SOT layer 122. Therefore, the etch stop layer 124 in this embodiment can protect the second SOT layer 122 from damage, thereby improving process yield and component reliability.

[0043] After forming the trench 133, the manufacturing method further includes forming a via 131. The via 131 extends from the bottom surface of the trench 133, which is not blocked by the etch stop layer 124, through the second dielectric layer 120, the protective layer 118, the first dielectric layer 106, and the capping layer 104, to reach the second lower metal conductor layer 102B. The step of forming the trench 133 before the via 131 can be referred to as a trench-first process. However, the present invention is not limited thereto; in other embodiments, the via 131 may also be formed before the trench 133, i.e., a via-first process. The trench 133 and the via 131 may be spatially connected to form a dual damascene opening. Subsequently, metal material is simultaneously filled into the trench 133 and the via 131 to form a dual damascene metal structure 130, thereby completing the MRAM component of the present invention. In one embodiment, the metallic material is, for example, copper, and can be formed by physical vapor deposition (PVD) or electroplating. In this embodiment, the dual damascene metal structure 130 may include a conductive via 132 and an upper metal conductor layer 134 disposed on the conductive via 132.

[0044] like Figure 7As shown, the MRAM component of this embodiment includes: a bottom electrode 108 disposed on a lower metal interconnect layer 102; a memory stack structure 110 disposed on the bottom electrode 108; a second SOT layer 122 disposed on the memory stack structure 110; an etch stop layer 124 disposed on the second SOT layer 122; and an upper metal interconnect layer 134 passing through the etch stop layer 124 and landing on the second SOT layer 122. In one embodiment, the memory stack structure 110 may be embedded in a back-end (BEOL) structure and vertically sandwiched between the lower metal interconnect layer 102 (e.g., the second metal layer M2) and the upper metal interconnect layer 134 (e.g., the third metal layer M3). Notably, the upper metal interconnect layer 134 may land directly on the second SOT layer 122 to increase the contact area between the upper metal interconnect layer 134 and the second SOT layer 122, thereby increasing the drive current. Furthermore, compared to the existing structure where the upper metal wire 134 lands directly on the second SOT layer 122, this embodiment can effectively shorten the electrical path between the second SOT layer 122 and the transistor in the front-end structure by directly landing the upper metal wire 134 on the second SOT layer 122, thereby reducing manufacturing costs and interconnect resistance, and thus improving component performance. For example, the second SOT layer 122 can be electrically connected to the lower second transistor through the electrical path formed by the upper metal wire 134, the conductive via 132, and the second lower metal wire layer 102B, without the need for other additional wiring.

[0045] Furthermore, the MRAM component in this embodiment can be, for example, a three-terminal memory component. Specifically, the memory stack structure 110 can be electrically connected to the first transistor via the bottom electrode 108 and the first lower metal conductor layer 102A. One end of the second SOT layer 122 can be electrically connected to a second transistor, different from the first transistor, via an electrical path formed by the upper metal conductor 134, the conductive via 132, and the second lower metal conductor layer 102B. The other end of the second SOT layer 122 (i.e., the end perpendicular to the plane of the paper, not shown in this cross-section) can be grounded via another electrical path.

[0046] In summary, this embodiment of the invention uses a thin silicon nitride layer as an etching stop layer and forms it on the second SOT layer to prevent damage to the second SOT layer from the formation of trenches or vias in subsequent back-end processes, thereby improving process yield and device reliability. In this case, the upper metal conductor can land directly on the second SOT layer to increase the contact area between the upper metal conductor and the second SOT layer, thereby increasing the drive current. Furthermore, the direct landing of the upper metal conductor on the second SOT layer can effectively shorten the electrical path between the second SOT layer and the transistors in the front-end structure, reducing manufacturing costs and interconnect resistance, thereby improving device performance.

[0047] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A magnetoresistive random access memory (RAM) assembly, characterized in that, include: A magnetic tunneling junction structure is disposed on the bottom electrode; A first spin-orbit torque layer is disposed on the magnetic tunneling junction structure; A top cover layer is disposed on the first spin-orbit torque layer; A second spin-orbit torque layer is disposed on the top cover layer; An etching stop layer is disposed on the second spin-orbit torque layer; The upper metal wire layer passes through the etching stop layer and lands on the second spin orbit torque layer; A protective layer covers the sidewalls of the magnetic tunneling junction structure, the sidewalls of the first spin-orbit torque layer, and the sidewalls of the top cover layer; An interlayer dielectric layer is disposed on the protective layer and laterally surrounds the magnetic tunneling junction structure, the first spin-orbit torque layer, the top cap layer, the second spin-orbit torque layer, the etch stop layer, and the upper metal conductor layer. A first lower metal conductor layer is disposed directly below the bottom electrode, wherein the bottom electrode is electrically connected to the first transistor through the first lower metal conductor layer; as well as A second lower metal conductor layer is disposed next to the first lower metal conductor layer, wherein the upper metal conductor layer is electrically connected to the second lower metal conductor layer through a conductive via penetrating the interlayer dielectric layer and the protective layer, and the second lower metal conductor layer is electrically connected to a second transistor different from the first transistor.

2. The magnetoresistive random access memory assembly of claim 1, wherein the etch stop layer is made of SiN and the thickness of the etch stop layer is between 100 angstroms and 500 angstroms.

3. The magnetoresistive random access memory assembly of claim 1, wherein the material of the top cover layer includes Ta, TaN, Pt, WN, or a combination thereof.

4. The magnetoresistive random access memory assembly of claim 1, wherein the material of the first spin-orbit torque layer comprises W, and the material of the second spin-orbit torque layer comprises TiN.

5. The magnetoresistive random access memory assembly of claim 1, wherein the material of the protective layer includes SiN.

6. The magnetoresistive random access memory assembly of claim 1, wherein the area of ​​the second spin-orbit torque layer is greater than the area of ​​the first spin-orbit torque layer.

7. A method for forming a magnetoresistive random access memory (RAM) assembly, comprising: A bottom electrode is formed in the first dielectric layer; A memory stack structure is formed on the bottom electrode; A protective layer is formed to conformally cover the top surface and sidewalls of the memory stack structure; A second dielectric layer is formed on the protective layer; A planarization process is performed to expose the top surface of the memory stack structure; A spin orbital torque material layer and an etch stop material layer are sequentially formed on the top surface of the second dielectric layer and the memory stack structure; The etch stop material layer and the spin orbit torque material layer are patterned to form a second spin orbit torque layer and etch stop layer corresponding to the memory stack structure; A third dielectric layer is formed on the etch stop layer and the second dielectric layer; An upper metal conductor layer is formed in the third dielectric layer and conductive vias are formed in the first dielectric layer, the second dielectric layer and the protective layer, wherein the upper metal conductor layer passes through the etch stop layer and stops on the second spin orbit torque layer; A first lower metal conductor layer is formed directly below the bottom electrode, wherein the bottom electrode is electrically connected to the first transistor through the first lower metal conductor layer; as well as A second lower metal conductor layer is formed next to the first lower metal conductor layer, wherein the upper metal conductor layer is electrically connected to the second lower metal conductor layer through the conductive via penetrating the second dielectric layer, the first dielectric layer and the protective layer, and the second lower metal conductor layer is electrically connected to a second transistor different from the first transistor.

8. The method for forming a magnetoresistive random access memory assembly as described in claim 7, wherein the memory stack structure comprises, from bottom to top, the following: The magnetic tunneling junction structure, the first spin-orbit torque layer, and the top cover layer.

9. The method of forming a magnetoresistive random access memory assembly as claimed in claim 8, wherein the first spin-orbit torque layer and the second spin-orbit torque layer are made of different materials, the material of the first spin-orbit torque layer includes W, and the material of the second spin-orbit torque layer includes TiN.

10. The method of forming a magnetoresistive random access memory assembly as claimed in claim 7, wherein the material of the etch stop layer comprises SiN, and the thickness of the etch stop layer is between 100 angstroms and 500 angstroms.

11. The method of forming a magnetoresistive random access memory assembly as claimed in claim 7, wherein after the formation of the second dielectric layer, the top surface of the second dielectric layer located on the memory stack structure is higher than the top surface of the second dielectric layer located adjacent to the memory stack structure.

12. The method of forming a magnetoresistive random access memory assembly as claimed in claim 7, wherein after the planarization process, the top surface of the memory stack structure is substantially flush with the top surface of the second dielectric layer.

13. The method of forming a magnetoresistive random access memory assembly as claimed in claim 7, wherein after the patterning of the etch stop material layer and the spin-orbit torque material layer, the second spin-orbit torque layer and the etch stop layer are located directly above the memory stack structure, and a portion of the second dielectric layer is removed such that the top surface of the second dielectric layer is lower than the bottom surface of the second spin-orbit torque layer.

14. The method of forming a magnetoresistive random access memory assembly as claimed in claim 7, wherein after the patterning of the etch stop material layer and the spin-orbit torque material layer, the second spin-orbit torque layer further extends to cover the top surface of the second dielectric layer.

15. The method of forming a magnetoresistive random access memory assembly as claimed in claim 7, wherein forming the upper metal conductor layer comprises: A hard mask layer is formed on the third dielectric layer, wherein the hard mask layer has an opening that partially overlaps with the second spin-orbit torque layer; Using the hard mask layer as a mask, a portion of the third dielectric layer is removed to form a trench in the third dielectric layer, wherein the trench stops on the etch stop layer; An etching process is performed to remove part of the etching stop layer, so that the trench extends downward and stops on the second spin orbit torque layer; as well as Metal material is filled into the trench.

16. The method of forming a magnetoresistive random access memory assembly as claimed in claim 15, wherein after forming the trench, the method further comprises forming a via, wherein the via extends from the bottom surface of the trench through the second dielectric layer, the protective layer, and the first dielectric layer to reach the lower metal conductor layer.

17. The method of forming a magnetoresistive random access memory assembly as claimed in claim 15, wherein prior to forming the trench, the method further comprises forming a via in the first dielectric layer and the second dielectric layer adjacent to the memory stack structure, wherein the trench is formed on the via to communicate with the via space.

18. The method of forming a magnetoresistive random access memory assembly as claimed in claim 17, wherein the metal material is simultaneously filled into the trench and the via to form the upper metal conductor layer and the conductive via.

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