Display panel

Abstract

This application discloses a display panel, including a display area and a non-display area. The display panel includes a substrate, a buffer layer, a gate insulating layer, an interlayer dielectric layer, a first metal element, a cathode insulating layer, an organic layer, and a cathode layer. The buffer layer, gate insulating layer, and interlayer dielectric layer are sequentially stacked on the substrate. The first metal element is disposed on the portion of the interlayer dielectric layer located in the non-display area. The first metal element includes a first metal bottom, a first metal middle portion, and a first metal top portion, sequentially stacked. A first recess is provided on a surface of the first metal middle portion near or away from the display area. A first portion of the cathode insulating layer covers a surface of the first metal top portion facing away from the substrate, and a first portion of the cathode insulating layer covers a surface of the first metal element facing away from the first recess. The first recess is located below the first portion of the cathode insulating layer. This application aims to solve the problem of display panel packaging failure.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel. Background Technology

[0002] The polarizer of an OLED (Organic Light-Emitting Diode) display panel contains potassium (K) elements. In a high-temperature and high-humidity environment, the K elements in the polarizer dissolve in water. The portion of the cathode layer located in the encapsulation area is in a negatively charged state. The electric field generated by this negative charge will migrate K+ ions to the encapsulation layer. The K+ ions react with SiOx in the encapsulation layer to generate K2SiO3 and hydrogen gas. The encapsulation layer expands and deforms, leading to the failure of the display panel encapsulation.

[0003] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0004] The purpose of this application is to provide a display panel that addresses the problem of display panel encapsulation failure.

[0005] To solve the above problems, the technical solution of this application is as follows:

[0006] This application proposes a display panel, including a display area and a non-display area located around the display area. The display panel includes:

[0007] Substrate;

[0008] A buffer layer is disposed on the substrate;

[0009] A gate insulating layer is disposed on the buffer layer;

[0010] An interlayer dielectric layer is disposed on the gate insulating layer;

[0011] A first metal component is disposed on the portion of the interlayer dielectric layer located in the non-display area. The first metal component includes a first metal bottom, a first metal middle portion, and a first metal top portion. The first metal bottom portion is disposed on the interlayer dielectric layer, the first metal middle portion is disposed on the first metal bottom portion, and the first metal top portion is disposed on the first metal middle portion. A first recess is provided on a surface of the first metal middle portion that is close to or far from the display area.

[0012] A cathode insulating layer, wherein a first portion of the cathode insulating layer covers a surface of the first metal member facing away from the substrate, and a second portion of the cathode insulating layer covers a surface of the first metal member facing away from the first recess;

[0013] An organic layer, comprising a first organic portion and a second organic portion, wherein the first organic portion is disposed on the interlayer dielectric layer, and the second organic portion is disposed on the cathode insulating layer, the first organic portion and the second organic portion being spaced apart; and

[0014] The cathode layer includes a first cathode portion and a second cathode portion, wherein the first cathode portion is disposed on the first organic portion, the second cathode portion is disposed on the second organic portion, and the first cathode portion and the second cathode portion are spaced apart.

[0015] The first recess is located below the first portion of the cathode insulating layer.

[0016] In one embodiment of this application, the cathode insulating layer comprises:

[0017] A first insulating portion is disposed on the first metal member and covers a surface of the first metal member facing away from the substrate; the first recess is located below the first insulating portion; and

[0018] The second insulating portion is disposed on the interlayer dielectric layer and covers a surface of the first metal part away from the first recess. The second insulating portion is connected to the first insulating portion, and the surface of the first insulating portion away from the substrate and the surface of the second insulating portion away from the substrate are flush.

[0019] The second organic part is disposed on the first insulating part and the second insulating part.

[0020] In one embodiment of this application, the projection of the first metal middle portion on the substrate is located within the projection range of the first metal top portion on the substrate, and the distance from a surface of the first metal top portion away from the second insulating portion to a surface of the first metal middle portion away from the second insulating portion is in the range of 0.1 μm to 0.5 μm.

[0021] In one embodiment of this application, the display panel further includes a pad layer disposed on the portion of the gate insulating layer located in the non-display area, and the pad layer is located between the interlayer dielectric layer and the gate insulating layer;

[0022] The interlayer dielectric layer includes a first dielectric portion and a second dielectric portion. The first dielectric portion is disposed on the gate insulating layer, and the second dielectric portion is disposed on the pad layer. The first metal component, the cathode insulating layer, the second organic portion, and the second cathode portion are sequentially stacked on the second dielectric portion.

[0023] In one embodiment of this application, the non-display area includes an encapsulation area and a via area located on the side of the encapsulation area away from the display area. The display panel further includes a baffle wall, which is disposed on the portion of the interlayer dielectric layer located in the encapsulation area and divides the encapsulation area into a first encapsulation area and a second encapsulation area.

[0024] The first encapsulation area is located on the side of the barrier wall closer to the display area, the second encapsulation area is located on the side of the barrier wall away from the display area, and the first metal component is disposed on the portion of the interlayer dielectric layer located in the first encapsulation area.

[0025] In one embodiment of this application, the first recess is disposed on a surface of the first metal member away from the display area, and the second insulating portion is disposed on a surface of the first metal member close to the display area;

[0026] Wherein, the top surface of the first metal near the display area, the middle surface of the first metal near the display area, and the bottom surface of the first metal near the display area are flush with each other. The top surface of the first metal near the display area abuts against the second insulating part, the middle surface of the first metal near the display area abuts against the second insulating part, and the bottom surface of the first metal near the display area abuts against the second insulating part.

[0027] In one embodiment of this application, the first recess is disposed on a surface of the first metal member near the display area, and the second insulating portion is disposed on a surface of the first metal member away from the display area;

[0028] Wherein, the top surface of the first metal away from the display area, the middle surface of the first metal away from the display area, and the bottom surface of the first metal away from the display area are flush with each other. The top surface of the first metal away from the display area abuts against the second insulating part, the middle surface of the first metal away from the display area abuts against the second insulating part, and the bottom surface of the first metal away from the display area abuts against the second insulating part.

[0029] In one embodiment of this application, the thickness of the pad layer is in the range of 40 nm to 1500 nm;

[0030] The thickness of the first metal part is in the range of 700nm to 1000nm.

[0031] In one embodiment of this application, a plurality of pads are spaced apart in the non-display area along a direction from the display area to the non-display area, at least one second medium portion is provided with the first metal member, and at least one second medium portion is provided with a second metal member, the second metal member comprising:

[0032] A second metal bottom is disposed on the second dielectric portion;

[0033] A second metal middle portion is disposed on the bottom of the second metal portion. A second recess is provided on one surface of the second metal middle portion near the display area, and a third recess is provided on one surface of the second metal middle portion away from the display area.

[0034] The second metal top is provided on the middle part of the second metal, wherein the second recess and the third recess are both located below the second metal top;

[0035] The organic layer further includes a third organic part, which is disposed on the top of the second metal, and the third organic part, the first organic part, and the second organic part are spaced apart.

[0036] The cathode layer further includes a third cathode portion, which is disposed on the third organic portion, and the third cathode portion, the first cathode portion, and the second cathode portion are spaced apart.

[0037] In one embodiment of this application, the non-display area includes a winding area, an encapsulation area, and a via area. The winding area is located on the side of the encapsulation area closer to the display area, and the via area is located on the side of the encapsulation area away from the display area. The display panel further includes a planarization layer, which is disposed on the portion of the interlayer dielectric layer located on the winding area.

[0038] The second insulating portion is disposed on the portion of the interlayer dielectric layer located in the winding region and on the side of the planarization layer near the encapsulation region. The surface of the second insulating portion facing away from the substrate is flush with the surface of the planarization layer facing away from the substrate.

[0039] The first metal component is disposed on the portion of the interlayer dielectric layer located in the winding region, and is located on the side of the second insulating portion near the encapsulation region;

[0040] The first recess is located on the side of the first metal part near the encapsulation area.

[0041] In this application, a first recess is provided on a surface of the first metal middle portion near or away from the display area. During the formation of the organic layer by vapor deposition, the organic layer is interrupted at the first recess, forming a first organic portion and a second organic portion spaced apart. During the formation of the cathode layer by vapor deposition, the cathode layer is interrupted at the first recess, forming a first cathode portion and a second cathode portion spaced apart. At this time, because the first cathode portion and the second cathode portion are separated, and a cathode insulating layer is provided between the second cathode portion and the first metal component, the first cathode portion and the second cathode portion cannot be connected through the first metal component. This makes the second cathode portion located in the non-display area uncharged, significantly slowing down the migration rate of K element to the encapsulation layer, reducing the gaseous products generated by the reaction of K element with the encapsulation layer, avoiding expansion and deformation of the encapsulation layer, and solving the problem of display panel encapsulation failure. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of an embodiment of the display panel of this application;

[0043] Figure 2 yes Figure 1 Enlarged view of point A in the middle;

[0044] Figure 3 This is a schematic diagram of another embodiment of the display panel of this application;

[0045] Figure 4 yes Figure 3 Enlarged view of point B in the middle;

[0046] Figure 5 This is a schematic diagram of yet another embodiment of the display panel of this application;

[0047] Figure 6 yes Figure 5 A magnified view of point C in the middle. Detailed Implementation

[0048] The terms used in this specification and claims have the meanings that are commonly understood by one of ordinary skill in the art to which this application pertains. The terms used in this specification and claims are for the purpose of facilitating the description and understanding of this application only, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.

[0049] Reference Figures 1 to 6This application proposes a display panel 100, including a display area AA and a non-display area NA located around the display area AA. The display panel 100 includes: a substrate 11; a buffer layer 12 disposed on the substrate 11; a gate insulating layer 13 disposed on the buffer layer 12; an interlayer dielectric layer 20 disposed on the gate insulating layer 13; a first metal member 30 disposed on the portion of the interlayer dielectric layer 20 located in the non-display area NA, the first metal member 30 including a first metal bottom 31, a first metal middle portion 32, and a first metal top 33, wherein the first metal bottom 31 is disposed on the interlayer dielectric layer 20, the first metal middle portion 32 is disposed on the first metal bottom 31, the first metal top 33 is disposed on the first metal middle portion 32, and a first recess 321 is provided on a surface of the first metal middle portion 32 near or away from the display area AA; and a cathode insulating layer 40, wherein the cathode... A first portion of the insulating layer 40 covers a surface of the first metal top 33 facing away from the substrate 11, and a second portion of the cathode insulating layer 40 covers a surface of the first metal part 30 facing away from the first recess 321; an organic layer 50, comprising a first organic portion 51 and a second organic portion 52, wherein the first organic portion 51 is disposed on the interlayer dielectric layer 20, and the second organic portion 52 is disposed on the cathode insulating layer 40, with the first organic portion 51 and the second organic portion 52 spaced apart; and a cathode layer 60, comprising a first cathode portion 61 and a second cathode portion 62, wherein the first cathode portion 61 is disposed on the first organic portion 51, and the second cathode portion 62 is disposed on the second organic portion 52, with the first cathode portion 61 and the second cathode portion 62 spaced apart; wherein the first recess 321 is located below the first portion of the cathode insulating layer 40.

[0050] In the display panel 100, to accommodate front-facing camera modules, front-facing infrared modules, and other corresponding modules, the display panel 100 requires laser cutting (O-CUT) on the display area during manufacturing. The cut portion forms a non-display area NA, which includes a through-hole area NA3, a packaging area NA2, and a winding area NA1. The through-hole area NA3 is at the center of the non-display area NA. The packaging area NA2 surrounds the through-hole area NA3, the winding area NA1 surrounds the packaging area NA2, and the display area AA surrounds the winding area NA1.

[0051] Reference Figure 2 , Figure 4 and Figure 6In this application, a first recess 321 is provided on a surface of the first metal intermediate portion 32 near or away from the display area AA. During the formation of the organic layer 50 by vapor deposition, the organic layer 50 is interrupted at the first recess 321, forming a first organic portion 51 and a second organic portion 52 spaced apart. During the formation of the cathode layer 60 by vapor deposition, the cathode layer 60 is interrupted at the first recess 321, forming a first cathode portion 61 and a second cathode portion 62 spaced apart. At this time, since the first cathode portion 61 and the second cathode portion 62 are interrupted, and a cathode insulating layer 40 is provided between the second cathode portion 62 and the first metal component 30, the first cathode portion 61 and the second cathode portion 62 cannot be connected through the first metal component 30. This makes the second cathode portion 62 located in the non-display area NA uncharged, significantly slowing down the migration rate of K element to the encapsulation layer, reducing the gaseous products generated by the reaction of K element with the encapsulation layer, avoiding the expansion and deformation of the encapsulation layer, and solving the problem of encapsulation failure of the display panel 100.

[0052] The display panel 100 is an OLED display panel 100, including a display area AA and a non-display area NA located around the display area AA. The non-display area NA includes an encapsulation area NA2, a winding area NA1 located on the side of the encapsulation area NA2 close to the display area AA, and a through-hole area NA3 located on the side of the encapsulation area NA2 away from the display area AA.

[0053] The display panel 100 also includes an encapsulation layer disposed on the cathode layer.

[0054] The substrate 11 is a rigid substrate 11, and the material of the substrate 11 is glass; or, the substrate 11 is a flexible substrate 11, and the material of the substrate 11 is polyimide (PI).

[0055] A buffer layer 12 (BL) is disposed between the substrate 11 and the gate insulating layer 13 to buffer the stress caused by direct contact between the two. The material of the buffer layer 12 is one or more of silicon oxide, silicon nitride, silicon dioxide, and gallium nitride.

[0056] The gate insulating layer 13 is made of one or more insulating materials such as silicon nitride, silicon dioxide, and silicon oxynitride.

[0057] The material of the interlayer dielectric layer 20 is one or more insulating materials such as silicon nitride, silicon dioxide, and silicon oxynitride.

[0058] The first metal component 30 is disposed on the insulating interlayer dielectric layer 20. The first metal component 30 includes a first metal bottom 31, a first metal middle portion 32, and a first metal top 33. The first metal bottom 31, the first metal middle portion 32, and the first metal top 33 are made of the same material. The material of the first metal component 30 is one or more of copper, aluminum, iron, silver, and molybdenum. Alternatively, the first metal component 30 is a Ti-Al-Ti three-layer stack, wherein the first metal bottom 31 is made of titanium (Ti), the first metal middle portion 32 is made of aluminum (Al), and the first metal top 33 is made of titanium. A first recess 321 is provided on a surface of the first metal middle portion 32 that is near or far from the display area AA.

[0059] The cathode insulating layer 40 is made of one of borosilicate glass (BPSG), silicon dioxide, and silicon nitride.

[0060] In the manufacturing method of the display panel 100, a buffer layer 12, a gate insulating layer 13, and an interlayer dielectric layer 20 are sequentially formed on a substrate 11; a first metal element 30 of titanium-aluminum-titanium stack is formed on the interlayer dielectric layer 20; a cathode insulating layer 40 is formed on the interlayer dielectric layer 20, wherein the cathode insulating layer 40 covers the first metal element 30; the cathode insulating layer 40 is patterned, wherein the side of the first metal element 30 near or away from the display area AA is exposed to the cathode insulating layer 40, and a portion of the surface of the first metal element 30 facing away from the substrate 11 is exposed to the cathode insulating layer 40; the first metal element 30 is etched to form a first recess 321 on the side of the first metal middle portion 32 near or away from the display area AA, the first recess 321 being located below the cathode insulating layer 40; an organic layer 50 is formed on the interlayer dielectric layer 20 by vapor deposition; and a cathode layer 60 is formed on the organic layer 50 by vapor deposition.

[0061] In the etching step of the first metal part 30, after the portion of the first metal top 33, made of titanium, exposed to the cathode insulating layer 40 is etched away using a wet etching process, the etching solution contains silver ions. The silver ions undergo a displacement reaction with the aluminum in the middle portion 32 of the first metal, generating aluminum ions which dissolve in the etching solution, thereby forming a first recess 321 on the side of the middle portion 32 of the first metal near or away from the display area AA. The surface of the first metal part 30 facing away from the first recess 321 is not etched because it is covered by the cathode insulating layer 40.

[0062] In the step of forming the organic layer 50 on the interlayer dielectric layer 20 by vapor deposition, the organic layer 50 is interrupted at the first recess 321, forming a first organic portion 51 and a second organic portion 52 spaced apart. This is because during the vapor deposition of the organic layer 50, organic material is deposited on the surface of the interlayer dielectric layer 20 away from the substrate 11, but the organic material cannot be deposited at the opening of the first recess 321. Furthermore, due to the obstruction of the cathode insulating layer 40, the organic material cannot be deposited on the inner wall of the first recess 321, causing the organic layer 50 to be discontinuous at the first recess 321, resulting in an interruption. During the manufacturing process of the display panel 100, a laser is used to cut the through-hole area NA3. After cutting, the organic layer 50 becomes a transport channel for external water and oxygen to invade the internal structure of the display panel 100. When the organic layer 50 is interrupted in the non-display area NA, the water vapor intrusion path is blocked, improving the reliability of the display panel 100.

[0063] Reference Figure 2 , Figure 4 and Figure 6 In the step of forming the cathode layer 60 on the organic layer 50 by vapor deposition, the organic layer 50 is interrupted at the first recess 321, forming a first cathode portion 61 and a second cathode portion 62 that are spaced apart. This is because during the vapor deposition of the cathode layer 60, the cathode layer 60 is deposited on the organic layer 50, but the organic layer 50 is interrupted at the first recess 321, and the cathode layer 60 also cannot be deposited at the opening of the first recess 321. In addition, due to the obstruction of the cathode insulating layer 40, the organic material cannot be deposited on the inner wall of the first recess 321, so the cathode layer 60 is discontinuous at the first recess 321 and is interrupted, forming a first cathode portion 61 on the first organic portion 51 and a second cathode portion 62 on the second organic portion 52. Since the cathode insulating layer 40 is spaced apart between the second cathode portion 62 and the first metal part 30, the second cathode portion 62 cannot be connected to the charged first cathode portion 61 through the first metal part 30. After the cathode layer 60 is isolated, the isolated second cathode portion 62 is not charged, which slows down the migration rate of K element to the encapsulation layer, thereby reducing the gas products generated by the reaction of K element with the encapsulation layer, avoiding the expansion and deformation of the encapsulation layer, and solving the problem of encapsulation failure of display panel 100.

[0064] The first recess 321 is located below the first part of the cathode insulating layer 40. At this time, the surface of the first metal top 33 near the display area AA is flush with the surface of the cathode insulating layer 40 near the display area AA. The projection of the first metal top 33 on the substrate 11 is within the projection range of the first metal bottom 31 on the substrate 11; or, the projection of the first metal top 33 on the substrate 11 coincides with the projection of the first metal bottom 31 on the substrate 11. The length of the first metal bottom 31 can be controlled by etching time, etching speed, etc.

[0065] Reference Figure 2 , Figure 4 and Figure 6 In one embodiment of this application, the cathode insulating layer 40 includes:

[0066] A first insulating portion 41 is disposed on the first metal part 30 and covers a surface of the first metal top 33 that is away from the substrate 11, and a first recess 321 is located below the first insulating portion 41.

[0067] The second insulating portion 42 is disposed on the interlayer dielectric layer 20 and covers the surface of the first metal part 30 away from the first recess 321. The second insulating portion 42 is connected to the first insulating portion 41. The surface of the first insulating portion 41 away from the substrate 11 and the surface of the second insulating portion 42 away from the substrate 11 are flush.

[0068] The second organic part 52 is disposed on the first insulating part 41 and the second insulating part 42.

[0069] The first insulating portion 41 is located between the second cathode portion 62 and the first metal top 33, preventing the second cathode portion 62 and the first metal top 33 from conducting. The second insulating portion 42 covers the surface of the first metal member 30 facing away from the first recess 321. During the etching process of the first metal member 30 to form the first recess 321, the surface of the first metal member 30 facing away from the first recess 321 will not be etched due to the obstruction of the first insulating portion 41 and the second insulating portion 42. During the formation of the organic layer 50 by vapor deposition, the second organic portion 52 will cover the surface of the first insulating portion 41 facing away from the substrate 11, the surface of the second insulating portion 42 facing away from the substrate 11, and the surface of the second insulating portion 42 facing away from the first recess 321, and will be spaced apart from the first organic portion 51 located on the side of the first metal member 30 near the display area AA. The spaced arrangement of the first organic portion 51 and the second organic portion 52 blocks the path of moisture intrusion and improves the reliability of the display panel 100. The first cathode portion 61 is disposed on the first organic portion 51, and the second cathode portion 62 is disposed on the second organic portion 52. The first cathode portion 61 and the second cathode portion 62 are separated at the first recess 321. The first cathode portion 61 is connected to the portion of the cathode layer 60 located in the display area AA and is charged. The second cathode portion 62 is connected to the portion of the cathode layer 60 located in the non-display area NA and is not charged. A cathode insulating layer 40 is disposed between the first metal member 30 and the second cathode portion 62, so that the first cathode portion 61 cannot conduct to the second cathode portion 62 through the first metal member 30, so that the second cathode portion 62 is not charged, thereby improving the reliability of the display panel 100 packaging.

[0070] Reference Figure 2 , Figure 4 and Figure 6In one embodiment of this application, the projection of the first metal middle portion 32 on the substrate 11 is located within the projection range of the first metal top portion 33 on the substrate 11, and the distance from the surface of the first metal top portion 33 away from the second insulating portion 42 to the surface of the first metal middle portion 32 away from the second insulating portion 42 is in the range of 0.1 μm to 0.5 μm.

[0071] The distance from the surface of the first metal top 33 away from the second insulating portion 42 to the surface of the first metal middle portion 32 away from the second insulating portion 42 is one of the following values: 0.10μm, 0.15μm, 0.20μm, 0.25μm, 0.30μm, 0.35μm, 0.40μm, 0.45μm, and 0.50μm. The distance from the surface of the first metal top 33 away from the second insulating portion 42 to the surface of the first metal middle portion 32 away from the second insulating portion 42 is the depth of the first recess 321. The depth of the first recess 321 can be changed by adjusting the etching time, etching speed, and etching solution concentration. During the process of forming the organic layer 50 by vapor deposition, if the depth of the first recess 321 is less than the preset value, the organic layer 50 will not be interrupted at the first recess 321, but will form a continuous first organic portion 51 and second organic portion 52. During the formation of the cathode layer 60 by vapor deposition, if the depth of the first recess 321 is less than a preset value, the cathode layer 60 will not be interrupted at the first recess 321, but will instead form a continuous first cathode portion 61 and a second cathode portion 62. Therefore, when the depth of the first recess 321 is less than the preset value, the continuously arranged first organic portion 51 and second organic portion 52 will become channels for external moisture intrusion. The continuously arranged first cathode portion 61 and second cathode portion 62 will cause the portion of the cathode layer 60 located in the encapsulation region NA2 to become charged. The electric field present therein will cause K+ ions to migrate to the encapsulation layer and react with it, causing the encapsulation layer to expand and deform, leading to encapsulation failure of the display panel 100. When the depth of the first recess 321 is in the range of 0.1 μm to 0.5 μm, both the organic layer 50 and the cathode layer 60 will be interrupted at the first recess 321, improving the stability of the display panel 100 encapsulation.

[0072] Reference Figures 1 to 6 In one embodiment of this application, the display panel 100 further includes a pad 70, which is disposed on the portion of the gate insulating layer 13 located in the non-display area NA, and the pad 70 is located between the interlayer dielectric layer 20 and the gate insulating layer 13.

[0073] The interlayer dielectric layer 20 includes a first dielectric portion 21 and a second dielectric portion 22. The first dielectric portion 21 is disposed on the gate insulating layer 13, and the second dielectric portion 22 is disposed on the pad layer 70. The first metal component 30, the cathode insulating layer 40, the second organic portion 52, and the second cathode portion 62 are sequentially stacked on the second dielectric portion 22.

[0074] The pad 70 is made of one of the following materials: metal, silicon dioxide, silicon nitride, and silicon oxynitride. When the pad 70 is made of metal, since the interlayer dielectric layer 20 is an insulating material and is located between the pad 70 and the first metal part 30, the pad 70 will not be connected to the first metal part 30 or the first cathode part 61.

[0075] In the manufacturing method of the display panel 100, a plurality of spaced pads 70 are formed on the gate insulating layer 13; an interlayer dielectric layer 20 is formed on the gate insulating layer 13, wherein the interlayer dielectric layer 20 covers the plurality of pads 70, the portion of the interlayer dielectric layer 20 disposed on the pads 70 is the second dielectric portion 22, and the portion of the interlayer dielectric layer 20 disposed on the gate insulating layer 13 is the first dielectric portion 21. Since the pads 70 raise the second dielectric portion 22, the surface of the second dielectric portion 22 facing away from the substrate 11 is not flush with the surface of the first dielectric portion 21 facing away from the substrate 11, and a step difference is formed between the second dielectric portion 22 and the first dielectric portion 21, which is beneficial for the organic layer 50 and the cathode layer 60 to be separated at the first recess 321, thereby improving the reliability of the display panel 100 packaging.

[0076] Reference Figures 1 to 6 In one embodiment of this application, the non-display area NA includes a packaging area NA2 and a via area NA3 located on the side of the packaging area NA2 away from the display area AA. The display panel 100 also includes a barrier 80, which is disposed on the portion of the interlayer dielectric layer 20 located in the packaging area NA2 and divides the packaging area NA2 into a first packaging area NA21 and a second packaging area NA22.

[0077] Wherein, the first encapsulation area NA21 is located on the side of the barrier 80 close to the display area AA, the second encapsulation area NA22 is located on the side of the barrier 80 away from the display area AA, and the first metal part 30 is disposed on the portion of the interlayer dielectric layer 20 located in the first encapsulation area NA21.

[0078] The non-display area NA includes a packaging area NA2, a winding area NA1, and a via area NA3. The winding area NA1 is located on the side of the packaging area NA2 closer to the display area AA, and the via area NA3 is located on the side of the packaging area NA2 away from the display area AA. A barrier 80 divides the packaging area NA2 into a first packaging area NA21 and a second packaging area NA22. The barrier 80 is used to prevent organic material located in the first packaging area NA21 from flowing into the second packaging area NA22. Compared to the scheme where the first metal component 30 and the cathode insulating layer 40 are located in the second encapsulation region NA22, the scheme where the first metal component 30 and the cathode insulating layer 40 are located in the first encapsulation region NA21 has a better encapsulation effect. This is because when the first metal component 30 and the cathode insulating layer 40 are located in the second encapsulation region NA22, the portion of the cathode layer 60 in the encapsulation region NA2 is isolated in the second encapsulation region NA22, and the size of the charged portion of the cathode layer 60 in the encapsulation region NA2 is larger. However, when the first metal component 30 and the cathode insulating layer 40 are located in the first encapsulation region NA21, the portion of the cathode layer 60 in the encapsulation region NA2 is isolated in the first encapsulation region NA21, and the size of the charged portion of the cathode layer 60 in the encapsulation region NA2 is smaller. This can slow down the migration rate of the K element to the encapsulation layer and improve the reliability of the display panel 100 encapsulation.

[0079] Reference Figure 3 and Figure 4 In one embodiment of this application, the first recess 321 is disposed on a surface of the first metal member 30 away from the display area AA, and the second insulating portion 42 is disposed on a surface of the first metal member 30 close to the display area AA.

[0080] Among them, the surface of the first metal top 33 near the display area AA, the surface of the first metal middle portion 32 near the display area AA, and the surface of the first metal bottom 31 near the display area AA are flush. The surface of the first metal top 33 near the display area AA abuts against the second insulating portion 42, the surface of the first metal middle portion 32 near the display area AA abuts against the second insulating portion 42, and the surface of the first metal bottom 31 near the display area AA abuts against the second insulating portion 42.

[0081] At this time, the second cathode portion 62 and the cathode layer 60 are connected and energized in the portion located in the display area AA, while the first cathode portion 61 is isolated from the second cathode portion 62 and is not energized. The surface of the first metal part 30 near the display area AA is covered by the cathode insulating layer 40, and its surface will not be etched. Therefore, the surface of the first metal top 33 near the display area AA, the surface of the first metal middle portion 32 near the display area AA, and the surface of the first metal bottom 31 near the display area AA are flush.

[0082] Reference Figure 1 and Figure 2 In one embodiment of this application, the first recess 321 is disposed on a surface of the first metal member 30 near the display area AA, and the second insulating portion 42 is disposed on a surface of the first metal member 30 away from the display area AA.

[0083] Wherein, the surface of the first metal top 33 away from the display area AA, the surface of the first metal middle portion 32 away from the display area AA, and the surface of the first metal bottom 31 away from the display area AA are flush with each other. The surface of the first metal top 33 away from the display area AA abuts against the second insulating portion 42. The surface of the first metal middle portion 32 away from the display area AA abuts against the second insulating portion 42. The surface of the first metal bottom 31 away from the display area AA abuts against the second insulating portion 42.

[0084] At this time, the portion of the first cathode 61 and the cathode layer 60 located in the display area AA are connected and energized, while the second cathode 62 is isolated from the first cathode 61 and is not energized. The surface of the first metal part 30 away from the display area AA is covered by the cathode insulating layer 40, and its surface will not be etched. Therefore, the surface of the first metal top 33 away from the display area AA, the surface of the first metal middle part 32 away from the display area AA, and the surface of the first metal bottom 31 away from the display area AA are flush.

[0085] In one embodiment of this application, the thickness of the pad 70 is in the range of 40 nm to 1500 nm;

[0086] The thickness of the first metal part 30 is in the range of 700nm to 1000nm.

[0087] The thickness of the padding layer 70 is one of the following values: 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, 750nm, 800nm, 850nm, 900nm, 950nm, 1000nm, 1050nm, 1100nm, 1150nm, 1200nm, 1250nm, 1300nm, 1350nm, 1400nm, 1450nm, and 1500nm.

[0088] The thickness of the first metal layer is one of the following values: 700nm, 720nm, 740nm, 760nm, 780nm, 800nm, 820nm, 840nm, 860nm, 880nm, 900nm, 920nm, 940nm, 960nm, 980nm, and 1000nm.

[0089] The pad 70 needs to have a certain thickness to increase the step difference between the first cathode portion 61 and the second cathode portion 62, so that the first cathode portion 61 and the second cathode portion 62 are separated in the first recess 321. The thickness of the pad 70 should not be too thick, otherwise the encapsulation layer above the pad 70 will be difficult to level.

[0090] The first metal component 30 needs to have a certain thickness so that the organic layer 50 and the cathode layer 60 can be separated in the first recess 321. When the first metal component 30 is too thin, the organic layer 50 and the cathode layer 60 cannot be separated in the first recess 321. When the first metal component 30 is too thick, the encapsulation layer above the first metal component 30 will be difficult to level.

[0091] Reference Figures 1 to 6 In one embodiment of this application, a plurality of pads 70 are spaced apart in the non-display area NA in a direction from the display area AA to the non-display area NA. At least one second medium portion 22 is provided with the first metal member 30, and at least one second medium portion 22 is provided with a second metal member 90. The second metal member 90 includes:

[0092] The second metal bottom 91 is provided on the second medium portion 22.

[0093] The second metal middle portion 92 is disposed on the second metal bottom 91. The second metal middle portion 92 has a second recess 921 on a surface close to the display area AA, and a third recess 922 on a surface away from the display area AA.

[0094] A second metal top 93 is provided on the second metal middle portion 92, wherein the second recess 921 and the third recess 922 are both located below the second metal top 93.

[0095] The organic layer 50 further includes a third organic part 53, which is disposed on the second metal top 93, and the third organic part 53, the first organic part 51 and the second organic part 52 are spaced apart.

[0096] The cathode layer 60 further includes a third cathode portion 63, which is disposed on the third organic portion 53, and the third cathode portion 63, the first cathode portion 61 and the second cathode portion 62 are spaced apart.

[0097] The number of pads 70 can be one of two, three, four, five, six, seven, eight, nine, or ten. A portion of the pads 70 are located in the first packaging region NA21, and another portion of the pads 70 are located in the second packaging region NA22.

[0098] When there are two pads 70, one pad 70 is located in the second encapsulation region NA22 and the other pad 70 is located in the first encapsulation region NA21. The pad 70 located in the second encapsulation region NA22 is provided with a second metal element 90. When the organic layer 50 is formed in the second encapsulation region NA22, the organic layer 50 is broken at the second recess 921 and the third recess 922, forming a first organic portion 51 and a third organic portion 53 spaced apart. The broken organic layer 50 blocks the moisture intrusion path, improving the reliability of the display panel 100. The pad 70 located in the first encapsulation region NA21 is provided with a first metal element 30, used to break the connection between the organic layer 50 and the cathode layer 60, further blocking the moisture intrusion path and making the portion of the cathode layer 60 located in the encapsulation region NA2 uncharged, thus improving the reliability of the encapsulation layer.

[0099] When there are three pads 70, two pads 70 are located in the first encapsulation area NA21 and one pad 70 is located in the second encapsulation area NA22. The two pads 70 located in the first encapsulation area NA21 are respectively disposed on the first metal part 30 and the second metal part 90, and the pad 70 located in the second encapsulation area NA22 is provided with the second metal part 90.

[0100] When the number of pads 70 is four or more, at least two pads 70 are located in the first encapsulation area NA21 and are respectively provided with a first metal part 30 and a second metal part 90, and at least two pads 70 are located in the second encapsulation area NA22 and are both provided with a second metal part 90.

[0101] In one embodiment, when at least two pads 70 are located in the first encapsulation region NA21, a second metal element 90 is provided above at least one pad 70 near the display area AA, and a first metal element 30 and a cathode insulating layer 40 are provided above at least one pad 70 away from the display area AA. A first recess 321 is provided on a surface of the first metal element 30 away from the display area AA, and a second insulating portion 42 is provided on a surface of the first metal element 30 near the display area AA; or, the first recess 321 is provided on a surface of the first metal element 30 near the display area AA, and the second insulating portion 42 is provided on a surface of the first metal element 30 away from the display area AA.

[0102] In another embodiment, when at least two pads 70 are located in the first encapsulation region NA21, a first metal element 30 and a cathode insulating layer 40 are provided above at least one pad 70 near the display area AA, and a second metal element 90 is provided above at least one pad 70 away from the display area AA. A first recess 321 is provided on a surface of the first metal element 30 away from the display area AA, and a second insulating portion 42 is provided on a surface of the first metal element 30 near the display area AA; or, the first recess 321 is provided on a surface of the first metal element 30 near the display area AA, and the second insulating portion 42 is provided on a surface of the first metal element 30 away from the display area AA.

[0103] Reference Figure 5 and Figure 6 In one embodiment of this application, the non-display area NA includes a winding area NA1, a packaging area NA2, and a via area NA3. The winding area NA1 is located on the side of the packaging area NA2 closer to the display area AA, and the via area NA3 is located on the side of the packaging area NA2 away from the display area AA. The display panel 100 also includes a planarization layer 14, which is disposed on the portion of the interlayer dielectric layer 20 located in the winding area NA1.

[0104] The second insulating portion 42 is disposed on the portion of the interlayer dielectric layer 20 located in the winding region NA1, and is located on the side of the planarization layer 14 near the encapsulation region NA2. The surface of the second insulating portion 42 facing away from the substrate 11 is flush with the surface of the planarization layer 14 facing away from the substrate 11.

[0105] The first metal part 30 is disposed on the portion of the interlayer dielectric layer 20 located in the winding region NA1, and is located on the side of the second insulating portion 42 near the encapsulation region NA2.

[0106] The first recess 321 is provided on the side of the first metal part 30 near the encapsulation area NA2.

[0107] The planarization layer 14 and the cathode insulating layer 40 are made of the same material. The material of the planarization layer 14 is one of borosilicate glass (BPSG), silicon dioxide, and silicon nitride.

[0108] When the first metal part 30 and the cathode insulating layer 40 are located in the winding area NA1, the size of the charged part of the cathode layer 60 located in the non-display area NA can be further reduced, the migration rate of the K element to the encapsulation layer can be reduced, and the encapsulation effect of the display panel 100 can be improved.

[0109] The specific embodiments of this application have been described in detail above. The embodiments disclosed above are merely preferred embodiments of this application. Those skilled in the art can make many modifications and improvements without departing from the concept of this application. All such modifications and improvements fall within the scope of protection defined by the claims of this application.

Claims

1. A display panel, comprising a display area and a non-display area located around the periphery of the display area, characterized in that, The display panel includes: Substrate; A buffer layer is disposed on the substrate; A gate insulating layer is disposed on the buffer layer; An interlayer dielectric layer is disposed on the gate insulating layer; A first metal component is disposed on the portion of the interlayer dielectric layer located in the non-display area. The first metal component includes a first metal bottom, a first metal middle portion, and a first metal top portion. The first metal bottom portion is disposed on the interlayer dielectric layer, the first metal middle portion is disposed on the first metal bottom portion, and the first metal top portion is disposed on the first metal middle portion. A first recess is provided on a surface of the first metal middle portion that is close to or far from the display area. A cathode insulating layer, wherein a first portion of the cathode insulating layer covers a surface of the first metal member facing away from the substrate, and a second portion of the cathode insulating layer covers a surface of the first metal member facing away from the first recess; An organic layer, comprising a first organic portion and a second organic portion, wherein the first organic portion is disposed on the interlayer dielectric layer, and the second organic portion is disposed on the cathode insulating layer, the first organic portion and the second organic portion being spaced apart; and The cathode layer includes a first cathode portion and a second cathode portion, wherein the first cathode portion is disposed on the first organic portion, the second cathode portion is disposed on the second organic portion, and the first cathode portion and the second cathode portion are spaced apart. The first recess is located below the first portion of the cathode insulating layer.

2. The display panel as described in claim 1, characterized in that, The cathode insulating layer comprises: A first insulating portion is disposed on the first metal member and covers a surface of the first metal member facing away from the substrate; the first recess is located below the first insulating portion; and The second insulating portion is disposed on the interlayer dielectric layer and covers a surface of the first metal part away from the first recess. The second insulating portion is connected to the first insulating portion, and the surface of the first insulating portion away from the substrate and the surface of the second insulating portion away from the substrate are flush. The second organic part is disposed on the first insulating part and the second insulating part.

3. The display panel as described in claim 2, characterized in that, The projection of the first metal middle portion onto the substrate is located within the projection range of the first metal top portion onto the substrate, and the distance from the surface of the first metal top portion away from the second insulating portion to the surface of the first metal middle portion away from the second insulating portion is in the range of 0.1 μm to 0.5 μm.

4. The display panel as described in claim 2, characterized in that, The display panel further includes a pad layer, which is disposed on the portion of the gate insulating layer located in the non-display area, and the pad layer is located between the interlayer dielectric layer and the gate insulating layer; The interlayer dielectric layer includes a first dielectric portion and a second dielectric portion. The first dielectric portion is disposed on the gate insulating layer, and the second dielectric portion is disposed on the pad layer. The first metal component, the cathode insulating layer, the second organic portion, and the second cathode portion are sequentially stacked on the second dielectric portion.

5. The display panel as described in claim 2, characterized in that, The non-display area includes an encapsulation area and a via area located on the side of the encapsulation area away from the display area. The display panel also includes a baffle wall, which is disposed on the portion of the interlayer dielectric layer located in the encapsulation area and divides the encapsulation area into a first encapsulation area and a second encapsulation area. The first encapsulation area is located on the side of the barrier wall closer to the display area, the second encapsulation area is located on the side of the barrier wall away from the display area, and the first metal component is disposed on the portion of the interlayer dielectric layer located in the first encapsulation area.

6. The display panel as described in claim 5, characterized in that, The first recess is provided on a surface of the first metal member away from the display area, and the second insulating portion is provided on a surface of the first metal member close to the display area; Wherein, the top surface of the first metal near the display area, the middle surface of the first metal near the display area, and the bottom surface of the first metal near the display area are flush with each other. The top surface of the first metal near the display area abuts against the second insulating part, the middle surface of the first metal near the display area abuts against the second insulating part, and the bottom surface of the first metal near the display area abuts against the second insulating part.

7. The display panel as described in claim 5, characterized in that, The first recess is provided on a surface of the first metal member close to the display area, and the second insulating portion is provided on a surface of the first metal member away from the display area; Wherein, the top surface of the first metal away from the display area, the middle surface of the first metal away from the display area, and the bottom surface of the first metal away from the display area are flush with each other. The top surface of the first metal away from the display area abuts against the second insulating part, the middle surface of the first metal away from the display area abuts against the second insulating part, and the bottom surface of the first metal away from the display area abuts against the second insulating part.

8. The display panel as described in claim 4, characterized in that, The thickness of the padding layer is in the range of 40 nm to 1500 nm; The thickness of the first metal part is in the range of 700nm to 1000nm.

9. The display panel as described in claim 4, characterized in that, Multiple pads are spaced apart in the non-display area along a direction from the display area to the non-display area. At least one second medium portion has the first metal element, and at least one second medium portion has a second metal element. The second metal element includes: The second metal bottom is disposed on the second dielectric portion; A second metal middle portion is disposed on the bottom of the second metal portion. A second recess is provided on one surface of the second metal middle portion near the display area, and a third recess is provided on one surface of the second metal middle portion away from the display area. The second metal top is provided on the middle part of the second metal, wherein the second recess and the third recess are both located below the second metal top; The organic layer further includes a third organic part, which is disposed on the top of the second metal, and the third organic part, the first organic part, and the second organic part are spaced apart. The cathode layer further includes a third cathode portion, which is disposed on the third organic portion, and the third cathode portion, the first cathode portion, and the second cathode portion are spaced apart.

10. The display panel as claimed in claim 2, characterized in that, The non-display area includes a winding area, a packaging area, and a via area. The winding area is located on the side of the packaging area closer to the display area, and the via area is located on the side of the packaging area away from the display area. The display panel also includes a planarization layer, which is disposed on the portion of the interlayer dielectric layer located on the winding area. The second insulating portion is disposed on the portion of the interlayer dielectric layer located in the winding region and on the side of the planarization layer near the encapsulation region. The surface of the second insulating portion facing away from the substrate is flush with the surface of the planarization layer facing away from the substrate. The first metal component is disposed on the portion of the interlayer dielectric layer located in the winding region, and is located on the side of the second insulating portion near the encapsulation region; The first recess is located on the side of the first metal part near the encapsulation area.

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