Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate includes: a plurality of light-emitting output lines (EMLs) connected to a light-emitting driving circuit (100) and a plurality of scan output lines (GNLs) connected to a scan driving circuit (200); at least one light-emitting output line includes at least two interconnected light-emitting output portions, and the scan output lines are integrally formed, or, the light-emitting output lines are integrally formed and at least one scan output line includes at least two interconnected scan output portions, or, at least one light-emitting output line includes at least two interconnected light-emitting output portions and at least one scan output line includes at least two interconnected scan output portions; wherein at least two light-emitting output portions located on the same light-emitting output line are disposed in different layers and the resistivity of the light-emitting output portions disposed in different layers is different, and at least two scan output portions located on the same scan output line are disposed in different layers and the resistivity of the scan output portions disposed in different layers is different.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting elements and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, this disclosure also provides a display substrate, comprising: a display area and a non-display area. The display substrate includes: a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes: a plurality of pixel driving circuits located in the display area and arranged in an array, and a light-emitting driving circuit, a scanning driving circuit, and a control driving circuit located in the non-display area. The light-emitting driving circuit and the scanning driving circuit are located on the side of the control driving circuit away from the display area. At least one pixel driving circuit includes: a write transistor, a compensation reset transistor, and a light-emitting transistor. The scanning driving circuit is configured to provide a driving signal to the compensation reset transistor, the control driving circuit is configured to provide a driving signal to the write transistor, and the light-emitting driving circuit is configured to provide a driving signal to the light-emitting transistor. The display substrate further includes: multiple light-emitting output lines connected to the light-emitting driving circuit and multiple scan output lines connected to the scan driving circuit; At least one of the light-emitting output lines includes at least two interconnected light-emitting output portions, and the scanning output line is an integrally formed structure; or, the light-emitting output line is an integrally formed structure, and at least one scanning output line includes at least two interconnected scanning output portions; or, at least one of the light-emitting output lines includes at least two interconnected light-emitting output portions, and at least one scanning output line includes at least two interconnected scanning output portions. In this configuration, at least two light-emitting output sections located on the same light-emitting output line are arranged in different layers, and the resistivity of the light-emitting output sections arranged in different layers is different. Similarly, at least two scan output sections located on the same scan output line are arranged in different layers, and the resistivity of the scan output sections arranged in different layers is different.

[0005] In some possible implementations, the pixel driving circuit includes: a data signal terminal, a control signal terminal, a scan signal terminal, and a light emission signal terminal; the display substrate further includes: N data signal lines, 2M control signal lines, 2M light emission signal lines, and 2M scan signal lines; The write transistor is electrically connected to the control signal terminal and the data signal terminal respectively, the compensation reset transistor is electrically connected to the scan signal terminal, and the light-emitting transistor is electrically connected to the light-emitting signal terminal. The data signal lines extend along a first direction, and N data signal lines are arranged along a second direction. 2M control signal lines, 2M light emission signal lines, and 2M scanning signal lines extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect. For the pixel driving circuit in row s and column t, the control signal terminal is electrically connected to the s-th control signal line, the light emission signal terminal is electrically connected to the s-th light emission signal line, the scan signal terminal is electrically connected to the s-th scan signal line, and the data signal terminal is electrically connected to the t-th data signal line. s 2M, 1 t N; The light-emitting driving circuit includes: M cascaded light-emitting shift registers, with at least one stage of the light-emitting shift register electrically connected to two light-emitting signal lines; the scanning driving circuit includes: M cascaded scanning shift registers, with at least one stage of the scanning shift register electrically connected to two scanning signal lines; the control driving circuit includes: 2M cascaded control shift registers, with at least one stage of the control shift register electrically connected to one control signal line. i M; The light-emitting shift register, scan shift register, and control shift register include: input terminals and output terminals; The output of the i-th stage light-emitting shift register is electrically connected to the 2i-1 light-emitting signal line to the 2i light-emitting signal line through the i-th light-emitting output line; the output of the i-th stage scan shift register is electrically connected to the 2i-1 scan signal line to the 2i scan signal line through the i-th scan output line; the output of the s-th stage control shift register is electrically connected to the s-th control signal line.

[0006] In some possible implementations, the circuit structure layer includes: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a first planarization layer, and a fourth conductive layer, which are sequentially stacked on a substrate. When at least one of the light-emitting output lines includes at least two interconnected light-emitting output parts, the at least two light-emitting output parts located on the same light-emitting output line are located in one of the first conductive layer and the second conductive layer and one of the third conductive layer and the fourth conductive layer. When at least one of the scan output lines includes at least two interconnected scan output sections, the at least two scan output sections located on the same scan output line are located in one of the first conductive layer and the second conductive layer and one of the third conductive layer and the fourth conductive layer. When the light-emitting output line is an integrally formed structure, the light-emitting output line is located in the fourth conductive layer; When the scan output line is an integrally formed structure, the scan output line is located in the second conductive layer; The resistivity of the first conductive layer and the resistivity of the second conductive layer are both greater than the resistivity of the third conductive layer and the resistivity of the fourth conductive layer.

[0007] In some possible implementations, the circuit structure layer includes: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a fifth conductive layer, a sixth insulating layer, a third conductive layer, a fourth insulating layer, a first planarization layer, a fourth conductive layer, a seventh insulating layer, and a sixth conductive layer, which are sequentially stacked on a substrate. When at least one of the light-emitting output lines includes at least two interconnected light-emitting output parts, the at least two light-emitting output parts located on the same light-emitting output line are located in one of the first conductive layer, the second conductive layer, and the fifth conductive layer, and one of the third conductive layer, the fourth conductive layer, and the sixth conductive layer. When at least one of the scan output lines includes at least two interconnected scan output sections, the at least two scan output sections located on the same scan output line are located in one of the first conductive layer, the second conductive layer, and the fifth conductive layer, and one of the third conductive layer, the fourth conductive layer, and the sixth conductive layer. When the light-emitting output line is an integrally formed structure, the light-emitting output line is located in the fourth conductive layer; When the scan output line is an integrally formed structure, the scan output line is located in the second conductive layer; The resistivity of the first conductive layer, the second conductive layer, and the third conductive layer are all greater than the resistivity of the third conductive layer, the fourth conductive layer, and the sixth conductive layer.

[0008] In some possible implementations, when at least one of the scan output lines includes at least two interconnected scan output sections, the scan output line includes: a first scan output section, a second scan output section, a third scan output section, and a fourth scan output section extending along a second direction; The first scan output section and the second scan output section are disposed on the same layer, the third scan output section and the fourth scan output section are disposed on the same layer, and the third scan output section is located on the side of the first scan output section away from the substrate; The third scan output unit is located on the side of the first scan output unit away from the display area, the fourth scan output unit is located on the side of the first scan output unit closer to the display area, and the second scan output unit is located on the side of the fourth scan output unit closer to the display area. The first scan output unit is connected to the third scan output unit and the fourth scan output unit respectively, and the fourth scan output unit is connected to the second scan output unit. The first scan output of the i-th scan output line is connected to the output of the i-th stage scan shift register, the second scan output of the i-th scan output line is connected to the (2i-1)-th scan signal line and the 2i-th scan signal line, and the third scan output of the i-th scan output line is connected to the input of the (i+1)-th stage scan shift register.

[0009] In some possible implementations, the i-th scan output line is located between the i-th level scan shift register and the (i+1)-th level scan shift register.

[0010] In some possible implementations, when at least one of the light-emitting output lines includes at least two interconnected light-emitting output portions, the light-emitting output line includes: a first light-emitting output portion, a second light-emitting output portion, and a third light-emitting output portion extending along a second direction; The second light-emitting part and the third light-emitting part are disposed on the same layer, and the third light-emitting part is located on the side of the first light-emitting part away from the substrate; The second light-emitting part is located on the side of the first light-emitting part away from the display area, and the third light-emitting part is located on the side of the first light-emitting part closer to the display area. The first light-emitting part is connected to the second light-emitting part and the third light-emitting part, respectively. The second light-emitting output section of the i-th light-emitting output line is connected to the output terminal of the i-th stage light-emitting shift register, and the third light-emitting output section of the i-th light-emitting output line is connected to the 2i-1 light-emitting signal line and the 2i light-emitting signal line.

[0011] In some possible implementations, the first and third light-emitting output sections of the i-th light-emitting output line are located between the (2i+1)-th stage control shift register and the (2i+2)-th stage control shift register; The second light-emitting output portion of the i-th light-emitting output line includes: a first output connection portion, a second output connection portion, and a third output connection portion; the first output connection portion and the third output connection portion extend along a second direction, and the second output connection portion extends along a first direction; The first output connection is located between the i-th level scan shift register and the (i+1)-th level scan shift register, and is connected to the second output connection and the output terminal of the i-th level light-emitting shift register; The second output connection is located between the i-th stage scan shift register and the (2i-1)-th stage control shift register, and is connected to the third output connection. The third output connection is located between the 2i+1 level control shift register and the 2i+2 level control shift register, and is connected to the 2i-1 light-emitting signal line and the 2i light-emitting signal line.

[0012] In some possible implementations, the system further includes: an initial light-emitting signal line, a first light-emitting clock signal line to a third light-emitting clock signal line, a first high-level power supply line, a first low-level power supply line, a scan initial signal line, a first scan clock signal line to a third scan clock signal line, a second high-level power supply line, a second low-level power supply line, a control initial signal line, a first control clock signal line, a second control clock signal line, a third high-level power supply line, and a third low-level power supply line, all located in a non-display area and extending along a first direction; wherein, there are two of each of the first low-level power supply line, the second low-level power supply line, the first scan clock signal line, and the third scan clock signal line. Specifically, the input terminal of the first-stage light-emitting shift register is electrically connected to the initial light-emitting signal line, and the output terminal of the i-th-stage light-emitting shift register is electrically connected to the input terminal of the (i+1)-th stage light-emitting shift register; the first clock signal terminal of the i-th-stage light-emitting shift register is electrically connected to the first light-emitting clock signal line, the second clock signal terminal is electrically connected to the second light-emitting clock signal line, and the third clock signal terminal is electrically connected to the third light-emitting clock signal line; the first clock signal terminal of the (i+1)-th stage light-emitting shift register is electrically connected to the third light-emitting clock signal line, the second clock signal terminal is electrically connected to the second light-emitting clock signal line, and the third clock signal terminal is electrically connected to the first light-emitting clock signal line; the first power supply terminal of the i-th-stage light-emitting shift register is electrically connected to the first high-level power supply line, and the second power supply terminal of the i-th-stage light-emitting shift register is electrically connected to the first low-level power supply line; the input terminal of the first-stage scan shift register is electrically connected to the initial scan signal line, and the output terminal of the i-th-stage scan shift register is electrically connected to the input terminal of the (i+1)-th stage scan shift register; the first clock signal terminal of the i-th-stage scan shift register is electrically connected to the first light-emitting clock signal line, the second clock signal terminal is electrically connected to the second light-emitting clock signal line, and the third clock signal terminal is electrically connected to the first light-emitting clock signal line; the first power supply terminal of the i-th-stage light-emitting shift register is electrically connected to the first high-level power supply line, and the second power supply terminal of the i-th-stage light-emitting shift register is electrically connected to the first low-level power supply line; the input terminal of the first-stage scan shift register is electrically connected to the initial scan signal line, and the output terminal of the i-th-stage scan shift register is electrically connected to the input terminal of the (i+1)-th stage scan shift register; the first clock signal terminal of the i- The clock signal terminal is electrically connected to the first scan clock signal line, the second clock signal terminal is electrically connected to the second scan clock signal line, and the third clock signal terminal is electrically connected to the third scan clock signal line. The first power supply terminal of the i-th stage scan shift register is electrically connected to the second high-level power supply line, and the second power supply terminal of the i-th stage scan shift register is electrically connected to the second low-level power supply line. The input terminal of the first stage control shift register is electrically connected to the control initial signal line, and the output terminal of the s-th stage control shift register is electrically connected to the input terminal of the s+1-th stage control shift register. The first clock signal terminal of the s-th stage control shift register is electrically connected to the first control clock signal line, and the second clock signal terminal is electrically connected to the second control clock signal line. The first clock signal terminal of the s+1-th stage control shift register is electrically connected to the second control clock signal line, and the second clock signal terminal is electrically connected to the first control clock signal line. The first power supply terminal of the i-th stage control shift register is electrically connected to the third high-level power supply line, and the second power supply terminal of the s-th stage control shift register is electrically connected to the third low-level power supply line.

[0013] In some possible implementations, a light-emitting structure layer located on the side of the circuit structure layer away from the substrate is also included. The light-emitting structure layer includes light-emitting elements located in the display area and arranged in an array. The light-emitting elements include an anode, an organic light-emitting layer, and a cathode. The anode is located on the side of the organic light-emitting layer closer to the substrate, and the cathode is located on the side of the organic light-emitting layer away from the substrate. The circuit structure layer also includes a second power line located in the non-display area, which is electrically connected to the cathode of the light-emitting element.

[0014] In some possible implementations, the light-emitting shift register includes multiple light-emitting transistors and multiple light-emitting capacitors; the scan shift register includes multiple scan transistors and multiple scan capacitors; the control shift register includes multiple control transistors and multiple control capacitors; and the light-emitting capacitors, the scan capacitors, and the control capacitors all include a first electrode and a second electrode. The semiconductor layer includes: an active layer of multiple light-emitting transistors, an active layer of multiple scanning transistors, and an active layer of multiple control transistors. The first conductive layer includes: control electrodes of multiple light-emitting transistors, first plates of multiple light-emitting capacitors, control electrodes of multiple scanning transistors, first plates of multiple scanning capacitors, control electrodes of multiple control transistors, first plates of multiple first control capacitors, a first connecting electrode, and a second connecting electrode. The second conductive layer includes: second plates of multiple first light-emitting capacitors, second plates of multiple scanning capacitors, second plates of multiple control capacitors, and third to fifth connecting electrodes; The third conductive layer includes: an initial light-emitting signal line, a first high-level power supply line, a first low-level power supply line, a first light-emitting clock signal line to a third light-emitting clock signal line, a first electrode and a second electrode of a plurality of light-emitting transistors, a scan initial signal line, a second high-level power supply line, a second low-level power supply line, a first scan clock signal line to a third scan clock signal line, a first electrode and a second electrode of a plurality of scan transistors, a control initial signal line, a third high-level power supply line, a third low-level power supply line, a first control clock signal line, a second control clock signal line, a first electrode and a second electrode of a plurality of control transistors, and a sixth connecting electrode; The fourth conductive layer includes: a second power line.

[0015] In some possible implementations, the light-emitting shift register includes thirteen light-emitting transistors and three light-emitting capacitors; the scan shift register includes fourteen scan transistors and three scan capacitors; the control shift register includes eight control transistors and two control capacitors; the second terminal of the tenth light-emitting transistor is multiplexed as the output terminal of the light-emitting shift register; and the second terminal of the tenth scan transistor is multiplexed as the output terminal of the scan shift register. The control electrodes of the first light-emitting transistor to the eighth light-emitting transistor and the control electrodes of the eleventh light-emitting transistor to the thirteenth light-emitting transistor are located on the side of the control electrodes of the ninth and tenth light-emitting transistors that are far from the display area; the control electrodes of the ninth and tenth light-emitting transistors are arranged along the first direction. The control electrodes of the first scanning transistor to the eighth scanning transistor and the control electrodes of the eleventh scanning transistor to the fourteenth scanning transistor are located on the side of the control electrodes of the ninth scanning transistor and the tenth scanning transistor that are far from the display area; the control electrodes of the ninth scanning transistor and the tenth scanning transistor are arranged along the first direction; The control electrodes of the first control transistor to the third control transistor and the control electrodes of the sixth control transistor to the eighth control transistor are located on the side of the control electrodes of the fourth control transistor and the fifth control transistor that are away from the display area; the control electrodes of the fourth control transistor and the fifth control transistor are arranged along the first direction; The first connection electrode is located on the side of the control electrode of the ninth scanning transistor and the control electrode of the tenth scanning transistor away from the display area, and extends along the second direction; the second connection electrode is connected to the first electrode of the fourth scanning transistor. The second connection electrode is located on the side of the control electrode of the fourth control transistor that is far from the control electrode of the fifth control transistor, and extends along the second direction; the second connection electrode is connected to the second electrode of the fifth control transistor of the previous stage light-emitting shift register.

[0016] In some possible implementations, the second plates of the first light-emitting capacitor and the second plates of the second light-emitting capacitor are arranged along a second direction, and the second plate of the first light-emitting capacitor is located on the side of the second plate of the second light-emitting capacitor away from the display area, while the second plates of the second light-emitting capacitor and the second plates of the third light-emitting capacitor are arranged along a first direction. The second plates of the first scanning capacitor and the second plates of the second scanning capacitor are arranged along the second direction, and the second plate of the first scanning capacitor is located on the side of the second plate of the second scanning capacitor away from the display area. The second plates of the second scanning capacitor and the second plates of the third scanning capacitor are arranged along the first direction. The second plates of the first control capacitor and the second control capacitor are arranged along the first direction. The third connecting electrode is located on the side of the second plate of the third light-emitting capacitor away from the second plate of the second light-emitting capacitor, and extends along the second direction. The third connecting electrode is connected to the second electrode of the tenth light-emitting transistor and the first electrode of the first light-emitting transistor of the next stage light-emitting shift register, respectively. The fourth connection electrode is located on the side of the second plate of the third scanning capacitor away from the second plate of the second scanning capacitor, and extends along the second direction. The fourth connection electrode is connected to the first electrode of the first scanning transistor of the next-stage scanning shift register. The fifth connecting electrode and the second plate of the first control capacitor are arranged along the first direction, and the fifth connecting electrode is located on the side of the second plate of the first control capacitor away from the display area. The fifth connecting electrode is connected to the second electrode of the second control transistor.

[0017] In some possible implementations, the initial light-emitting signal line, the third scan clock signal line, the first scan clock signal line, the first low-level power supply line, and the first scan clock signal line are arranged sequentially along the direction close to the display area. The first and second electrodes of the first light-emitting transistor to the first and second electrodes of the eighth light-emitting transistor and the first and second electrodes of the eleventh light-emitting transistor to the first and second electrodes of the thirteenth light-emitting transistor are located between the first low-level power supply line and the second scan clock signal line. The second scan clock signal line is located on the side of the first low-level power supply line close to the display area, and the first high-level power supply line is located on the side of the second scan clock signal line close to the display area. The first and second electrodes of the ninth light-emitting transistor to the first and second electrodes of the tenth light-emitting transistor are located between the first high-level power supply line and the second low-level power supply line. The second low-level power supply line is located on the side of the first high-level power supply line close to the display area. The initial scan signal line, the first and third scan clock signal lines, the first scan clock signal line, the second and third scan clock signal lines, the second and first scan clock signal lines, and the first and second low-level power supply lines are arranged sequentially along the side of the second and first low-level power supply lines closest to the display area. The first and second poles of the first scan transistor to the first and second poles of the eighth scan transistor, the first and second poles of the tenth scan transistor to the first and second poles of the fourteenth scan transistor, and the third scan output section are located between the first and second low-level power supply lines and the second scan clock signal lines. The second scan clock signal line is located on the side of the first and second low-level power supply lines closest to the display area, and the second high-level power supply line is located on the side of the second scan clock signal lines closest to the display area. The first and second poles of the ninth scan transistor to the first and second poles of the tenth scan transistor are located between the second high-level power supply lines and the second low-level power supply lines. The second low-level power supply line is located on the side of the second high-level power supply lines closest to the display area. The control initial signal line, the first control clock signal line, the second control clock signal line, and the third low-level power supply line are arranged sequentially along the direction of the second low-level power supply line near the display area. The first and second poles of the first control transistor to the first and second poles of the eighth control transistor and the sixth connection electrode are located between the third low-level power supply line and the third high-level power supply line. The third high-level power supply line is located on the side of the third low-level power supply line near the display area. The sixth connection electrode is connected to the fifth connection electrode and the control electrode of the fourth control transistor, respectively.

[0018] In some possible implementations, the orthographic projection of the second power line onto the substrate at least partially overlaps with the orthographic projection of the light-emitting driving circuit onto the substrate; The orthographic projection of the second power line on the substrate covers the orthographic projections of the initial light-emitting signal line, the first high-level power line, the first low-level power line, the first light-emitting clock signal line to the third light-emitting clock signal line on the substrate, and does not overlap with the orthographic projection of the second low-level power line on the substrate.

[0019] In some possible implementations, the second conductive layer further includes: the first scan output section and the second scan output section.

[0020] In some possible implementations, the third conductive layer further includes a third scan output section and a fourth scan output section.

[0021] In some possible implementations, the first conductive layer further includes a first light-emitting output section.

[0022] In some possible implementations, the fourth conductive layer includes a second light-emitting portion and a third light-emitting portion.

[0023] In some possible implementations, the third conductive layer may also include: a seventh connecting electrode and an eighth connecting electrode; The seventh connecting electrode is connected to the first light-emitting part and the second light-emitting part, respectively, and the eighth connecting electrode is connected to the first light-emitting part and the third light-emitting part, respectively.

[0024] Secondly, this disclosure also provides a display device including the aforementioned display substrate.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0027] Figure 1 This is a schematic diagram of the structure of a display substrate; Figure 2A Schematic diagram of the display substrate provided in the embodiments of this disclosure Figure 1 ; Figure 2B Schematic diagram 2 of the display substrate provided in the embodiments of this disclosure; Figure 3 This is a schematic diagram of the scan output lines; Figure 4 This is a schematic diagram of the light output line; Figure 5A This is a schematic diagram of an equivalent circuit for a pixel driving circuit. Figure 5B This is a timing diagram of a pixel driving circuit. Figure 6A An equivalent circuit diagram of a light-emitting shift register provided for an exemplary embodiment; Figure 6B for Figure 6A The timing diagram of the provided light-emitting shift register; Figure 7A An equivalent circuit diagram of a scan shift register provided for an exemplary embodiment; Figure 7B for Figure 7A The timing diagram for the provided scan shift register; Figure 8A An equivalent circuit diagram of a control shift register provided for an exemplary embodiment; Figure 8B for Figure 8A The timing diagram for the control shift register is provided; Figure 9 This is a schematic diagram after the semiconductor layer has been formed; Figure 10 Schematic diagram of the first conductive layer Figure 1 ; Figure 11 Schematic diagram after the formation of the first conductive layer Figure 1 ; Figure 12 This is a schematic diagram of the second conductive layer; Figure 13 Schematic diagram after the formation of the second conductive layer Figure 1 ; Figure 14 Schematic diagram of the third insulating layer Figure 1 ; Figure 15 Schematic diagram after the formation of the third insulating layer Figure 1 ; Figure 16 Schematic diagram of the third conductive layer Figure 1 ; Figure 17 Schematic diagram after the formation of the third conductive layer Figure 1 ; Figure 18 Schematic diagram of the first flattening layer Figure 1 ; Figure 19 A schematic diagram after the formation of the first planarization layer. Figure 1 ; Figure 20 Schematic diagram of the fourth conductive layer Figure 1 ; Figure 21 Schematic diagram after the formation of the fourth conductive layer Figure 1 ; Figure 22 Schematic diagram 2 of the first conductive layer; Figure 23 Schematic diagram 2 after the formation of the first conductive layer; Figure 24 Schematic diagram 2 after the formation of the second conductive layer; Figure 25 Schematic diagram 2 for the third insulating layer; Figure 26 Schematic diagram 2 showing the formation of the third insulating layer; Figure 27 Schematic diagram 2 of the third conductive layer; Figure 28 Schematic diagram 2 after the formation of the third conductive layer; Figure 29 Schematic diagram 2 of the first flattening layer; Figure 30 Schematic diagram 2 after the formation of the first flattening layer; Figure 31 Schematic diagram 2 of the fourth conductive layer; Figure 32 This is a schematic diagram of the fourth conductive layer after its formation. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs. In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0029] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0030] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0031] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0032] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0033] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0034] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0035] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0036] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0037] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0038] The display substrate uses Low Temperature Poly-Silicon (LTPS) technology, which boasts advantages such as high resolution, fast response speed, high brightness, and high aperture ratio. Despite its market popularity, LTPS technology also has some drawbacks, such as high production costs and high power consumption. To address these issues, Low Temperature Polycrystalline Oxide (LTPO) technology emerged. Compared to LTPS, LTPO technology has lower leakage current and faster pixel response. The addition of an oxide layer to the display substrate reduces the energy required to excite the pixels, thus lowering the power consumption during screen display. However, compared to displays using LTPS, displays using LTPO require an additional driving circuit to control the metal-oxide transistors. This results in a larger bezel in LTPO displays. The longer output lines of the driving circuit, located on the bezel and providing driving signals to the display area, lead to static electricity near the output lines. Furthermore, the higher load on the output lines can cause output step issues, degrading the display effect.

[0039] Figure 1 This is a schematic diagram of the structure of a display substrate. Figure 2A Schematic diagram of the display substrate provided in the embodiments of this disclosure Figure 1 , Figure 2B Schematic diagram two of the display substrate provided in the embodiments of this disclosure. Figure 3 This is a schematic diagram of the scan output lines. Figure 4 This is a schematic diagram of the light-emitting output line. (Example) Figures 1 to 4As shown, the display substrate provided in this embodiment includes a display area AA and a non-display area AA'. The display substrate includes a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes a plurality of pixel driving circuits arranged in an array in the display area, and a light-emitting driving circuit 100, a scanning driving circuit 200, and a control driving circuit 300 located in the non-display area. The light-emitting driving circuit 100 and the scanning driving circuit 200 are located on the side of the control driving circuit 300 away from the display area. At least one pixel driving circuit includes a write transistor, a compensation reset transistor, and a light-emitting transistor. The scanning driving circuit is configured to provide a driving signal to the compensation reset transistor, the control driving circuit is configured to provide a driving signal to the write transistor, and the light-emitting driving circuit is configured to provide a driving signal to the light-emitting transistor. The display substrate also includes a plurality of light-emitting output lines EML connected to the light-emitting driving circuit 100 and a plurality of scan output lines GNL connected to the scanning driving circuit.

[0040] In this disclosure, at least one light-emitting output line includes at least two interconnected light-emitting output portions, and the scanning output line is a one-piece molded structure; alternatively, the light-emitting output line is a one-piece molded structure, and at least one scanning output line includes at least two interconnected scanning output portions; or, at least one light-emitting output line includes at least two interconnected light-emitting output portions, and at least one scanning output line includes at least two interconnected scanning output portions. Figure 2 illustrates an example where the light-emitting output line is a one-piece molded structure, and at least one scanning output line includes at least two interconnected scanning output portions. Figure 3 The following is an example of at least one light-emitting output line including at least two interconnected light-emitting output sections and at least one scan output line including at least two interconnected scan output sections.

[0041] In this disclosure, at least two light-emitting output sections located on the same light-emitting output line are arranged in different layers, and the resistivity of the light-emitting output sections arranged in different layers is different. At least two scan output sections located on the same scan output line are arranged in different layers, and the resistivity of the scan output sections arranged in different layers is different. Figure 2A , Figure 2B and Figure 3 This explanation uses an example of at least one scan output line comprising four scan output sections. Figure 2B and Figure 4 This explanation is based on the example of at least one light-emitting output line including three light-emitting output sections.

[0042] In one exemplary embodiment, the display substrate may be an LTPO display substrate or an LTPS display substrate.

[0043] In one exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be one or more of glass and metal sheets, but is not limited to; the flexible substrate may be one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers, but is not limited to.

[0044] In one exemplary embodiment, the pixel driving circuit may include: 2M rows and N columns, Figure 1 In this context, R(s) represents the pixel driving circuit of the s-th row.

[0045] In one exemplary embodiment, such as Figure 1 As shown, the positional relationship between the control driving circuit, the scanning driving circuit, and the light-emitting circuit can be determined according to the structure and function of the display substrate. For example, the control driving circuit can be located on the side of the scanning driving circuit closer to the display area, and the light-emitting circuit can be located on the side of the scanning driving circuit farther from the display area. This disclosure does not impose any limitations on this.

[0046] The light-emitting driving circuit 100 can be located on the side of the scanning driving circuit 200 away from the display area.

[0047] In one exemplary embodiment, the display area includes a first side and a second side disposed opposite to each other, the light-emitting driving circuit 100 may be located on the first side and / or the second side of the display area, the scanning driving circuit 200 may be located on the first side and / or the second side of the display area, and the control driving circuit 300 may be located on the first side and / or the second side of the display area. Figure 1 The description is based on the example of the light-emitting driving circuit 100, the scanning driving circuit 200, and the control driving circuit 300 being located on the first and second sides of the display area.

[0048] The display substrate provided in this embodiment includes a display area and a non-display area. The display substrate includes a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes a plurality of pixel driving circuits arranged in an array in the display area and a light-emitting driving circuit, a scanning driving circuit, and a control driving circuit located in the non-display area. The light-emitting driving circuit and the scanning driving circuit are located on the side of the control driving circuit away from the display area. At least one pixel driving circuit includes a write transistor, a compensation reset transistor, and a light-emitting transistor. The scanning driving circuit is configured to provide a driving signal to the compensation reset transistor, the control driving circuit is configured to provide a driving signal to the write transistor, and the light-emitting driving circuit is configured to provide a driving signal to the light-emitting transistor. The display substrate also includes a light-emitting driving circuit... The system includes multiple light-emitting output lines connected to a dynamic circuit and multiple scan output lines connected to a scan driving circuit; at least one light-emitting output line includes at least two interconnected light-emitting output portions, and the scan output lines are integrally formed, or, the light-emitting output lines are integrally formed and at least one scan output line includes at least two interconnected scan output portions, or, at least one light-emitting output line includes at least two interconnected light-emitting output portions and at least one scan output line includes at least two interconnected scan output portions; wherein, at least two light-emitting output portions located on the same light-emitting output line are disposed in different layers, and the resistivity of the differently disposed light-emitting output portions is different, and at least two scan output portions located on the same scan output line are disposed in different layers, and the resistivity of the differently disposed scan output portions is different. This disclosure reduces the resistance of the scan output lines and / or light-emitting output lines and reduces the length of the scan output lines and / or light-emitting output lines on the same film layer by making the scan output lines and / or light-emitting output lines multiple segments located in different film layers, thereby improving electrostatic problems and enhancing the display effect of the display product.

[0049] In one exemplary embodiment, the display substrate may further include: a light-emitting structure layer located on the side of the circuit structure layer away from the substrate, the light-emitting structure layer including: light-emitting elements located in the display area and arranged in an array, the light-emitting elements including: a first electrode (anode), an organic light-emitting layer and a second electrode (cathode), the anode being located on the side of the organic light-emitting layer close to the substrate, and the cathode being located on the side of the organic light-emitting layer away from the substrate; the light-emitting elements are electrically connected to the pixel driving circuit.

[0050] In one exemplary embodiment, the circuit structure layer may further include a second power line located in a non-display area, the second power line being electrically connected to the cathode of the light-emitting element.

[0051] In one exemplary embodiment, the light-emitting element may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). The OLED may include a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0052] In one exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In one exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0053] In one exemplary embodiment, Figure 5A This is a schematic diagram of an equivalent circuit for a pixel driving circuit. (Example) Figure 5A As shown, the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8), 1 capacitor C and 8 signal terminals (data signal terminal Data, control signal terminal G, scan signal terminal S, reset signal terminal Reset, light emission signal terminal E, initial signal terminal VINIT, first power supply terminal VDD and second power supply terminal VSS).

[0054] In one exemplary embodiment, the first plate of capacitor C is connected to the first power supply terminal VDD, and the second plate of capacitor C is connected to the first node N1. The control electrode of the first transistor T1 is connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is connected to the initial signal terminal Vinit, and the second electrode of the first transistor is connected to the fourth node N4. The control electrode of the second transistor T2 is connected to the control signal terminal G, the first electrode of the second transistor T2 is connected to the fourth node N4, and the second electrode of the second transistor T2 is connected to the second node N2. The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The control electrode of the fourth transistor T4 is connected to the control signal terminal G, the first electrode of the fourth transistor T4 is connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is connected to the third node N3. The control electrode of the fifth transistor T5 is connected to the light emission signal terminal E, the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is connected to the third node N3. The control electrode of the sixth transistor T6 is connected to the light-emitting signal terminal E. The first electrode of the sixth transistor T6 is connected to the second node N2, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element. The control electrode of the seventh transistor T7 is connected to the reset signal terminal Reset. The first electrode of the seventh transistor T7 is connected to the initial signal terminal Vinit. The second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is connected to the second power supply terminal VSS. The control electrode of the eighth transistor T8 is connected to the scan signal terminal S. The first electrode of the eighth transistor T8 is connected to the first node N1, and the second electrode of the eighth transistor T8 is connected to the fourth node N4.

[0055] In one exemplary embodiment, the first transistor T1 can be referred to as the reset transistor. When the reset signal terminal Reset inputs an effective level signal, the first transistor T1 transmits an initialization voltage to the first node N1 to initialize the charge of the first node N1.

[0056] In an exemplary embodiment, the eighth transistor T8 can be referred to as a compensation reset transistor. When a valid level signal is input to the scan signal terminal S, the eighth transistor T8 transmits the signal of the fourth node N4 to the first node N1. This not only initializes the charge of the first node but also performs threshold compensation on the third transistor T3.

[0057] In one exemplary embodiment, the third transistor T3 may be referred to as the driving transistor, which determines the driving current flowing between the first power supply terminal VDD and the second power supply terminal VSS based on the potential difference between the control terminal and the first terminal.

[0058] In one exemplary embodiment, the fourth transistor T4 can be referred to as the write transistor. When the control signal terminal S1 receives an effective level signal, the fourth transistor T4 causes the data voltage of the data signal terminal Data to be input to the pixel driving circuit.

[0059] In one exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an effective level signal is input to the light-emitting signal terminal E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting element to emit light by forming a drive current path between the first power supply terminal VDD and the second power supply terminal VSS.

[0060] In one exemplary embodiment, the signal at the first power supply terminal VDD is a continuously high-level signal, and the signal at the second power supply terminal VSS is a low-level signal.

[0061] In one exemplary embodiment, the eighth transistor T8 is a metal-oxide transistor and is an N-type transistor, while the first transistor T1 to the seventh transistor T7 are low-temperature polysilicon transistors and are P-type transistors.

[0062] In one exemplary embodiment, the eighth transistor T8 is an oxide transistor, which can reduce leakage current, improve the performance of the pixel driving circuit, and reduce the power consumption of the pixel driving circuit.

[0063] In one exemplary embodiment, the first power supply terminal VDD is configured to continuously provide a high-level signal, and the second power supply terminal VSS is configured to continuously provide a low-level signal.

[0064] Figure 5B This is a timing diagram of a pixel driving circuit. The following is a breakdown of the circuit's operation. Figure 5B The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 5A The pixel driving circuit includes 8 transistors (first transistor T1 to eighth transistor T8), 1 capacitor C, and 8 signal terminals (data signal terminal Data, control signal terminal G, scan signal terminal S, reset signal terminal Reset, light emission signal terminal E, initial signal terminal Vinit, first power supply terminal VDD, and second power supply terminal VSS).

[0065] In one exemplary embodiment, the operation of the pixel driving circuit may include: In the first stage, A1, also known as the reset stage, the signals at the control signal terminal G, the light-emitting signal terminal E, and the scan signal terminal S are all high-level signals, while the reset signal terminal Reset is low-level. When the Reset signal is low, the first transistor T1 is turned on, the initial signal terminal Vinit is supplied to the fourth node N4, the seventh transistor T7 is turned on, and the initial voltage of Vinit is supplied to the first terminal of the light-emitting element L, initializing (resetting) the first terminal of the light-emitting element L, clearing its internal pre-stored voltage, and ensuring that the light-emitting element L does not emit light. When the scan signal terminal S is high, the eighth transistor T8 is turned on, and the signal from the fourth node N4 is supplied to the first node N1, initializing the capacitor C and clearing the original data voltage in capacitor C. When the control signal terminal G and the light-emitting signal terminal E are high-level signals, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off. During this stage, the light-emitting element L does not emit light.

[0066] The second stage, A2, is called the data writing stage or threshold compensation stage. During this stage, the control signal G is low, while the reset signal, the light emission signal E, and the scan signal S are high. The data signal outputs a data voltage. Since the first node N1 is low, the third transistor T3 is turned on. With the control signal G low, the second transistor T2 and the fourth transistor T4 are turned on. With the scan signal S high, the eighth transistor T8 is turned on. The turn-on of the second transistor T2, the fourth transistor T4, and the eighth transistor T8 allows the data voltage output from the data signal terminal Data to be supplied to the first node N1 via the third node N3, the turned-on third transistor T3, the second node N2, the turned-on second transistor T2, the fourth node N4, and the turned-on eighth transistor T8. The difference between the data voltage output from the data signal terminal Data and the threshold voltage of the third transistor T3 is charged into capacitor C until the voltage at the first node N1 is Vd - |Vth|, where Vd is the data voltage output from the data signal terminal Data, and Vth is the threshold voltage of the third transistor T3. When the reset signal is low, transistors T1 and T7 are off. When the light emission signal is high, transistors T5 and T6 are off.

[0067] The third stage, A3, is called the light-emitting stage. Both the scan signal terminal S and the light-emitting signal terminal E are low-level signals, while the control signal terminal G and the reset signal terminal Reset are high-level signals. When the reset signal terminal Reset is low, the first transistor T1 and the seventh transistor T7 are off. When the scan signal terminal S is low, and the control signal terminal G and the reset signal terminal Reset are high, the second transistor T2, the fourth transistor T4, and the eighth transistor T8 are off. When the light-emitting signal terminal E is low, the fifth transistor T5 and the sixth transistor T6 are on. The power supply voltage output from the first power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting element L through the on-conducting fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element L to emit light.

[0068] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage at the first node N1 is Vd - |Vth|, the driving current of the third transistor T3 is: I = K (Vgs-Vth) 2 =K [(Vdd-Vd+|Vth|)-Vth] 2 =K [(Vdd-Vd) 2 Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal terminal Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0069] In one exemplary embodiment, such as Figure 1 As shown, the display substrate also includes: N data signal lines and 2M control signal lines GL1 to GL2. 2M 2M scan signal lines SL1 to SL 2M And 2M light-emitting signal lines EL1 to EL 2M .

[0070] In one exemplary embodiment, the data signal line extends along a first direction, and the N data signals are arranged along a second direction.

[0071] In one exemplary embodiment, the control signal lines extend along a second direction, and 2M control signal lines are arranged along a first direction; In one exemplary embodiment, the scan signal lines extend along a second direction, and 2M scan signal lines are arranged along a first direction.

[0072] In one exemplary embodiment, the light-emitting signal lines extend along a second direction, and 2M light-emitting signal lines are arranged along a first direction.

[0073] For the pixel driving circuit in row s and column t, the control signal terminal is electrically connected to the s-th control signal line, the scan signal terminal is electrically connected to the s-th scan signal line, the light emission signal terminal is connected to the s-th light emission signal line, and the data signal terminal is electrically connected to the t-th data signal line. s 2M, 1 t N.

[0074] In one exemplary embodiment, such as Figure 1 As shown, the light-emitting driving circuit 100 includes M cascaded light-emitting shift registers EM(1) to EM(M), with at least one stage of the light-emitting shift register electrically connected to two light-emitting signal lines. Each light-emitting shift register includes an input terminal and an output terminal. The output terminal of the i-th stage light-emitting shift register EM(i) is connected to the (2i-1)-th light-emitting signal line EL via the i-th light-emitting output line. 2i-1 Up to the 2i light-emitting signal line EL 2i Electrical connection, 1 i M.

[0075] In one exemplary embodiment, such as Figure 1 As shown, the scan drive circuit 200 includes M cascaded scan shift registers GN(1) to GN(M), with at least one scan shift register electrically connected to two scan signal lines. Each scan shift register includes an input terminal and an output terminal. The output terminal of the i-th scan shift register GN(i) is connected to the (2i-1)-th scan signal line SL via the i-th scan output line. 2i-1 Up to the 2i scan signal line SL 2i Electrical connection.

[0076] In one exemplary embodiment, such as Figure 1 As shown, the control drive circuit 300 includes 2M cascaded control shift registers GP(1) to GP(2M), with at least one stage of the control shift register electrically connected to a control signal line. Each control shift register includes an input terminal and an output terminal. The output terminal of the s-th stage control shift register GP(s) is connected to the s-th control signal line GL. s Electrical connection.

[0077] In one exemplary embodiment, such as Figure 1As shown, the circuit structure layer may include: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a first planarization layer, and a fourth conductive layer, sequentially stacked on a substrate. Wherein, when at least one light-emitting output line includes at least two interconnected light-emitting output portions, the at least two light-emitting output portions located on the same light-emitting output line are located in one of the first and second conductive layers and one of the third and fourth conductive layers; when at least one scan output line includes at least two interconnected scan output portions, the at least two scan output portions located on the same scan output line are located in one of the first and second conductive layers and one of the third and fourth conductive layers; when the light-emitting output line is an integrally formed structure, the light-emitting output line is located in the fourth conductive layer; when the scan output line is an integrally formed structure, the scan output line is located in the second conductive layer. Figure 2A and Figure 2B The circuit structure layer can be illustrated by the following example: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a first planarization layer, and a fourth conductive layer stacked sequentially on a substrate.

[0078] In one exemplary embodiment, the resistivity of both the first and second conductive layers is greater than the resistivity of both the third and fourth conductive layers. The first and second conductive layers can be made of molybdenum. The third and fourth conductive layers can be made of titanium / aluminum / titanium.

[0079] In one exemplary embodiment, when at least one light-emitting output line includes at least two interconnected light-emitting output portions, the at least two light-emitting output portions located on the same light-emitting output line may be located on the first conductive layer and the third conductive layer, or on the first conductive layer and the fourth conductive layer, or on the second conductive layer and the third conductive layer, or on the second conductive layer and the fourth conductive layer.

[0080] In one exemplary embodiment, when at least one scan output line includes at least two interconnected scan output portions, the at least two scan output portions located on the same scan output line may be located on the first conductive layer and the third conductive layer, or on the first conductive layer and the fourth conductive layer, or on the second conductive layer and the third conductive layer, or on the second conductive layer and the fourth conductive layer.

[0081] In one exemplary embodiment, the circuit structure layer may include: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a fifth conductive layer, a sixth insulating layer, a third conductive layer, a fourth insulating layer, a first planarization layer, a fourth conductive layer, a seventh insulating layer, and a sixth conductive layer, sequentially stacked on a substrate. Wherein, when at least one light-emitting output line includes at least two interconnected light-emitting output portions, the at least two light-emitting output portions located on the same light-emitting output line are located in one of the first, second, and fifth conductive layers and one of the third, fourth, and sixth conductive layers; when at least one scan output line includes at least two interconnected scan output portions, the at least two scan output portions located on the same scan output line are located in one of the first, second, and fifth conductive layers and one of the third, fourth, and sixth conductive layers; when the light-emitting output line is an integrally formed structure, the light-emitting output line is located in the fourth conductive layer; when the scan output line is an integrally formed structure, the scan output line is located in the second conductive layer.

[0082] In one exemplary embodiment, the resistivity of the first conductive layer, the resistivity of the second conductive layer, and the resistivity of the fifth conductive layer are all greater than the resistivity of the third conductive layer, the resistivity of the fourth conductive layer, and the resistivity of the sixth conductive layer. The first, second, and fifth conductive layers can be made of molybdenum. The third, fourth, and sixth conductive layers can be made of titanium / aluminum / titanium.

[0083] In one exemplary embodiment, when at least one light-emitting output line includes at least two interconnected light-emitting output portions, the at least two light-emitting output portions located on the same light-emitting output line may be located on the first conductive layer and the third conductive layer, or on the first conductive layer and the fourth conductive layer, or on the first conductive layer and the sixth conductive layer, or on the second conductive layer and the third conductive layer, or on the second conductive layer and the fourth conductive layer, or on the second conductive layer and the sixth conductive layer, or on the fifth conductive layer and the third conductive layer, or on the fifth conductive layer and the fourth conductive layer, or on the fifth conductive layer and the sixth conductive layer.

[0084] In one exemplary embodiment, when at least one scan output line includes at least two interconnected scan output portions, the at least two scan output portions located on the same scan output line may be located on the first conductive layer and the third conductive layer, or on the first conductive layer and the fourth conductive layer, or on the first conductive layer and the sixth conductive layer, or on the second conductive layer and the third conductive layer, or on the second conductive layer and the fourth conductive layer, or on the second conductive layer and the sixth conductive layer, or on the fifth conductive layer and the third conductive layer, or on the fifth conductive layer and the fourth conductive layer, or on the fifth conductive layer and the sixth conductive layer.

[0085] In one exemplary embodiment, such as Figure 2A , Figure 2B and Figure 3 As shown, when at least one scan output line includes at least two interconnected scan output sections, the scan output line GNL includes: a first scan output section GNL1, a second scan output section GNL2, a third scan output section GNL3, and a fourth scan output section GNL4 extending along a second direction.

[0086] In one exemplary embodiment, the first scan output unit GNL1 and the second scan output unit GNL2 are disposed on the same layer, the third scan output unit GNL3 and the fourth scan output unit GNL4 are disposed on the same layer, and the third scan output unit GNL3 is located on the side of the first scan output unit GNL1 away from the substrate.

[0087] In one exemplary embodiment, the third scan output unit GNL3 is located on the side of the first scan output unit GNL1 away from the display area, the fourth scan output unit GNL4 is located on the side of the first scan output unit GNL1 close to the display area, and the second scan output unit GNL2 is located on the side of the fourth scan output unit GNL4 close to the display area. The first scan output unit GNL1 is connected to the third scan output unit GNL3 and the fourth scan output unit GNL4 respectively, and the fourth scan output unit GNL4 is connected to the second scan output unit GNL2.

[0088] In one exemplary embodiment, the first scan output section GNL1 of the i-th scan output line is connected to the output terminal of the i-th stage scan shift register, the second scan output section GNL2 of the i-th scan output line is connected to the (2i-1)-th scan signal line and the 2i-th scan signal line, and the third scan output section GNL3 of the i-th scan output line is connected to the input terminal of the (i+1)-th stage scan shift register.

[0089] In one exemplary embodiment, the i-th scan output line is located between the i-th level scan shift register and the (i+1)-th level scan shift register.

[0090] In one exemplary embodiment, such as Figure 2A , Figure 2B and Figure 3 As shown, when at least one light-emitting output line includes at least two interconnected light-emitting output sections, the light-emitting output line EML includes: a first light-emitting output section EML1, a second light-emitting output section EML2, and a third light-emitting output section EML3 extending along a second direction.

[0091] In one exemplary embodiment, the second light-emitting output portion EML2 and the third light-emitting output portion EML3 are disposed in the same layer, and the third light-emitting output portion EML3 is located on the side of the first light-emitting output portion EML1 away from the substrate.

[0092] In one exemplary embodiment, the second light-emitting output unit EML2 is located on the side of the first light-emitting output unit EML1 away from the display area, and the third light-emitting output unit EML3 is located on the side of the first light-emitting output unit EML1 close to the display area. The first light-emitting output unit EML1 is connected to the second light-emitting output unit EML2 and the third light-emitting output unit EML3 respectively.

[0093] In one exemplary embodiment, the second light-emitting output section EML2 of the i-th light-emitting output line is connected to the output terminal of the i-th stage light-emitting shift register, and the third light-emitting output section EML3 of the i-th light-emitting output line is connected to the (2i-1)-th and 2i-th light-emitting signal lines.

[0094] In one exemplary embodiment, the first light-emitting output section EML1 and the third light-emitting output section EML3 of the i-th light-emitting output line are located between the 2i+1-th stage control shift register and the 2i+2-th stage control shift register.

[0095] In one exemplary embodiment, the second light-emitting output portion EML2 of the i-th light-emitting output line includes: a first output connection portion EML2A, a second output connection portion EML2B, and a third output connection portion EML2C; the first output connection portion EML2A and the third output connection portion EML2C extend along a second direction, and the second output connection portion EML2B extends along a first direction.

[0096] In one exemplary embodiment, the first output connection EML2A is located between the i-th level scan shift register and the (i+1)-th level scan shift register, and is connected to the second output connection EML2B and the output terminal of the i-th level light-emitting shift register.

[0097] In one exemplary embodiment, the second output connection EML2B is located between the i-th stage scan shift register and the (2i-1)-th stage control shift register, and is connected to the third output connection EML2C.

[0098] In one exemplary embodiment, the third output connection unit EML2C is located between the 2i+1 level control shift register and the 2i+2 level control shift register, and is connected to the 2i-1 light emission signal line and the 2i light emission signal line.

[0099] In one exemplary embodiment, the portion of the light-emitting output line input to the display area may employ a third, fourth, or sixth conductive layer with low resistivity, while the portion of the light-emitting output line input to the next stage may employ a first, second, or fifth conductive layer.

[0100] In one exemplary embodiment, the portion of the scan output line input to the display area may employ a third, fourth, or sixth conductive layer with low resistivity, while the portion of the scan output line input to the next stage may employ a first, second, or fifth conductive layer.

[0101] In one exemplary embodiment, the display substrate may further include a timing controller and a source drive circuit located in a non-display area.

[0102] In one exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the source drive circuit specifications to the source drive circuit, provide clock signals, scan start signals, etc. suitable for the scan drive circuit specifications to the scan drive circuit, provide clock signals, control start signals, etc. suitable for the control drive circuit specifications to the control drive circuit, and provide clock signals, emission stop signals, etc. suitable for the light emission drive circuit specifications to the light emission drive circuit.

[0103] In one exemplary embodiment, the source driver circuit may use grayscale values ​​and control signals received from a timing controller to generate a data voltage to be provided to the data signal line. For example, the source driver circuit may use a clock signal to sample the grayscale values ​​and apply the data voltage corresponding to the grayscale values ​​to the data signal line on a pixel-by-pixel basis.

[0104] In one exemplary embodiment, the scan drive circuit can generate signals to be provided to the scan signal lines SL1, SL2, SL3, ... and SL4 by receiving clock signals, scan start signals, etc. from a timing controller. M The scan signal. For example, a scan drive circuit can sequentially provide scan signals with on-level pulses to the scan signal lines. For example, the scan drive circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal.

[0105] In one exemplary embodiment, the control drive circuit can generate control signals to be provided to the control signal lines by receiving clock signals, control start signals, etc., from a timing controller. For example, the control drive circuit can sequentially provide control signals with on-level pulses to the control signal lines. For example, the control drive circuit can be configured as a shift register and can generate control signals by sequentially transmitting control start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal.

[0106] In one exemplary embodiment, the light-emitting driving circuit can generate a transmit signal to be provided to the light-emitting signal line by receiving a clock signal, a transmit stop signal, etc., from a timing controller. For example, the light-emitting driving circuit can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal line. For example, the light-emitting driving circuit can be configured as a shift register and can generate the light-emitting signal by sequentially transmitting the light-emitting stop signal in the form of cutoff level pulses to the next stage circuit under the control of a clock signal.

[0107] In one exemplary embodiment, the light-emitting shift register may include a plurality of light-emitting transistors and a plurality of light-emitting capacitors. The circuit structure of the light-emitting shift register may be 13T3C or 10T3C, and this disclosure does not limit it in any way.

[0108] In one exemplary embodiment, the scan shift register may include a plurality of scan transistors and a plurality of scan capacitors. The circuit structure of the scan shift register may be 14T3C, 13T3C, or 10T3C, and this disclosure does not limit it in any way.

[0109] In one exemplary embodiment, the control shift register includes a plurality of control transistors and a plurality of control capacitors. The circuit structure of the control shift register can be 8T2C, and this disclosure does not limit it in any way.

[0110] Figure 6A An equivalent circuit diagram of an emissive shift register is provided for an exemplary embodiment. Figure 6B for Figure 6A The timing diagram of the provided light-emitting shift register is shown. Figure 6A As shown, in one exemplary embodiment, the light-emitting shift register includes: a first light-emitting transistor ET1 to a thirteenth light-emitting transistor ET13 and a first light-emitting capacitor EC1 to a third light-emitting capacitor EC3.

[0111] In one exemplary embodiment, the control electrode of the first light-emitting transistor ET1 is electrically connected to the third clock signal terminal ECK3, the first electrode of the first light-emitting transistor ET1 is electrically connected to the input terminal EIN, and the second electrode of the first light-emitting transistor ET1 is electrically connected to the first node E1. The control electrode of the second light-emitting transistor ET2 is electrically connected to the first node E1, the first electrode of the second light-emitting transistor ET2 is electrically connected to the third clock signal terminal ECK3, and the second electrode of the second light-emitting transistor ET2 is electrically connected to the second node E2. The control electrode of the third light-emitting transistor ET3 is electrically connected to the third clock signal terminal ECK3, the first electrode of the third light-emitting transistor ET3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third light-emitting transistor ET3 is electrically connected to the second node E2. The control electrode of the fourth light-emitting transistor ET4 is electrically connected to the third node E3, the first electrode of the fourth light-emitting transistor ET4 is electrically connected to the first clock signal terminal ECK1, and the second electrode of the fourth light-emitting transistor ET4 is electrically connected to the fifth node E5. The control electrode of the fifth light-emitting transistor ET5 is electrically connected to the fourth node E4, the first electrode of the fifth light-emitting transistor ET5 is electrically connected to the fifth node E5, and the second electrode of the fifth light-emitting transistor ET5 is electrically connected to the first power supply terminal VGH. The control electrode of the sixth LED ET6 is electrically connected to the fourth node E4, the first electrode of the sixth LED ET6 is electrically connected to the first clock signal terminal ECK1, and the second electrode of the sixth LED ET6 is electrically connected to the sixth node E6. The control electrode of the seventh LED ET7 is electrically connected to the first clock signal terminal ECK1, the first electrode of the seventh LED ET7 is electrically connected to the sixth node E6, and the second electrode of the seventh LED ET7 is electrically connected to the seventh node E7. The control electrode of the eighth LED ET8 is electrically connected to the first node E1, the first electrode of the eighth LED ET8 is electrically connected to the first power supply terminal VGH, and the second electrode of the eighth LED ET8 is electrically connected to the seventh node E7. The control electrode of the ninth LED ET9 is electrically connected to the seventh node E7, the first electrode of the ninth LED ET9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth LED ET9 is electrically connected to the output terminal EOUT. The control electrode of the tenth LED ET10 is electrically connected to the third node E3, the first electrode of the tenth LED ET10 is electrically connected to the second power supply terminal VGL, and the second electrode of the tenth LED ET10 is electrically connected to the output terminal EOUT. The control terminal of the eleventh LED ET11 is electrically connected to the second power supply terminal VGL. The first terminal of the eleventh LED ET11 is electrically connected to the second node E2, and the second terminal of the eleventh LED ET11 is electrically connected to the fourth node E4. The control terminal of the twelfth LED ET12 is electrically connected to the second power supply terminal VGL. The first terminal of the twelfth LED ET12 is electrically connected to the first node E1, and the second terminal of the twelfth LED ET12 is electrically connected to the third node E3.The control electrode of the thirteenth LED ET13 is electrically connected to the second clock signal terminal ECK2. The first electrode of the thirteenth LED ET13 is electrically connected to the first node E1, and the second electrode of the thirteenth LED ET13 is electrically connected to the first power supply terminal VGH. The first plate EC11 of the first LED capacitor EC1 is electrically connected to the fourth node E4, and the second plate EC12 of the first LED capacitor EC1 is electrically connected to the sixth node E6. The first plate EC21 of the second LED capacitor EC2 is electrically connected to the seventh node E7, and the second plate EC22 of the second LED capacitor EC2 is electrically connected to the first power supply terminal VGH. The first plate EC31 of the third LED capacitor EC3 is electrically connected to the third node E3, and the second plate EC32 of the third LED capacitor EC3 is electrically connected to the fifth node E5.

[0112] In one exemplary embodiment, the first light-emitting transistor ET1 to the thirteenth light-emitting transistor ET13 can be either P-type transistors or N-type transistors.

[0113] In one exemplary embodiment, the first power supply terminal VGH continuously provides a high-level signal, and the second power supply terminal VGL continuously provides a low-level signal. Because the second power supply terminal VGL continuously provides a low-level signal, the eleventh light-emitting transistor ET11 and the twelfth light-emitting transistor ET12 are continuously turned on.

[0114] In one exemplary embodiment, the second clock signal terminal ECK2 is a low-level signal during the power-on initialization phase to prevent the ninth and tenth LEDs ET9 and ET10 of the last-stage LED shift register from conducting simultaneously due to output signal delay, or it is a low-level signal during the abnormal power-off phase to prevent the ninth and tenth LEDs ET9 and ET10 from conducting simultaneously. The second clock signal terminal ECK2 continuously provides a high-level signal during the normal display phase, meaning that the thirteenth LED ET13 remains continuously off during the normal display phase.

[0115] Taking the first light-emitting transistor ET1 to the thirteenth light-emitting transistor ET13 as P-type transistors as an example, such as Figure 6B As shown, the operation of an exemplary embodiment of the light-emitting shift register includes the following stages: In the first stage B1, the signal at the first clock signal terminal ECK1 is a high-level signal, and the signal at the third clock signal terminal ECK3 is a low-level signal. When the signal at the third clock signal terminal ECK3 is low, the first LED ET1, the third LED ET3, and the twelfth LED ET12 are turned on. The turned-on first LED ET1 transmits the high-level signal at its input terminal EIN to the first node E1, thus making the level of the first node E1 high. The turned-on twelfth LED ET12 transmits the high-level signal from the first node E1 to the third node E2, while the second LED ET2, the fourth LED ET4, the eighth LED ET8, and the tenth LED ET10 are turned off. Meanwhile, the turned-on third LED ET3 transmits the low-level signal at the third power supply terminal VGL to the second node E2, thus making the level of the second node E2 low. The turned-on eleventh LED ET11 transmits the low-level signal from the second node E2 to the fourth node E4, thus making the level of the fourth node E4 low. The fifth LED ET5 and the sixth LED ET6 are turned on. The first clock signal ECK1 is high, and the seventh LED ET7 is off. Additionally, due to the action of the third LED capacitor EC3, the ninth LED ET9 is off. In the first stage P1, since both the ninth and tenth LEDs ET9 and ET10 are off, the output EOUT signal remains at its previous low level.

[0116] In the second stage B2, the first clock signal terminal ECK1 is at a low level, and the third clock signal terminal ECK3 is at a high level. With the first clock signal terminal ECK1 at a low level, the seventh LED ET7 is turned on. With the third clock signal terminal ECK3 at a high level, the first LED ET1 and the third LED ET3 are turned off. Under the influence of the third LED capacitor EC3, the first node E1 and the third node E3 can maintain the high level signal from the previous stage. Under the influence of the first LED capacitor EC1, the fourth node E4 can maintain the low level from the previous stage, so the fifth LED ET5 and the sixth LED ET6 are turned on. The second LED ET2, the fourth LED ET4, the eighth LED ET8, and the tenth LED ET10 are turned off. In addition, the low-level signal of the first clock signal terminal ECK1 is transmitted to the seventh node E7 through the sixth light-emitting transistor ET6 and the seventh light-emitting transistor ET7, and the ninth light-emitting transistor ET9 is turned on. The turned-on ninth light-emitting transistor ET9 outputs the high-level signal of the first power supply terminal VGH, so the signal of the output terminal EOUT is a high-level signal.

[0117] In stage B3, the signal at the third clock signal terminal ECK3 is low, and the signal at the first clock signal terminal ECK1 is high. With the first clock signal terminal ECK1 high, the seventh LED ET7 is turned off. The second LED ET2, fourth LED ET4, eighth LED ET8, and tenth LED ET10 are also turned off. With the third clock signal terminal ECK3 low, the first LED ET1 and the third LED ET3 are turned on. Under the influence of the second LED capacitor EC3, the ninth LED ET9 remains on, outputting a high-level signal from the first power supply terminal VGH. Therefore, the signal at the output terminal EOUT remains high.

[0118] In stage B4, the first clock signal ECK1 is low, and the third clock signal ECK3 is high. With ECK3 high, the first and third LEDs ET1 and ET3 are turned off. With ECK1 low, the seventh LED ET7 is turned on. Due to the storage function of the third LED capacitor EC3, the levels of nodes E1 and E3 remain high from the previous stage, thus turning off the second, fourth, eighth, and tenth LEDs ET2, ET4, ET8, and ET10. Due to the storage function of the first LED capacitor EC1, node E4 remains low from the previous stage, thus turning on the fifth and sixth LEDs ET5 and ET6. In addition, the low-level signal of the first clock signal terminal ECK1 is transmitted to the seventh node E7 through the sixth light-emitting transistor ET6 and the seventh light-emitting transistor ET7, and the ninth light-emitting transistor ET9 outputs the high-level signal of the first power supply terminal VGH, so the signal of the output terminal EOUT is still a high-level signal.

[0119] In stage B5, the signal at the first clock signal terminal ECK1 is high, and the signal at the third clock signal terminal ECK3 is low. When the signal at the third clock signal terminal ECK3 is low, the first LED ET1 and the third LED ET3 are turned on. When the signal at the first clock signal terminal ECK1 is high, the seventh LED ET7 is turned off. The turned-on first LED ET1 transmits the low-level signal at the input terminal EIN to the first node E1, thus making the level of the first node E1 low. The turned-on twelfth LED ET12 transmits the low-level signal from the first node E1 to the third node E3, thus making the level of the third node E3 low. The second LED ET2, the fourth LED ET4, the eighth LED ET8, and the tenth LED ET10 are turned on. The second LED, ET2, transmits the low-level signal from the third clock signal terminal, ECK3, to the second node, E2, further pulling down the level of E2. Therefore, nodes E2 and E4 remain at the low level of the previous stage, turning on the fifth and sixth LEDs, ET5 and ET6. The first clock signal terminal, ECK1, is high, and the seventh LED, ET7, is turned off. Additionally, the eighth LED, ET8, transmits the high-level signal from the first power supply terminal, VGH, to the seventh node, E7, turning off the ninth LED, ET9. The tenth LED, ET10, outputs the low-level signal from the second power supply terminal, VGL, causing the output terminal, EOUT, to go low.

[0120] In one exemplary embodiment, the display substrate may further include: an initial light-emitting signal line extending along a first direction, a first light-emitting clock signal line to a third light-emitting clock signal line, a first high-level power supply line, and a first low-level power supply line. The input terminal of the first-stage light-emitting shift register is electrically connected to the initial light-emitting signal line, and the output terminal of the i-th-stage light-emitting shift register is electrically connected to the input terminal of the (i+1)-th stage light-emitting shift register. The first clock signal terminal of the i-th-stage light-emitting shift register is electrically connected to the first light-emitting clock signal line, the second clock signal terminal is electrically connected to the second light-emitting clock signal line, and the third clock signal terminal is electrically connected to the third light-emitting clock signal line. The first clock signal terminal of the (i+1)-th stage light-emitting shift register is electrically connected to the third light-emitting clock signal line, the second clock signal terminal is electrically connected to the second light-emitting clock signal line, and the third clock signal terminal is electrically connected to the first light-emitting clock signal line. The first power supply terminal of the i-th-stage light-emitting shift register is electrically connected to the first high-level power supply line, and the second power supply terminal of the i-th-stage light-emitting shift register is electrically connected to the first low-level power supply line.

[0121] Figure 7A An equivalent circuit diagram of a scan shift register is provided for an exemplary embodiment. Figure 7Bfor Figure 7A The timing diagram for the provided scan shift register is shown. Figure 7A As shown, in one exemplary embodiment, the scan shift register includes: a first scan transistor ST1 to a fourteenth scan transistor ST14 and a first scan capacitor SC1 to a third scan capacitor SC3.

[0122] In one exemplary embodiment, the control electrode of the first scanning transistor ST1 is electrically connected to the third clock signal terminal SCK3, the first electrode of the first scanning transistor ST1 is electrically connected to the input terminal SIN, and the second electrode of the first scanning transistor ST1 is electrically connected to the first node S1. The control electrode of the second scanning transistor ST2 is electrically connected to the first node S1, the first electrode of the second scanning transistor ST2 is electrically connected to the third clock signal terminal SCK3, and the second electrode of the second scanning transistor ST2 is electrically connected to the second node S2. The control electrode of the third scanning transistor ST3 is electrically connected to the third clock signal terminal SCK3, the first electrode of the third scanning transistor ST3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third scanning transistor ST3 is electrically connected to the second node S2. The control electrode of the fourth scanning transistor ST4 is electrically connected to the third node S3, the first electrode of the fourth scanning transistor ST4 is electrically connected to the first clock signal terminal SCK1, and the second electrode of the fourth scanning transistor ST4 is electrically connected to the second plate SC32 of the third scanning capacitor. The control electrode and the first electrode of the fifth scanning transistor ST5 are electrically connected to the third node S3, and the second electrode of the fifth scanning transistor ST5 is electrically connected to the fifth node S5. The control electrode of the sixth scanning transistor ST6 is electrically connected to the fourth node S4, the first electrode of the sixth scanning transistor ST6 is electrically connected to the first clock signal terminal SCK1, and the second electrode of the sixth scanning transistor ST6 is electrically connected to the sixth node S6. The control electrode of the seventh scanning transistor ST7 is electrically connected to the first clock signal terminal SCK1, the first electrode of the seventh scanning transistor ST7 is electrically connected to the sixth node S6, and the second electrode of the seventh scanning transistor ST7 is electrically connected to the seventh node S7. The control electrode of the eighth scanning transistor ST8 is electrically connected to the first node S1, the first electrode of the eighth scanning transistor ST8 is electrically connected to the first power supply terminal VGH, and the second electrode of the eighth scanning transistor ST8 is electrically connected to the seventh node S7. The control electrode of the ninth scanning transistor ST9 is electrically connected to the seventh node S7, the first electrode of the ninth scanning transistor ST9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth scanning transistor ST9 is electrically connected to the output terminal SOUT. The control electrode of the tenth scanning transistor ST10 is electrically connected to the fifth node S5, the first electrode of the tenth scanning transistor ST10 is electrically connected to the second power supply terminal VGL, and the second electrode of the tenth scanning transistor ST10 is electrically connected to the output terminal SOUT.The control electrode of the eleventh scanning transistor ST11 is electrically connected to the second power supply terminal VGL. The control electrode of the eleventh scanning transistor ST11 is also connected to the sixth node S6. The first electrode of the eleventh scanning transistor ST11 is electrically connected to the first power supply terminal VGH. The second electrode of the eleventh scanning transistor ST11 is electrically connected to the fifth node S5. The control electrode of the twelfth scanning transistor ST12 is connected to the second clock signal terminal SCK2. The first electrode of the twelfth scanning transistor ST12 is electrically connected to the first power supply terminal VGH. The second electrode of the twelfth scanning transistor ST12 is electrically connected to the fifth node S5. The control electrode of the thirteenth scanning transistor ST13 is electrically connected to the second power supply terminal VGL. The first electrode of the thirteenth scanning transistor ST13 is electrically connected to the first node S1. The second electrode of the thirteenth scanning transistor ST13 is electrically connected to the third node S3. The control electrode of the fourteenth scanning transistor ST14 is electrically connected to the second power supply terminal VGL. The first electrode of the fourteenth scanning transistor ST14 is electrically connected to the second node S2. The second electrode of the fourteenth scanning transistor ST14 is electrically connected to the fourth node S4. The first plate SC11 of the first scanning capacitor SC1 is electrically connected to the fourth node S4, and the second plate SC12 of the first scanning capacitor SC1 is electrically connected to the sixth node S6. The first plate SC21 of the second scanning capacitor SC2 is electrically connected to the seventh node S7, and the second plate SC22 of the second scanning capacitor SC2 is electrically connected to the first power supply terminal VGH. The first plate SC31 of the third scanning capacitor SC3 is electrically connected to the third node S3.

[0123] In one exemplary embodiment, the first scanning transistor ST1 to the thirteenth scanning transistor ST13 can be either P-type transistors or N-type transistors. The tenth scanning transistor ST10 is an output transistor.

[0124] In one exemplary embodiment, the first power supply terminal VGH continuously provides a high-level signal, and the second power supply terminal VGL continuously provides a low-level signal. Because the second power supply terminal VGL continuously provides a low-level signal, the thirteenth scan transistor ST13 and the fourteenth scan transistor ST14 are continuously turned on.

[0125] In one exemplary embodiment, the second clock signal terminal SCK2 is a low-level signal during the power-on initialization phase to prevent the ninth and tenth scan transistors ST9 and ST10 of the last-stage scan shift register from conducting simultaneously due to output signal delays, or it is a low-level signal during the abnormal power-off phase to prevent the ninth and tenth scan transistors ST9 and ST10 from conducting simultaneously. The second clock signal terminal SCK2 continuously provides a high-level signal during the normal display phase, meaning that the thirteenth scan transistor ST13 remains continuously off during the normal display phase.

[0126] Taking the first scanning transistor ST1 to the fourteenth scanning transistor ST14 as P-type transistors as an example, Figure 7B As shown, the operation of a scan shift register provided in an exemplary embodiment includes the following stages: In the first stage C1, the signal at the first clock signal terminal SCK1 is high, and the signal at the third clock signal terminal SCK3 is low. With the third clock signal terminal SCK3 low, the first scanning transistor ST1 and the third scanning transistor ST3 are turned on. The turned-on first scanning transistor ST1 transmits the high-level signal at the input terminal SIN to the first node S1, thus making the level of the first node S1 high. The turned-on thirteenth scanning transistor ST13 transmits the high-level signal from the first node S1 to the third node S2. The second scanning transistor ST2, the fourth scanning transistor ST4, the fifth scanning transistor ST5, and the eighth scanning transistor ST8 are turned off. Meanwhile, the turned-on third scanning transistor ST3 transmits the low-level signal at the second power supply terminal VGL to the second node S2, thus making the level of the second node S2 low. The turned-on fourteenth scanning transistor ST14 transmits the low-level signal from the second node S2 to the fourth node S4, thus making the level of the fourth node S4 low. The sixth scanning transistor ST6 is turned on. The first clock signal line SCK1 is high, and the seventh scan transistor ST7 and the eleventh scan transistor ST11 are turned off. Additionally, under the influence of the second scan capacitor SC2, the ninth scan transistor ST9 is turned off. In the first stage C1, since both the ninth scan transistor ST9 and the tenth scan transistor ST10 are turned off, the output SOUT signal remains at its previous low level.

[0127] In the second stage C2, the signal at the first clock signal terminal SCK1 is low, and the signal at the third clock signal terminal SCK3 is high. With the first clock signal terminal SCK1 low, the seventh scanning transistor ST7 is turned on. With the third clock signal terminal SCK3 high, the first scanning transistor ST1 and the third scanning transistor ST3 are turned off. Under the influence of the third scanning capacitor SC3, the first node S1 and the third node S3 can maintain the high level signal from the previous stage, and under the influence of the first scanning capacitor SC1, the fourth node S4 can maintain the low level signal from the previous stage, turning on the sixth scanning transistor ST6. The second scanning transistor ST2, the fourth scanning transistor ST4, the fifth scanning transistor ST5, and the eighth scanning transistor ST8 are turned off. In addition, the low-level signal of the first clock signal terminal SCK1 is transmitted to the seventh node S7 through the sixth scanning transistor ST6 and the seventh scanning transistor ST7, which are turned on. The ninth scanning transistor ST9 and the eleventh scanning transistor ST11 are turned on, and the high-level signal of the first power supply terminal VGH is transmitted to the fifth node S5. The tenth scanning transistor ST10 is turned off, and the turned-on ninth scanning transistor ST9 outputs the high-level signal of the first power supply terminal VGH. Therefore, the signal of the output terminal SOUT is a high-level signal.

[0128] In the third stage C3, the signal at the third clock signal terminal SCK3 is low, and the signal at the first clock signal terminal SCK1 is high. With the first clock signal terminal SCK1 high, the seventh scanning transistor ST7 is turned off. Under the action of the first scanning capacitor SC1, the fourth node S4 remains low, the sixth scanning transistor ST6 is turned on, and the high-level signal from the first clock signal terminal SCK1 is transmitted to the sixth node S6, turning off the eleventh scanning transistor ST11. With the third clock signal terminal SCK3 low, the first scanning transistor ST1 and the third scanning transistor ST3 are turned on. The turned-on first scanning transistor ST1 transmits the high-level signal from its input terminal SIN to the first node S1, making the level of the first node S1 high. The turned-on thirteenth scanning transistor ST13 transmits the high-level signal from the first node S1 to the third node S2, turning off the second scanning transistor ST2, the fourth scanning transistor ST4, the fifth scanning transistor ST5, and the eighth scanning transistor ST8. Under the action of the third scanning capacitor SC3, the ninth scanning transistor ST9 remains in the conducting state. The conducting ninth scanning transistor ST9 outputs a high-level signal from the first power supply terminal VGH, so the signal at the output terminal SOUT is still a high-level signal.

[0129] In the fourth stage C4, the signal at the first clock signal terminal SCK1 is low, and the signal at the third clock signal terminal SCK3 is high. With the third clock signal terminal SCK3 high, the first scanning transistor ST1 and the third scanning transistor ST3 are cut off. With the first clock signal terminal SCK1 low, the seventh scanning transistor ST7 is turned on. Due to the storage effect of the third scanning capacitor SC3, the levels at the first node S1 and the third node S3 remain high from the previous stage, thus turning off scanning transistors ST2, ST4, ST5, and ST8. Due to the storage effect of the first scanning capacitor SC1, the fourth node S4 continues to remain low from the previous stage, thus turning on the sixth scanning transistor ST6. In addition, the low-level signal of the first clock signal terminal SCK1 is transmitted to the seventh node S7 through the sixth scanning transistor ST6 and the seventh scanning transistor ST7. The ninth scanning transistor ST9 and the eleventh scanning transistor ST11 are turned on, the high-level signal of the first power supply terminal VGH is transmitted to the fifth node S5, the tenth scanning transistor ST10 is turned off, and the turned-on ninth scanning transistor ST9 outputs the high-level signal of the first power supply terminal VGH. Therefore, the signal of the output terminal SOUT is still a high-level signal.

[0130] In stage C5, the signal at the first clock signal terminal SCK1 is high, and the signal at the third clock signal terminal SCK3 is low. When the signal at the third clock signal terminal SCK3 is low, the first scanning transistor ST1 and the third scanning transistor ST3 are turned on. When the signal at the first clock signal terminal SCK1 is high, the seventh scanning transistor ST7 is turned off. The turned-on first scanning transistor ST1 transmits the low-level signal at the input terminal SIN to the first node S1, thus making the level of the first node S1 low. The turned-on twelfth scanning transistor ST12 transmits the low-level signal from the first node S1 to the third node S3, thus making the level of the third node S3 low. The second scanning transistor ST2, the fourth scanning transistor ST4, the fifth scanning transistor ST5, the eighth scanning transistor ST8, and the tenth scanning transistor ST10 are turned on. The conducting second scanning transistor ST2 transmits the low-level signal from the third clock signal terminal SCK3 to the second node S2, further pulling down the level of the second node S2. Therefore, the second node S2 and the fourth node S4 continue to maintain the low level of the previous stage, thus turning on the sixth scanning transistor ST6. The signal at the first clock signal terminal SCK1 is a high-level signal, and the seventh scanning transistor ST7 is turned off. In addition, the conducting eighth scanning transistor ST8 transmits the high-level signal from the first power supply terminal VGH to the seventh node S7, and the ninth scanning transistor ST9 is turned off. The conducting tenth scanning transistor ST10 outputs the low-level signal from the second power supply terminal VGL, so the signal at the output terminal SOUT becomes low.

[0131] In one exemplary embodiment, the display substrate may further include: a scan initial signal line extending along a first direction, a first scan clock signal line to a third scan clock signal line, a second high-level power supply line, and a second low-level power supply line. Specifically, there are two first scan clock signal lines and two third scan clock signal lines.

[0132] The input terminal of the first-stage scan shift register is electrically connected to the scan initial signal line. The output terminal of the i-th-stage scan shift register is electrically connected to the input terminal of the (i+1)-th-stage scan shift register. The first clock signal terminal of the i-th-stage scan shift register is electrically connected to the first scan clock signal line. The second clock signal terminal is electrically connected to the second scan clock signal line. The third clock signal terminal is electrically connected to the third scan clock signal line. The first power supply terminal of the i-th-stage scan shift register is electrically connected to the second high-level power supply line. The second power supply terminal of the i-th-stage scan shift register is electrically connected to the second low-level power supply line.

[0133] Figure 8A An equivalent circuit diagram of a control shift register is provided for an exemplary embodiment. Figure 8B for Figure 8AThe timing diagram for the control shift register is provided. (Example:) Figure 8A As shown, the control shift register includes: first control transistors GT1 to eighth control transistors GT8, first control capacitor GC1, and second control capacitor GC2.

[0134] In one exemplary embodiment, the control electrode of the first control transistor GT1 is electrically connected to the first clock signal terminal CK, the first terminal of the first control transistor GT1 is electrically connected to the input terminal GIN, and the second terminal of the first control transistor GT1 is electrically connected to the first node G1; the control electrode of the second control transistor GT2 is electrically connected to the first node G1, the first terminal of the second control transistor GT2 is electrically connected to the first clock signal terminal CK, and the second terminal of the second control transistor GT2 is electrically connected to the second node G2; the control electrode of the third control transistor GT3 is electrically connected to the first clock signal terminal GCK1, the first terminal of the third control transistor GT3 is electrically connected to the second power supply terminal VGL, and the second terminal of the third control transistor GT3 is electrically connected to the second node G2; the control electrode of the fourth control transistor GT4 is electrically connected to the second node G2, the first terminal of the fourth control transistor GT4 is electrically connected to the first power supply terminal VGH, and the second terminal of the fourth control transistor GT4 is electrically connected to the output terminal GOUT; the control electrode of the fifth control transistor GT5 is electrically connected to the third node G3, and the first terminal of the fifth control transistor GT5 is electrically connected to the second clock signal terminal CK. Terminal GCK2 is electrically connected; the second terminal of the fifth control transistor GT5 is electrically connected to the output terminal GOUT; the control terminal of the sixth control transistor GT6 is electrically connected to the second node G2; the first terminal of the sixth control transistor GT6 is electrically connected to the first power supply terminal VGH; the second terminal of the sixth control transistor GT6 is electrically connected to the first terminal of the seventh control transistor GT7; the control terminal of the seventh control transistor GT7 is electrically connected to the second clock signal terminal GCK2; the second terminal of the seventh control transistor GT7 is electrically connected to the first node G1; the control terminal of the eighth control transistor GT8 is electrically connected to the second power supply terminal VGL; the first terminal of the eighth control transistor GT8 is electrically connected to the first node G1; the second terminal of the eighth control transistor GT8 is electrically connected to the third node G3; the first plate GC11 of the first control capacitor GC1 is electrically connected to the first power supply terminal VGH; the second plate GC12 of the first control capacitor GC1 is electrically connected to the second node G2; the first plate GC21 of the second control capacitor GC2 is electrically connected to the output terminal GOUT; the second plate GC22 of the second control capacitor GC2 is electrically connected to the third node G3.

[0135] In one exemplary embodiment, the first control transistor GT1 to the eighth control transistor GT8 can be either a P-type transistor or an N-type transistor.

[0136] In one exemplary embodiment, the first power supply terminal VGH continuously provides a high-level signal, and the second power supply terminal VGL continuously provides a low-level signal.

[0137] Taking the first control transistor GT1 to the eighth control transistor GT8 as P-type transistors as an example, Figure 8B As shown, the operation of the control shift register provided by an exemplary embodiment includes the following stages: During input phase D1, the signals at the first clock signal terminal GCK1 and the input terminal GIN are low-level signals, while the signal at the second clock signal terminal GCK2 is high-level. Since the signal at the first clock signal terminal GCK1 is low, the first control transistor GT1 is turned on, and the signal at the input terminal GIN is transmitted to the first node G1 via the first control transistor GT1. Because the signal at the eighth control transistor GT8 receives the low-level signal at the second power supply terminal VGL, the eighth control transistor GT8 is in the on state. The level of the third node G3 can control the fifth control transistor GT5 to turn on, and the signal at the second clock signal terminal GCK2 is transmitted to the output terminal GOUT via the fifth control transistor GT5. That is, during input phase D1, the output terminal GOUT is the signal at the second clock signal terminal GCK2, which is high. Additionally, since the signal at the first clock signal terminal GCK1 is low, the third control transistor GT3 is turned on, and the low-level signal at the second power supply terminal VGL is transmitted to the second node G2 via the third control transistor GT3. At this time, both the fourth control transistor GT4 and the sixth control transistor GT6 are turned on. Since the signal at the second clock signal terminal GCK2 is a high-level signal, the seventh control transistor GT7 is turned off.

[0138] In output stage D2, the signal at the first clock signal terminal GCK1 is high, the signal at the second clock signal terminal GCK2 is low, and the signal at the input terminal GIN is high. The fifth control transistor GT5 is turned on, and the signal at the second clock signal terminal GCK2 is used as the signal at the output terminal GOUT via the fifth control transistor GT5. In output stage D2, the level at one end of the second control capacitor GC2 connected to the output terminal OUT becomes the signal at the second power supply terminal VGL. Due to the bootstrap effect of the second control capacitor GC2, the eighth control transistor GT8 is turned off, allowing the fifth control transistor GT5 to be turned on more effectively, resulting in a low signal at the output terminal GOUT. Additionally, the signal at the first clock signal terminal GCK1 is high, thus turning off both the first control transistor GT1 and the third control transistor GT3. The second control transistor GT2 is turned on, and the high-level signal at the first clock signal terminal GCK1 is transmitted to the second node G2 via the second control transistor GT2, thereby turning off both the fourth control transistor GT4 and the sixth control transistor GT6. Since the signal at the second clock signal terminal GCK2 is low, the seventh control transistor GT7 is turned on.

[0139] During buffer phase D3, both the first clock signal terminal GCK1 and the second clock signal terminal GCK2 are high-level signals, and the input terminal GIN is also high-level. The fifth control transistor GT5 is turned on, and the second clock signal terminal GCK2 is used as the output signal GOUT via the fifth control transistor GT5. Due to the bootstrap effect of the second control capacitor C2, the level of the first node G1 becomes VGL-VthN1. Furthermore, the first clock signal terminal GCK1 is high-level, thus the first control transistor GT1 and the third control transistor GT3 are both turned off, the eighth control transistor GT8 is turned on, and the second control transistor GT2 is turned on. The high-level signal of the first clock signal terminal GCK1 is transmitted to the second node G2 via the second control transistor GT2, thereby turning off the fourth control transistor GT4 and the sixth control transistor GT6. Since the second clock signal terminal GCK2 is high-level, the seventh control transistor GT7 is turned off.

[0140] In the first sub-stage D41 of the stable phase D4, the signal at the first clock signal terminal GCK1 is low, while the signals at the second clock signal terminal GCK2 and the input terminal GIN are high. Because the signal at the first clock signal terminal GCK1 is low, the first control transistor GT1 is turned on, and the signal at the input terminal GIN is transmitted to the first node G1 via the first control transistor GT1. The second control transistor GT2 is turned off. Because the eighth control transistor GT8 is on, the fifth control transistor GT5 is turned off. Because the signal at the first clock signal terminal GCK1 is low, the third control transistor GT3 is turned on, and both the fourth and sixth control transistors GT4 and GT6 are turned on. The high-level signal at the first power supply terminal VGH is transmitted to the output terminal GOUT via the fourth control transistor GT4, meaning the signal at the output terminal GOUT is high.

[0141] In the second sub-stage D42 of the stable phase D4, the signal at the first clock signal terminal GCK1 is high, the signal at the second clock signal terminal GCK2 is low, and the signal at the input terminal GIN is high. The fifth control transistor GT5 and the second control transistor GT2 are both off. Because the signal at the first clock signal terminal GCK1 is high, the first control transistor GT1 and the third control transistor GT3 are both off. Due to the holding effect of the first control capacitor GC1, the fourth control transistor GT4 and the sixth control transistor GT6 are both on. The high-level signal is transmitted to the output terminal GOUT via the fourth control transistor GT4, meaning the signal at the output terminal GOUT is high.

[0142] In the second sub-stage D42, since the signal at the second clock signal terminal GCK2 is a low-level signal, the seventh control transistor GT7 is turned on, so that the high-level signal is transmitted to the third node G3 and the first node G1 via the sixth control transistor GT6 and the seventh control transistor GT7, so that the signals of the third node G3 and the first node G1 remain high-level signals.

[0143] In the third sub-stage D43, both the first clock signal terminal GCK1 and the second clock signal GCK2 are high-level signals, and the input terminal GIN is also high-level. The fifth control transistor GT5 and the second control transistor GT2 are off. Because the first clock signal terminal GCK1 is high-level, both the first control transistor GT1 and the third control transistor GT3 are off, while the fourth control transistor GT4 and the sixth control transistor GT6 are on. The high-level signal is transmitted to the output terminal GOUT via the fourth control transistor GT4, meaning the output terminal GOUT is high-level.

[0144] In one exemplary embodiment, the display substrate may further include: a control initial signal line, a first control clock signal line, a second control clock signal line, a third high-level power supply line, and a third low-level power supply line extending along a first direction.

[0145] The input terminal of the first-stage control shift register is electrically connected to the control initial signal line, and the output terminal of the j-th stage control shift register is electrically connected to the input terminal of the (j+1)-th stage control shift register. The first clock signal terminal of the j-th stage control shift register is electrically connected to the first control clock signal line, and the second clock signal terminal is electrically connected to the second control clock signal line. The first clock signal terminal of the (j+1)-th stage control shift register is electrically connected to the second control clock signal line, and the second clock signal terminal is electrically connected to the first control clock signal line. The first power supply terminal of the j-th stage control shift register is electrically connected to the third high-level power supply line, and the second power supply terminal of the j-th stage control shift register is electrically connected to the third low-level power supply line.

[0146] In one exemplary embodiment, the boundary of the display area AA includes at least one arcuate boundary. In another exemplary embodiment, the shape of the boundary of the display area may be a rounded rectangle.

[0147] The display substrate provided in this disclosure can achieve large-angle bending on all four sides, which improves the problem of wrinkles in module bonding and increases product yield.

[0148] In one exemplary embodiment, the display substrate may also include other film layers, such as spacers, etc., which are not limited herein.

[0149] The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made by depositing, coating, or other processes onto a substrate using a certain material. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0150] The following describes an exemplary embodiment of a display substrate provided, using the example of a display substrate fabrication process comprising a first scan output section to a fourth scan output section and a circuit structure layer comprising four conductive layers.

[0151] (1) Forming a semiconductor layer on a substrate includes: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film using a patterning process to form a semiconductor layer. For example... Figure 9 As shown, Figure 9 This is a schematic diagram after the semiconductor layer has been formed.

[0152] In one exemplary embodiment, the semiconductor layer includes: the active layer ET11 of the first light-emitting transistor to the active layer ET131 of the thirteenth light-emitting transistor, the active layer ST11 of the first scanning transistor to the active layer ST141 of the fourteenth scanning transistor, and the active layer GT11 of the first control transistor to the active layer GT81 of the eighth control transistor.

[0153] In one exemplary embodiment, the active layers ET11, ET21, ET31, ET51, ET71, ET81, ET91, ET101, ET11, and ET121 of the first, second, third, and eleventh light-emitting transistors (LEDs) extend along a first direction, while the active layers ET41, ET61, and ET131 of the fourth, sixth, and thirteenth LEDs extend along a second direction. Specifically, the active layers ET91 and ET101 of the ninth and tenth LEDs are integrally formed structures, as are the active layers ET41, ET51, ET81, and ET131 of the fourth, fifth, eighth, and thirteenth LEDs.

[0154] In one exemplary embodiment, the active layers ST11, ST21, ST31, ST51, ST71, ST81, ST91, ST91, ST101, ST111, ST121, ST131, and ST141 of the first and eleventh scanning transistors extend along a first direction, while the active layers ST41 and ST61 of the fourth and sixth scanning transistors extend along a second direction. Among them, the active layer ST81 of the eighth scanning transistor, the active layer ST111 of the eleventh scanning transistor, and the active layer ST121 of the twelfth scanning transistor are integrally formed structures, and the active layer ST91 of the ninth scanning transistor and the active layer ST101 of the tenth scanning transistor are integrally formed structures.

[0155] In one exemplary embodiment, the active layers GT21, GT31, GT61, GT71, and GT81 of the second control transistor, the third control transistor, and the sixth control transistor extend along a first direction, while the active layer GT11 of the first control transistor extends along a second direction. The active layers GT21 and GT31 of the second and third control transistors are integrally formed structures, as are the active layers GT61, GT71, GT41, and GT51 of the fourth and fifth control transistors.

[0156] (2) Forming a first conductive layer includes: depositing a second insulating film on a substrate on which an active layer is formed; patterning the second insulating film using a patterning process to form a first insulating layer; depositing a first conductive film on the first insulating layer; and patterning the first conductive film using a patterning process to form a first conductive layer, such as... Figure 10 and Figure 11 As shown, Figure 10 Schematic diagram of the first conductive layer Figure 1 , Figure 11 Schematic diagram after the formation of the first conductive layer Figure 1 .

[0157] In one exemplary embodiment, the first conductive layer may include: the control electrode ET12 of the first light-emitting transistor to the control electrode ET132 of the thirteenth light-emitting transistor, the first electrode EC11 of the first light-emitting capacitor to the first electrode EC31 of the third light-emitting capacitor, the control electrode ST12 of the first scanning transistor to the control electrode ST142 of the fourteenth scanning transistor, the first electrode SC11 of the first scanning capacitor to the first electrode SC31 of the third scanning capacitor, the control electrode GT12 of the first control transistor to the control electrode GT82 of the eighth control transistor, the first electrode GC11 of the first control capacitor and the first electrode GC21 of the second control capacitor, the first connecting electrode VL1 and the second connecting electrode VL2.

[0158] In one exemplary embodiment, the control electrodes ET12 to ET82 of the first light-emitting transistor and ET112 to ET132 of the eleventh light-emitting transistor are located on the side away from the display area of ​​the control electrodes ET92 and ET102 of the ninth and tenth light-emitting transistors. The control electrodes ET92 and ET102 of the ninth and tenth light-emitting transistors are arranged along a first direction. Specifically, the control electrodes ET112 and ET122 of the eleventh and twelfth light-emitting transistors are integrally formed; the control electrode ET62 of the sixth light-emitting transistor and the first plate EC11 of the first light-emitting capacitor are integrally formed; the control electrode ET42 of the fourth light-emitting transistor, the first plate EC31 of the third light-emitting capacitor, and the control electrode ET102 of the tenth light-emitting transistor are integrally formed; and the control electrode ET92 of the ninth light-emitting transistor and the first plate EC21 of the second light-emitting capacitor are integrally formed.

[0159] In one exemplary embodiment, the control electrodes ST12 to ST82 of the first scanning transistor, ST112 to ST142 of the eleventh scanning transistor, and the first connection electrode VL1 are located on the side away from the display area of ​​the control electrodes ST92 and ST102 of the ninth and tenth scanning transistors. The control electrodes ST92 and ST102 of the ninth and tenth scanning transistors are arranged along a first direction. The control electrodes ST22 and ST82 of the second and eighth scanning transistors are integrally formed; the control electrodes ST132 and ST142 of the thirteenth and fourteenth scanning transistors are integrally formed; the control electrode ST62 of the sixth scanning transistor and the first plate SC11 of the first scanning capacitor are integrally formed; the control electrode ST42 of the fourth scanning transistor, the first plate SC31 of the third scanning capacitor, and the control electrode ST52 of the fifth scanning transistor are integrally formed; and the control electrode ST92 of the ninth scanning transistor and the first plate SC21 of the second scanning capacitor are integrally formed.

[0160] In one exemplary embodiment, the control electrodes GT12 to GT32 of the first control transistor and GT62 to GT82 of the sixth control transistor are located on the side of the control electrodes GT42 and GT52 of the fifth control transistor away from the display area. The control electrodes GT42 and GT52 of the fourth and fifth control transistors are arranged along a first direction. The second connection electrode VL2 is located on the side of the control electrode GT42 of the fourth control transistor away from the control electrode GT52 of the fifth control transistor and extends along a second direction. The control electrodes GT42 and GT62 of the fourth and sixth control transistors and the first plate GC11 of the first control capacitor are integrally formed, and the control electrode GT52 of the fifth control transistor and the first plate GC21 of the second control capacitor are integrally formed.

[0161] (3) Forming a second conductive layer includes: depositing a second insulating film on a substrate on which a first conductive layer has been formed, and patterning the second insulating film using a patterning process to form a second insulating layer. For example, depositing a second conductive film on a substrate on which a second insulating layer has been formed, and patterning the second conductive film using a patterning process to form a second conductive layer. Figure 12 and Figure 13 As shown, Figure 12 This is a schematic diagram of the second conductive layer. Figure 13 Schematic diagram after the formation of the second conductive layer Figure 1 .

[0162] In one exemplary embodiment, the second conductive layer includes: the second electrode EC12 of the first light-emitting capacitor to the second electrode EC32 of the third light-emitting capacitor, the third connecting electrode VL3, the second electrode SC12 of the first scanning capacitor to the second electrode SC32 of the third scanning capacitor, the fourth connecting electrode VL4, the first scanning output section GNL1, the second scanning output section GNL2, the second electrode GC12 of the first control capacitor, the second electrode GC22 of the second control capacitor, and the fifth connecting electrode VL5.

[0163] In one exemplary embodiment, the second plates EC12 of the first light-emitting capacitor and EC22 of the second light-emitting capacitor are arranged along a second direction, with the second plate EC12 of the first light-emitting capacitor located on the side of the second plate EC22 of the second light-emitting capacitor away from the display area. The second plates EC22 of the second light-emitting capacitor and EC32 of the third light-emitting capacitor are arranged along a first direction, and the third connecting electrode VL3 is located on the side of the second plate EC32 of the third light-emitting capacitor away from the second plate EC22 of the second light-emitting capacitor, and extends along the second direction.

[0164] In one exemplary embodiment, the second plates SC12 and SC22 of the first scanning capacitor are arranged along a second direction, with the second plate SC12 of the first scanning capacitor located on the side of the second plate SC22 of the second scanning capacitor away from the display area. The second plates SC22 of the second scanning capacitor and SC32 of the third scanning capacitor are arranged along a first direction, and the fourth connecting electrode VL4 is located on the side of the second plate SC32 of the third scanning capacitor away from the second plate SC22 of the second scanning capacitor, and extends along the second direction. The first scan output section GNL1 and the second scan output section GNL2 are located on the side of the second plate SC32 of the third scanning capacitor away from the second plate SC22 of the second scanning capacitor, and extend along the second direction. The first scan output section GNL1 and the second scan output section GNL2 are arranged along the second direction.

[0165] In one exemplary embodiment, the second plate GC12 of the first control capacitor and the second plate GC22 of the second control capacitor are arranged along a first direction. The second plate GC12 of the first control capacitor and the fifth connecting electrode VL5 are arranged along the first direction, and the fifth connecting electrode VL5 is located on the side of the second plate GC12 of the first control capacitor away from the display area.

[0166] (4) Forming a third insulating layer includes: depositing a third insulating film on a substrate on which a second conductive layer has been formed, and patterning the third insulating film using a patterning process to form a third insulating layer. Figure 14 and Figure 15 As shown, Figure 14 Schematic diagram of the third insulating layer Figure 1 , Figure 15 Schematic diagram after the formation of the third insulating layer Figure 1 .

[0167] In one exemplary embodiment, the third insulating layer may include a plurality of via patterns. The plurality of via patterns may include: a first via V1 to a thirteenth via V13 penetrating the first insulating layer, the second insulating layer, and the third insulating layer; a fourteenth via V14 to a twenty-fourth via V24 penetrating the second insulating layer and the third insulating layer; and a twenty-fifth via V25 to a twenty-eighth via V28 penetrating the third insulating layer.

[0168] In one exemplary embodiment, a first via V1 exposes the active layer of a first light-emitting transistor (LED), a second via V2 exposes the active layer of a second LED, a third via V3 exposes the active layer of a third LED, a fourth via V4 exposes the active layer of a fourth LED, a fifth via V5 exposes the active layer of a fifth LED, a sixth via V6 exposes the active layer of a sixth LED, a seventh via V7 exposes the active layer of a seventh LED, an eighth via V8 exposes the active layer of an eighth LED, a ninth via V9 exposes the active layer of a ninth LED, a tenth via V10 exposes the active layer of a tenth LED, an eleventh via V11 exposes the active layer of an eleventh LED, a twelfth via V12 exposes the active layer of a twelfth LED, a thirteenth via V13 exposes the active layer of a thirteenth LED, a fourteenth via V14 exposes the control electrode of the first LED, and a fifteenth via... V15 exposes the control electrode of the second LED; V16 exposes the control electrode of the third LED; V17 exposes the control electrode of the fourth LED; V18 exposes the control electrode of the fifth LED; V19 exposes the control electrode of the sixth LED; V20 exposes the control electrode of the seventh LED; V21 exposes the control electrode of the eighth LED; V22 exposes the control electrode of the ninth LED; V23 exposes the control electrode of the eleventh LED; V24 exposes the control electrode of the thirteenth LED; V25 exposes the second electrode of the first LED; V26 exposes the second electrode of the second LED; V27 exposes the second electrode of the third LED; and V28 exposes the third connection electrode.

[0169] In one exemplary embodiment, the plurality of via patterns may further include: a 29th via V29 to a 42nd via V42 penetrating the first insulating layer, the second insulating layer and the third insulating layer, a 43rd via V43 to a 54th via V54 penetrating the second insulating layer and the third insulating layer, and a 55th via V55 to a 60th via V60 penetrating the third insulating layer.

[0170] In one exemplary embodiment, via V29 exposes the active layer of the first scanning transistor, via V30 exposes the active layer of the second scanning transistor, via V31 exposes the active layer of the third scanning transistor, via V32 exposes the active layer of the fourth scanning transistor, via V33 exposes the active layer of the fifth scanning transistor, via V34 exposes the active layer of the sixth scanning transistor, via V35 exposes the active layer of the seventh scanning transistor, and via V36 exposes the active layer of the third scanning transistor. The active layer of the eight-scan transistor is exposed by via V37 (37th via), via V38 (38th via), via V39 (39th via), via V40 (40th via), via V41 (41st via), via V42 (42nd via), via V43 (43rd via), and via V44 (44th via). Via V45 exposes the control electrode of the second scanning transistor; via V45 exposes the control electrode of the third scanning transistor; via V46 exposes the control electrode of the fourth scanning transistor; via V47 exposes the control electrode of the sixth scanning transistor; via V48 exposes the control electrode of the seventh scanning transistor; via V49 exposes the control electrode of the ninth scanning transistor; via V50 exposes the control electrode of the tenth scanning transistor; via V51 exposes the control electrode of the eleventh scanning transistor; via V52 exposes the control electrode of the eleventh scanning transistor. The control electrode of the twelfth scanning transistor is exposed; the control electrode of the thirteenth scanning transistor is exposed through via V53; the first connection electrode is exposed through via V54; the first plate of the first scanning capacitor is exposed through via V55; the first plate of the second scanning capacitor is exposed through via V56; the first plate of the third scanning capacitor is exposed through via V57; the fourth connection electrode VL3 is exposed through via V58; the first scan output section is exposed through via V59; and the second scan output section is exposed through via V60.

[0171] In one exemplary embodiment, the plurality of via patterns may further include: sixty-first vias V61 to sixty-eighth vias V68 penetrating the first insulating layer, the second insulating layer and the third insulating layer, sixty-ninth vias V69 to seventy-sixth vias V76 penetrating the second insulating layer and the third insulating layer, and seventy-seventh vias V77 to seventy-ninth vias V79 penetrating the third insulating layer.

[0172] In one exemplary embodiment, via V61 exposes the active layer of the first control transistor, via V62 exposes the active layer of the second control transistor, via V63 exposes the active layer of the third control transistor, via V64 exposes the active layer of the fourth control transistor, via V65 exposes the active layer of the fifth control transistor, via V66 exposes the active layer of the sixth control transistor, via V67 exposes the active layer of the seventh control transistor, via V68 exposes the active layer of the eighth control transistor, and via V69 exposes the control electrode of the first control transistor. Via 70 exposes the control electrode of the second control transistor; via 71 exposes the control electrode of the third control transistor; via 72 exposes the control electrode of the fourth control transistor; via 73 exposes the control electrode of the fifth control transistor; via 74 exposes the control electrode of the seventh control transistor; via 75 exposes the control electrode of the eighth control transistor; via 76 exposes the second connection electrode; via 77 exposes the first plate of the first control capacitor; via 78 exposes the second plate of the second control capacitor; and via 79 exposes the fifth connection electrode.

[0173] (5) Forming a third conductive layer includes: depositing a third conductive thin film on a substrate on which a third insulating layer is formed, and patterning the third conductive thin film using a patterning process to form a third conductive layer, such as... Figure 16 and Figure 17 As shown, Figure 16 Schematic diagram of the third conductive layer Figure 1 , Figure 17 Schematic diagram after the formation of the third conductive layer Figure 1 .

[0174] In one exemplary embodiment, the third conductive layer may include: an initial light-emitting signal line ESTV, a first high-level power supply line VGH1, a first low-level power supply line VGL1, a first light-emitting clock signal line ECLK1 to a third light-emitting clock signal line ECLK3, the first terminal ET13 and the second terminal ET14 of the first light-emitting transistor to the first terminal ET133 and the second terminal ET134 of the thirteenth light-emitting transistor, a scan initial signal line SSTV, a second high-level power supply line VGH2, a second low-level power supply line VGL2, and a first scan clock signal line SCLK1 to a third scan clock signal line SCLK3. K3, the first electrode ST13 and the second electrode ST14 of the first scanning transistor to the first electrode ST143 and the second electrode ST144 of the fourteenth scanning transistor, the control initial signal line GSTV, the third high-level power supply line VGH3, the third low-level power supply line VGL3, the first control clock signal line GCLK1, the second control clock signal line GCLK2, the first electrode GT13 and the second electrode GT14 of the first control transistor to the first electrode GT83 and the second electrode GT84 of the eighth control transistor, the third scan output section GNL3, the sixth connection electrode VL6, and the fourth scan output section GNL4.

[0175] In one exemplary embodiment, the display substrate includes two first low-level power lines VGL1.

[0176] In one exemplary embodiment, the initial light-emitting signal line ESTV, the first high-level power supply line VGH1, the first low-level power supply line VGL1, the first light-emitting clock signal line ECLK1 to the third light-emitting clock signal line ECLK3 extend along a first direction. The third scan clock signal line ECLK3 is located on the side of the initial light-emitting signal line ESTV closest to the display area, the first scan clock signal line ECLK1 is located on the side of the third scan clock signal line ECLK3 closest to the display area, the first low-level power supply line VGL1 is located on the side of the first scan clock signal line ECLK1 closest to the display area, and the first terminals ET13 and ET14 of the first light-emitting transistor to the first terminals ET83 and ET84 of the eighth light-emitting transistor, and the first terminals ET113 and ET114 of the eleventh light-emitting transistor to the first terminals ET133 and ET134 of the thirteenth light-emitting transistor are located along the first low-level power supply line VGL1. The first low-level power line VGL1 is located between the first low-level power line VGL1 and the second scan clock signal line ECLK2, with the second scan clock signal line ECLK2 located on the side of the first low-level power line VGL1 closest to the display area. The first high-level power line VGH1 is located on the side of the second scan clock signal line ECLK2 closest to the display area. The first electrode ET93 and the second electrode ET94 of the ninth light-emitting transistor to the first electrode ET103 and the second electrode ET104 of the tenth light-emitting transistor are located between the first high-level power line VGH1 and the second first low-level power line VGL1, with the second first low-level power line VGL1 located on the side of the first high-level power line VGH1 closest to the display area.

[0177] In one exemplary embodiment, the first low-level power line VGL1 and the first terminal ET33 of the third light-emitting transistor are integrally formed; the second low-level power line VGL1 and the first terminal E104 of the tenth light-emitting transistor are integrally formed; the first high-level power line VGH1, the first terminal ET83 of the eighth light-emitting transistor, and the first terminal ET133 of the thirteenth light-emitting transistor are integrally formed; the second terminals ET24 of the second light-emitting transistor, ET34 of the third light-emitting transistor, and the first terminal ET113 of the eleventh light-emitting transistor are integrally formed; the first terminals ET43 of the fourth light-emitting transistor and ET63 of the sixth light-emitting transistor are integrally formed; the second terminals ET44 of the fourth light-emitting transistor and ET54 of the fifth light-emitting transistor are integrally formed; the first terminals ET83 of the eighth light-emitting transistor and ET133 of the thirteenth light-emitting transistor are integrally formed; and the second terminals ET94 of the ninth light-emitting transistor and ET104 of the tenth light-emitting transistor are integrally formed. The second electrode of the seventh light-emitting transistor ET74 and the second electrode of the eighth light-emitting transistor ET84 are integrally molded structures, and the second electrode of the sixth light-emitting transistor ET64 and the first electrode of the seventh light-emitting transistor ET73 are integrally molded structures.

[0178] In one exemplary embodiment, for an odd-level light-emitting shift register, the first terminal ET13 and the second terminal ET14 of the first light-emitting transistor are electrically connected to the active layer of the first light-emitting transistor through a first via. The second terminal ET14 of the first light-emitting transistor is connected to the control terminal of the second light-emitting transistor through a fifteenth via. The control terminal of the first light-emitting transistor is connected to the third light-emitting clock signal line ECLK3 and the first terminal ET23 of the second light-emitting transistor through a fourteenth via. The first terminal ET23 and the second terminal ET24 of the second light-emitting transistor are connected to the active layer of the second light-emitting transistor through a second via. The first terminal ET33 and the second terminal ET34 of the third light-emitting transistor are connected to the active layer of the third light-emitting transistor through a third via. The control terminal of the third light-emitting transistor is connected to the third light-emitting clock signal line ECLK3 through a sixteenth via. The first terminal ET43 and the second terminal ET44 of the fourth light-emitting transistor are connected to the active layer of the fourth light-emitting transistor through a fourth via. The second terminal ET44 of the fourth light-emitting transistor is connected to the second plate of the third light-emitting capacitor through a twenty-seventh via. The first terminal ET53 and the second terminal ET54 of the fifth LED are connected to the active layer of the fifth LED through the fifth via. The first terminal ET63 and the second terminal ET64 of the sixth LED are connected to the active layer of the sixth LED through the sixth via. The second terminal ET64 of the sixth LED is connected to the second plate of the first LED through the twenty-fifth via. The first terminal ET73 and the second terminal ET74 of the seventh LED are connected to the active layer of the seventh LED through the seventh via. The control terminal of the seventh LED is connected to the first LED clock signal line ECLK1 and the first terminal ET43 of the fourth LED through the twentieth via. The first terminal ET83 and the second terminal ET84 of the eighth LED are connected to the active layer of the eighth LED through the eighth via. The control terminal of the eighth LED is connected to the second terminal ET134 of the thirteenth LED through the twenty-first via. The first electrode ET93 and the second electrode ET94 of the ninth light-emitting transistor are connected to the active layer of the ninth light-emitting transistor through the ninth via. The first electrode ET93 of the ninth light-emitting transistor is connected to the second plate of the second light-emitting capacitor through the twenty-sixth via. The control electrode of the ninth light-emitting transistor is connected to the second electrode T74 of the seventh light-emitting transistor through the twenty-second via. The first electrode ET103 and the second electrode ET104 of the tenth light-emitting transistor are connected to the active layer of the tenth light-emitting transistor through the tenth via. The first electrode ET103 of the tenth light-emitting transistor is connected to the third connection electrode VL3 through the twenty-eighth via.The first electrode ET113 and the second electrode ET114 of the eleventh LED are connected to the active layer of the eleventh LED through the eleventh via. The second electrode ET114 of the eleventh LED is connected to the control electrode of the fifth LED through the eighteenth via, and to the control electrode of the sixth LED through the nineteenth via. The control electrode of the eleventh LED is connected to the first low-level power line VGL1 through the twenty-third via. The first electrode ET123 and the second electrode ET124 of the twelfth LED are connected to the active layer of the twelfth LED through the twelfth via. The first electrode ET123 of the twelfth LED is connected to the control electrode of the second LED through the fifteenth via. The second electrode ET124 of the twelfth LED is connected to the active layer of the twelfth LED through the twelfth via, and to the first plate of the third LED through the seventeenth via. The first electrode ET133 and the second electrode ET134 of the thirteenth light-emitting transistor are connected to the active layer of the thirteenth light-emitting transistor through the thirteenth via. The second electrode ET134 of the thirteenth light-emitting transistor is connected to the control electrode of the second light-emitting transistor through the fifteenth via. The control electrode of the thirteenth light-emitting transistor is connected to the second light-emitting clock signal line ECLK2 through the twenty-fourth via. Figure 17 This explanation uses an odd-level light-emitting shift register as an example.

[0179] In one exemplary embodiment, for an even-level light-emitting shift register, the first terminal ET13 and the second terminal ET14 of the first light-emitting transistor are electrically connected to the active layer of the first light-emitting transistor through a first via. The second terminal ET14 of the first light-emitting transistor is connected to the control terminal of the second light-emitting transistor through a fifteenth via. The control terminal of the first light-emitting transistor is connected to the first light-emitting clock signal line ECLK1 and the first terminal ET23 of the second light-emitting transistor through a fourteenth via. The first terminal ET23 and the second terminal ET24 of the second light-emitting transistor are connected to the active layer of the second light-emitting transistor through a second via. The first terminal ET33 and the second terminal ET34 of the third light-emitting transistor are connected to the active layer of the third light-emitting transistor through a third via. The control terminal of the third light-emitting transistor is connected to the first light-emitting clock signal line ECLK1 through a sixteenth via. The first terminal ET43 and the second terminal ET44 of the fourth light-emitting transistor are connected to the active layer of the fourth light-emitting transistor through a fourth via. The second terminal ET44 of the fourth light-emitting transistor is connected to the second plate of the third light-emitting capacitor through a twenty-seventh via. The first terminal ET53 and the second terminal ET54 of the fifth LED are connected to the active layer of the fifth LED through the fifth via. The first terminal ET63 and the second terminal ET64 of the sixth LED are connected to the active layer of the sixth LED through the sixth via. The second terminal ET64 of the sixth LED is connected to the second plate of the first LED through the twenty-fifth via. The first terminal ET73 and the second terminal ET74 of the seventh LED are connected to the active layer of the seventh LED through the seventh via. The control terminal of the seventh LED is connected to the third LED clock signal line ECLK3 and the first terminal ET43 of the fourth LED through the twentieth via. The first terminal ET83 and the second terminal ET84 of the eighth LED are connected to the active layer of the eighth LED through the eighth via. The control terminal of the eighth LED is connected to the second terminal ET134 of the thirteenth LED through the twenty-first via. The first electrode ET93 and the second electrode ET94 of the ninth light-emitting transistor are connected to the active layer of the ninth light-emitting transistor through the ninth via. The first electrode ET93 of the ninth light-emitting transistor is connected to the second plate of the second light-emitting capacitor through the twenty-sixth via. The control electrode of the ninth light-emitting transistor is connected to the second electrode T74 of the seventh light-emitting transistor through the twenty-second via. The first electrode ET103 and the second electrode ET104 of the tenth light-emitting transistor are connected to the active layer of the tenth light-emitting transistor through the tenth via. The first electrode ET103 of the tenth light-emitting transistor is connected to the third connection electrode VL3 through the twenty-eighth via.The first electrode ET113 and the second electrode ET114 of the eleventh LED are connected to the active layer of the eleventh LED through the eleventh via. The second electrode ET114 of the eleventh LED is connected to the control electrode of the fifth LED through the eighteenth via, and to the control electrode of the sixth LED through the nineteenth via. The control electrode of the eleventh LED is connected to the first low-level power line VGL1 through the twenty-third via. The first electrode ET123 and the second electrode ET124 of the twelfth LED are connected to the active layer of the twelfth LED through the twelfth via. The first electrode ET123 of the twelfth LED is connected to the control electrode of the second LED through the fifteenth via. The second electrode ET124 of the twelfth LED is connected to the active layer of the twelfth LED through the twelfth via, and to the first plate of the third LED through the seventeenth via. The first electrode ET133 and the second electrode ET134 of the thirteenth light-emitting transistor are connected to the active layer of the thirteenth light-emitting transistor through the thirteenth via. The second electrode ET134 of the thirteenth light-emitting transistor is connected to the control electrode of the second light-emitting transistor through the fifteenth via. The control electrode of the thirteenth light-emitting transistor is connected to the second light-emitting clock signal line ECLK2 through the twenty-fourth via.

[0180] In one exemplary embodiment, the third connection electrode VL3 is also connected to the first electrode of the first light-emitting transistor of the next-stage light-emitting shift register.

[0181] In one exemplary embodiment, the display substrate may further include: two second low-level power supply lines VGL2, two first scan clock signal lines ECLK1, and two second scan clock signal lines ECLK3.

[0182] In one exemplary embodiment, the initial scan signal line SSTV, the second high-level power supply line VGH2, the second low-level power supply line VGL2, the first scan clock signal line SCLK1 to the third scan clock signal line SCLK3 extend along a first direction. The initial scan signal line SSTV, the first third scan clock signal line SCLK3, the first first scan clock signal line SCLK1, the second third scan clock signal line SCLK3, the second first scan clock signal line SCLK1, and the first second low-level power supply line VGL2 are arranged sequentially along the side of the second first low-level power supply line closest to the display area. The first terminal ST13 and second terminal ST14 of the first scanning transistor to the first terminal ST83 and second terminal ST84 of the eighth scanning transistor, the first terminal ST103 and second terminal ST104 of the tenth scanning transistor to the first terminal ST143 and second terminal ST144 of the fourteenth scanning transistor, and the third scanning output section GNL3 are located between the first second low-level power supply line VGL2 and the second scanning clock signal line SCLK2, with the second scanning clock signal line SCLK2 located on the side of the first second low-level power supply line VGL2 closer to the display area. The second high-level power supply line VGH2 is located on the side of the second scanning clock signal line SCLK2 closer to the display area. The first terminal ST93 and second terminal ST94 of the ninth scanning transistor to the first terminal ST103 and second terminal ST104 of the tenth scanning transistor are located between the second high-level power supply line VGH2 and the second second low-level power supply line VGL2, with the second second low-level power supply line VGL2 located on the side of the second high-level power supply line VGH2 closer to the display area.

[0183] In one exemplary embodiment, the third scan output section GNL3 and the fourth scan output section GNL4 extend along a second direction. The fourth scan output section GNL4 of the i-th stage scan shift register is located between the 2i-th stage control shift register and the 2i+1-th stage control shift register.

[0184] In one exemplary embodiment, the first second low-level power line VGL2 and the first terminal ST33 of the third scanning transistor are integrally formed; the second second low-level power line VGL2 and the first terminal ST103 of the tenth scanning transistor are integrally formed; the second high-level power line VGH2, the first terminal ST83 of the eighth scanning transistor, the first terminal ST113 of the eleventh scanning transistor, and the first terminal ST123 of the twelfth scanning transistor are integrally formed; the second terminal ST24 of the second scanning transistor, the second terminal ST34 of the third scanning transistor, and the first terminal ST143 of the fourteenth scanning transistor are integrally formed; the second terminal ST54 of the fifth scanning transistor, the second terminal ST114 of the eleventh scanning transistor, and the second terminal ST124 of the twelfth scanning transistor are integrally formed; the second terminal ST64 of the sixth scanning transistor and the first terminal ST73 of the seventh scanning transistor are integrally formed; and the second terminal ST74 of the seventh scanning transistor and the second terminal ST84 of the eighth scanning transistor are integrally formed.

[0185] In one exemplary embodiment, for an odd-level scan shift register, the first terminal ST13 and the second terminal ST14 of the first scan transistor are electrically connected to the active layer of the first scan transistor through a twenty-ninth via. The second terminal ST14 of the first scan transistor is connected to the control terminal of the second scan transistor through a forty-fourth via. The control terminal of the first scan transistor is connected to the second third scan clock signal line SCLK3 and the first terminal ST23 of the second scan transistor through a forty-third via. The first terminal ST23 and the second terminal ST24 of the second scan transistor are connected to the active layer of the second scan transistor through a thirtieth via. The first terminal ST33 and the second terminal ST34 of the third scan transistor are connected to the active layer of the third scan transistor through a thirty-first via. The control terminal of the third scan transistor is connected to the first third scan clock signal line SCLK3 through a forty-fifth via. The first electrode ST43 and the second electrode ST44 of the fourth scanning transistor are connected to the active layer of the fourth scanning transistor through the thirty-second via. The first connection electrode VL1 is connected to the second first scanning clock signal line SCLK1 and the first electrode ST43 of the fourth scanning transistor through the fifty-fourth via. The second electrode ST44 of the fourth scanning transistor is connected to the second plate of the third scanning capacitor through the fifty-seventh via. The first electrode ST53 and the second electrode ST54 of the fifth scanning transistor are connected to the active layer of the fifth scanning transistor through the thirty-third via. The first electrode ST53 of the fifth scanning transistor is connected to the control electrode of the fourth scanning transistor through the forty-sixth via. The second electrode ST54 of the fifth scanning transistor is connected to the control electrode of the tenth scanning transistor through the fiftieth via. The first electrode ST63 and the second electrode ST64 of the sixth scanning transistor are connected to the active layer of the sixth scanning transistor through the thirty-fourth via. The first electrode ST63 of the sixth scanning transistor is connected to the control electrode of the seventh scanning transistor through the forty-eighth via. The second electrode ST64 of the sixth scanning transistor is connected to the second plate of the first scanning capacitor through the fifty-fifth via and to the control electrode of the eleventh scanning transistor through the fifty-first via. The first terminal ST73 and the second terminal ST74 of the seventh scanning transistor are connected to the active layer of the seventh scanning transistor through the seventh via. The second terminal ST74 of the seventh scanning transistor is connected to the control terminal of the ninth scanning transistor through the forty-ninth via. The control terminal of the seventh scanning transistor is connected to the first scan clock signal line SCLK1 through the forty-eighth via. The first terminal ST83 and the second terminal ST84 of the eighth scanning transistor are connected to the active layer of the eighth scanning transistor through the thirty-sixth via. The first terminal ST93 and the second terminal ST94 of the ninth scanning transistor are connected to the active layer of the ninth scanning transistor through the thirty-seventh via. The first terminal ST93 of the ninth scanning transistor is connected to the second plate of the second scanning capacitor through the fifty-sixth via.The first terminal ST103 and the second terminal ST104 of the tenth scanning transistor are connected to the active layer of the tenth scanning transistor through the thirty-eighth via. The second terminal ST104 of the tenth scanning transistor is connected to the first scanning output section through the fifty-ninth via. The first terminal ST113 and the second terminal ST114 of the eleventh scanning transistor are connected to the active layer of the eleventh scanning transistor through the fortieth via. The first terminal ST123 and the second terminal ST124 of the twelfth scanning transistor are connected to the active layer of the twelfth scanning transistor through the fortieth via. The control terminal of the twelfth scanning transistor is connected to the second scanning clock signal line SCLK2 through the fifty-second via. The first electrode ST133 and the second electrode ST134 of the thirteenth scanning transistor are connected to the active layer of the thirteenth scanning transistor through the forty-first via. The first electrode ST133 of the thirteenth scanning transistor is connected to the control electrode of the second scanning transistor through the forty-fourth via. The second electrode ST134 of the thirteenth scanning transistor is connected to the control electrode of the fourth scanning transistor through the forty-sixth via. The control electrode of the thirteenth scanning transistor is connected to the first second low-level power supply line VGL2 through the fifty-third via. The first electrode ST143 and the second electrode ST144 of the fourteenth scanning transistor are connected to the active layer of the fourteenth scanning transistor through the forty-second via. The second electrode ST144 of the fourteenth scanning transistor is connected to the control electrode of the sixth scanning transistor through the forty-seventh via. The third scanning output section GNL3 is connected to the fourth connection electrode through the fifty-eighth via and to the first scanning output section through the fifty-ninth via. The fourth scanning output section GNL4 is connected to the first scanning output section through the fifty-ninth via and to the second scanning output section through the sixtieth via. Figure 17 This explanation uses an odd-level scan shift register as an example.

[0186] In one exemplary embodiment, for an even-level scan shift register, the first terminal ST13 and the second terminal ST14 of the first scan transistor are electrically connected to the active layer of the first scan transistor through a twenty-ninth via. The second terminal ST14 of the first scan transistor is connected to the control terminal of the second scan transistor through a forty-fourth via. The control terminal of the first scan transistor is connected to the first third scan clock signal line SCLK3 and the first terminal ST23 of the second scan transistor through a forty-third via. The first terminal ST23 and the second terminal ST24 of the second scan transistor are connected to the active layer of the second scan transistor through a thirtieth via. The first terminal ST33 and the second terminal ST34 of the third scan transistor are connected to the active layer of the third scan transistor through a thirty-first via. The control terminal of the third scan transistor is connected to the second third scan clock signal line SCLK3 through a forty-fifth via. The first electrode ST43 and the second electrode ST44 of the fourth scanning transistor are connected to the active layer of the fourth scanning transistor through the thirty-second via. The first connection electrode VL1 is connected to the first scan clock signal line SCLK1 and the first electrode ST43 of the fourth scanning transistor through the fifty-fourth via. The second electrode ST44 of the fourth scanning transistor is connected to the second plate of the third scanning capacitor through the fifty-seventh via. The first electrode ST53 and the second electrode ST54 of the fifth scanning transistor are connected to the active layer of the fifth scanning transistor through the thirty-third via. The first electrode ST53 of the fifth scanning transistor is connected to the control electrode of the fourth scanning transistor through the forty-sixth via. The second electrode ST54 of the fifth scanning transistor is connected to the control electrode of the tenth scanning transistor through the fiftieth via. The first electrode ST63 and the second electrode ST64 of the sixth scanning transistor are connected to the active layer of the sixth scanning transistor through the thirty-fourth via. The first electrode ST63 of the sixth scanning transistor is connected to the control electrode of the seventh scanning transistor through the forty-eighth via. The second electrode ST64 of the sixth scanning transistor is connected to the second plate of the first scanning capacitor through the fifty-fifth via and to the control electrode of the eleventh scanning transistor through the fifty-first via. The first terminal ST73 and the second terminal ST74 of the seventh scanning transistor are connected to the active layer of the seventh scanning transistor through the seventh via. The second terminal ST74 of the seventh scanning transistor is connected to the control terminal of the ninth scanning transistor through the forty-ninth via. The control terminal of the seventh scanning transistor is connected to the second first scanning clock signal line SCLK1 through the forty-eighth via. The first terminal ST83 and the second terminal ST84 of the eighth scanning transistor are connected to the active layer of the eighth scanning transistor through the thirty-sixth via. The first terminal ST93 and the second terminal ST94 of the ninth scanning transistor are connected to the active layer of the ninth scanning transistor through the thirty-seventh via. The first terminal ST93 of the ninth scanning transistor is connected to the second plate of the second scanning capacitor through the fifty-sixth via.The first terminal ST103 and the second terminal ST104 of the tenth scanning transistor are connected to the active layer of the tenth scanning transistor through the thirty-eighth via. The second terminal ST104 of the tenth scanning transistor is connected to the first scanning output section through the fifty-ninth via. The first terminal ST113 and the second terminal ST114 of the eleventh scanning transistor are connected to the active layer of the eleventh scanning transistor through the fortieth via. The first terminal ST123 and the second terminal ST124 of the twelfth scanning transistor are connected to the active layer of the twelfth scanning transistor through the fortieth via. The control terminal of the twelfth scanning transistor is connected to the second scanning clock signal line SCLK2 through the fifty-second via. The first electrode ST133 and the second electrode ST134 of the thirteenth scanning transistor are connected to the active layer of the thirteenth scanning transistor through the forty-first via. The first electrode ST133 of the thirteenth scanning transistor is connected to the control electrode of the second scanning transistor through the forty-fourth via. The second electrode ST134 of the thirteenth scanning transistor is connected to the control electrode of the fourth scanning transistor through the forty-sixth via. The control electrode of the thirteenth scanning transistor is connected to the first second low-level power supply line VGL2 through the fifty-third via. The first electrode ST143 and the second electrode ST144 of the fourteenth scanning transistor are connected to the active layer of the fourteenth scanning transistor through the forty-second via. The second electrode ST144 of the fourteenth scanning transistor is connected to the control electrode of the sixth scanning transistor through the forty-seventh via. The third scanning output section GNL is connected to the fourth connection electrode through the fifty-eighth via and to the first scanning output section through the fifty-ninth via. The fourth scanning output section GNL4 is connected to the first scanning output section through the fifty-ninth via and to the second scanning output section through the sixtieth via.

[0187] In one exemplary embodiment, the fourth connection electrode VL4 is also connected to the first electrode of the first scan transistor of the next-stage scan shift register.

[0188] In one exemplary embodiment, the initial control signal line GSTV, the third high-level power supply line VGH3, the third low-level power supply line VGL3, the first control clock signal line GCLK1, and the second control clock signal line GCLK2 extend along a first direction. The initial control signal line GSTV, the first control clock signal line GCLK1, the second control clock signal line GCLK2, and the third low-level power supply line VGL3 are arranged sequentially along the direction of the second low-level power supply line VGL2 towards the display area. The first electrode GT13 and the second electrode GT14 of the first control transistor to the first electrode GT83 and the second electrode GT84 of the eighth control transistor, and the sixth connection electrode VL6 are located between the third low-level power supply line VGL3 and the third high-level power supply line VGH3, with the third high-level power supply line VGH3 located on the side of the third low-level power supply line VGL3 closest to the display area.

[0189] In one exemplary embodiment, the third low-level power line VL3 and the first terminal GT33 of the third control transistor are integrally molded. The third high-level power line VGH3, the first terminal GT43 of the fourth control transistor, and the first terminal GT63 of the sixth control transistor are integrally molded; the second terminals GT14 of the first control transistor, GT74 of the seventh control transistor, and GT83 of the eighth control transistor are integrally molded; the second terminals GT24 of the second control transistor and GT34 of the third control transistor are integrally molded; and the second terminals GT44 of the fourth control transistor and GT53 of the fifth control transistor are integrally molded.

[0190] In one exemplary embodiment, the active layers of the sixth control transistor and the seventh control transistor after being conductord are reused as the first electrode GT63 of the sixth control transistor and the first electrode GT73 of the seventh control transistor, and the first electrode GT63 of the sixth control transistor and the first electrode GT73 of the seventh control transistor are integrally formed structures.

[0191] In one exemplary embodiment, for an odd-level control shift register, the first electrode GT13 and the second electrode GT14 of the first control transistor are electrically connected to the active layer of the first control transistor through a sixty-first via. The first electrode GT13 of the first control transistor is connected to the second connection electrode through a seventy-sixth via. The second electrode GT14 of the first control transistor is connected to the control electrode of the second control transistor through a seventieth via. The control electrode of the first control transistor is connected to the first control clock signal line GCLK1 and the first electrode GT23 of the second control transistor through a sixty-ninth via. The first electrode GT23 and the second electrode GT24 of the second control transistor are connected to the active layer of the second control transistor through a sixty-second via. The second electrode GT24 of the second control transistor is connected to the fifth connection electrode through a seventy-ninth via V79. The first electrode GT33 and the second electrode GT34 of the third control transistor are connected to the active layer of the third control transistor through a sixty-third via. The control electrode of the third control transistor is connected to the first control clock signal line GCLK1 through a seventy-first via. The first terminal GT43 and the second terminal GT44 of the fourth control transistor are connected to the active layer of the fourth control transistor through the sixty-fourth via. The first terminal GT43 of the fourth control transistor is connected to the first plate of the first control capacitor through the seventy-seventh via, and the second terminal GT44 of the fourth control transistor is connected to the second plate of the second control capacitor through the seventy-eighth via. The first terminal GT53 and the second terminal GT54 of the fifth control transistor are connected to the active layer of the fifth control transistor through the sixty-fifth via, and the second terminal GT54 of the fifth control transistor is connected to the control electrode of the seventh control transistor through the seventy-fourth via. The first terminal GT63 of the sixth control transistor is connected to the active layer of the sixth control transistor through the sixty-sixth via. The second terminal GT74 of the seventh control transistor is connected to the active layer of the seventh control transistor through the sixty-seventh via, and the control electrode of the seventh control transistor is connected to the second control clock signal line GCLK2 and the second terminal GT54 of the fifth control transistor through the seventy-fourth via. The first electrode GT83 and the second electrode GT84 of the eighth control transistor are connected to the active layer of the eighth control transistor through the sixty-eighth via. The second electrode GT84 of the eighth control transistor is connected to the control electrode of the fifth control transistor through the seventy-third via. The sixth connection electrode VL6 is connected to the control electrode of the fourth control transistor through the seventy-second via, and is also connected to the fifth connection electrode through the seventy-ninth electrode.

[0192] In one exemplary embodiment, for an even-level control shift register, the first electrode GT13 and the second electrode GT14 of the first control transistor are electrically connected to the active layer of the first control transistor through a sixty-first via. The first electrode GT13 of the first control transistor is connected to the second connection electrode through a seventy-sixth via. The second electrode GT14 of the first control transistor is connected to the control electrode of the second control transistor through a seventieth via. The control electrode of the first control transistor is connected to the second control clock signal line GCLK2 and the first electrode GT23 of the second control transistor through a sixty-ninth via. The first electrode GT23 and the second electrode GT24 of the second control transistor are connected to the active layer of the second control transistor through a sixty-second via. The second electrode GT24 of the second control transistor is connected to the fifth connection electrode through a seventy-ninth via V79. The first electrode GT33 and the second electrode GT34 of the third control transistor are connected to the active layer of the third control transistor through a sixty-third via. The control electrode of the third control transistor is connected to the second control clock signal line GCLK2 through a seventy-first via. The first terminal GT43 and the second terminal GT44 of the fourth control transistor are connected to the active layer of the fourth control transistor through the sixty-fourth via. The first terminal GT43 of the fourth control transistor is connected to the first plate of the first control capacitor through the seventy-seventh via, and the second terminal GT44 of the fourth control transistor is connected to the second plate of the second control capacitor through the seventy-eighth via. The first terminal GT53 and the second terminal GT54 of the fifth control transistor are connected to the active layer of the fifth control transistor through the sixty-fifth via, and the second terminal GT54 of the fifth control transistor is connected to the control electrode of the seventh control transistor through the seventy-fourth via. The first terminal GT63 of the sixth control transistor is connected to the active layer of the sixth control transistor through the sixty-sixth via. The second terminal GT74 of the seventh control transistor is connected to the active layer of the seventh control transistor through the sixty-seventh via, and the control electrode of the seventh control transistor is connected to the first control clock signal line GCLK1 and the second terminal GT54 of the fifth control transistor through the seventy-fourth via. The first electrode GT83 and the second electrode GT84 of the eighth control transistor are connected to the active layer of the eighth control transistor through the sixty-eighth via. The second electrode GT84 of the eighth control transistor is connected to the control electrode of the fifth control transistor through the seventy-third via. The sixth connection electrode VL6 is connected to the control electrode of the fourth control transistor through the seventy-second via, and is also connected to the fifth connection electrode through the seventy-ninth electrode.

[0193] In one exemplary embodiment, the second connection electrode is connected to the second electrode of the fifth control transistor of the previous stage light-emitting shift register through the seventy-sixth via. (6) Forming the first planarization layer includes: depositing a fourth insulating film on a substrate on which a third conductive layer has been formed; patterning the fourth insulating film using a patterning process to form a fourth insulating layer; coating the first planarization film on the fourth insulating layer; and patterning the first planarization film using a patterning process to form the first planarization layer, as shown below. Figure 18 and Figure 19 As shown, Figure 18 Schematic diagram of the first flattening layer Figure 1 , Figure 19 A schematic diagram after the formation of the first planarization layer. Figure 1 .

[0194] In one exemplary embodiment, the first planarization layer may include a via pattern. The via pattern includes an 80th via V80 penetrating the fourth insulating layer and the first planarization layer. The 80th via V80 exposes the second electrode of the 10th light-emitting transistor.

[0195] (7) Forming a fourth conductive layer includes: depositing a fourth conductive thin film on a substrate on which a first planarization layer has been formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer, such as... Figure 20 and Figure 21 As shown, Figure 20 Schematic diagram of the fourth conductive layer Figure 1 , Figure 21 Schematic diagram after the formation of the fourth conductive layer Figure 1 .

[0196] In one exemplary embodiment, the fourth conductive layer may include: a second power line VSSL and a light output line EML.

[0197] In one exemplary embodiment, the orthographic projection of the second power line VSSL on the substrate at least partially overlaps with the orthographic projection of the light-emitting driving circuit on the substrate. Specifically, the orthographic projection of the second power line VSSL on the substrate covers the orthographic projections of the initial light-emitting signal line, the first high-level power line, the first first low-level power line, and the first light-emitting clock signal lines ECLK1 to ECLK3 on the substrate, and does not overlap with the orthographic projection of the first first low-level power line on the substrate.

[0198] In one exemplary embodiment, the light output line EML is connected to the second electrode of the tenth light-emitting transistor through the eightieth via.

[0199] (8) Forming a light-emitting structure layer includes: coating a second planar thin film on a substrate on which a fourth conductive layer is formed; patterning the second planar thin film using a patterning process to form a second planar layer; depositing an anode thin film on the second planar layer; patterning the anode thin film using a patterning process to form an anode; depositing a pixel definition thin film on the anode; patterning the pixel definition thin film using a patterning process to form a pixel definition layer; evaporating an organic light-emitting thin film on the pixel definition layer; patterning the organic light-emitting thin film using a patterning process to form an organic light-emitting layer; depositing a cathode thin film on the organic light-emitting layer; and patterning the cathode thin film using a patterning process to form a cathode.

[0200] The following describes an exemplary embodiment of a display substrate provided, using the example of a scan output line including a first scan output section to a fourth scan output section and a light emission output line including a first light emission output section to a third light emission output section, through the fabrication process of the display substrate.

[0201] (1) Forming a semiconductor layer on a substrate includes: depositing a semiconductor thin film on the substrate and patterning the semiconductor thin film using a patterning process to form a semiconductor layer. As shown in Figure 5, Figure 5 is a schematic diagram after the semiconductor layer is formed.

[0202] (2) Forming a first conductive layer includes: depositing a second insulating film on a substrate on which an active layer is formed; patterning the second insulating film using a patterning process to form a first insulating layer; depositing a first conductive film on the first insulating layer; and patterning the first conductive film using a patterning process to form a first conductive layer, such as... Figure 22 and Figure 23 As shown, Figure 22 Schematic diagram 2 of the first conductive layer. Figure 23 Schematic diagram 2 shows the result after the first conductive layer has been formed.

[0203] Figure 22 and Figure 10 The difference is that, Figure 22 The first conductive layer may further include: a first light-emitting output section EML1.

[0204] In one exemplary embodiment, the first light-emitting output section EML1 extends along the second direction, and the first light-emitting output section EML1 of the light-emitting output line of the i-th stage light-emitting shift register is located between the first plate GC21 of the second control capacitor of the 2i+1-th stage control shift register and the first plate GC11 of the first control capacitor of the 2i+2-th stage control shift register.

[0205] (3) Forming a second conductive layer includes: depositing a second insulating film on a substrate on which a first conductive layer has been formed, and patterning the second insulating film using a patterning process to form a second insulating layer. For example, depositing a second conductive film on a substrate on which a second insulating layer has been formed, and patterning the second conductive film using a patterning process to form a second conductive layer. Figure 12 and Figure 24 As shown, Figure 24 This is a schematic diagram of the formation of the second conductive layer.

[0206] (4) Forming a third insulating layer includes: depositing a third insulating film on a substrate on which a second conductive layer has been formed, and patterning the third insulating film using a patterning process to form a third insulating layer. Figure 25 and Figure 26 As shown, Figure 25 Schematic diagram 2 for the third insulating layer. Figure 26 Schematic diagram 2 shows the result after the third insulating layer has been formed.

[0207] Figure 25 and Figure 14 The difference is that the multiple via pattern may also include: an eighty-first via V81 that penetrates the second insulating layer and the third insulating layer, the eighty-first via V81 exposing the first light-emitting output section.

[0208] (5) Forming a third conductive layer includes: depositing a third conductive thin film on a substrate on which a third insulating layer is formed, and patterning the third conductive thin film using a patterning process to form a third conductive layer, such as... Figure 27 and Figure 28 As shown, Figure 27 Schematic diagram 2 for the third conductive layer. Figure 28 This is a schematic diagram of the formation of the third conductive layer.

[0209] Figure 27 and Figure 16 The difference is that the third conductive layer may also include a seventh connecting electrode VL7 and an eighth connecting electrode VL8.

[0210] In one exemplary embodiment, the seventh connecting electrode VL7 is connected to the first light-emitting output unit through the eighty-first via, and the eighth connecting electrode VL8 is connected to the first light-emitting output unit through the eighty-first via.

[0211] In one exemplary embodiment, the seventh connecting electrode VL7 and the eighth connecting electrode VL8 extend along the second direction and are arranged along the second direction.

[0212] (6) Forming the first planarization layer includes: depositing a fourth insulating film on a substrate on which a third conductive layer has been formed; patterning the fourth insulating film using a patterning process to form a fourth insulating layer; coating the first planarization film on the fourth insulating layer; and patterning the first planarization film using a patterning process to form the first planarization layer, as shown below. Figure 29 and Figure 30 As shown, Figure 29 This is a schematic diagram of the first flattening layer. Figure 23 Schematic diagram 2 after the formation of the first flattening layer.

[0213] Figure 28 and Figure 18 The difference lies in that the via pattern may also include: an 82nd via V82 and an 83rd via V83 penetrating the fourth insulating layer and the first planarization layer. The 82nd via V82 exposes the seventh connection electrode, and the 83rd via V83 exposes the eighth connection electrode.

[0214] (7) Forming a fourth conductive layer includes: depositing a fourth conductive thin film on a substrate on which a first planarization layer has been formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer, such as... Figure 31 and Figure 32 As shown, Figure 31 Schematic diagram 2 for the fourth conductive layer. Figure 32 This is a schematic diagram of the fourth conductive layer after its formation.

[0215] Figure 32 and Figure 20 The difference is that the fourth conductive layer includes: a second power line VSSL, a second light-emitting part EML2, and a third light-emitting part EML3.

[0216] In one exemplary embodiment, the orthographic projection of the second power line VSSL on the substrate at least partially overlaps with the orthographic projection of the light-emitting driving circuit on the substrate. Specifically, the orthographic projection of the second power line VSSL on the substrate covers the orthographic projections of the initial light-emitting signal line, the first high-level power line, the first first low-level power line, and the first light-emitting clock signal lines ECLK1 to ECLK3 on the substrate, and does not overlap with the orthographic projection of the first first low-level power line on the substrate.

[0217] In one exemplary embodiment, the second light-emitting output portion EML2 extends along a second direction. In one exemplary embodiment, the second light-emitting output unit EML2 is connected to the seventh connecting electrode through the eighty-second via, and the third light-emitting output unit EML3 is connected to the eighth connecting electrode through the eighty-third via.

[0218] In one exemplary embodiment, the second light-emitting output section EML2 includes: a first output connection section EML2A, a second output connection section EML2B, and a third output connection section EML2C. The second output connection section EML2B is connected to both the first output connection section EML2A and the third output connection section EML2C. The first output connection section EML2A extends along a second direction and is located between the i-th level scan shift register and the (i+1)-th level scan shift register. The second output connection section EML2B extends along a first direction and is located between the i-th level scan shift register and the (2i-1)-th level control shift register. The third output connection section EML2C extends along the second direction and is located between the (2i+1)-th level control shift register and the (2i+2)-th level control shift register.

[0219] In one exemplary embodiment, the third light-emitting output portion EML3 extends along the second direction.

[0220] In one exemplary embodiment, the third light-emitting output section EML3 of the light-emitting output line of the i-th stage light-emitting shift register is located between the first plate GC21 of the second control capacitor of the 2i+1-th stage control shift register and the first plate GC11 of the first control capacitor of the 2i+2-th stage control shift register.

[0221] (8) Forming a light-emitting structure layer includes: coating a second planar thin film on a substrate on which a fourth conductive layer is formed; patterning the second planar thin film using a patterning process to form a second planar layer; depositing an anode thin film on the second planar layer; patterning the anode thin film using a patterning process to form an anode; depositing a pixel definition thin film on the anode; patterning the pixel definition thin film using a patterning process to form a pixel definition layer; evaporating an organic light-emitting thin film on the pixel definition layer; patterning the organic light-emitting thin film using a patterning process to form an organic light-emitting layer; depositing a cathode thin film on the organic light-emitting layer; and patterning the cathode thin film using a patterning process to form a cathode.

[0222] In one exemplary embodiment, the semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer. The active layer thin film may be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene; that is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0223] In one exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layers. The first insulating layer is called a buffer layer and is used to improve the substrate's resistance to water and oxygen.

[0224] In one exemplary embodiment, the first to fourth conductive films may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti.

[0225] In one exemplary embodiment, the first planarization layer and the second planarization layer may be made of organic materials. In one exemplary embodiment, the anode film may be indium tin oxide (ITO) or indium zinc oxide (IZO).

[0226] The display substrate described in this embodiment can be used in display products of any resolution.

[0227] This disclosure also provides a display device, including a display substrate.

[0228] In one exemplary embodiment, the display device can be a monitor, television, mobile phone, tablet computer, navigator, digital photo frame, wearable display product, or any product or component with display function.

[0229] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0230] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0231] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0232] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

[0233] In the description of the embodiments of this utility model, unless otherwise expressly specified and limited, the terms "connection," "direct connection," "indirect connection," "fixed connection," "installation," and "assembly" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection. The terms "installation," "connection," and "fixed connection" can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal communication between two components. For those skilled in the art, the specific meaning of the above terms in this utility model can be understood according to the specific circumstances.

[0234] Although the embodiments disclosed in this utility model are as described above, the content described is only for the purpose of facilitating understanding of this utility model and is not intended to limit this utility model. Any person skilled in the art to which this utility model pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this utility model, but the patent protection scope of this utility model shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: The display substrate includes a display area and a non-display area, comprising: a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes: a plurality of pixel driving circuits arranged in an array in the display area, and a light-emitting driving circuit, a scanning driving circuit, and a control driving circuit located in the non-display area. The light-emitting driving circuit and the scanning driving circuit are located on the side of the control driving circuit away from the display area. At least one pixel driving circuit includes: a write transistor, a compensation reset transistor, and a light-emitting transistor. The scanning driving circuit is configured to provide a driving signal to the compensation reset transistor, the control driving circuit is configured to provide a driving signal to the write transistor, and the light-emitting driving circuit is configured to provide a driving signal to the light-emitting transistor. The display substrate further includes: multiple light-emitting output lines connected to the light-emitting driving circuit and multiple scan output lines connected to the scan driving circuit; At least one of the light-emitting output lines includes at least two interconnected light-emitting output portions, and the scanning output line is an integrally formed structure; or, the light-emitting output line is an integrally formed structure, and at least one scanning output line includes at least two interconnected scanning output portions; or, at least one of the light-emitting output lines includes at least two interconnected light-emitting output portions, and at least one scanning output line includes at least two interconnected scanning output portions. Among them, at least two light-emitting output sections located on the same light-emitting output line are arranged in different layers, and the resistivity of the light-emitting output sections arranged in different layers is different; at least two scan output sections located on the same scan output line are arranged in different layers, and the resistivity of the scan output sections arranged in different layers is different. The pixel driving circuit includes: a data signal terminal, a control signal terminal, a scan signal terminal, and a light emission signal terminal; the display substrate also includes: N data signal lines, 2M control signal lines, 2M light emission signal lines, and 2M scan signal lines; The write transistor is electrically connected to the control signal terminal and the data signal terminal respectively, the compensation reset transistor is electrically connected to the scan signal terminal, and the light-emitting transistor is electrically connected to the light-emitting signal terminal. The data signal lines extend along a first direction, and N data signal lines are arranged along a second direction. 2M control signal lines, 2M light emission signal lines, and 2M scanning signal lines extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect. For the pixel driving circuit in row s and column t, the control signal terminal is electrically connected to the s-th control signal line, the light emission signal terminal is electrically connected to the s-th light emission signal line, the scan signal terminal is electrically connected to the s-th scan signal line, and the data signal terminal is electrically connected to the t-th data signal line. s 2M, 1 t N; The light-emitting driving circuit includes: M cascaded light-emitting shift registers, with at least one stage of the light-emitting shift register electrically connected to two light-emitting signal lines; the scanning driving circuit includes: M cascaded scanning shift registers, with at least one stage of the scanning shift register electrically connected to two scanning signal lines; the control driving circuit includes: 2M cascaded control shift registers, with at least one stage of the control shift register electrically connected to one control signal line. i M; The light-emitting shift register, scan shift register, and control shift register include: input terminals and output terminals; The output of the i-th stage light-emitting shift register is electrically connected to the 2i-1 light-emitting signal lines to the 2i light-emitting signal lines via the i-th light-emitting output line; the output of the i-th stage scan shift register is electrically connected to the 2i-1 scan signal lines to the 2i scan signal lines via the i-th scan output line; the output of the s-th stage control shift register is electrically connected to the s-th control signal line. The circuit structure layer includes: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a first planarization layer, and a fourth conductive layer, which are sequentially stacked on a substrate. When at least one of the light-emitting output lines includes at least two interconnected light-emitting output parts, the at least two light-emitting output parts located on the same light-emitting output line are located in one of the first conductive layer and the second conductive layer and one of the third conductive layer and the fourth conductive layer. When at least one of the scan output lines includes at least two interconnected scan output sections, the at least two scan output sections located on the same scan output line are located in one of the first conductive layer and the second conductive layer and one of the third conductive layer and the fourth conductive layer. When the light-emitting output line is an integrally formed structure, the light-emitting output line is located in the fourth conductive layer; When the scan output line is an integrally formed structure, the scan output line is located in the second conductive layer; The resistivity of the first conductive layer and the resistivity of the second conductive layer are both greater than the resistivity of the third conductive layer and the resistivity of the fourth conductive layer.

2. The display substrate according to claim 1, wherein, The circuit structure layer further includes: a fifth conductive layer, a sixth insulating layer, a seventh insulating layer, and a sixth conductive layer; A semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a fifth conductive layer, a sixth insulating layer, a third conductive layer, a fourth insulating layer, a first planarization layer, a fourth conductive layer, a seventh insulating layer, and a sixth conductive layer are sequentially stacked on a substrate. When at least one of the light-emitting output lines includes at least two interconnected light-emitting output parts, the at least two light-emitting output parts located on the same light-emitting output line are located in one of the first conductive layer, the second conductive layer, and the fifth conductive layer, and one of the third conductive layer, the fourth conductive layer, and the sixth conductive layer. When at least one of the scan output lines includes at least two interconnected scan output sections, the at least two scan output sections located on the same scan output line are located in one of the first conductive layer, the second conductive layer, and the fifth conductive layer, and one of the third conductive layer, the fourth conductive layer, and the sixth conductive layer. The resistivity of the first conductive layer, the resistivity of the second conductive layer, and the resistivity of the fifth conductive layer are all greater than the resistivity of the third conductive layer, the resistivity of the fourth conductive layer, and the resistivity of the sixth conductive layer.

3. The display substrate according to claim 1, wherein, When at least one of the scan output lines includes at least two interconnected scan output sections, the scan output line includes: a first scan output section, a second scan output section, a third scan output section, and a fourth scan output section extending along a second direction; The first scan output section and the second scan output section are disposed on the same layer, the third scan output section and the fourth scan output section are disposed on the same layer, and the third scan output section is located on the side of the first scan output section away from the substrate; The third scan output unit is located on the side of the first scan output unit away from the display area, the fourth scan output unit is located on the side of the first scan output unit closer to the display area, and the second scan output unit is located on the side of the fourth scan output unit closer to the display area. The first scan output unit is connected to the third scan output unit and the fourth scan output unit respectively, and the fourth scan output unit is connected to the second scan output unit. The first scan output of the i-th scan output line is connected to the output of the i-th stage scan shift register, the second scan output of the i-th scan output line is connected to the (2i-1)-th scan signal line and the 2i-th scan signal line, and the third scan output of the i-th scan output line is connected to the input of the (i+1)-th stage scan shift register.

4. The display substrate according to claim 3, wherein, The i-th scan output line is located between the i-th level scan shift register and the (i+1)-th level scan shift register.

5. The display substrate according to claim 3, wherein, When at least one of the light-emitting output lines includes at least two interconnected light-emitting output portions, the light-emitting output line includes: a first light-emitting output portion, a second light-emitting output portion, and a third light-emitting output portion extending along a second direction; The second light-emitting part and the third light-emitting part are disposed in the same layer, and the third light-emitting part is located on the side of the first light-emitting part away from the substrate; The second light-emitting part is located on the side of the first light-emitting part away from the display area, and the third light-emitting part is located on the side of the first light-emitting part closer to the display area. The first light-emitting part is connected to the second light-emitting part and the third light-emitting part, respectively. The second light-emitting output section of the i-th light-emitting output line is connected to the output terminal of the i-th stage light-emitting shift register, and the third light-emitting output section of the i-th light-emitting output line is connected to the 2i-1 light-emitting signal line and the 2i light-emitting signal line.

6. The display substrate according to claim 5, wherein, The first and third light-emitting output sections of the i-th light-emitting output line are located between the (2i+1)-th stage control shift register and the (2i+2)-th stage control shift register; The second light-emitting output portion of the i-th light-emitting output line includes: a first output connection portion, a second output connection portion, and a third output connection portion; the first output connection portion and the third output connection portion extend along a second direction, and the second output connection portion extends along a first direction; The first output connection is located between the i-th level scan shift register and the (i+1)-th level scan shift register, and is connected to the second output connection and the output terminal of the i-th level light-emitting shift register; The second output connection is located between the i-th stage scan shift register and the (2i-1)-th stage control shift register, and is connected to the third output connection. The third output connection is located between the 2i+1 level control shift register and the 2i+2 level control shift register, and is connected to the 2i-1 light-emitting signal line and the 2i light-emitting signal line.

7. The display substrate according to claim 6, further comprising: Located in the non-display area and extending along a first direction, there are: an initial light emission signal line, a first light emission clock signal line to a third light emission clock signal line, a first high-level power supply line, a first low-level power supply line, a scan initial signal line, a first scan clock signal line to a third scan clock signal line, a second high-level power supply line, a second low-level power supply line, a control initial signal line, a first control clock signal line, a second control clock signal line, a third high-level power supply line, and a third low-level power supply line; wherein, there are two of each of the first low-level power supply line, the second low-level power supply line, the first scan clock signal line, and the third scan clock signal line. Specifically, the input terminal of the first-stage light-emitting shift register is electrically connected to the initial light-emitting signal line, and the output terminal of the i-th-stage light-emitting shift register is electrically connected to the input terminal of the (i+1)-th stage light-emitting shift register; the first clock signal terminal of the i-th-stage light-emitting shift register is electrically connected to the first light-emitting clock signal line, the second clock signal terminal is electrically connected to the second light-emitting clock signal line, and the third clock signal terminal is electrically connected to the third light-emitting clock signal line; the first clock signal terminal of the (i+1)-th stage light-emitting shift register is electrically connected to the third light-emitting clock signal line, the second clock signal terminal is electrically connected to the second light-emitting clock signal line, and the third clock signal terminal is electrically connected to the first light-emitting clock signal line; the first power supply terminal of the i-th-stage light-emitting shift register is electrically connected to the first high-level power supply line, and the second power supply terminal of the i-th-stage light-emitting shift register is electrically connected to the first low-level power supply line; the input terminal of the first-stage scan shift register is electrically connected to the initial scan signal line, and the output terminal of the i-th-stage scan shift register is electrically connected to the input terminal of the (i+1)-th stage scan shift register; the first clock signal terminal of the i-th-stage scan shift register is electrically connected to the first light-emitting clock signal line, the second clock signal terminal is electrically connected to the second light-emitting clock signal line, and the third clock signal terminal is electrically connected to the first light-emitting clock signal line; the first power supply terminal of the i-th-stage light-emitting shift register is electrically connected to the first high-level power supply line, and the second power supply terminal of the i-th-stage light-emitting shift register is electrically connected to the first low-level power supply line; the input terminal of the first-stage scan shift register is electrically connected to the initial scan signal line, and the output terminal of the i-th-stage scan shift register is electrically connected to the input terminal of the (i+1)-th stage scan shift register; the first clock signal terminal of the i- The clock signal terminal is electrically connected to the first scan clock signal line, the second clock signal terminal is electrically connected to the second scan clock signal line, and the third clock signal terminal is electrically connected to the third scan clock signal line. The first power supply terminal of the i-th stage scan shift register is electrically connected to the second high-level power supply line, and the second power supply terminal of the i-th stage scan shift register is electrically connected to the second low-level power supply line. The input terminal of the first stage control shift register is electrically connected to the control initial signal line, and the output terminal of the s-th stage control shift register is electrically connected to the input terminal of the s+1-th stage control shift register. The first clock signal terminal of the s-th stage control shift register is electrically connected to the first control clock signal line, and the second clock signal terminal is electrically connected to the second control clock signal line. The first clock signal terminal of the s+1-th stage control shift register is electrically connected to the second control clock signal line, and the second clock signal terminal is electrically connected to the first control clock signal line. The first power supply terminal of the i-th stage control shift register is electrically connected to the third high-level power supply line, and the second power supply terminal of the s-th stage control shift register is electrically connected to the third low-level power supply line.

8. The display substrate according to claim 7, further comprising: A light-emitting structure layer located on the side of the circuit structure layer away from the substrate, the light-emitting structure layer comprising: light-emitting elements located in the display area and arranged in an array, the light-emitting elements comprising: an anode, an organic light-emitting layer and a cathode, the anode being located on the side of the organic light-emitting layer closer to the substrate and the cathode being located on the side of the organic light-emitting layer away from the substrate; The circuit structure layer also includes a second power line located in the non-display area, which is electrically connected to the cathode of the light-emitting element.

9. The display substrate according to claim 8, wherein, The light-emitting shift register includes multiple light-emitting transistors and multiple light-emitting capacitors; the scan shift register includes multiple scan transistors and multiple scan capacitors; the control shift register includes multiple control transistors and multiple control capacitors; the light-emitting capacitors, the scan capacitors, and the control capacitors all include a first electrode and a second electrode. The semiconductor layer includes: an active layer of multiple light-emitting transistors, an active layer of multiple scanning transistors, and an active layer of multiple control transistors. The first conductive layer includes: control electrodes of multiple light-emitting transistors, first plates of multiple light-emitting capacitors, control electrodes of multiple scanning transistors, first plates of multiple scanning capacitors, control electrodes of multiple control transistors, first plates of multiple first control capacitors, a first connecting electrode, and a second connecting electrode. The second conductive layer includes: second plates of multiple first light-emitting capacitors, second plates of multiple scanning capacitors, second plates of multiple control capacitors, and third to fifth connecting electrodes; The third conductive layer includes: an initial light-emitting signal line, a first high-level power supply line, a first low-level power supply line, a first light-emitting clock signal line to a third light-emitting clock signal line, a first electrode and a second electrode of a plurality of light-emitting transistors, a scan initial signal line, a second high-level power supply line, a second low-level power supply line, a first scan clock signal line to a third scan clock signal line, a first electrode and a second electrode of a plurality of scan transistors, a control initial signal line, a third high-level power supply line, a third low-level power supply line, a first control clock signal line, a second control clock signal line, a first electrode and a second electrode of a plurality of control transistors, and a sixth connecting electrode; The fourth conductive layer includes: a second power line.

10. The display substrate according to claim 9, wherein, The light-emitting shift register includes thirteen light-emitting transistors and three light-emitting capacitors; the scan shift register includes fourteen scan transistors and three scan capacitors; the control shift register includes eight control transistors and two control capacitors; the second terminal of the tenth light-emitting transistor is multiplexed as the output terminal of the light-emitting shift register, and the second terminal of the tenth scan transistor is multiplexed as the output terminal of the scan shift register. The control electrodes of the first light-emitting transistor to the eighth light-emitting transistor and the control electrodes of the eleventh light-emitting transistor to the thirteenth light-emitting transistor are located on the side of the control electrodes of the ninth and tenth light-emitting transistors that are far from the display area; the control electrodes of the ninth and tenth light-emitting transistors are arranged along the first direction. The control electrodes of the first scanning transistor to the eighth scanning transistor and the control electrodes of the eleventh scanning transistor to the fourteenth scanning transistor are located on the side of the control electrodes of the ninth scanning transistor and the tenth scanning transistor that are away from the display area; the control electrodes of the ninth scanning transistor and the tenth scanning transistor are arranged along the first direction; The control electrodes of the first control transistor to the third control transistor and the control electrodes of the sixth control transistor to the eighth control transistor are located on the side of the control electrodes of the fourth control transistor and the fifth control transistor that are away from the display area; the control electrodes of the fourth control transistor and the fifth control transistor are arranged along the first direction; The first connection electrode is located on the side of the control electrode of the ninth scanning transistor and the control electrode of the tenth scanning transistor away from the display area, and extends along the second direction; the second connection electrode is connected to the first electrode of the fourth scanning transistor. The second connection electrode is located on the side of the control electrode of the fourth control transistor that is away from the control electrode of the fifth control transistor, and extends along the second direction; the second connection electrode is connected to the second electrode of the fifth control transistor of the previous stage light-emitting shift register.

11. The display substrate according to claim 10, wherein, The second plates of the first light-emitting capacitor and the second plates of the second light-emitting capacitor are arranged along the second direction, and the second plate of the first light-emitting capacitor is located on the side of the second plate of the second light-emitting capacitor away from the display area. The second plates of the second light-emitting capacitor and the second plates of the third light-emitting capacitor are arranged along the first direction. The second plates of the first scanning capacitor and the second plates of the second scanning capacitor are arranged along the second direction, and the second plate of the first scanning capacitor is located on the side of the second plate of the second scanning capacitor away from the display area. The second plates of the second scanning capacitor and the second plates of the third scanning capacitor are arranged along the first direction. The second plates of the first control capacitor and the second control capacitor are arranged along the first direction. The third connecting electrode is located on the side of the second plate of the third light-emitting capacitor away from the second plate of the second light-emitting capacitor, and extends along the second direction. The third connecting electrode is connected to the second electrode of the tenth light-emitting transistor and the first electrode of the first light-emitting transistor of the next stage light-emitting shift register, respectively. The fourth connection electrode is located on the side of the second plate of the third scanning capacitor away from the second plate of the second scanning capacitor, and extends along the second direction. The fourth connection electrode is connected to the first electrode of the first scanning transistor of the next-stage scanning shift register. The fifth connecting electrode and the second plate of the first control capacitor are arranged along the first direction, and the fifth connecting electrode is located on the side of the second plate of the first control capacitor away from the display area. The fifth connecting electrode is connected to the second electrode of the second control transistor.

12. The display substrate according to claim 10, wherein, The initial light-emitting signal line, the third scan clock signal line, the first scan clock signal line, the first low-level power supply line, and the first scan clock signal line are arranged sequentially along the direction close to the display area. The first and second electrodes of the first light-emitting transistor to the first and second electrodes of the eighth light-emitting transistor and the first and second electrodes of the eleventh light-emitting transistor to the first and second electrodes of the thirteenth light-emitting transistor are located between the first low-level power supply line and the second scan clock signal line. The second scan clock signal line is located on the side of the first low-level power supply line close to the display area. The first high-level power supply line is located on the side of the second scan clock signal line close to the display area. The first and second electrodes of the ninth light-emitting transistor to the first and second electrodes of the tenth light-emitting transistor are located between the first high-level power supply line and the second low-level power supply line. The second low-level power supply line is located on the side of the first high-level power supply line close to the display area. The initial scan signal line, the first and third scan clock signal lines, the first scan clock signal line, the second and third scan clock signal lines, the second and first scan clock signal lines, and the first and second low-level power supply lines are arranged sequentially along the side of the second and first low-level power supply lines closest to the display area. The first and second poles of the first scan transistor to the first and second poles of the eighth scan transistor, the first and second poles of the tenth scan transistor to the first and second poles of the fourteenth scan transistor, and the third scan output section are located between the first and second low-level power supply lines and the second scan clock signal lines. The second scan clock signal line is located on the side of the first and second low-level power supply lines closest to the display area, and the second high-level power supply line is located on the side of the second scan clock signal lines closest to the display area. The first and second poles of the ninth scan transistor to the first and second poles of the tenth scan transistor are located between the second high-level power supply lines and the second low-level power supply lines. The second low-level power supply line is located on the side of the second high-level power supply lines closest to the display area. The control initial signal line, the first control clock signal line, the second control clock signal line, and the third low-level power supply line are arranged sequentially along the direction of the second low-level power supply line near the display area. The first and second poles of the first control transistor to the first and second poles of the eighth control transistor and the sixth connection electrode are located between the third low-level power supply line and the third high-level power supply line. The third high-level power supply line is located on the side of the third low-level power supply line near the display area. The sixth connection electrode is connected to the fifth connection electrode and the control electrode of the fourth control transistor, respectively.

13. The display substrate according to claim 9, wherein, The orthographic projection of the second power line on the substrate at least partially overlaps with the orthographic projection of the light-emitting driving circuit on the substrate; The orthographic projection of the second power line on the substrate covers the orthographic projections of the initial light-emitting signal line, the first high-level power line, the first low-level power line, the first light-emitting clock signal line to the third light-emitting clock signal line on the substrate, and does not overlap with the orthographic projection of the second low-level power line on the substrate.

14. The display substrate according to claim 10, wherein, The second conductive layer further includes: the first scan output section and the second scan output section.

15. The display substrate according to claim 14, wherein, The third conductive layer further includes a third scan output section and a fourth scan output section.

16. The display substrate according to claim 10, wherein, The first conductive layer further includes a first light-emitting output section.

17. The display substrate according to claim 16, wherein, The fourth conductive layer includes a second light-emitting part and a third light-emitting part.

18. The display substrate according to claim 17, wherein, The third conductive layer may also include: a seventh connecting electrode and an eighth connecting electrode; The seventh connecting electrode is connected to the first light-emitting part and the second light-emitting part, respectively, and the eighth connecting electrode is connected to the first light-emitting part and the third light-emitting part, respectively.

19. A display device comprising a display substrate as described in any one of claims 1 to 18.

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