Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate includes a plurality of sub-pixels (10) on a substrate (001), a plurality of power signal lines (300) extending along a first direction and arranged along a second direction; at least part of the sub-pixels (10) includes a plurality of first sub-pixels (010), along a third direction perpendicular to the substrate (001), at least one power signal line (300) includes a first power supply part (301), the first power supply part (301) includes a first main body part (31) and a second main body part (32); in the second direction, the maximum size of the main body electrode (1040) of the first sub-pixel (010) is not less than the maximum size of the first power supply part (301), the maximum size of the first main body part (31) is greater than the maximum size of the second main body part (32), the line connecting the two end points of the main body electrode (1040) of the first sub-pixel (010) farthest apart in the second direction is an end point connecting line, and in the third direction, the end point connecting line intersects the first main body part (31). It is beneficial to increase the flatness of the connecting electrode in the light-emitting element and reduce the color deviation phenomenon of the display product.

Description

Technical Field

[0001] At least one embodiment of this disclosure relates to a display substrate and a display device. Background Technology

[0002] Currently, active-matrix organic light-emitting diode (AMOLED) flexible screen technology is maturing, possessing characteristics such as flexibility, high contrast, and low power consumption, thus showing great development potential. With the continuous development of display technology, optimizing display effects has become an inevitable trend. To improve the performance of display devices, some display products reduce color shift by optimizing the arrangement of conductive structures and light-emitting elements within pixels. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a display substrate and a display device.

[0004] This disclosure provides a display substrate, comprising: a substrate; a plurality of sub-pixels located on the substrate, at least a portion of the sub-pixels including light-emitting elements and pixel circuits, the light-emitting element including a light-emitting functional layer and a first electrode and a second electrode located on both sides of the light-emitting functional layer along a direction perpendicular to the substrate, the first electrode being located between the light-emitting functional layer and the substrate, the light-emitting element being at least partially located in a light-emitting region, the first electrode of the light-emitting element including a main electrode overlapping the light-emitting region; and a plurality of power signal lines, at least a portion of the plurality of power signal lines extending along a first direction and arranged along a second direction, the plurality of power signal lines being located between the substrate and the first electrode of the light-emitting element, the first direction being perpendicular to the substrate and the second electrode being arranged along a second direction. The second direction intersects, wherein at least some sub-pixels include a plurality of first sub-pixels, and along a third direction perpendicular to the substrate, at least one power signal line includes a first power portion overlapping with the main electrode of at least one of the plurality of first sub-pixels, each first power portion including a first main portion and a second main portion; in the second direction, the maximum size of the main electrode of the first sub-pixel is not less than the maximum size of its corresponding first power portion, the maximum size of the first main portion in the first power portion is greater than the maximum size of the second main portion, and the line connecting the two endpoints of the main electrodes of the first sub-pixel that are furthest apart in the second direction is an endpoint connection line, and in the third direction, the endpoint connection line overlaps with the first main portion.

[0005] For example, according to an embodiment of this disclosure, the plurality of power signal lines include a first power signal line and a second power signal line, wherein the maximum dimensions of the first power signal line and the second power signal line in the second direction are a first dimension and a second dimension, respectively, and the second dimension is smaller than the first dimension.

[0006] For example, according to an embodiment of this disclosure, the plurality of first sub-pixels include at least one first type sub-pixel, the first power supply portion overlapping with the main electrode of the first type sub-pixel is a first type power supply portion, and the first main body portion of the first type power supply portion has an asymmetrical structure.

[0007] For example, according to an embodiment of the present disclosure, the first main body of the first type of power supply includes a first protrusion located on one side of a first symmetrical center line extending along the first direction of the second main body.

[0008] For example, according to an embodiment of this disclosure, the extension direction of the center line of symmetry of the portion of the first type power supply unit other than the first protrusion intersects the extension direction of the second center line of symmetry of the main electrode of the first type sub-pixel.

[0009] For example, according to an embodiment of this disclosure, the plurality of first sub-pixels further includes at least one second type sub-pixel, the first power supply portion overlapping with the main electrode of the second type sub-pixel is the second type power supply portion, the second type power supply portion includes a third symmetry center line extending along the first direction, the main electrode of the second type sub-pixel includes a fourth symmetry center line extending along the first direction, the third symmetry center line of the second type power supply portion in the same column of power signal lines and the fourth symmetry center line of the second type sub-pixel overlapping with the second type power supply portion are located in the same plane perpendicular to the substrate.

[0010] For example, according to an embodiment of the present disclosure, the main electrode of the first sub-pixel includes opposing first corner portions and second corner portions, as well as opposing third and fourth corner portions, wherein the orthographic projection of at least one of the first and second corner portions on the substrate at least partially overlaps with the orthographic projection of the first symmetry center line on the substrate, and the orthographic projection of the fourth corner portion on the substrate at least partially overlaps with the orthographic projection of the first protrusion on the substrate.

[0011] For example, according to an embodiment of the present disclosure, the first main body of the second type power supply includes a second protrusion and a third protrusion, the second protrusion and the third protrusion being symmetrically distributed with respect to the third symmetry center line, the main electrode of the second type sub-pixel including opposing first corner and second corner, and opposing third triangular and fourth corner, the orthographic projection of the second protrusion on the substrate at least partially overlapping the orthographic projection of one of the first corner and the second corner on the substrate, and the orthographic projection of the third protrusion on the substrate at least partially overlapping the orthographic projection of the other of the first corner and the second corner on the substrate.

[0012] For example, according to an embodiment of this disclosure, along the third direction, the light-emitting area of ​​the second type of sub-pixel overlaps with at least one of the second protrusion and the third protrusion.

[0013] For example, according to an embodiment of the present disclosure, in the second direction, the maximum size of the first main body of the second type power supply is greater than the maximum size of the first main body of the first type power supply, and the ratio of the maximum size of the second main body of the first type power supply to the maximum size of the second main body of the second type power supply is 0.9 to 1.1.

[0014] For example, according to an embodiment of this disclosure, the maximum dimension of the first main body of the second type of power supply in the second direction is 1.1-2 times the maximum dimension of the second main body of the second type of power supply in the second direction.

[0015] For example, according to an embodiment of this disclosure, each of the multiple adjacent power signal lines includes a plurality of power supply sections arranged along the first direction, and a first connection section electrically connected to both adjacent power supply sections is provided between two adjacent power supply sections. The plurality of power supply sections include the first power supply section, and the ratio of the maximum dimension of the power supply section in the second direction to the maximum dimension of the first connection section in the second direction is 1.5-5.

[0016] For example, according to an embodiment of the present disclosure, the first type power supply unit includes a first subtype power supply unit and a second subtype power supply unit. The second main body of the first type power supply unit includes a first side and a second side opposite to each other in the second direction. The first protrusion in the first subtype power supply unit is disposed on the first side of the second main body, and the first protrusion in the second subtype power supply unit is disposed on the second side of the second main body.

[0017] For example, according to an embodiment of this disclosure, the main electrode of the first sub-pixel includes a plurality of corners, the plurality of corners including the first corner, the second corner, the third corner and the fourth corner, each side of the main electrode or its extension line is connected sequentially to form a polygon, and the plurality of vertices of the polygon have regions that do not overlap with the plurality of corners of the corresponding main electrode; the area of ​​the third corner and the vertices of the polygon corresponding to it that do not overlap is greater than the area of ​​at least some of the other corners and the vertices of the polygon corresponding to that corner that do not overlap.

[0018] For example, according to an embodiment of this disclosure, the at least some sub-pixels further include a plurality of second sub-pixels. Along the third direction, the at least one power signal line includes a second power portion overlapping with the main electrode of at least one of the plurality of second sub-pixels. The second power portion includes a fifth symmetry center line extending along the first direction. The main electrode of the second sub-pixel includes a sixth symmetry center line extending along the first direction. The fifth symmetry center line of the second power portion in the same column of power signal lines and the sixth symmetry center line of the second sub-pixel overlapping with the second power portion are located in the same plane perpendicular to the substrate.

[0019] For example, according to an embodiment of the present disclosure, the orthographic projection of the main electrode of the second sub-pixel on the substrate overlaps with the orthographic projection of the second power supply portion on the substrate, and the overlapping area is at least 90% of the orthographic projection area of ​​the main electrode of the second sub-pixel on the substrate.

[0020] For example, according to an embodiment of the present disclosure, in the second direction, the maximum size of the second power supply portion is smaller than the maximum size of the first main body portion of the first power supply portion, and the ratio of the maximum size of the second power supply portion to the maximum size of the second main body portion of the first power supply portion is 0.9 to 1.1.

[0021] For example, according to an embodiment of this disclosure, the display substrate further includes: a plurality of data lines extending along the first direction and arranged along the second direction, the plurality of data lines being disposed on the same layer as the plurality of power signal lines, wherein the data lines disposed between two adjacent power signal lines include a first data line and a second data line arranged along the second direction, the first data line and the second data line being symmetrically distributed with respect to a seventh symmetry center line between the first data line and the second data line; the at least some sub-pixels further include a plurality of third sub-pixels, the main electrode of the light-emitting element of at least one of the plurality of third sub-pixels at least partially overlapping the data lines, and the overlapping area of ​​the main electrode of the third sub-pixel and the data lines being substantially symmetrical with respect to the seventh symmetry center line.

[0022] For example, according to an embodiment of this disclosure, the display substrate further includes: a plurality of second connection portions disposed on the same layer as at least a portion of the plurality of power signal lines, each second connection portion including a first connector and a second connector, the plurality of second connection portions being arranged in an array along the first direction and the second direction to form a plurality of second connection portion rows and a plurality of second connection portion columns, the power signal lines including a plurality of power portions arranged along the first direction, a first connection portion electrically connected to both adjacent power portions being disposed between two adjacent power portions, the power portions included in the plurality of power signal lines being arranged in an array along the first direction and the second direction to form a plurality of power portion rows and a plurality of power portion columns, the plurality of second connection portion rows and the plurality of power portion rows being arranged alternately in the first direction, and two adjacent second connection portions in the same second connection portion row being disposed on both sides of the data line.

[0023] For example, according to an embodiment of this disclosure, the connecting electrode of the light-emitting element does not substantially overlap with the first connecting portion; in the first direction, the maximum size of the main electrode of the first sub-pixel is not less than the maximum size of the first main portion in the corresponding first power supply portion.

[0024] For example, according to an embodiment of this disclosure, the first connector is electrically connected to the connection electrode of the first sub-pixel or the connection electrode of the second sub-pixel, and the second connector is electrically connected to the connection electrode of the third sub-pixel.

[0025] For example, according to an embodiment of the present disclosure, the first connecting portion includes at least one perforated portion, the area of ​​which is 1 / 4 to 1 / 3 of the area of ​​the first connecting portion.

[0026] This disclosure provides a display device including any of the above-described display substrates. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0028] Figure 1A This is a schematic diagram of a partial cross-sectional structure of a display substrate.

[0029] Figure 1B This is a schematic diagram of a partial cross-sectional structure of another type of display substrate.

[0030] Figure 2A This is a schematic diagram showing the relationship between pixel arrangement and conductive layer overlap in a display substrate.

[0031] Figure 2BThis is a schematic diagram showing the relationship between pixel arrangement and conductive layer overlap in another type of display substrate.

[0032] Figure 3 This is a schematic diagram of a pixel arrangement structure in a display substrate according to an embodiment of the present disclosure.

[0033] Figure 4 For along Figure 3 A schematic diagram of the local cross-section structure intercepted by line AA'.

[0034] Figure 5 This is a schematic diagram of the stacked structure of a second conductive layer and a first electrode of a light-emitting element in a display substrate according to an embodiment of the present disclosure.

[0035] Figure 6 This is a partial structural diagram of the second conductive layer in a display substrate according to an embodiment of the present disclosure.

[0036] Figure 7 This is a partial structural schematic diagram of the first electrode of a light-emitting element in a display substrate according to an embodiment of the present disclosure.

[0037] Figure 8 This is an equivalent diagram of a pixel circuit provided according to an embodiment of the present disclosure.

[0038] Figure 9 This is a schematic diagram of the stacked structure of the light-shielding layer, active semiconductor pattern, and first connection layer in the pixel circuit provided according to an embodiment of the present disclosure.

[0039] Figure 10 This is a schematic diagram of the stacked structure of a light-shielding layer, an active semiconductor pattern, a first connection layer, a second connection layer, a semiconductor layer, and a third connection layer in a pixel circuit according to an embodiment of the present disclosure.

[0040] Figure 11 This is a partial structural schematic diagram of the first conductive layer provided according to an embodiment of the present disclosure.

[0041] Figure 12 This is a schematic diagram of the stacked structure of a light-shielding layer, an active semiconductor pattern, a first connection layer, a second connection layer, a semiconductor layer, a third connection layer, and a first conductive layer in a pixel circuit according to an embodiment of the present disclosure.

[0042] Figure 13 This is a schematic diagram of the stacked structure of the first conductive layer and the second conductive layer according to an embodiment of the present disclosure. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0044] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0045] The features such as "perpendicular," "parallel," and "identical" used in this disclosure include those strictly defined as "perpendicular," "parallel," and "identical," as well as those containing a certain degree of error, such as "approximately perpendicular," "approximately parallel," and "approximately identical." Taking into account measurement and the errors associated with the measurement of a specific quantity (i.e., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. The term "center" in this disclosure can include a strictly geometrically centered location and an approximate center location within a small area surrounding the geometrically centered location. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0046] The performance specifications of organic light-emitting diode (OLED) display products can include power consumption, brightness, and color shift. Factors affecting color shift in OLED display products include the flatness of the anode. Optimizing the flatness of the anode in the light-emitting element can prevent the deviation of the emitted light, thereby reducing color shift and other phenomena in the display product.

[0047] Figure 1A This is a schematic diagram of a partial cross-sectional structure of a display substrate. (Example) Figure 1AAs shown, the display substrate includes a film layer 91, which includes a substrate, an active semiconductor layer on the substrate, and at least one interconnect layer on the side of the active semiconductor layer away from the substrate. The display substrate also includes a conductive layer 11 on the film layer 91, which may include traces such as data lines or power signal lines. The display substrate further includes a planarization layer 12 on the side of the conductive layer 11 away from the film layer 91, an anode 13 on the side of the planarization layer 12 away from the conductive layer 11, and a pixel defining layer 14 on the side of the anode 13 away from the planarization layer 12. The pixel defining layer 14 includes a plurality of openings 15-17 for defining the light-emitting area of ​​a sub-pixel. The plurality of openings 15-17 expose portions of the anode 13. When a subsequent organic light-emitting layer is formed in the openings 15-17 of the pixel defining layer 14, the organic light-emitting layer contacts the anode 13, thereby enabling this portion to drive the organic light-emitting layer to emit light.

[0048] For example, in a display substrate, the provision of the conductive layer 11 may have a significant impact on the light emission effect of the light-emitting element. For instance, it may disrupt the anode flatness in the light-emitting element, thereby causing color shift in the light-emitting element.

[0049] like Figure 1A As shown, the conductive layer 11 has a relatively large thickness, for example, 0.6-0.9 μm, which causes the surface of the planarization layer 12 on the conductive layer 11 facing the anode 13 to be uneven. For example, the distance between the surface of the planarization layer 12 away from the film layer 91 and the surface of the film layer 91 away from the planarization layer 12 directly above the conductive layer 11 (e.g., data lines, power signal lines, and patterns of the same material as it), is h1. The distance between the surface of the planarization layer 12 away from the film layer 91 and the surface of the film layer 91 away from the planarization layer 12 at the location directly above the area where the conductive layer 11 is not provided, is h2. h1>h2.

[0050] like Figure 1AAs shown, within opening 16, a conductive layer 11 is positioned directly beneath a portion of the planarization layer 12, while no conductive layer 11 is positioned directly beneath the other portion. Consequently, the surface of the planarization layer 12 facing the anode 13 within opening 16 is not flat, resulting in an uneven surface for the anode 13 located on the planarization layer 12. For example, for the anode 13 located within opening 16, the distance between the surface of the anode 13 directly above the conductive layer 11 that is away from the film layer 91 and the surface of the film layer 91 that is away from the anode 13 is h3; the distance between the surface of the anode 13 located where the conductive layer 11 is not positioned and the surface of the film layer 91 that is away from the anode 13 is h4, where h3 > h4. Therefore, the anode 13 within opening 16 is "tilted." Similarly, the anode 13 within opening 15 is also "tilted," and depending on the position of the conductive layer 11, the "tilting direction" of the anode 13 within opening 15 differs from that within opening 16, resulting in inconsistent intensity of light emitted by the sub-pixels corresponding to openings 15 and 16 in different directions. For example, taking the direction indicated by the arrow in the X direction as right, the light intensity emitted by the sub-pixel light-emitting areas defined by openings 15 and 16 is inconsistent to the left and right. No conductive layer 11 is provided directly below the anode 13 within opening 17, therefore the surface of the anode 13 within opening 17 is essentially flat and not "tilted," resulting in consistent light intensity emitted by the sub-pixel light-emitting areas defined by opening 17 in different directions. For the light-emitting areas of three adjacent sub-pixels of different colors defined by openings 15-17, the anode 13 within opening 15 is "tilted" to the left, the anode 13 within opening 16 is "tilted" to the right, and the anode 13 within opening 17 is not tilted. Thus, the "tilt" directions of the anodes 13 of different colors are different, causing a mismatch in the light intensity emitted by the light-emitting areas of the three sub-pixels to the left and right. Display devices using such a display substrate will experience large-viewing-angle color shift, resulting in a color shift phenomenon similar to one side appearing red and the other bluish when viewed by the human eye.

[0051] Figure 1B This is a schematic diagram of a partial cross-sectional structure of another type of display substrate. Figure 1B The display substrate shown includes Figure 1A The diagram shows a film layer 91, a conductive layer 11, a planarization layer 12, an anode 13, and a pixel defining layer 14. (As shown...) Figure 1B As shown, the planarization layer 12 in the display substrate includes vias 18 to allow the anode 13 to be electrically connected to the conductive layer 11. The pixel defining layer 14 includes openings 19 to expose a portion of the anode 13, and when a subsequent organic light-emitting layer is formed in the openings 19, the organic light-emitting layer contacts the anode 13 to form a light-emitting area.

[0052] like Figure 1BAs shown, via 18 is located outside the light-emitting area. Since the anode 13 located around via 18 is tilted, a certain distance should be set between the light-emitting area and via 18 to ensure the flatness of the anode 13 in the light-emitting area, thereby avoiding color shift of the display substrate.

[0053] refer to Figures 1A-1B The positional relationship between the conductive layer 11 and the anode 13, and the positional relationship between the via 18 provided in the planarization layer 12 and the anode 13, will affect the planarity of the anode 13 in the light-emitting area, thereby causing the display substrate to be prone to color shift.

[0054] Figure 2A This is a schematic diagram showing the relationship between pixel arrangement and conductive layer overlap in a display substrate; Figure 2B Figure 2C is a schematic diagram of the pixel arrangement and the overlapping relationship of the conductive layer in another display substrate; Figure 2C is a schematic diagram of the overlapping relationship of a sub-pixel and the conductive layer in a display substrate.

[0055] For clarity of illustration, Figure 2A and Figure 2B This illustrates the matching relationship between the anode of the light-emitting element and the conductive layer connected to it in a pixel circuit. (Reference) Figure 2A and Figure 2B The conductive layer includes multiple conductive components, and along a direction perpendicular to the substrate of the display substrate, the anode of the light-emitting element at least partially overlaps with the conductive components in the conductive layer. The display substrate includes multiple sub-pixels, such as a blue sub-pixel 01 configured to emit blue light, a red sub-pixel 02 configured to emit red light, and a green sub-pixel 03 configured to emit green light, wherein the green sub-pixel 03 configured to emit green light includes a first green sub-pixel 031 and a second green sub-pixel 032. The light-emitting element of each sub-pixel includes a light-emitting area, which, for example, can be defined by multiple openings in the pixel defining layer.

[0056] like Figure 2A As shown, the luminous area corresponding to each sub-pixel can be referenced to the range indicated by the dashed lines. For the blue sub-pixel 01 configured to emit blue light, its luminous area includes an overlapping area 0110 and a non-overlapping area 0111, and the area of ​​the non-overlapping area 0111 is larger than the area of ​​the overlapping area 0110. Figure 1AAs can be seen from the display substrate, in the overlapping region 0110, the distance between the surface of the anode layer (not shown in the figure) of the substrate away from the substrate and the surface of the substrate away from the anode corresponds to h3. In the non-overlapping region 0111, the distance between the surface of the anode layer away from the substrate and the surface of the substrate layer away from the anode corresponds to h4, where h3 > h4. Therefore, the anode 13 in the light-emitting area of ​​the blue sub-pixel 01 will be "tilted". Simultaneously, the distribution of the non-overlapping region 0111 relative to the overlapping region 0110 is not symmetrical.

[0057] For example, in some embodiments of this disclosure, when the non-overlapping areas within the light-emitting region are symmetrically distributed relative to the overlapping areas, the anode within the light-emitting region will undergo "symmetrical tilting," meaning that the direction of light tilt caused by the non-overlapping areas within the light-emitting region is symmetrical. At this time, relative to... Figure 2A The color shift of the sub-pixels will be weakened to a certain extent when the non-overlapping areas 0111 and 0110 are symmetrically distributed relative to the overlapping areas due to the asymmetrical arrangement of the non-overlapping areas and the overlapping areas.

[0058] like Figure 2B As shown, the display substrate includes multiple sub-pixels, such as a blue sub-pixel 04 configured to emit blue light, a red sub-pixel 05 configured to emit red light, and a green sub-pixel 06 configured to emit green light. The green sub-pixel 06 configured to emit green light includes a first green sub-pixel 0061 and a second green sub-pixel 0062. Compared to... Figure 2A , and like Figure 2B In sub-pixels 04 and 05, the overlapping conductive layers of the anodes within the light-emitting regions need to have good flatness. In sub-pixels 0062 or 0061, the non-overlapping areas of the anodes and conductive layers within the light-emitting regions have a certain degree of symmetry relative to the overlapping areas. Therefore, Figure 2B The color shift of the display substrate in the middle is relatively weak.

[0059] Therefore, in pixel circuits, the conductive layer overlapping the anode in the light-emitting region of the sub-pixel's light-emitting element must maintain a certain degree of flatness to prevent the anode in the sub-pixel's light-emitting region from "tilting". At the same time, when non-overlapping areas are generated due to actual pattern requirements, the symmetry of the distribution of non-overlapping areas relative to overlapping areas will also affect the light-emitting effect.

[0060] This disclosure provides a display substrate and a display device. The display substrate includes a substrate, a plurality of sub-pixels, and a plurality of power signal lines. Multiple sub-pixels are located on a substrate. At least some sub-pixels include light-emitting elements and pixel circuits. The light-emitting element includes a light-emitting functional layer and a first electrode and a second electrode located on both sides of the light-emitting functional layer along a direction perpendicular to the substrate. The first electrode is located between the light-emitting functional layer and the substrate. The light-emitting element is at least partially located in the light-emitting area. The first electrode of the light-emitting element includes a main electrode overlapping the light-emitting area. At least some of multiple power signal lines extend along a first direction and are arranged along a second direction. The multiple power signal lines are located between the substrate and the first electrode of the light-emitting element. The first direction and the second direction intersect. At least some sub-pixels include multiple first sub-pixels. Along a third direction perpendicular to the substrate, at least one power signal line includes a first power portion overlapping at least one main electrode of the multiple first sub-pixels. Each first power portion includes a first main portion and a second main portion. In the second direction, the maximum size of the main electrode of the first sub-pixel is not less than the maximum size of its corresponding first power portion. The maximum size of the first main portion in the first power portion is greater than the maximum size of the second main portion. The line connecting the two farthest endpoints of the main electrodes of the first sub-pixel in the second direction is the endpoint connection line. In the third direction, the endpoint connection line overlaps with the first main portion. The present invention designs the matching form between the pixel circuit and the light-emitting element, which helps to improve the flatness of the conductive layer overlapping with the light-emitting element and reduces the probability of color shift and other phenomena in the display product.

[0061] The display substrate and display device provided in the embodiments of this disclosure are described below with reference to the accompanying drawings.

[0062] Figure 3 This is a schematic diagram of a pixel arrangement structure in a display substrate according to an embodiment of the present disclosure; Figure 4 It is along Figure 3 A schematic diagram of the local cross-section structure intercepted by line AA' shown; Figure 5 This is a schematic diagram of the stacked structure of a second conductive layer and a first electrode of a light-emitting element in a display substrate according to an embodiment of the present disclosure; Figure 6 This is a partial structural schematic diagram of the second conductive layer in a display substrate according to an embodiment of the present disclosure; Figure 7 This is a partial structural schematic diagram of the first electrode of a light-emitting element in a display substrate according to an embodiment of the present disclosure.

[0063] refer to Figure 3 and Figure 4 The display substrate includes a substrate 001 and a plurality of sub-pixels 10, the plurality of sub-pixels 10 being located on the substrate 001, and at least some of the sub-pixels 10 including a light-emitting element 100 and a pixel circuit 200 (see [reference]). Figure 13For example, pixel circuit 200 is configured to drive light-emitting element 100 to emit light. Light-emitting element 100 includes light-emitting functional layer 101 and a first electrode 102 and a second electrode 1022 located on both sides of light-emitting functional layer 101 along a direction Z perpendicular to substrate 001. The first electrode 102 is located between light-emitting functional layer 101 and substrate 001.

[0064] refer to Figure 3 and Figure 4 A structural layer 1004 is disposed on the side of the first electrode 102 of the light-emitting element 100 away from the second electrode 1022. The structural layer 1004 may include, for example, a substrate, an active semiconductor pattern layer, a gate line layer, a data line layer, and multiple insulating layers. The display substrate also includes a pixel defining pattern 150, which is located on the side of the first electrode 102 of the light-emitting element 100 away from the substrate 001. The pixel defining pattern 150 includes multiple openings 160 and defining portions 170 surrounding the multiple openings 160. The multiple light-emitting elements 100 are at least partially located in the multiple openings 160.

[0065] For example, the limiting portion 170 may define the size of the opening 160. For example, the material of the limiting portion 170 may include polyimide, acrylic, or polyethylene terephthalate, etc.

[0066] refer to Figure 3 and Figure 4 The pixel circuit 200 includes a light-emitting control transistor T6 (see [link]). Figure 8 The first electrode 102 of the light-emitting element 100 is electrically connected to the light-emitting control transistor T6.

[0067] For example, the light-emitting element 100 is at least partially located in the light-emitting region 103, and the first electrode 102 of the light-emitting element 100 includes a main electrode 104 overlapping the light-emitting region 103. The portion of the light-emitting element 100 located in the opening 160 is the light-emitting region 103, and the orthogonal projection area of ​​the light-emitting region 103 on the substrate 001 is surrounded by the orthogonal projection of the main electrode 104 on the substrate. For example, the main electrode 104 may be the portion of the first electrode 102 excluding the connecting electrode (see description below). In some embodiments of this disclosure, the electrode portion of the first electrode 102 excluding the connecting electrode and the main electrode also includes a protruding electrode (not shown in the figures), for example, the protruding electrode protrudes relative to the main electrode of the first electrode 102. For example, the protruding electrode may be configured to shield a portion of the structure in the pixel circuit 200. For example, the protruding electrode may also be configured to form a capacitor with some conductive structures in the pixel circuit 200.

[0068] For example, the shape of the main electrode 104 may be the same as the shape of the opening 160 of the pixel-defining pattern 150; for example, the shape of the main electrode 104 may also be different from the shape of the opening 160 of the pixel-defining pattern 150, and the embodiments of this disclosure are not limited in this regard. For example, the main electrode 104 may be polygonal. For example, the apex corner of the polygonal main electrode 104 may be chamfered. For example, the boundary of the main electrode 104 may be formed by the edges of the protruding electrodes in the main electrode 104 smoothly transitioning from both ends of the protruding electrodes. For example, the main electrode 104 may include multiple protruding electrodes.

[0069] For example, the opening 160 of the pixel-defined pattern 150 is configured to define the light-emitting area 103 of the light-emitting element 100. For example, the light-emitting elements 100 of a plurality of sub-pixels 10 can be provided in a one-to-one correspondence with a plurality of openings 160. For example, the light-emitting element 100 may include a portion located in the opening 160, and a portion overlapping with the defining portion 170 in a direction perpendicular to the substrate 001. For example, the orthogonal projection area of ​​the light-emitting element 100 on the substrate 001 may be larger than the orthogonal projection area of ​​the opening region of the opening 160 on the substrate 001.

[0070] For example, the opening 160 of the pixel defining pattern 150 is configured to expose the first electrode 102 of the light-emitting element 100, and the exposed first electrode 102 is at least partially in contact with the light-emitting functional layer 101 in the light-emitting element 100. For example, at least a portion of the first electrode 102 is located between the defining portion 170 and the substrate 001. For example, when the light-emitting functional layer 101 is located in the opening 160 of the pixel defining pattern 150, the first electrode 102 and the second electrode 1022 located on both sides of the light-emitting functional layer 101 can drive the light-emitting functional layer 101 in the opening 160 of the pixel defining pattern 150 to emit light.

[0071] For example, the first electrode 102 can be an anode, and the second electrode 1022 can be a cathode. For example, the cathode can be formed of a material with high conductivity and low work function; for example, the cathode can be made of a metallic material. For example, the anode can be formed of a conductive material with a high work function.

[0072] For example, the light-emitting area 103 mentioned above can refer to the area where the light-emitting element 100 effectively emits light, and the shape of the light-emitting area 103 refers to a two-dimensional shape. For example, the shape of the light-emitting area 103 can be the same as the shape of the opening 160 of the pixel-defined pattern 150. For example, the opening 160 of the pixel-defined pattern 150 can be a shape with a smaller size on the side closer to the substrate 001 and a larger size on the side farther from the substrate 001. For example, the shape of the light-emitting area 103 can be approximately the same in size and shape as the opening 160 of the pixel-defined pattern 150 on the side closer to the substrate 001.

[0073] refer to Figure 3 , Figure 4 and Figure 6 The display substrate also includes a plurality of power signal lines 300, at least a portion of which extend along a first direction N and are arranged along a second direction Y. The plurality of power signal lines 300 are located between the substrate 001 and the first electrode 102 of the light-emitting element 100, and the first direction N intersects the second direction Y. For example, the first direction N may be perpendicular to the second direction Y.

[0074] For example, pixel circuit 200 also includes light-emitting control transistor T5 (such as...) Figure 8 As shown, the light-emitting control transistor T5 is electrically connected to the power signal line 300. For example, multiple power signal lines 300 can be disposed in the same conductive layer and configured to provide power signals to the pixel circuit.

[0075] refer to Figures 3-6 At least some of the sub-pixels 10 include a plurality of first sub-pixels 010, and along a third direction Z perpendicular to the substrate 001, at least one power signal line 300 includes a first power supply section 301 that overlaps with the main electrode 1040 of at least one of the plurality of first sub-pixels 010.

[0076] For example, such as Figure 3 As shown, the first sub-pixel 010 can be a blue sub-pixel configured to emit blue light. The first sub-pixel 010 can include different types of first sub-pixels. Figure 3 The various first sub-pixels 010 shown include four different configurations. In some embodiments of this disclosure, multiple arrangement methods may also be adopted according to the actual layout design requirements, and the embodiments of this disclosure do not limit this.

[0077] For example, refer to Figures 3-5 The main electrode 1040 in the first sub-pixel 010 is disposed on the side of the first power supply section 301 away from the substrate 001, and the first power supply section 301 and the main electrode 1040 overlap at least partially for each main electrode 1040.

[0078] refer to Figures 3-5 Each first power supply unit 301 includes a first main body 31 and a second main body 32. In the second direction Y, the maximum size M1 of the main electrode 1040 of the first sub-pixel 010 is not less than the maximum size L1 of its corresponding first power supply unit 301. The maximum size L11 of the first main body 31 in the first power supply unit 301 is greater than the maximum size L12 of the second main body 32. For example, the first power supply unit 301 corresponding to the main electrode 1040 of the first sub-pixel 010 refers to the first power supply unit 301 that overlaps with the main electrode 1040 of the first sub-pixel 010.

[0079] refer to Figures 3-5 The connection between the two farthest endpoints A1 and A2 of the main electrode 1040 of the first sub-pixel 010 in the second direction Y is the endpoint connection line L2. In the third direction Z, the endpoint connection line L2 overlaps with the first main body 31.

[0080] For example, refer to Figures 3-5 The first main body portion 31 and the second main body portion 32 are two adjacent parts of the first power supply portion 301. In the second direction Y, the maximum size L11 of the first main body portion 31 in the main electrode 1040 of the first power supply portion 301 is greater than the maximum size L12 of the second main body portion 32. The orthographic projection area of ​​the first main body portion 31 on the substrate 001 is greater than the orthographic projection area of ​​the second main body portion 32 on the substrate 001. By overlapping the endpoint connection line L2 of the main electrode 1040 with the first main body portion 31, the larger area portion of the main electrode 1040 can overlap with the first main body portion 31, thereby ensuring a large overlap area between the main electrode 1040 and the first power supply portion 301. For example, the extension direction of the endpoint connection line L2 on the main electrode 1040 can be determined according to the arrangement direction of the main electrode 1040. For example, the endpoint connection line L2 can extend along the first direction N; for example, the endpoint connection line L2 can also extend along the second direction Y. The embodiments of this disclosure do not limit this.

[0081] For example, the first main body 31 and the second main body 32 are an integrated structure.

[0082] For example, in the second direction Y, in this embodiment, the maximum size L1 of the first power supply unit 301 is equal to the maximum size L11 of the first main body unit 31. When the maximum size M1 of the main electrode 1040 of the first sub-pixel 010 is not less than the maximum size L1 of the first power supply unit 301, the orthogonal projection of the main electrode 1040 of the first sub-pixel 010 on the substrate 001 can cover the orthogonal projection of the first power supply unit 301 on the substrate 001 as much as possible, thereby enhancing the flatness of the main electrode 1040 corresponding to the light-emitting area 103.

[0083] For example, the first power supply unit 301 may also include portions other than the first main body unit 31 and the second main body unit 32, and the embodiments disclosed herein are not limited in this respect.

[0084] The embodiments disclosed herein, by designing the matching form between the pixel circuit and the light-emitting element, are beneficial to improving the flatness of the first electrode in the light-emitting element and reducing the probability of color shift and other phenomena in the display product.

[0085] For example, refer to Figures 4-6The multiple power signal lines 300 include a first power signal line 300-1 and a second power signal line 300-2. The maximum dimensions of the first power signal line 300-1 and the second power signal line 300-2 in the second direction Y are a first dimension Lm and a second dimension Ln, respectively, and the second dimension Ln is smaller than the first dimension Lm. The maximum dimensions of the multiple power signal lines in the second direction Y provided in this embodiment are not completely the same, and can be set according to the shape and arrangement of the first electrode 102 of the first sub-pixel 010 to improve the flatness of the first electrode 102 in the first sub-pixel 010.

[0086] For example, in the multiple power signal lines provided in the embodiments of this disclosure, the shape and arrangement of the first power supply section 301 can be selected according to the type of the first sub-pixel 010. For example, the display substrate may include first power supply sections 301 with different sizes in the second direction, such as first power supply sections 301 with different maximum sizes in the second direction, respectively corresponding to the first sub-pixel 010 with a smaller size or a smaller size of the main electrode 1040 in the second direction, to adapt to the needs of actual patterning, and at the same time, to make the main electrode 1040 of the first sub-pixel 010 have good flatness, reducing the risk of color shift in the display substrate.

[0087] For example, in the embodiments of this disclosure, the first power supply section 301 with different sizes in the second direction Y is not limited to two types, and can be set according to actual design requirements, and there is no limitation thereto.

[0088] For example, refer to Figure 3 , Figure 5 and Figure 6 The plurality of first sub-pixels 010 in the display substrate may include at least one first type sub-pixel 111, and the first power supply portion 301 overlapping with the main electrode 1041 of the first type sub-pixel 111 is the first type power supply portion 3010. For example, the overlapping area between the main electrode 1041 of the first type sub-pixel 111 and the first main body portion 311 of the first type power supply portion 3010 may be an asymmetrical area.

[0089] For example, the first main body 311 of the first type power supply unit 3010 has an asymmetrical structure. For example, the region in the first type power supply unit 3010 that overlaps with the main electrode 1041 of the first type sub-pixel 111 is an asymmetrical region. In the embodiments of this disclosure, "asymmetrical" can mean that the structure or region is not symmetrically arranged in any direction parallel to the substrate.

[0090] For example, refer to Figure 3 and Figure 5The main electrode 1041 of the first type sub-pixel 111 and the first type power supply unit 3010 have a large overlapping area, and the overlapping area is generally asymmetrical. For example, the orthogonal projection area of ​​the overlapping area on the substrate 001 can be 60% to 95% of the orthogonal projection area of ​​the main electrode 1041 on the substrate 001. The orthogonal projection of the light-emitting area 103 of the first sub-pixel 111 on the substrate is located inside the orthogonal projection of the main electrode 1041 on the substrate. At this time, the overlapping area and the light-emitting area 103 almost coincide, that is, the part of the main electrode 1041 overlapping with the light-emitting area 103 is uniformly and flatly disposed, thereby improving the uniformity of the light emission intensity of the first type sub-pixel 111 and reducing the probability of color shift. For example, the orthogonal projection area of ​​the overlapping area on the substrate 001 can be 65% to 90%, or 70% to 85%, or 75% to 80%, etc., of the orthogonal projection area of ​​the main electrode 1041 on the substrate 001.

[0091] For example, such as Figure 6 As shown, the first main body 311 of the first type power supply section 3010 in the display substrate may include a first protrusion 313, which is located on one side of the first symmetry center line L3 extending along the first direction N of the second main body 312.

[0092] For example, refer to Figure 5 and Figure 6 The extension direction of the center line L4 of the first type power supply section 3010 in the display substrate, excluding the first protrusion 313, intersects the extension direction of the second center line L5 of the main electrode 1041 of the first type sub-pixel 111.

[0093] For example, the first center line of symmetry L3 and the center line of symmetry L4 may coincide. Of course, the embodiments of this disclosure are not limited to this, and the two may also be distributed at intervals.

[0094] For example, refer to Figures 3-6 The second main body portion 312 of the first type power supply portion 3010 is symmetrically distributed with respect to the first symmetry center line L3. When the first protrusion 313 is not provided, the maximum dimension of the first main body portion 311 in the second direction is the same as that of the second main body portion 312, and the first type power supply portion 3010 is also symmetrically distributed with respect to the first symmetry center line L3. In order to match the arrangement of the main electrode 1041 of the first type sub-pixel 111 as much as possible, the first protrusion 313 can be provided only on one side of the first main body portion 311 with respect to the first symmetry center line L3. In this way, the provision of the first protrusion 313 can increase the overlap area between the main electrode 1041 and the first type power supply portion 3010, and can better make the main electrode 1041 covering it tend to be flat, thereby increasing the flatness of the main electrode 1041.

[0095] For example, the arrangement of the main electrode 1041 in the first type of power supply unit 3010 can be diverse. For example, refer to Figure 3 and Figure 5 The main electrode 1041 is basically symmetrically distributed with respect to the second symmetry center line L5. For example, in this embodiment, the symmetry center line L4 is set perpendicular to the second symmetry center line L5, which maximizes the overlap area between the first type power supply unit 3010 and the main electrode 1041. At the same time, it also allows the protruding corner of the main electrode 1041 to cover the first protrusion 313 of the first type power supply unit 3010, thereby improving the flatness of the main electrode 1041.

[0096] For example, the angle between the extension directions of the center line of symmetry L4 and the second center line of symmetry L5 can be 20 to 90 degrees, such as 30 to 80 degrees, or 45 to 60 degrees, etc.

[0097] For example, refer to Figure 3 , Figure 5 and Figure 6 The plurality of first sub-pixels 010 in the display substrate also include at least one second type sub-pixel 112, and the first power supply section 301 overlapping with the main electrode 1042 of the second type sub-pixel 112 is the second type power supply section 3011.

[0098] For example, refer to Figure 3 , Figure 5 and Figure 6 The second type power supply unit 3011 includes a third symmetry center line L6 extending along the first direction N, and the main electrode 1042 of the second type sub-pixel 112 includes a fourth symmetry center line L7 extending along the second direction N. The third symmetry center line L6 of the second type power supply unit 3011 and the fourth symmetry center line L7 of the second type sub-pixel 112 overlapping with the second type power supply unit 3011 are located in the same plane perpendicular to the substrate 001. For example, the orthographic projection of the third symmetry center line L6 on the substrate coincides with the orthographic projection of the fourth symmetry center line L7 on the substrate.

[0099] For example, refer to Figure 3 , Figure 5 and Figure 6The second type sub-pixel 112 is disposed on the side of the second type power supply unit 3011 away from the substrate, and the second type power supply unit 3011 is symmetrically distributed with respect to the second symmetry center line. For example, depending on the arrangement of the first sub-pixel 010 in the display substrate, the main electrode 1042 of the second type sub-pixel 112 can be considered to be obtained by rotating the main electrode 1041 of the first type sub-pixel 111 clockwise or counterclockwise by a certain angle. In this embodiment, the rotation angle is 90°. Therefore, the fourth symmetry center line L7 of the main electrode 1042 of the second type sub-pixel 112 is also rotated clockwise or counterclockwise with respect to the main electrode 1041 of the first type sub-pixel 111. The main electrode 1042 of the second type sub-pixel 112 is disposed on the side of the second type power supply section 3011 away from the substrate. Therefore, the third symmetry center line L6 of the second type power supply section 3011 and the fourth symmetry center line L7 of the second type sub-pixel 112 that overlaps with the second type power supply section 3011 are parallel and are both located in the same plane perpendicular to the substrate 001. For example, when multiple second type sub-pixels 112 correspond to the same column of power signal lines 300, the multiple third symmetry center lines L6 of the multiple second type power supply sections 3011 and the multiple fourth symmetry center lines L7 of the multiple second type sub-pixels 112 that overlap with the multiple second type power supply sections 3011 are all located in the same plane perpendicular to the substrate 001.

[0100] For example, refer to Figure 3 , Figure 5 , Figure 6 and Figure 7 The main electrode 1040 of the first sub-pixel 010 includes a first corner portion 141 and a second corner portion 142, as well as a third corner portion 143 and a fourth corner portion 144. The orthographic projection of at least one of the first corner portion 141 and the second corner portion 142 on the substrate 001 at least partially overlaps with the orthographic projection of the first symmetry center line L3 on the substrate 001. The orthographic projection of the fourth corner portion 144 on the substrate 001 at least partially overlaps with the orthographic projection of the first protrusion 313 on the substrate 001.

[0101] For example, refer to Figure 3 , Figure 5 , Figure 6 and Figure 7The extension lines forming the first corner 141, second corner 142, third corner 143, and fourth corner 144 make the main electrode 1040 approximately quadrilateral. For the main electrode 1041 of the first type sub-pixel 111, the first corner 141 and the second corner 142 are arranged opposite to each other, and the pointing direction of the vertex of the first corner 141 to the vertex of the second corner 142 intersects the extension direction of the second symmetry center line L5, for example, in this embodiment, it is perpendicular.

[0102] For example, at least one of the first corner 141, the second corner 142, the third corner 143, and the fourth corner 144 can be formed by extending 1 to 5 micrometers from the extension lines on both sides of the corner vertex. For example, the extension length of the extension lines on both sides of the corner vertex can be 1 / 10 of the length of the edge line between two adjacent corners in the main electrode 1040. For example, when the vertex of at least one of the first corner 141, the second corner 142, the third corner 143, and the fourth corner 144 is a rounded corner, the corresponding corner can be formed by extending 1 to 5 micrometers from the arc lines on both sides of the rounded corner. For example, the angle of at least one of the first corner portion 141, the second corner portion 142, the third corner portion 143, and the fourth corner portion 144 can be in the range of 70° to 150°; for example, the angle of at least one of the first corner portion 141, the second corner portion 142, the third corner portion 143, and the fourth corner portion 144 can be in the range of 80° to 120°; the angle of at least one of the first corner portion 141, the second corner portion 142, the third corner portion 143, and the fourth corner portion 144 can be in the range of 90° to 100°.

[0103] For example, when the main electrode 1041 of the first type sub-pixel 111 is disposed on the side of the first type power supply unit 3010 away from the substrate 001, the pointing direction of the vertex of the first corner 141 to the vertex of the second corner 142 is the same as the extending direction of the symmetry center line L4 of the first type power supply unit 3010, and the pointing direction of the vertex of the third corner 143 to the vertex of the fourth corner 144 is substantially coincident with the second symmetry center line L5. At this time, as... Figure 5 As shown, the orthographic projection of the first protrusion 313 on the substrate 001 falls into the orthographic projection of the fourth corner portion 144 on the substrate 001, thereby maximizing the overlap area between the first type power supply portion 3010 and the main electrode 1041 and improving the flatness of the main electrode 1041.

[0104] For example, refer to Figure 3 , Figure 5 , Figure 6 and Figure 7 The first main body 314 of the second type power supply unit 3011 includes a second protrusion 317 and a third protrusion 318, and the second protrusion 317 and the third protrusion 318 are symmetrically distributed with respect to the third symmetry center line L6.

[0105] For example, refer to Figure 3 , Figure 5 , Figure 6 and Figure 7 The main electrode 1042 of the second type sub-pixel 112 includes opposing first corner portions 141 and second corner portions 142, as well as opposing third corner portions 143 and fourth corner portions 144. The orthographic projection of the second protrusion 317 on the substrate 001 at least partially overlaps with the orthographic projection of one of the first corner portions 141 and the second corner portions 142 on the substrate 001. The orthographic projection of the third protrusion 318 on the substrate 001 at least partially overlaps with the orthographic projection of the other of the first corner portions 141 and the second corner portions 142 on the substrate 001.

[0106] For example, refer to Figure 3 , Figure 5 , Figure 6 and Figure 7 The configuration of the second type sub-pixel 112 is different from that of the first type sub-pixel 111. The main electrode 1042 of the second type sub-pixel 112 is rotated 90° counterclockwise relative to the main electrode 1041 of the first type sub-pixel 111. For example, the direction in which the vertex of the third corner 143 points to the vertex of the fourth corner 144 is basically coincident with the third symmetry center line L6. Therefore, the second type sub-pixel 112 based on the second type power supply unit 3011 can include two configuration forms, such as making the orthographic projection of the second protrusion 317 on the substrate 001 overlap with the first corner 141, and the orthographic projection of the third protrusion 318 on the substrate 001 overlap with the orthographic projection of the second corner 142 on the substrate 001; or making the orthographic projection of the second protrusion 317 on the substrate 001 overlap with the second corner 142, and the orthographic projection of the third protrusion 318 on the substrate 001 overlap with the orthographic projection of the first corner 141 on the substrate 001. According to the two configuration methods described above, the pointing directions of the vertices of the third corner 143 and the fourth corner 144 in two adjacent second-type sub-pixels 112 are opposite. In this case, the orthographic projections of the second protrusion 317 and the third protrusion 318 in the second-type power supply section 3011 onto the substrate 001 fall into the orthographic projection of the main electrode 1042 onto the substrate 001, thereby improving the flatness of the main electrode 1042. The term "two adjacent second-type sub-pixels" can refer to a direction parallel to the substrate where no other second-type sub-pixels are disposed between these two second-type sub-pixels, but other types of sub-pixels can be disposed there.

[0107] For example, refer to Figure 3 , Figure 5 and Figure 6 ,by Figure 5The arrow pointing in the N direction indicates downwards. The second type sub-pixel 112 may include a first seed pixel with its third corner 143 located above the fourth corner 144 and a second seed pixel with its third corner 143 located below the fourth corner 144. At least a portion of the third corner 143 in the first seed pixel overlaps with the first main body 314 of the second type power supply section 3011, and at least a portion of the third corner 143 in the second seed pixel overlaps with the second main body 315 of the second type power supply section 3011. For example, the first electrode 102 of each sub-pixel also includes a connection electrode electrically connected to the pixel circuit 200 (see description below). The third corner 143 in the first seed pixel is closer to the connection electrode than the fourth corner 144, and the fourth corner 144 in the second seed pixel is closer to the connection electrode than the third corner 143.

[0108] For example, in embodiments of this disclosure, reference is made to... Figures 3-6 Along the third direction Z, the light-emitting area 1032 of the second type sub-pixel 112 overlaps with at least one of the second protrusion 317 and the third protrusion 318. The light-emitting area 1032 defines the light-emitting range of the second type sub-pixel 112. When the second type sub-pixel 112 is arranged according to the two configurations described above based on the second type power supply unit 3011, the orthographic projections of the second protrusion 317 and the third protrusion 318 on the substrate 001 fall into or overlap with the orthographic projection portion of the light-emitting area 1032 of the main electrode 1042 on the substrate 001. At this time, the flatness of the main electrode 1042 corresponding to the light-emitting area 1032 can be enhanced, thereby preventing color shift.

[0109] For example, refer to Figure 3 and Figure 6 Depending on the different configuration of the first sub-pixel 111, the shape design of the first type power supply unit 3010 and the second type sub-pixel 3011 are also different.

[0110] For example, in the second direction Y, the maximum dimension L13 of the first main body portion 314 of the second type power supply unit 3011 is larger than the maximum dimension L11 of the first main body portion 311 of the first type power supply unit 3010, and the ratio of the maximum dimension L12 of the second main body portion 312 of the first type power supply unit 3010 to the maximum dimension L13 of the second main body portion 315 of the second type power supply unit 3011 is 0.9 to 1.1. For example, the maximum dimension L12 of the second main body portion 312 of the first type power supply unit 3010 is equal to the maximum dimension L13 of the second main body portion 315 of the second type power supply unit 3011.

[0111] For example, refer to Figure 5 and Figure 6The main electrode 1042 of the second type sub-pixel 112 is rotated 90° clockwise or counterclockwise relative to the main electrode 1041 of the first type sub-pixel 111. The main electrode 1042 of the first sub-pixel 010 has a symmetrical structure. For example, the main electrode 1042 of the second type sub-pixel 112 is symmetrically distributed with respect to the fourth symmetry center line L7, and the second type power supply section 3011 is symmetrically distributed with respect to the second symmetry center point L6. The third symmetry center line L6 and the fourth symmetry center line L7 are parallel and are both located in the same plane perpendicular to the substrate 001.

[0112] For example, the distance between the vertices of the first corner 141 and the second corner 142 is less than the distance between the vertices of the third corner 143 and the fourth corner 144. The first corner 141 and the second corner 142 are distributed on both sides of the fourth symmetry center line L7 of the main electrode 1042, and on the side of the second type power supply unit 3011 away from the substrate 001, the first corner 141 and the second corner 142 correspond to the second protrusion 317 and the third protrusion 318, respectively. On the side of the first type power supply unit 3010 away from the substrate 001, the fourth corner 144 corresponds to the first protrusion 313 of the first type power supply unit 3010. Therefore, the maximum dimension L13 of the first main body portion 314 of the second type power supply unit 3011 is greater than the maximum dimension L11 of the first main body portion 311 of the first type power supply unit 3010.

[0113] For example, such as Figure 5 As shown, the main electrode 1041 of the first type sub-pixel 111 includes two parts located on both sides of the endpoint connection line L2, and in at least one of these two parts, the maximum size of the main electrode 1041 in the second direction Y gradually decreases along a direction parallel to the first direction N and gradually away from the endpoint connection line L2.

[0114] For example, the second main body 312 of the first type power supply unit 3010 corresponds to the part where the maximum size of the main body electrode 1041 gradually decreases. Therefore, there is no need to add other protruding structures to the second main body 312 to improve the flatness of the main body electrode 1041 corresponding to this part. The maximum size of the second main body 312 in the second direction Y is smaller than the maximum size of the first main body 311 in the second direction Y.

[0115] Similarly, for the second type sub-pixel 112, the maximum size L14 of the second main body 315 of the second type power supply 3011 in the second direction Y is also smaller than the maximum size L13 of the first main body 314 in the second direction Y.

[0116] In some embodiments of this disclosure, the maximum size of the main electrode 1041 of the first type sub-pixel 111 in the second direction Y is not significantly different from the maximum size of the main electrode 1042 of the second type sub-pixel 112 in the second direction Y. Therefore, the size reduction trend of the main electrode 1041 in the first direction N is also not significantly different from that of the main electrode 1042 in the first direction N. The maximum sizes of the second main body 312 of the first type power supply section 3010 and the second main body 315 of the second type power supply section 3011 in the second direction Y can also be similar. For example, the ratio of the maximum size L12 of the second main body 312 of the first type power supply section 3010 to the maximum size L13 of the second main body 315 of the second type power supply section 3011 can be 0.9 to 1.1, for example, 1, that is, L12 and L13 are equal. This can facilitate product manufacturing and reduce manufacturing costs while satisfying the flatness of the main electrode 1041 or the main electrode 1042.

[0117] For example, the maximum dimension L13 of the first main body portion 314 in the second direction Y of the second type power supply unit 3011 can be 1.1 to 2 times the maximum dimension L14 of the second main body portion 315 in the second direction Y of the second type power supply unit 3011. For example, in the second type power supply unit 3011, the maximum dimension L13 of the first main body portion 314 can be 1.2 to 1.9 times the maximum dimension L14 of the second main body portion. For example, in the second type power supply unit 3011, the maximum dimension L13 of the first main body portion 314 can be 1.3 to 1.8 times the maximum dimension L14 of the second main body portion. For example, in the second type power supply unit 3011, the maximum dimension L13 of the first main body portion 314 can be 1.4 to 1.7 times the maximum dimension L14 of the second main body portion. For example, in the second type power supply unit 3011, the maximum dimension L13 of the first main body portion 314 can be 1.5 to 1.6 times the maximum dimension L14 of the second main body portion.

[0118] For example, in the first type of power supply section, the maximum dimension of the first main body in the second direction can be 1.1 to 1.8 times, such as 1.2 to 1.7 times, 1.3 to 1.6 times, or 1.4 to 1.5 times, etc., the maximum dimension of the second main body in the second direction.

[0119] For example, the maximum size L13 of the first main body 314 of the second type power supply unit 3011 in the second direction Y can be set as large as possible. For example, in some embodiments of this disclosure, the maximum size L13 of the first main body 314 in the second direction Y can be 1.5 times the maximum size L14 of the second main body 315 in the second direction Y. This allows the first corner 141 and the second corner 142 in the main electrode 1042 of the second type sub-pixel 112 to just cover the first protrusion 317 and the second protrusion 318 of the first main body 314, satisfying the requirement for the flatness of the main electrode 1042 of the second type sub-pixel 112. At the same time, it can also make the ratio between the maximum size L13 and the maximum size L14 as uniform as possible, which is beneficial to simplifying the layout design and manufacturing.

[0120] For example, refer to Figure 5 and Figure 6 Each of the multiple adjacent power signal lines 300 in the display substrate includes multiple power supply sections 300-3 arranged along the first direction N. A first connection section 330 electrically connected to both adjacent power supply sections 300-3 is provided between two adjacent power supply sections 300-3. The multiple power supply sections 300-3 include the aforementioned first power supply section 301. The ratio of the maximum dimension of each power supply section in the second direction Y to the maximum dimension L30 of the first connection section 330 in the second direction Y is 1.5-5.

[0121] For example, the ratio of the maximum dimension of each power supply part 300-3 in the second direction Y to the maximum dimension L30 of the first connecting part 330 in the second direction Y is 2-4.5, such as 2.5-4, such as 3-3.5, etc.

[0122] For example, refer to Figures 3-6The display substrate includes multiple power signal lines 300 extending along a first direction N, and each power signal line 300 has at least one power supply section 300-3. The power supply section 300-3 can be either a first power supply section 301 or a second power supply section 302. The first power supply section 301 corresponds to a first sub-pixel 010, and the second power supply section 302 corresponds to a second sub-pixel. The first power supply section 301 may further include a first-type power supply section 3010 corresponding to a first-type sub-pixel 111, and a second-type power supply section 3011 corresponding to a second-type sub-pixel 112. For each power supply section 300-3, the orthographic projection of the power supply section 300-3 onto the substrate 001 at least partially overlaps with the orthographic projection of its corresponding main electrode onto the substrate 001. For example, the overlap area between the orthographic projection of each power supply unit 300-3 on the substrate 001 and the orthographic projection of its corresponding main electrode on the substrate 001 should be as large as possible. For example, the overlap area can be at least 90% of the orthographic projection area of ​​the main electrode corresponding to the power supply unit 300-3 on the substrate 001, so that the main electrode corresponding to the power supply unit 300-3 has a high flatness.

[0123] refer to Figure 5 and Figure 6 Adjacent power supply units 300-3 are electrically connected via the first connecting part 330, meaning all power supply units 300-3 on the same power signal line 300 are electrically connected. The ratio of the maximum dimension of each power supply unit 300-3 in the second direction Y to the maximum dimension L30 of the first connecting part 330 in the second direction Y can be 1.5-5, for example, 4, 2, or 3. Relative to each power supply unit 300-3, the maximum dimension L30 of the first connecting part 330 in the second direction Y can be designed to be smaller while still achieving the electrical connection function. This allows for more space on the layout, which is beneficial for layout arrangement.

[0124] For example, refer to Figure 5 and Figure 6 The first type power supply unit 3010 includes a first subtype power supply unit 3016 and a second subtype power supply unit 3017. The second main body 312 of the first type power supply unit 3010 includes a first side K1 and a second side K2 opposite to each other in the second direction Y. A first protrusion 3131 in the first subtype power supply unit 3016 is provided on the first side K1 of the second main body 312, and a first protrusion 3132 in the second subtype power supply unit 3017 is provided on the second side K2 of the second main body 312.

[0125] For example, such as Figure 6As shown, with the direction of the arrow in the Y direction pointing to the right, the first protrusion 3131 of the first subtype power supply unit 3016 is located on the left side of the second main body 312, and the first protrusion 3132 of the second subtype power supply unit 3017 is located on the right side of the second main body 312.

[0126] For example, the first subtype power supply unit 3016 and the second subtype power supply unit 3017, which are adjacent to each other along the Y direction, are symmetrically distributed with respect to a straight line extending along the N direction. Here, "the first subtype power supply unit 3016 and the second subtype power supply unit 3017 that are adjacent to each other" can mean that there are no other first subtype power supply units 3016 and second subtype power supply units 3017 between these two power supply units, but other types of power supply units can be provided.

[0127] For example, the multiple power supply sections on each power signal line 300 can be different. For instance, the maximum size of different power supply sections in the second direction Y can be different, thereby flexibly adapting to different arrangements of the main body electrodes and meeting different flatness requirements of the main body electrodes.

[0128] For example, refer to Figure 5 and Figure 6 The first type of subpixel 111 can include two setting methods. For example, as... Figure 5 and Figure 6 As shown, the first type sub-pixel 111 may include a third seed pixel with the third corner 143 located to the left of the fourth corner 144 and a fourth seed pixel with the third corner 143 located to the right of the fourth corner 144. The fourth corner 144 of the third seed pixel overlaps with the first protrusion 313 of the first sub-type power supply section 3016, and the fourth corner 144 of the fourth seed pixel overlaps with the first protrusion 313 of the second sub-type power supply section 3017.

[0129] For example, such as Figure 5 As shown, the main electrode 1041 of the first type sub-pixel 111 is symmetrically distributed with respect to the plane P1. Correspondingly, the first protrusion 3131 in the first sub-type power supply section 3016 and the first protrusion 3132 in the second sub-type power supply section 3017 are disposed on opposite sides. Thus, in both of the above-described arrangements, the orthographic projection of the fourth corner portion 144 of the main electrode 1041 of the first type sub-pixel 111 onto the substrate 001 can cover the orthographic projection of the first protrusion 3131 or the second protrusion 3132 onto the substrate 001, thereby ensuring the flatness of the main electrode 1041 at the fourth corner portion 144.

[0130] For example, refer to Figure 5 and Figure 6The main electrode 1040 of the first sub-pixel 010 includes a first corner 141, a second corner 142, a third corner 143 and a fourth corner 144. Each side of the main electrode 1040 or its extension is connected in sequence to form a polygon H10. Multiple vertices of the polygon H10 have regions that do not overlap with multiple corners of the corresponding main electrode. The area A10 of the non-overlapping region of the third corner 143 and the vertices of the corresponding polygon H10 is greater than the area of ​​the non-overlapping region of each of the other corners and the vertices of the polygons corresponding to that corner.

[0131] For example, refer to Figure 5 and Figure 6 The four extended lines H1, H2, H3, and H4 of the main electrode 1040 form a polygon H10. Corresponding to the first corner 141, polygon H10 includes a non-overlapping region A10 at its apex; corresponding to the second corner 142, polygon H10 includes a non-overlapping region A11 at its apex; corresponding to the third corner 143, polygon H10 includes a non-overlapping region A12 at its apex; and corresponding to the fourth corner 144, polygon H10 includes a non-overlapping region A13 at its apex.

[0132] For example, the four corners of the main electrode 1040 can each include chamfers of different sizes. For instance, in this embodiment, the chamfer at the third corner 143 is larger than the chamfers at the other corners, thereby making the area A12 of the region where the third corner 143 and the apex of its corresponding polygon H10 do not overlap larger than the area of ​​the region where each of the other corners and the apex of its corresponding polygon H10 do not overlap. Of course, in some embodiments, the size of the chamfers at each corner of the main electrode 1040 can be designed according to the size requirements of each light-emitting area. The shapes of the main electrodes provided in the embodiments of this disclosure are merely exemplary and not limiting. Thus, the shape design of the main electrode can be made flexible.

[0133] For example, the aforementioned chamfer can refer to the apex angle formed by a curve. This curve can be an arc or an irregular curve, such as a curve truncated from an ellipse, a wavy line, etc. The embodiments of this disclosure schematically show that the curve has a shape that convexes outward relative to the center of the sub-pixel, but it is not limited to this; the curve can also have a shape that is concave inward relative to the center of the sub-pixel. For example, when the curve is an arc, the central angle of the arc can range from 10° to 150°. For example, the central angle of the arc can range from 60° to 120°. For example, the central angle of the arc can range from 90°. For example, the curve length of the rounded chamfer included in the third corner 143 can be 10 to 60 micrometers. For example, the radius of curvature of the chamfer at the third corner 143 is greater than the radius of curvature of the chamfers at other corners.

[0134] For example, such as Figure 5 and Figure 6 As shown, the second main body portion 32 of the first type power supply portion 3010 and the second type power supply portion 3011 includes two straight edges extending along the first direction N. For example, the edge of the first main body portion 311 of the first type power supply portion 3010 that is opposite to the first protrusion 313 can be a straight edge extending along the first direction N, and this straight edge is on the same straight line as a straight edge of the second main body portion 312.

[0135] For example, such as Figure 5 and Figure 6 As shown, the first protrusion 313 includes an inclined side connected to the straight edge of the second main body 312. The angle between the inclined side and the first direction N can be 10–90 degrees, such as 20–80 degrees, 30–70 degrees, 40–60 degrees, or 45 degrees. For example, the angle between the inclined side and the side connecting the fourth corner 144 and the first corner 141 can be 0–30 degrees, such as 2–25 degrees, 5–20 degrees, 7–15 degrees, or 8–10 degrees. For example, the side of the first protrusion 313 away from the second main body 312 can be parallel to the second direction Y. The connecting line between one end of the center line extending along the first direction N away from the second main body 312 and the end of the inclined side away from the center line can be a broken line or a curve.

[0136] For example, such as Figure 5 and Figure 6 As shown, one of the second protrusion 317 and the third protrusion 318 has the same shape and size as the first protrusion 313, and the second protrusion 317 and the third protrusion 318 are symmetrically distributed with respect to the third symmetry center line L6 extending along the first direction N of the second type power supply section 3011.

[0137] For example, such as Figure 5 and Figure 6 As shown, the shape and size of the second main body portion 32 in the first type power supply portion 3010 and the second type power supply portion 3011 can be the same. The shape and size of the first main body portion 311 of the first type power supply portion 3010, except for the first protrusion 313, and the first main body portion 314 of the second type power supply portion 3011, except for the second protrusion 317 and the third protrusion 318, can be the same.

[0138] For example, such as Figure 5 and Figure 6 As shown, the first sub-pixel is a sub-pixel that emits light of one color, such as a sub-pixel that emits blue light. The shape of the overlapping part of the power signal line with the first electrode of a different sub-pixel that emits the same color of light can be different, and the area of ​​the overlapping region can be different.

[0139] For example, the first sub-pixels 111 with the aforementioned four corners can be evenly distributed in the display area of ​​the display substrate, but this is not the limitation. The display substrate may include a first display area and a second display area, and the first sub-pixels 111 with the aforementioned four corners may only be distributed in the first display area. For example, the first display area may be the area where the under-display camera is located, and the second display area may be the normal display area. By setting the first sub-pixels 111 with the aforementioned four corners in the area where the under-display camera is located, it is beneficial to improve the light transmittance of the second display area.

[0140] For example, refer to Figures 3-6 At least some sub-pixels also include a plurality of second sub-pixels 020. Along the third direction Z, at least one power signal line 300 includes a second power supply portion 302 that overlaps with the main electrode 1050 of at least one of the plurality of second sub-pixels 020. The second power supply portion 302 includes a fifth symmetry center line L32 extending along the first direction N, and the main electrode 1050 of the second sub-pixel 020 includes a sixth symmetry center line L33 extending along the first direction N. The fifth symmetry center line L32 of the second power supply portion 302 in the same column of power signal lines 300 and the sixth symmetry center line L33 of the second sub-pixel that overlaps with the second power supply portion 302 are located in the same plane perpendicular to the substrate 001.

[0141] For example, refer to Figures 3-6The orthographic projection of the main electrode 1050 of the second sub-pixel 020 onto the substrate 001 is smaller than the orthographic projection area of ​​the main electrode 1040 of the first sub-pixel 010 onto the substrate 001. Furthermore, the maximum size of the main electrode 1050 of the second sub-pixel 020 in the first direction N is smaller than the maximum size of the main electrode 1040 of the first sub-pixel 010 in the first direction N, and the maximum size of the main electrode 1050 of the second sub-pixel 020 in the second direction Y is smaller than the maximum size of the main electrode 1040 of the first sub-pixel 010 in the second direction Y. The main electrode 1050 of the second sub-pixel 020 is symmetrically distributed with respect to the sixth symmetry center line L33 extending along the first direction N, and the second power supply section 302 is symmetrically distributed with respect to the fifth symmetry center line L32 extending along the first direction N. The main electrode 1050 is disposed on the side of the second power supply section 302 away from the substrate 001. Therefore, for the same second sub-pixel 020, the fifth symmetry center line L32 of the second power supply section 302 and the sixth symmetry center line L33 of the second sub-pixel overlapping with the second power supply section 302 are located in the same plane perpendicular to the substrate 001. The fifth symmetry center line L32 and the sixth symmetry center line L33 are parallel and both are located in the same plane perpendicular to the substrate 001. When the same column of power signal lines 300 corresponds to multiple second sub-pixels 020, the fifth symmetry center line L32 and the sixth symmetry center line L33 in the same column of power signal lines 300 are both located in the same plane perpendicular to the substrate 001.

[0142] Therefore, the orthogonal projection of the main electrode 1050 on the substrate 001 can cover the orthogonal projection of the second power supply unit 302 on the substrate 001 as much as possible, thereby making the main electrode 1050 tend to be flat.

[0143] For example, refer to Figures 3-6 The orthographic projection of the main electrode 1050 of the second sub-pixel 020 onto the substrate 001 overlaps with the orthographic projection of the second power supply unit 302 onto the substrate 001, and the overlap area AS1 is at least 90% of the orthographic projection area AS of the main electrode 1050 of the second sub-pixel 020 onto the substrate 001. For example, the overlap area AS1 is at least 92%, 95%, or 98% of the orthographic projection area AS of the main electrode 1050 of the second sub-pixel 020 onto the substrate 001.

[0144] For example, refer to Figures 3-6Compared to the orthographic projection of the second power supply unit 302 on the substrate 001, the orthographic projection of the main electrode 1050 on the substrate 001 is relatively small. Furthermore, when the overlapping area AS1 is more than 90% of the orthographic projection area AS of the main electrode 1050 of the second sub-pixel 020 on the substrate 001, the main electrode 1050 in the light-emitting area 1033 of the second sub-pixel 020 is almost entirely flat, thereby effectively preventing the generation of color shift.

[0145] For example, such as Figures 3-6 As shown, the second power supply unit 302 has a different shape from the first power supply unit 301. For example, the area of ​​the second power supply unit 302 is smaller than the area of ​​the first power supply unit 301. For example, the ratio of the maximum dimension of the second power supply unit 302 in the second direction Y to the maximum dimension of the second main body portion 32 of the first power supply unit 301 in the second direction Y can be 0.9 to 1.1. For example, the portion of the first type power supply unit 3010, except for the first protrusion 313, can have the same shape as the second power supply unit 302, and both have the same area. For example, the portion of the second type power supply unit 3011, except for the second protrusion 317 and the third protrusion 318, can have the same shape as the second power supply unit 302, and both have the same area.

[0146] For example, such as Figure 5 and Figure 6 As shown, the power signal line 300 includes a plurality of power supply sections 300-3 arranged along the first direction N, which may include alternating first power supply section 301 and second power supply section 302. The same power signal line 300 includes at least two types of power supply sections 300-3 with different shapes.

[0147] For example, such as Figure 5 and Figure 6 As shown, each of the second power supply sections 302 can have the same shape and area. For example, the different portions of the power signal line 300 that overlap with the first electrode 102 of different second sub-pixels 020 can have the same shape and area.

[0148] Of course, the embodiments disclosed herein are not limited to this. When the shape of the second sub-pixel 020 is set to include four corners similar to the first sub-pixel 010, the shape of the second power supply section 302 overlapping with different second sub-pixels 020 may be different. In this case, the shape of the second power supply section 302 may be determined according to the shape of the first electrode 102 of the second sub-pixel 020.

[0149] For example, refer to Figure 5 and Figure 6The display substrate also includes multiple data lines 400, which extend along a first direction N and are arranged along a second direction Y. The multiple data lines 400 are disposed on the same layer as multiple power signal lines 300. The data lines 400 disposed between two adjacent power signal lines 300 include a first data line 401 and a second data line 402 arranged along the second direction Y. The first data line 401 and the second data line 402 are symmetrically distributed with respect to the seventh symmetry center line L40 between the first data line 401 and the second data line 402.

[0150] For example, such as Figure 6 As shown, the maximum dimension V of the first data line 401 and the second data line 402 between two adjacent power signal lines 300 in the second direction Y is smaller than the maximum dimension L13 of the power signal line 300 in the second direction Y. Each data line also includes a connecting block 450 to achieve connection with the transistor in the pixel circuit 200. For the same power signal line 300, the connecting block is adjacent to and spaced apart from each power supply part. The minimum distance between the connecting block and each power supply part is approximately 1 / 3 to 2 / 3 of the dimension of the first connecting part 330 in the second direction Y. This helps to achieve a more spacious layout and prevent signal interference between the signal lines. The aforementioned maximum dimension V may include the line width of the first data line 401 and the second data line 402 and the distance between them.

[0151] For example, such as Figure 6 As shown, the distance between the first main body 311 of the first type power supply unit 3010 and the data lines (excluding the connecting blocks) located on both sides and adjacent to it is different. For example, the distance between the second main body 312 of the first type power supply unit 3010 and the data lines (excluding the connecting blocks) located on both sides and adjacent to it is the same. For example, the distance between the first main body 314 of the second type power supply unit 3011 and the data lines (excluding the connecting blocks) located on both sides and adjacent to it is the same. For example, the distance between the second main body 312 of the first type power supply unit 3010 and the data lines (excluding the connecting blocks) located on both sides and adjacent to it is the same. For example, the distance between the second power supply unit 302 and the data lines (excluding the connecting blocks) located on both sides and adjacent to it is the same.

[0152] For example, refer to Figure 5 and Figure 6 At least some sub-pixels 10 also include a plurality of third sub-pixels 030, at least one of the third sub-pixels 030 having a main electrode 1060 of the light-emitting element 100 that at least partially overlaps with the data line 400, and the overlapping area AS2 of the main electrode 1060 of the third sub-pixel 030 and the data line 400 is substantially symmetrical with respect to the seventh symmetry center line L40.

[0153] For example, refer to Figure 5 and Figure 6 The projected area of ​​the main electrode 1060 of the third sub-pixel 030 on the substrate 001 is smaller than the projected area of ​​the main electrode 1050 of the second sub-pixel 020 on the substrate 001. Furthermore, the maximum size of the main electrode 1060 of the third sub-pixel 030 in the first direction N is smaller than the maximum size of the main electrode 1050 of the second sub-pixel 020 in the first direction N, and the maximum size of the main electrode 1060 of the third sub-pixel 030 in the second direction Y is smaller than the maximum size of the main electrode 1050 of the second sub-pixel 020 in the second direction Y. For example, the third sub-pixel 030 can have two different configurations, and the two different configurations of the third sub-pixel 030 are symmetrically arranged with respect to the fourth symmetry center line L7. Figure 5 As shown, the overlapping area AS2 of the main electrode 1060 of the third sub-pixel 030 and the data line 400 comprises two parts, and the overlapping area AS2 is basically symmetrical with respect to the seventh symmetry center line L40. Therefore, by symmetrically distributing the overlapping area AS2 with respect to the seventh symmetry center line L40, the flatness of the main electrode 1060 of the third sub-pixel 030 can be increased, thereby reducing color shift and other phenomena in the third sub-pixel 030.

[0154] For example, such as Figure 5 As shown, the main electrode 1060 of the third sub-pixel 030 overlaps with the part of the data line 300 except for the connecting block 450.

[0155] For example, refer to Figure 5 and Figure 6 The display substrate also includes a plurality of second connection portions 500, which are disposed on the same layer as at least a portion of the plurality of power signal lines 300. Each second connection portion 500 includes a first connector 501 and a second connector 502. The plurality of second connection portions 500 are arranged in an array along a first direction N and a second direction Y to form a plurality of second connection portion rows 503 and a plurality of second connection portion columns 504.

[0156] The power signal line 300 includes a plurality of power supply sections arranged along the first direction N, such as a first power supply section 301 and a second power supply section 302. A first connection section 300 electrically connected to both adjacent power supply sections is provided between two adjacent power supply sections. The power supply sections included in the plurality of power signal lines 300 are arranged in an array along the first direction N and the second direction Y to form a plurality of power supply section rows 308 and a plurality of power supply section columns 309.

[0157] Multiple rows of second connection parts 503 and multiple rows of power supply parts 308 are arranged alternately in the first direction N, and two adjacent second connection parts 500 in the same row of second connection parts 503 are distributed on both sides of the data line 400.

[0158] For example, such as Figure 6As shown, the plurality of second connecting parts 500 include a plurality of first connecting members 501 and a plurality of second connecting members 502. The plurality of first connecting members 501 include a plurality of first connecting member columns arranged along the second direction Y, and the plurality of second connecting members 502 include a plurality of second connecting member columns arranged along the second direction Y. The plurality of first connecting member columns and the plurality of second connecting member columns are arranged alternately along the second direction Y.

[0159] For example, the first connector 501 and the second connector 502 may have the same shape or different shapes.

[0160] For example, two adjacent second connection parts 500 in the same second connection part row 503 are symmetrically distributed with respect to the seventh symmetry center line L40. In the second direction, the minimum distance between the first connector 501 or the second connector 502 and the data line 400 is basically the same as the minimum distance between the first connector 501 or the second connector 502 and the first connection part 300, thereby making the layout space distribution uniform and spacious.

[0161] For example, in some embodiments of this disclosure, multiple power signal lines can be arranged on different layers and electrically connected in parallel. Therefore, multiple second connection portions 500 can also be distributed on different layers, and the embodiments of this disclosure do not limit this. For example, two adjacent second connection portions 500 in the same row of second connection portions 503 may not be symmetrically distributed, and can be designed according to the actual layout requirements.

[0162] For example, refer to Figure 5 and Figure 6 The first electrode 102 of the light-emitting element 100 also includes a connecting electrode 105 electrically connected to the main electrode 104. The connecting electrode 105 does not overlap with the light-emitting area 103 of the light-emitting element 100, and the connecting electrode 105 is electrically connected to the light-emitting control transistor T6 through the second connecting part 500.

[0163] For example, refer to Figure 5 and Figure 6 In each pixel circuit, the connection electrode 105 of the main electrode 104 is disposed on one side of the main electrode 104, for example, with Figure 7 The arrow Y in the diagram points to the right, and the connecting electrodes 105 can all be disposed to the left of the center line extending along the first direction N of the main electrode 104. The area of ​​the orthographic projection of the connecting electrodes 105 on the substrate 001 is smaller than the area of ​​the orthographic projection of the main electrode 104 on the substrate 001. For example, the orthographic projection of the connecting electrodes 105 on the substrate 001 does not overlap with the orthographic projection of the data line 400 on the substrate 001, nor with the orthographic projection of the light-emitting area 103 on the substrate 001. This avoids interference of the connecting electrodes 105 with the signals in the data line and the light-emitting area 103, ensuring the performance of the pixel circuit 200.

[0164] For example, refer to Figure 5 and Figure 6 The connecting electrode 105 of the light-emitting element 100 does not overlap with the first connecting portion 300, and in the first direction N, the maximum size L975 of the main electrode 1040 of the first sub-pixel 010 is not less than the maximum size L985 of the first main portion 31 in the corresponding first power supply portion 301.

[0165] For example, the overlapping area of ​​the orthographic projection of the connecting electrode 105 of the light-emitting element 100 on the substrate 001 and the orthographic projection of the adjacent first connecting portion 300 on the substrate 001 is almost non-overlapping. For example, the overlapping area is no more than 1 / 15 of the orthographic projection area of ​​the connecting electrode 105 on the substrate 001, so as to reduce crosstalk that may occur between signal lines.

[0166] For example, refer to Figure 5 and Figure 6 The maximum size L975 of the main electrode 1040 of the first sub-pixel 010 can be larger than the maximum size L985 of the first main body portion 31. In some embodiments, the maximum size L985 of the first main body portion 31 can be 1 / 4 to 1 / 2 of the maximum size L975 of the main electrode 1040 of the first sub-pixel 010. For example, the maximum size L985 of the first main body portion 31 can be 1 / 3 to 2 / 3 of the maximum size L975 of the main electrode 1040 of the first sub-pixel 010. For example, the maximum size L975 of the main electrode 1040 of the first sub-pixel 010 is not smaller than the maximum size L985 of the first main body portion 31 in its corresponding first power supply portion 301, which is beneficial to enhancing the flatness of the main electrode 1040.

[0167] For example, in the second direction Y, a first connecting portion 300 is provided between the first connecting member 501 and the second connecting member 502 of the same second connecting portion 500, and the first connecting member 501 and the second connecting member 502 of the same second connecting portion 500 are spaced apart relative to the first connecting portion 300 between them.

[0168] For example, refer to Figure 5 and Figure 6Multiple rows of second connection portions 503 and multiple rows of power supply portions 308 are arranged alternately in the first direction N. That is, a second connection portion row 503 is provided between two adjacent power supply portion rows 308. In the same second connection portion row 503, a first connection portion 300 is provided between the first connector 501 and the second connector 502 of each second connection portion 500, and the first connection portion 300 is spaced apart from its nearest first connector 501 and second connector 502. The connection electrode 105 of the light-emitting element 100 is electrically connected to the first connector 501 and the second connector 502, and the first connector 501 and the second connector 502 in each second connection portion 500 are spaced apart from the adjacent first connection portion 300. This reduces the interference between the signal of the connection electrode 105 when connected to the second connection portion 500 and the signal on the first connection portion 300.

[0169] For example, by spacing the orthographic projection of the main electrode 104 of the light-emitting element 100 onto the substrate as much as possible with the orthographic projection of the second connection portion 500 onto the substrate, the flatness of the main electrode 104 can be avoided by the second connection portion 500. For example, symmetrically arranging the first connector 501 and the second connector 502 of the same second connection portion 500 with respect to the first connection portion 300 between them further facilitates the layout arrangement.

[0170] For example, refer to Figure 5 and Figure 6 The maximum dimension L51 of the first connector 501 or the second connector 502 in the first direction N is smaller than the maximum dimension L52 of the first connecting part 300 in the first direction N.

[0171] For example, refer to Figure 5 and Figure 6 A first connecting portion 300 is provided between the first connecting member 501 and the second connecting member 502 of the same second connecting portion 500. When the maximum dimension L52 of the first connecting portion 300 in the first direction N is large and larger than the maximum dimension L51 of the adjacent first connecting member 501 or second connecting member 502 in the first direction N, it is beneficial to have a certain distance between the two power supply portions connected to both ends of the first connecting portion 300 in the first direction N and the first connecting member 501 and the second connecting member 502. This also allows the main electrode 104 provided on the two power supply portions to also have a certain distance between the first connecting member 501 and the second connecting member 502, thereby preventing interference between signals.

[0172] For example, refer to Figure 5 and Figure 6The first connector 501 is electrically connected to the connection electrode 1051 of the first sub-pixel 010 or the connection electrode 1051 of the second sub-pixel 020, and the second connector 502 is electrically connected to the connection electrode 1061 of the third sub-pixel 030.

[0173] For example, refer to Figure 5 and Figure 6 In the first direction, the connection electrodes 1051 of the adjacent first sub-pixel 010, the connection electrodes 1051 of the second sub-pixel 020, and the connection electrodes 1051 of the third sub-pixel 030 are arranged sequentially at intervals. The connection electrodes 1051 of the first sub-pixel 010 and the connection electrodes 1051 of the third sub-pixel 030 are both located on the side of the second connecting portion 500 near the first connecting member 501, and the connection electrode 1051 of the second sub-pixel 020 is located on the side of the second connecting portion 500 near the second connecting member 502, thus also being arranged at intervals in the second direction. This facilitates the utilization and design of the layout space.

[0174] Of course, in some embodiments, the number and position of the connectors in the second connecting part 500 may vary depending on the actual configuration, and the embodiments disclosed herein do not limit this.

[0175] For example, such as Figure 7 As shown, the plurality of sub-pixels 10 includes a plurality of first sub-pixels 010, a plurality of second sub-pixels 020, and a plurality of third sub-pixels 030. For example, one of the first sub-pixels 010 and the second sub-pixels 020 is a blue sub-pixel that emits blue light, the other of the first sub-pixels 010 and the second sub-pixel 020 is a red sub-pixel that emits red light, and the third sub-pixel 030 is a green sub-pixel that emits green light. For example, the first sub-pixel 010 is a blue sub-pixel, the second sub-pixel 020 is a red sub-pixel, and the area of ​​the light-emitting area of ​​the blue sub-pixel is larger than the area of ​​the light-emitting area of ​​the red sub-pixel. For example, the area of ​​the light-emitting area of ​​the blue sub-pixel is larger than the area of ​​the light-emitting area of ​​the green sub-pixel. Of course, the embodiments of this disclosure are not limited to this, and the names of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be interchanged. For example, the first sub-pixel can be a green sub-pixel, the second sub-pixel can be a blue sub-pixel, and the third sub-pixel can be a red sub-pixel; or, the first sub-pixel can be a blue sub-pixel, the second sub-pixel can be a red sub-pixel, and the third sub-pixel can be a green sub-pixel, etc.

[0176] For example, such as Figure 7 As shown, multiple first sub-pixels 010 and multiple second sub-pixels 020 are alternately arranged along the first direction N and the second direction Y to form multiple first pixel rows 061 and multiple first pixel columns 062, and multiple third sub-pixels 030 are arranged in an array along the first direction N and the second direction Y to form multiple second pixel rows 071 and multiple second pixel columns 072.

[0177] Multiple first pixel rows 061 and multiple second pixel rows 071 are alternately arranged along a first direction N and staggered from each other in a second direction Y; multiple first pixel columns 062 and multiple second pixel columns 072 are alternately arranged along a second direction Y and staggered from each other in a first direction N.

[0178] The first direction and the second direction intersect. For example, the first direction and the second direction can be perpendicular. For example, the first direction and the second direction can be interchanged.

[0179] For example, the center of the light-emitting area of ​​the first sub-pixel 010 and the second sub-pixel 020 adjacent in the first pixel row 061, and the center of the light-emitting area of ​​the first sub-pixel 010 and the second sub-pixel 020 adjacent to each other along the column direction are the four vertices of a virtual quadrilateral, and the center of the light-emitting area of ​​a third sub-pixel 030 is set inside the virtual quadrilateral.

[0180] For example, such as Figure 7 As shown, a second pixel row 071 includes a plurality of third sub-pixel pairs 035 arranged along a second direction Y. Two third sub-pixels 030 in a third sub-pixel pair 035 are respectively a first pixel block 0301 and a second pixel block 0302, and the first pixel block 0301 and the second pixel block 0302 are alternately arranged along the second direction Y. For example, the first pixel block 0301 and the second pixel block 0302 in a second pixel column 072 are alternately arranged along a first direction N.

[0181] For example, at least two second pixel rows 071 include a plurality of third sub-pixel pairs 035 arranged along a first direction, wherein two third sub-pixels 030 in the at least two third sub-pixel pairs 035 are respectively a first pixel block 0301 and a second pixel block 0302, and the first pixel block 0301 and the second pixel block 0302 are alternately arranged along a second direction Y. For example, the first pixel block 0301 and the second pixel block 0302 in at least two second pixel columns 072 are alternately arranged along a first direction N.

[0182] For example, such as Figure 7As shown, the plurality of sub-pixels 10 include a plurality of minimum repeating units 700. Each minimum repeating unit 700 includes a first sub-pixel 010, a first pixel block 0301, a second pixel block 0302, and a second sub-pixel 020. For example, at least two minimum repeating units 700 include a first sub-pixel 010, a first pixel block 0301, a second pixel block 0302, and a second sub-pixel 020. For example, each minimum repeating unit 700 includes a first sub-pixel 010, a first pixel block 0301, a second pixel block 0302, and a second sub-pixel 020. For example, each minimum repeating unit 700 includes two rows and four columns of sub-pixels 10.

[0183] For example, such as Figure 7 As shown, in a minimum repeating unit 700, the first pixel block 0301 and the first sub-pixel 010 constitute the first pixel unit 701, and the second pixel block 0302 and the second sub-pixel 020 constitute the second pixel unit 702.

[0184] For example, in at least two minimum repeating units 700, the first pixel block 0301 and the first sub-pixel 010 constitute the first pixel unit 701, and the second pixel block 0302 and the second sub-pixel 020 constitute the second pixel unit 702.

[0185] The first and second pixel units mentioned above are not pixels in the strict sense, i.e., a pixel defined by a complete first sub-pixel 010, a second sub-pixel 020, and a third sub-pixel 030. The minimum repeating unit 700 here refers to the minimum repeating unit that can be included in the pixel arrangement structure.

[0186] For example, the first sub-pixel 010 and the second sub-pixel 020 are shared sub-pixels. Through a virtual algorithm, four sub-pixels can be used to achieve the display of two virtual pixel units.

[0187] It should be noted that the pixel arrangement provided in the embodiments of this disclosure is merely exemplary and not a limitation. In some embodiments of this disclosure, the pixel arrangement can be flexibly changed according to the actual layout design needs.

[0188] refer to Figure 3 and Figure 5 The connection electrodes 1051 of multiple first sub-pixels 010 and the connection electrodes 1051 of multiple second sub-pixels 020 are electrically connected to the corresponding second connection portions 500 through multiple first connection holes D0, and the multiple first connection holes D0 are located on multiple first connection lines X1.

[0189] The connection electrodes 1061 of the multiple third sub-pixels 030 are electrically connected to the corresponding second connection portions 500 through multiple second connection holes D1, and the multiple second connection holes D1 are located on multiple second connection lines X2. The first connection line X1 and the second connection line X2 both extend along the second direction Y and are spaced apart.

[0190] For example, such as Figure 3 As shown, the connection electrodes 1051 of multiple first sub-pixels 010 and multiple second sub-pixels 020 are all distributed on one side of the edge of the first connector, and the first connecting line X1 extends along the second direction Y. The connection electrodes 1061 of multiple third sub-pixels 030 are all distributed near the center of the first connector, and the second connecting line X2 also extends along the second direction Y. The first connecting line X1 and the second connecting line X2 are spaced apart in the first direction N, which also allows the multiple first sub-pixels 010, multiple second sub-pixels 020 and multiple third sub-pixels 030 to be spaced apart in the first direction N, so as to make the layout space more uniform.

[0191] For example, in some embodiments of this invention, the plurality of first connecting holes D0 may also have a certain deviation relative to the first connecting line X1, that is, the plurality of first connecting holes D0 may not be completely distributed on the first connecting line X1. For example, at least one first connecting hole D0 may have a deviation of 1-2 micrometers relative to the first connecting line X1. For example, at least one first connecting hole D0 may have a deviation of 2-3 micrometers relative to the first connecting line X1. Similarly, the plurality of second connecting holes D1 may also have a certain deviation relative to the second connecting line X2. For example, at least one second connecting hole D1 may have a deviation of 1-2 micrometers relative to the second connecting line X2. For example, at least one second connecting hole D1 may have a deviation of 2-3 micrometers relative to the second connecting line X21.

[0192] For example, refer to Figures 3-6In some embodiments of this disclosure, within the same minimum repeating unit 700, the first connecting holes D0 corresponding to the first sub-pixel 010 and the second sub-pixel 020 are located on the same first connecting line X1, and the second connecting holes D1 corresponding to the first pixel block 0301 and the second pixel block 0302 are located on the same second connecting line X2. In some embodiments of this disclosure, within the same minimum repeating unit 700, the first connecting hole D0 corresponding to the first sub-pixel 010, the first connecting hole D0 corresponding to the second sub-pixel 020, and the second connecting hole D1 corresponding to the first pixel block 0301 are located on the same first connecting line X1, and the second connecting hole D1 corresponding to the second pixel block 0302 is located on the second connecting line X2. For example, in the same minimum repeating unit 700, the first connecting hole D0 corresponding to the first sub-pixel 010 is located on the first connecting line X1, and the first connecting hole D0 corresponding to the second sub-pixel 020, the second connecting hole D1 corresponding to the first pixel block 0301, and the second connecting hole D1 corresponding to the second pixel block 0302 are located on the second connecting line X2. The embodiments of this disclosure do not limit this.

[0193] For example, the first connection hole D0 corresponding to the first sub-pixel 010, the first connection hole D0 corresponding to the second sub-pixel 020, the second connection hole D1 corresponding to the first pixel block 0301, and the second connection hole D1 corresponding to the second pixel block 0302 can be arranged at equal intervals. For example, depending on the actual layout design requirements, the first connection hole D0 corresponding to the first sub-pixel 010, the first connection hole D0 corresponding to the second sub-pixel 020, the second connection hole D1 corresponding to the first pixel block 0301, and the second connection hole D1 corresponding to the second pixel block 0302 can also be arranged at unequal intervals, and the embodiments of this disclosure do not limit this.

[0194] like Figure 6 As shown, the first connecting portion 330 includes at least one perforated portion 380, and the area of ​​the perforated portion 380 is 1 / 4 to 1 / 3 of the area of ​​the first connecting portion 330.

[0195] For example, in some embodiments of this disclosure, the perforated portion 380 on the first connecting portion 330 may be a through-hole or opening penetrating the first connecting portion 330 in a direction perpendicular to the substrate. For instance, the perforated portion 380 may expose the structure of the pixel circuit 200 on the side of the first connecting portion 330 near the substrate 001, or the first connecting portion 330 may have a hollowed-out pattern. For instance, the perforated portion 380 on the first connecting portion 330 may not substantially overlap with the first electrode 102. For instance, a display product can enhance its transmittance by providing the perforated portion 380. For instance, providing the perforated portion 380 on the first connecting portion 330 can improve the light transmittance of the display substrate, resulting in excellent display performance. For instance, the number of perforated portions 380 on the first connecting portion 380 can be determined according to actual layout design requirements, and the embodiments of this disclosure do not limit this. For instance, the perforated portion 380 may be designed with a regular shape, such as a polygon, ellipse, regular polygon, or circle. For instance, the perforated portion 380 may also be designed with an irregular shape. For example, the multiple cutouts 380 may have the same shape. Alternatively, the multiple cutouts 380 may be designed with different shapes. The embodiments of this disclosure do not limit the shape of the cutouts 380.

[0196] For example, the cutouts 380 on the same first connecting portion 330 may be symmetrically distributed with respect to a central symmetry line of the first connecting portion 330. For example, the position of the cutouts 380 in the first connecting portion 330 may also be determined according to the design requirements of the actual layout, and the embodiments of this disclosure do not limit this.

[0197] For example, in the same first connection portion 330, the distance between the boundary of the perforated portion 380 and the boundary of the first connection portion 330 is not less than 1 micrometer, so as to prevent the first connection portion 330 from being broken.

[0198] Figure 8 This is an equivalent diagram of a pixel circuit provided according to an embodiment of the present disclosure.

[0199] For example, such as Figure 8 As shown, the light-emitting control transistor T6 in the pixel circuit 200 can be the first light-emitting control transistor T6. The pixel circuit 200 also includes a second reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a second light-emitting control transistor T5, a first reset control transistor T7, and a storage capacitor C.

[0200] For example, the display substrate also includes reset power signal lines, scan signal lines, power signal lines, reset control signal lines, light emission control signal lines, and data lines.

[0201] For example, the first terminal of threshold compensation transistor T2 is electrically connected to the first terminal of driving transistor T3, and the second terminal of threshold compensation transistor T2 is electrically connected to the gate of driving transistor T3; the first terminal of the first reset control transistor T7 is electrically connected to the reset power supply signal line to receive the reset signal Vinit, and the second terminal of the first reset control transistor T7 is electrically connected to the first electrode of the light-emitting element 100 (i.e., node N4); the first terminal of data writing transistor T4 is electrically connected to the second terminal of driving transistor T3, and the second terminal of data writing transistor T4 is electrically connected to the data line to receive the data signal Data, and the gate of data writing transistor T4 is electrically connected to the scan signal line to receive the scan signal Gate; the first terminal of storage capacitor C is electrically connected to the power supply signal line, and the second terminal of storage capacitor C is electrically connected to the gate of driving transistor T3; the gate of threshold compensation transistor T2 is electrically connected to the scan signal line to receive the compensation control signal; and the gate of the first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Res. et(N+1); The first terminal of the second reset transistor T1 is electrically connected to the reset power supply signal line to receive the reset signal Vinit; the second terminal of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3; the gate of the second reset transistor T1 is electrically connected to the reset control signal line to receive the reset control signal Reset(N); The gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM; The first terminal of the first light-emitting control transistor T6 is electrically connected to the first terminal of the driving transistor T3; the second terminal of the first light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting element 100; The first terminal of the second light-emitting control transistor T5 is electrically connected to the power supply signal line to receive the first power supply signal VDD; the second terminal of the second light-emitting control transistor T5 is electrically connected to the second terminal of the driving transistor T3; the gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM; the second electrode of the light-emitting element 100 is connected to the voltage terminal VSS. The aforementioned power supply signal line refers to the signal line for outputting the voltage signal VDD, which can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.

[0202] For example, the scan signal and the compensation control signal can be the same; that is, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can be electrically connected to different signal lines; that is, the gate of the data writing transistor T3 is electrically connected to the first scan signal line, and the gate of the threshold compensation transistor T2 is electrically connected to the second scan signal line. The signals transmitted by the first scan signal line and the second scan signal line can be the same or different, thus allowing the gate of the data writing transistor T3 and the threshold compensation transistor T2 to be controlled separately, increasing the flexibility of the pixel circuit 200.

[0203] For example, the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can receive the same light-emitting control signal. That is, the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 can be electrically connected to different light-emitting control signal lines, and the signals transmitted by the different light-emitting control signal lines can be the same or different.

[0204] For example, the reset control signals input to the first reset transistor T7 and the second reset transistor T1 can be the same; that is, the gates of the first reset transistor T7 and the second reset transistor T1 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gates of the first reset transistor T7 and the second reset transistor T1 can be electrically connected to different reset control signal lines, in which case the signals on the different reset control signal lines can be the same or different.

[0205] For example, such as Figure 8 As shown, when the display substrate is working, in the first stage of screen display, the second reset transistor T1 is turned on to initialize the voltage of node N1; in the second stage of screen display, data is stored in node N1 through data writing transistor T4, driving transistor T3 and threshold compensation transistor T2; in the third stage of light emission, the second light emission control transistor T5, driving transistor T3 and the first light emission control transistor T6 are all turned on, and the light emission element 100 is forward-biased to emit light.

[0206] It should be noted that, in the embodiments of this disclosure, each pixel circuit can, in addition to being able to... Figure 8Besides the 7T1C (seven transistors and one capacitor) structure shown, other structures including different numbers of transistors are also possible, such as 7T2C, 6T1C, 6T2C, or 9T2C structures. This disclosure does not limit the specific implementation of these structures. The equivalent diagram of the pixel circuit in the display substrate shown in the above embodiments can be compared with... Figure 8 The equivalent diagram of the pixel circuit 200 shown is the same.

[0207] Figure 9 This is a schematic diagram of the stacked structure of the light-shielding layer, active semiconductor pattern, and first connection layer in the pixel circuit provided according to an embodiment of the present disclosure. Figure 10 This is a schematic diagram of the stacked structure of a light-shielding layer, an active semiconductor pattern, a first connection layer, a second connection layer, a semiconductor layer, and a third connection layer in a pixel circuit according to an embodiment of the present disclosure.

[0208] like Figure 9 As shown, an active semiconductor pattern LY1 is disposed on a light-shielding layer LY0. The active semiconductor pattern LY1 can be formed by patterning semiconductor material. The active semiconductor pattern LY0 and the first connection layer LY2 can be used to fabricate the active layers of the aforementioned driving transistor T3, data writing transistor T4, second light-emitting control transistor T5, first light-emitting control transistor T6, and first reset control transistor T7 to form the channel regions of the aforementioned transistors. The active semiconductor pattern LY0 includes the active layer pattern (channel region) and doped region pattern (source / drain region) of the aforementioned transistors in each sub-pixel, and the active layer pattern and doped region pattern of the aforementioned transistors in the same pixel circuit are integrally disposed.

[0209] For example, the active semiconductor pattern LY1 can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source and drain regions can be regions doped with n-type or p-type impurities.

[0210] For example, a metal layer, such as a gate metal layer, is disposed on the side of the active semiconductor pattern LY1 away from the substrate. This metal layer includes the aforementioned scan signal line, reset control signal line, light emission control signal line, and the gates of the driving transistor T3, data writing transistor T4, second light emission control transistor T5, first light emission control transistor T6, and first reset control transistor T7. Figure 9The dashed rectangles in the diagram illustrate the overlapping portions of the aforementioned metal layer and the active semiconductor pattern LY1, serving as the channel regions for each transistor. The active semiconductor pattern LY1 on both sides of each channel region is conductiveized through processes such as ion doping, serving as the first and second electrodes (i.e., the aforementioned source and drain regions) of each transistor. The source and drain electrodes of the transistor can be structurally symmetrical, so their physical structures can be indistinguishable. In the embodiments of this disclosure, to distinguish the transistors, except for the gate which serves as the control electrode, one electrode is directly described as the first electrode, and the other as the second electrode. Therefore, in the embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0211] For example, the semiconductor layer LY4 forming the channel region of the second reset transistor T1 and the threshold compensation transistor T2 in the pixel circuit can be located on the side of the active semiconductor pattern LY1 away from the substrate, and the semiconductor layer LY4 can include an oxide semiconductor material.

[0212] For example, in Figure 10 The pixel circuit provided according to the embodiments of this disclosure includes a light-shielding layer LY0, an active semiconductor pattern LY1, a first connection layer LY2, a second connection layer LY3, a semiconductor layer LY4, and a third connection layer LY5, which are laid out layer by layer.

[0213] like Figure 10 As shown, the dashed rectangle illustrates the channel regions of the second reset transistor T1 and the threshold compensation transistor T2. For example, the second interconnect layer LY3 can provide a bottom gate structure for the second reset transistor T1 and the threshold compensation transistor T2, the semiconductor layer LY4 overlaps with the second interconnect layer LY3, and a third interconnect layer LY5 is deposited on the side away from the substrate to serve as the top gate layer structure for the second reset transistor T1 and the threshold compensation transistor T2.

[0214] For example, when the active layer of the second reset transistor T1 and threshold compensation transistor T2 in the pixel circuit is made of oxide semiconductor, the oxide semiconductor transistor has good hysteresis characteristics, low leakage current, and low mobility. Therefore, the oxide semiconductor transistor can be used to replace the low temperature polycrystalline silicon material in the transistor to form a low temperature polycrystalline silicon-oxide (LTPO) pixel circuit, which achieves low leakage current and helps to improve the stability of the gate voltage of the transistor.

[0215] Of course, the embodiments disclosed herein are not limited to the active semiconductor pattern of the pixel circuit. Figure 9The active semiconductor pattern LY1 shown in Figure A can have its channel region semiconductor layer located on the same layer as the channel regions semiconductor layers of the second reset transistor T1 and the threshold compensation transistor T2. That is, the active semiconductor pattern can include the channel regions of the second reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the second light-emitting control transistor T5, the first light-emitting control transistor T6, and the first reset control transistor T7.

[0216] Figure 11 This is a partial structural schematic diagram of the first conductive layer provided according to an embodiment of the present disclosure; Figure 12 This is a schematic diagram of the stacked structure of a light-shielding layer, an active semiconductor pattern, a first connection layer, a second connection layer, a semiconductor layer, a third connection layer, and a first conductive layer in a pixel circuit according to an embodiment of the present disclosure. Figure 13 A is a schematic diagram of the stacked structure of the first conductive layer and the second conductive layer according to an embodiment of the present disclosure; Figure 13 B is a schematic diagram of the stacked structure of the first conductive layer, the second conductive layer, and the light-emitting element provided according to an embodiment of the present disclosure.

[0217] For example, refer to Figure 11 A, Figure 12 The display substrate includes a first conductive layer LY6 (such as layer SD1) located between the first electrode of the light-emitting element and the third connection layer LY5. The first conductive layer LY6 includes a reset power signal line 801, which is electrically connected to the first electrode of the first reset transistor T7 to provide a reset signal. For example, the aforementioned reset power signal line 801 can be a first reset power signal line electrically connected to the first electrode of the first reset transistor T7. The display substrate also includes a second reset power signal line, the first portion of which is located between the first conductive layer LY6 and the film layer containing the gate of the first reset transistor T7, and is configured to be electrically connected to the first electrode of the second reset transistor T1 to provide a reset signal.

[0218] For example, refer to Figure 6 , Figure 11 and Figure 12 The first conductive layer LY6 also includes a connection structure 802, and the second conductive layer LY7 also includes a connection block 450. The second electrode of the data writing transistor T4 is connected to the connection block 450 through the connection structure 802, and then electrically connected to the data line 400 to receive data signals.

[0219] For example, refer to Figure 6 , Figure 11 and Figure 12 The first conductive layer LY6 also includes a connection structure 803, through which the second reset transistor T1 is electrically connected to the second reset signal line.

[0220] For example, refer to Figure 6 , Figure 7 , Figure 11 , Figure 12 and Figure 13 The first conductive layer LY6 also includes a connection structure 804. The first electrode of the first light-emitting control transistor T6 and the second electrode of the first reset transistor T7 are electrically connected to the connection electrode 105 in the light-emitting element LY8 through the connection structure 804 and the second connection portion 500 in the second conductive layer LY7. The connection structure 804 is electrically connected to the connection electrode 105.

[0221] For example, refer to Figure 6 , Figure 11 , Figure 12 and Figure 13 The first conductive layer LY6 also includes a connection structure 805, which includes a first connection structure 805A and a second connection structure 805B. The first electrode of the second light-emitting control transistor T5 is electrically connected to the first connection structure 805A, and the second connection structure 805B is electrically connected to the first connection portion 330 in the second conductive layer LY7, thereby making the first electrode of the second light-emitting control transistor T5 electrically connected to the power signal line 300.

[0222] For example, refer to Figure 6 and Figure 12 The first conductive layer LY6 also includes a connection structure 806, through which the first electrode of the threshold compensation transistor T2 is electrically connected to the first electrode of the driving transistor T3 and the second electrode of the first light-emitting control transistor T6.

[0223] For example, refer to Figure 6 and Figure 12 The first conductive layer LY6 also includes a connection structure 807 to realize the electrical connection between the second electrode of the second reset transistor T1, the second electrode of the threshold compensation transistor T2, and the gate of the driving transistor T3.

[0224] refer to Figure 3 , Figure 6 , Figure 7 , Figure 11 , Figure 12 and Figure 13 The orthographic projection of the connection structure 804 on the substrate 001 is basically the same as the orthographic projection of the connection block 450 on the substrate 001, and the orthographic projection of the connection structure 804 and the light-emitting element 100 on the substrate 001 do not overlap, which is beneficial to the layout design and reduces signal interference between the light-emitting elements 100.

[0225] refer to Figure 12 and Figure 13The connection structure 805 also includes a third connection structure 805C. The first connection structure 805A and the second connection structure 805B are spaced apart in the first direction N and are electrically connected through the third connection structure 805C. This allows the first electrode of the second light-emitting control transistor T5 to be electrically connected to the power signal line 300. This connection method can be flexibly adapted to the current layout and minimizes wiring congestion between it and other transistors.

[0226] refer to Figure 3 and Figure 13 The orthographic projection of the first sub-pixel 010 on the substrate 001 overlaps with the orthographic projections of the reset power signal line 801 and the connection structure 807 on the substrate 001. Furthermore, the overlapping areas are substantially symmetrically distributed with respect to the symmetry center line W1 of the main electrode 1040 of the first sub-pixel 010. This improves the flatness of the main electrode 1040, thus reducing color shift. Similarly, the orthographic projection of the second pixel 02 on the substrate 001 also overlaps with the orthographic projections of the reset power signal line 801 and the connection structure 807 on the substrate 001. The overlapping areas are also substantially symmetrically distributed with respect to the symmetry center line W2 of the main electrode 1050 of the second sub-pixel 020, resulting in good flatness of the main electrode 1050.

[0227] refer to Figure 3 , Figure 5 , Figure 6 and Figure 13 The orthographic projection of the first connection structure 805A on the substrate 001 falls into the overlapping area AS2 of the main electrode 1060 and the data line 400 of the third sub-pixel 030, and is basically symmetrical with respect to the seventh symmetry center line L40. Thus, the flatness of the third sub-pixel 030 can be guaranteed to reduce the degree of color shift.

[0228] Another embodiment of this disclosure provides a display device including any of the above-described display substrates. The display device provided in this disclosure, through the design of the pixel circuit and the matching configuration between the pixel circuit and the light-emitting element, facilitates the enhancement of the flatness of the connection electrodes of the light-emitting element and reduces color shift and other phenomena in the display product.

[0229] For example, the display device provided in the embodiments of this disclosure can be an organic light-emitting diode display device.

[0230] For example, the display device may also include a cover plate located on the display side of the display substrate.

[0231] For example, the display device can be any product or component with display function, such as a mobile phone, tablet computer, laptop computer, or navigator with an under-display camera; this embodiment is not limited to this.

[0232] The following points need to be explained:

[0233] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0234] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0235] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A display substrate, comprising: Substrate; Multiple sub-pixels are located on the substrate. At least some of the sub-pixels include light-emitting elements and pixel circuits. The light-emitting elements include a light-emitting functional layer and a first electrode and a second electrode located on both sides of the light-emitting functional layer in a direction perpendicular to the substrate. The first electrode is located between the light-emitting functional layer and the substrate. The light-emitting elements are at least partially located in the light-emitting area. The first electrode of the light-emitting elements includes a main electrode that overlaps with the light-emitting area. Multiple power signal lines are provided, at least a portion of which extend along a first direction and are arranged along a second direction. These power signal lines are located between the substrate and the first electrode of the light-emitting element, and the first direction intersects the second direction. Wherein, the at least some sub-pixels include a plurality of first sub-pixels, and along a third direction perpendicular to the substrate, at least one power signal line includes a first power supply portion overlapping with the main electrode of at least one of the plurality of first sub-pixels, and each first power supply portion includes a first main body portion and a second main body portion. In the second direction, the maximum size of the main electrode of the first sub-pixel is not less than the maximum size of its corresponding first power supply portion, and the maximum size of the first main body portion in the first power supply portion is greater than the maximum size of the second main body portion. The line connecting the two endpoints of the main electrode of the first sub-pixel that are furthest apart in the second direction is the endpoint connection line. In the third direction, the endpoint connection line overlaps with the first main body portion. The plurality of first sub-pixels include at least one first type sub-pixel, and the first power supply portion overlapping with the main electrode of the first type sub-pixel is a first type power supply portion, the first main body portion of the first type power supply portion having an asymmetrical structure. The first main body of the first type of power supply includes a first protrusion located on one side of a first symmetrical center line extending along the first direction of the second main body.

2. The display substrate according to claim 1, wherein, The plurality of power signal lines include a first power signal line and a second power signal line. The maximum dimensions of the first power signal line and the second power signal line in the second direction are a first dimension and a second dimension, respectively, and the second dimension is smaller than the first dimension.

3. The display substrate according to claim 1, wherein, The extension direction of the center line of the first type of power supply part other than the first protrusion intersects the extension direction of the second center line of the main electrode of the first type of sub-pixel.

4. The display substrate according to claim 1 or 3, wherein, The plurality of first sub-pixels also include at least one second type sub-pixel, and the first power supply section overlapping with the main electrode of the second type sub-pixel is the second type power supply section. The second type of power supply includes a third symmetry center line extending along the first direction, and the main electrode of the second type of sub-pixel includes a fourth symmetry center line extending along the first direction. The third symmetry center line of the second type of power supply in the same column of power signal lines and the fourth symmetry center line of the second type of sub-pixel overlapping with the second type of power supply are located in the same plane perpendicular to the substrate.

5. The display substrate according to claim 1 or 3, wherein, The main electrode of the first sub-pixel includes opposing first and second corner portions, as well as opposing third and fourth corner portions. The orthographic projection of at least one of the first corner portion and the second corner portion on the substrate at least partially overlaps with the orthographic projection of the first symmetry center line on the substrate, and the orthographic projection of the fourth corner portion on the substrate at least partially overlaps with the orthographic projection of the first protrusion on the substrate.

6. The display substrate according to claim 4, wherein, The first main body of the second type of power supply includes a second protrusion and a third protrusion, which are symmetrically distributed with respect to the third center line of symmetry. The main electrode of the second type of sub-pixel includes opposing first and second corner portions, as well as opposing third and fourth corner portions. The orthographic projection of the second protrusion on the substrate at least partially overlaps with the orthographic projection of one of the first corner portion and the second corner portion on the substrate, and the orthographic projection of the third protrusion on the substrate at least partially overlaps with the orthographic projection of the other of the first corner portion and the second corner portion on the substrate.

7. The display substrate according to claim 6, wherein, Along the third direction, the light-emitting area of ​​the second type of sub-pixel overlaps with at least one of the second protrusion and the third protrusion.

8. The display substrate according to claim 4, wherein, In the second direction, the maximum size of the first main body of the second type power supply is greater than the maximum size of the first main body of the first type power supply, and the ratio of the maximum size of the second main body of the first type power supply to the maximum size of the second main body of the second type power supply is 0.9 to 1.

1.

9. The display substrate according to claim 4, wherein, The maximum dimension of the first main body of the second type of power supply in the second direction is 1.1 to 2 times the maximum dimension of the second main body of the second type of power supply in the second direction.

10. The display substrate according to any one of claims 1-3, wherein, Each of the multiple adjacent power signal lines includes multiple power supply sections arranged along the first direction. A first connection section electrically connected to both adjacent power supply sections is provided between any two adjacent power supply sections. The multiple power supply sections include the first power supply section. The ratio of the maximum dimension of the power supply part in the second direction to the maximum dimension of the first connection part in the second direction is 1.5-5.

11. The display substrate according to claim 5, wherein, The first type of power supply unit includes a first subtype power supply unit and a second subtype power supply unit. The second main body of the first type of power supply unit includes a first side and a second side opposite to each other in the second direction. In the first subtype power supply unit, the first protrusion is disposed on the first side of the second main body, and in the second subtype power supply unit, the first protrusion is disposed on the second side of the second main body.

12. The display substrate according to claim 5, wherein, The main electrode of the first sub-pixel includes multiple corners, including the first corner, the second corner, the third corner and the fourth corner. Each side of the main electrode or its extension line is connected in sequence to form a polygon, and multiple vertices of the polygon have areas that do not overlap with the multiple corners of the corresponding main electrode. The area of ​​the third corner and the apex of the corresponding polygon that do not overlap is greater than the area of ​​at least some of the other corners and the apex of the corresponding polygon that do not overlap.

13. The display substrate according to any one of claims 1-3, wherein, The at least some sub-pixels also include a plurality of second sub-pixels. Along the third direction, the at least one power signal line includes a second power supply portion overlapping with the main electrode of at least one of the plurality of second sub-pixels. The second power supply section includes a fifth symmetry center line extending along the first direction, and the main electrode of the second sub-pixel includes a sixth symmetry center line extending along the first direction. The fifth symmetry center line of the second power supply section corresponding to the same column of power signal lines and the sixth symmetry center line of the second sub-pixel overlapping with the second power supply section are located in the same plane perpendicular to the substrate.

14. The display substrate according to claim 13, wherein, The orthographic projection of the main electrode of the second sub-pixel on the substrate overlaps with the orthographic projection of the second power supply on the substrate, and the overlapping area is at least 90% of the orthographic projection area of ​​the main electrode of the second sub-pixel on the substrate.

15. The display substrate according to claim 13, wherein, In the second direction, the maximum size of the second power supply unit is smaller than the maximum size of the first main body of the first power supply unit, and the ratio of the maximum size of the second power supply unit to the maximum size of the second main body of the first power supply unit is 0.9 to 1.

1.

16. The display substrate according to claim 13, further comprising: Multiple data lines extend along the first direction and are arranged along the second direction, and the multiple data lines and the multiple power signal lines are arranged on the same layer. The data line between two adjacent power signal lines includes a first data line and a second data line arranged along the second direction, and the first data line and the second data line are symmetrically distributed with respect to the seventh symmetrical center line between the first data line and the second data line. The at least some sub-pixels also include a plurality of third sub-pixels, the main electrode of the light-emitting element of at least one of the plurality of third sub-pixels at least partially overlaps with the data line, and the overlapping area of ​​the main electrode of the third sub-pixel and the data line is substantially symmetrical with respect to the seventh symmetry center line.

17. The display substrate according to claim 16, further comprising: Multiple second connection portions are disposed on the same layer as at least a portion of the multiple power signal lines, and each second connection portion includes a first connector and a second connector. The plurality of second connecting portions are arranged in an array along the first direction and the second direction to form a plurality of rows of second connecting portions and a plurality of columns of second connecting portions. The power signal line includes a plurality of power supply sections arranged along the first direction. A first connection section electrically connected to both adjacent power supply sections is provided between two adjacent power supply sections. The power supply sections included in the plurality of power signal lines are arranged in an array along the first direction and the second direction to form a plurality of power supply section rows and a plurality of power supply section columns. Multiple rows of second connection portions and multiple rows of power supply portions are arranged alternately in the first direction, with two adjacent second connection portions in the same row of second connection portions distributed on both sides of the data line.

18. The display substrate according to claim 17, wherein, The first electrode of the light-emitting element includes a connecting electrode electrically connected to the main electrode, and the connecting electrode and the first connecting portion are substantially non-overlapping. In the first direction, the maximum size of the main electrode of the first sub-pixel is not less than the maximum size of the first main body portion in the corresponding first power supply portion.

19. The display substrate according to claim 17, wherein, The first connector is electrically connected to the connection electrode of the first sub-pixel or the connection electrode of the second sub-pixel, and the second connector is electrically connected to the connection electrode of the third sub-pixel.

20. The display substrate according to claim 10, wherein, The first connecting portion includes at least one perforated portion, the area of ​​which is 1 / 4 to 1 / 3 of the area of ​​the first connecting portion.

21. A display device comprising the display substrate according to any one of claims 1-20.

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