Memory for scan chain testing of column redundancy logic and multiplexing

Abstract

A memory is provided in which a scan chain covers redundancy logic for a column redundancy and a redundancy multiplexer in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexer during a scan operation mode.

Description

Technical Field

[0001] This application relates to a memory with column redundancy, and more specifically to a memory for which a scan chain test is performed on its column redundancy logic and column redundancy multiplexing. Background Technology

[0002] Memory with column redundancy will include redundant logic that determines whether a read or write operation on a column should be shifted to an adjacent column due to a column defect. Each column includes a redundant multiplexer for shifting read or write operations to adjacent columns. However, existing Design for Testability (DFT) scan chains do not test for errors in the redundant logic or redundant multiplexers. Summary of the Invention

[0003] A memory is provided, comprising: a plurality of columns, each column including: a bit line; a complementary bit line; a first read multiplexer transistor coupled to the bit line and having a read terminal; a second read multiplexer transistor coupled to the complementary bit line and having a complementary read terminal; a write driver having a write data output terminal and a complementary write data output terminal; a scan multiplexer having a first pair of input terminals coupled to the write data output terminal and the complementary write data output terminal, and a second pair of input terminals coupled to the read terminal and the complementary read terminal; and a sense amplifier coupled to the output of the scan multiplexer.

[0004] A method for testing columns in a memory is provided, the method comprising: responding to a column redundancy signal of the column being false during a scan operation mode; routing a shift-in signal to a write driver via a write column redundancy multiplexer in response to a trigger edge of a scan clock signal; processing the shift-in signal via the write driver to form a pair of write driver output signals; routing the pair of write driver output signals to a sense amplifier via a scan multiplexer; sensing the pair of write driver output signals in the sense amplifier to form a sensed version of the shift-in signal; and routing the sensed version of the shift-in signal to a data output latch via a read column redundancy multiplexer.

[0005] A memory is provided, comprising: a plurality of columns, each column including: a bit line; a complementary bit line; a first read multiplexer transistor coupled to the bit line and having a read terminal; a second read multiplexer transistor coupled to the complementary bit line and having a complementary read terminal; a sense amplifier having a first input terminal coupled to the read terminal and a second input terminal coupled to the complementary read terminal; a read column redundant multiplexer having a first input terminal coupled to the output terminal of the sense amplifier and a second input terminal coupled to a sense amplifier in an adjacent column; and a data output latch having an input terminal coupled to the output terminal of the read column redundant multiplexer via a direct electrical connection.

[0006] A memory is provided, comprising: a redundancy decoder including a gated logic gate and a fuse decoder having an enable input terminal coupled to an output terminal of the gated logic gate, the redundancy decoder also including multiple output terminals for multiple decoded address signals; multiple column redundancy logic circuits arranged in series, each column redundancy logic circuit having a set of input terminals for receiving a corresponding set of redundant address bits and an output terminal for a column redundancy signal; and a scan trigger configured to latch a column redundancy signal from the last column redundancy logic circuit in the column redundancy logic circuits.

[0007] These and other advantages can be better understood through the detailed description below. Attached Figure Description

[0008] Figure 1 This is a diagram of a memory according to one aspect of the present disclosure, wherein redundant logic circuitry and column redundant multiplexers are included within the DFT scan chain.

[0009] Figure 2 It is based on one aspect of this disclosure. Figure 1 A diagram of redundant logic circuits in a memory.

[0010] Figure 3 It is a graph of regular columns, in which the column redundancy multiplexer is bypassed by the DFT scan chain.

[0011] Figure 4 A column according to a first aspect of this disclosure is shown, wherein a column redundancy multiplexer is included within a DFT scan chain.

[0012] Figure 5 A column according to a second aspect of this disclosure is shown, wherein a column redundancy multiplexer is included within a DFT scan chain.

[0013] Figure 6 An example of a device according to one aspect of this disclosure is shown. Figure 1 Redundant decoders for memory.

[0014] Figure 7 It shows the relationship with Figure 6 Timing diagram of signals associated with redundant decoders.

[0015] Figure 8 This is a flowchart of a method for scanning a redundant multiplexer in a memory column according to one aspect of this disclosure.

[0016] The embodiments and advantages of this disclosure can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements shown in one or more of the figures. Detailed Implementation

[0017] An improved column redundancy scheme is provided for memory to allow errors in the DFT scan chain scanning redundancy logic and in the column redundancy multiplexer. Figure 1 An exemplary memory 100 with this improved column redundancy is shown. Memory 100 includes a plurality of N+1 column bit cells, ranging from column N to column zero, where N is a positive integer. Memory 100 also includes at least one redundant column. For simplicity, the expression "column" without further explanation should be understood herein to refer to a non-redundant column. During testing of memory 100, it is possible that there are no defective columns. In this case, redundant columns (or multiple redundant columns) are not used. Read or write operations addressing a particular column will therefore occur in that column. All columns in the plurality of columns are then considered unshifted columns because there is no shift when column redundancy is not enabled. However, this is not the case if defective columns are present. The column array can then be divided into unshifted columns and shifted columns based on the location of the defective column. For example, suppose column i is defective. Subsequent columns from column (i+1) to column (N+1) are unshifted, while previous columns from column i to column zero are shifted. For example, if a read or write operation is addressed to the zeroth column when column redundancy is enabled, the read or write operation actually occurs on the redundant column.

[0018] To achieve column redundancy, a fuse decoder (not shown) can function to decode the fuse word to generate multiple decoded redundant address signals. For example, decoding can generate three decoded redundant address signals fa<0:3>, fb<0:3>, and fc<0:3>. In an alternative embodiment, the number of decoded redundant address signals and their bit widths can be varied. To process the decoded redundant address signals, each column is associated with a corresponding redundant logic circuit. Thus, there exists an Nth redundant logic circuit (redundant logic column (N)) for the Nth column, an (N-1)th redundant logic circuit (redundant logic column (N-1)) for the (N-1)th column, etc., such that there exists a zeroth redundant logic circuit (redundant logic column (0)) for the zeroth column. The redundant logic circuit of each column receives one bit from each of the decoded redundant address signals fa<0:3>, fb<0:3>, and fc<0:3>. Each redundant logic circuit therefore receives three redundant address bits fa, fb, and fc.

[0019] In one implementation, the decoded redundant address bits fa, fb, and fc are active low. Therefore, in the active-low implementation, a defective column is identified by the fact that its decoded redundant address bits fa, fb, and fc are all logic zero. Alternatively, an active-high implementation can be used, wherein the decoded redundant address bits fa, fb, and fc are all logic one. As used herein, a binary signal is considered asserted when it is true, regardless of whether the true binary state is represented by the active-low or active-high convention. Each redundant logic circuit is configured to assert a column redundancy signal (designated match_next) if its decoded redundant address bits fa, fb, and fc are logically true (asserted). The terms "column redundancy signal" and "match_next" are used interchangeably herein. In the active-high implementation, each redundant logic circuit is therefore configured to assert its match_next signal if its bits fa, fb, and fc are all binary one.

[0020] Redundant logic circuits can be considered as a series arrangement starting from the Nth redundant logic circuit to the zeroth redundant logic circuit. The match_next signal from the preceding redundant logic circuit in this series arrangement is received as the match_prev signal at subsequent redundant logic circuits. For example, the match_next signal from the Nth redundant logic circuit is received by the (N-1)th redundant logic circuit as its match_prev signal. Each redundant logic circuit is configured to assert its match_next signal if its match_prev signal is asserted. In the previously discussed example where the i-th column is the defective column, the i-th redundant logic circuit will therefore assert its match_next signal. Subsequent redundant logic circuits from the (i-1)th to the zeroth redundant logic circuit will therefore also assert their match_next signals, since each of their match_prev signals will be asserted. In the following discussion, it will be assumed that the match_next signal is a logic high signal such that it is logic one when asserted.

[0021] exist Figure 2 The exemplary redundant logic circuit 200 is shown in more detail below. Logic gates (such as NAND gate 205) process the redundant address bits decoded from fa, fb, and fc to produce an output signal inverted by inverter 210. NOR gate 215 performs a NOR operation between the output signal from inverter 210 and the match_prev signal. Inverter 220 inverts the output signal from NOR gate 215 to produce the match_next signal. If any of the bits fa, fb, and fc is logic zero, the output of NAND gate 205 is logic one. This logic one is inverted by inverter 210 to produce logic zero for NOR gate 215. If the match_prev signal is also logic zero, the output of NOR gate 215 will therefore be logic one, which is inverted by inverter 220 to force the match_next signal to logic zero. However, if the fa, fb, and fc bit signals are all logic one and / or the match_prev signal is logic one, the match_next signal is asserted.

[0022] Referring again to memory 100, note that each column receives the match_next signal from its corresponding redundant logic circuit. As will be further explained herein, each column includes a write column redundant multiplexer and a read column redundant multiplexer. In a write operation to a column with an asserted match_next signal, the write column redundant multiplexer directs the write data bits to the previous column. For example, if column i has an asserted match_next signal, its write column redundant multiplexer directs the write data bits to be written to column (i-1). But if column i has a false match_next signal, its write column redundant multiplexer directs the write data bits to the write driver of column i. The read column redundant multiplexer is similar in that it selects the retrieved bits from the current column or from the previous column based on whether the match_next signal of the current column is true or false.

[0023] In conventional memory with column redundancy, the DFT scan chain typically does not overwrite either the write column redundancy multiplexer or the read column redundancy multiplexer. Figure 3 An exemplary conventional column 300 is shown. For clarity, only a single bit cell 305 is shown as coupled to bit line bl and complementary bit line blb, but it should be understood that a column (such as column 300) comprises multiple bit cells arranged according to rows. During a write operation on column 300, the input data bit din from the core power domain powered by the core power supply is level-shifted by level shifter (LS) 310 to the memory power domain din signal powered by the memory power supply. During scan operation mode, the shift-in signal is provided by scan chain flip-flops (such as master-slave flip-flops 315 for scan chains). During a write operation, a write column redundant multiplexer (write redundant multiplexer) 320 routes the level-shifted din signal based on whether the match_next signal is asserted or deasserted. If the match_next signal is false, the write column redundant multiplexer 320 passes the level-shifted din signal to the write driver 325. However, if the match_next signal is true, the write column redundancy multiplexer 320 passes the level-shifted din signal to the previous column as the din_next signal. If a subsequent column has asserted its match_next signal, column 300 will receive the din_next signal of that subsequent column at the write driver 325 as the din_prev signal. Based on the input signal of the write driver (a level-shifted din signal in the absence of redundancy, or a din_prev signal if a subsequent column has asserted its match_next signal), the write driver 325 drives the write data signal (wd) and the complementary write data signal (wd_n) accordingly.

[0024] During a write operation on column 300, the write multiplexer signal wm is asserted to turn on the n-type metal-oxide-semiconductor (NMOS) write multiplexer transistor M1 to couple the wd signal to bit line b1. Similarly, the assertion of the write multiplexer signal wm turns on another NMOS write multiplexer transistor M2 to couple the wd_n signal to the complementary bit line blb. Bit cell 305 can then be written accordingly to complete the write operation.

[0025] During a defect-free read operation of column 300, a low-level active read multiplexer signal rm is discharged to turn on p-type metal-oxide-semiconductor (PMOS) read multiplexer transistor P1 to couple the true bit line to sense amplifier (SAMP) 330. Similarly, the discharge of the read multiplexer signal rm turns on another PMOS read multiplexer transistor P2 to couple the complementary bit line blb to SAMP 330. SAMP 330 can then perform bit decisions. If the match_next signal of column 300 is false, the read column redundant multiplexer (read redundant multiplexer) 335 selects a bit decision from SAMP 330. If the match_next signal is true, the read column redundant multiplexer 335 selects a bit decision from the previous column (SAMP next). During a read operation of the subsequent column for which its match_next signal is asserted, the subsequent column selects a bit decision from SAMP 330 (SAMP prev).

[0026] During the read operation, the scan signal for the DFT scan of column 300 is not asserted. The scan signal controls the scan mux 340, which selects bit decisions from the read column redundancy multiplexer 335 during the read operation. The data output latch 345 can then latch the output data bits to complete the read operation. During scan operation mode, the scan mux 340 responds to the scan signal assertion by selecting the shift-in signal from the master-slave flip-flop 315. Therefore, such a regular DFT scan bypasses the operation of the write column redundancy multiplexer 320 and the read column redundancy multiplexer 335.

[0027] To provide the ability to include write and read column redundancy multiplexers in DFT scans, an improved column 400 is provided, such as... Figure 4As shown in the diagram. As discussed with respect to column 300, only a single bit cell 305 in column 400 is shown as coupled to bit line bl and complementary bit line blb, but it should be understood that column 400 includes multiple bit cells arranged according to row layout. Referring again to memory 100, each column ranging from column N to column zero can be implemented as shown with respect to column 400. Also discussed similarly with respect to column 300, during a write operation to column 400, the input data bit din from the core power domain powered by the core power supply is level-shifted by the level shifter (LS) 310 in column 400 to the memory power domain din signal powered by the memory power supply. During scan operation mode, the shift-in signal is provided by the master latch in the master-slave flip-flop 315 included in the scan chain. The write column redundancy multiplexer (write redundancy multiplexer) 320 multiplexes the level-shifted din signal according to whether the match_next signal is true or false. If the match_next signal of column 400 is false, the write column redundancy multiplexer 320 transmits a level-shifted din signal to the input terminal of the write driver 325 via its first output terminal during the write operation. However, if the match_next signal is true, the write column redundancy multiplexer 320 transmits a level-shifted din signal to the previous column as the din_next signal via its second output terminal. If a subsequent column has asserted its match_next signal, column 400 will receive the din_next signal of that subsequent column at the write driver 325 as the din_prev signal. Based on the input signal of the write driver (a level-shifted din signal in the absence of redundancy, or a din_prev signal if a subsequent column has asserted its match_next signal), the write driver 325 accordingly drives the write data signal (wd) and the complementary write data signal (wd_n).

[0028] During a write operation on column 400, a high-level active write multiplexer signal wm is asserted to turn on write multiplexer transistor M1 to couple the wd signal to bit line b1, and write multiplexer transistor M2 is turned on to couple the wd_n signal to the complementary bit line blb. Bit cell 305 can then be written accordingly to complete the write operation.

[0029] The read operation for column 400 is performed similarly to that discussed for column 300. During a defect-free read operation for column 400, the active-low read multiplexer signal rm is discharged to turn on read multiplexer transistors P1 and P2 to couple the true bit line and the complementary bit line to the scan multiplexer 405. The source of read multiplexer transistor P1 can be considered to form the read terminal. Similarly, the source of read multiplexer transistor P2 can be considered to form the complementary read terminal. The scan multiplexer 405 includes a first pair of input terminals coupled to the read terminal and the complementary read terminal. During the read operation, the scan signal is deasserted to control the scan multiplexer 405 to select its first pair of input terminals, and thus select the bit line signal routed through read multiplexer transistors P1 and P2. The SAMP 330 can then perform bit decisions. The read column redundancy multiplexer 410 includes a first input terminal coupled to the output terminal of the SAMP 330. If the match_next signal of column 400 is false, the read column redundancy multiplexer 420 selects this first input terminal, thus selecting a bit decision from the SAMP 330. The SAMP 330 also includes a second input terminal coupled to a sense amplifier in the preceding column. If the match_next signal is true, the read column redundancy multiplexer 410 selects this second input terminal, thus selecting a bit decision from the preceding column (SAMP next). The data output latch (Dout latch) 345 includes an input terminal coupled to the output terminal of the read column redundancy multiplexer 410, such that the data output latch 345 can then latch output data bits to complete the read operation. During a read operation on a subsequent column whose match_next signal is asserted, the subsequent column selects a bit decision from the SAMP 330 (SAMP prev).

[0030] During scan operation mode, master-slave flip-flop 315 provides a shift-in signal, which is routed through write column redundancy multiplexer 320 and write driver 325. Write driver 325 has a first output terminal for a write data signal wd (or a shift-in signal during scan mode) and a second output terminal for a complementary write data signal wd_n (or a complementary shift-in signal during scan mode). Scan multiplexer 405 includes a second pair of input terminals coupled to the first and second output terminals of write driver 325. If a scan signal is asserted, scan multiplexer 405 selects its second pair of input terminals to select a pair of output signals from write driver 325. Sensing amplifier SAMP 330 then makes a bit decision based on the shift-in signal. If the match_next signal is false, the shift-in signal bit decision from SAMP 330 is routed through read column redundancy multiplexer 410 to be latched in Dout latch 345. Conversely, if the match_next signal is true, the read column redundant multiplexer 410 selects the shift-in signal bit decision (SAMP next) from the sense amplifier in the previous column. Advantageously, the operation of the write column redundant multiplexer 320 can also be tested in scan mode, because if the match_next signal is false, the level-shifted shift-in signal will be routed through the write column redundant multiplexer 320 to the write driver 325 (and ultimately to the Dout latch 345). If the match_next signal is true, the shift-in signal is routed through the write column redundant multiplexer 320 to the write driver in the previous column.

[0031] exist Figure 5Alternative column implementations for scanning, also enabling read and write column redundancy multiplexers, are shown for column 500. Referring again to memory 100, each column ranging from column N to column zero can be implemented as shown for column 500. Read and write operations are performed similarly as discussed for column 400. For example, during a write operation to column 500, the input data bit din from the core power domain powered by the core power supply is level-shifted by level shifter (LS) 310 to the memory power domain din signal powered by the memory power supply. During scan operation mode, the shift-in signal can be provided by master-slave flip-flops 315 for the scan chain. During a write operation, the write column redundancy multiplexer (write redundancy multiplexer) 320 multiplexes the level-shifted din signal based on whether the match_next signal is true or false. If the match_next signal for column 500 is false, the write column redundancy multiplexer 320 passes the level-shifted din signal to the write driver 325. However, if the match_next signal is asserted for column 500, the write column redundancy multiplexer 320 passes a level-shifted din signal to the previous column as the din_next signal. If a subsequent column has already asserted its match_next signal, column 500 can receive the din_next signal of that subsequent column at the write driver 325 as the din_prev signal. Based on the input signal of the write driver during the write operation (a level-shifted din signal in the absence of redundancy, or a din_prev signal if the previous column asserted its match_next signal), the write driver 325 drives the write data signal (wd) and the complementary write data signal (wd_n) accordingly.

[0032] During a write operation on column 500, a high-level active write multiplexer signal wm is asserted to turn on write multiplexer transistor M1 to couple the wd signal to bit line b1 and to turn on write multiplexer transistor M2 to couple the wd_n signal to the complementary bit line blb. Bit cell 305 can then be written accordingly to complete the write operation.

[0033] The read operation for column 500 is performed similarly to that discussed for column 400. During the read operation where the match_next signal for column 500 is false, the active-low read multiplexer signal rm is discharged to turn on read multiplexer transistors P1 and P2 to couple the true bit line and the complementary bit line to the sense amplifier 330. The SAMP 330 can then make a bit decision. If the match_next signal for column 500 is false, the read column redundant multiplexer (read redundant multiplexer) 410 selects a bit decision from the SAMP 330. If the match_next signal for column 500 is true, the read column redundant multiplexer 410 selects a bit decision from the previous column (SAMP next). The data output latch (Dout latch) 345 can then latch the output data bits to complete the read operation. During the read operation of the subsequent column that makes its match_next signal asserted, the subsequent column is selected from the SAMP 330 bit decision (SAMP prev).

[0034] In scan operation mode, the memory controller (not shown) and write multiplexer transistors P1 and P2 simultaneously turn on read multiplexer transistors M1 and M2. A master-slave flip-flop 315 provides the shift-in signal. If the match_next signal of column 500 is false, the shift-in signal is passed through the write column redundant multiplexer 320 and driven as true and complementary wd and wd_n signals, respectively. During scan operation mode, the wd signal is coupled to bit line bl via write multiplexer transistor M1 and also via read multiplexer transistor P1 to drive sense amplifier 330. Similarly, the wd_n signal is coupled via write multiplexer transistor M2 and read multiplexer transistor P2 to drive sense amplifier 330 during scan operation mode. If the match_next signal is true during scan operation mode, the write column redundant multiplexer 320 passes the shift-in signal to the write driver in the previous column. Both the write multiplexer transistor and the read multiplexer transistor are turned on in the previous column, as discussed for column 500.

[0035] In the scan operation mode of column 500, sense amplifier 330 recovers the shift-in signal from the wd and wd_n signals. If the match_next signal of column 500 is false, read column redundant multiplexer 410 selects the recovered shift-in signal so that it can be latched in Dout latch 345. Direct electrical connection 505 extends from the output terminal of read column redundant multiplexer 410 to the input terminal of Dout latch 345. As used herein, the term "direct electrical connection" refers to an electrical path or lead that does not contain any switching elements, such as transistors within the multiplexer. If the match_next signal is false, the shift-in signal is thus passed through write column redundant multiplexer 320, read column redundant multiplexer 410, and direct electrical path 505 to be latched in Dout latch 345. The scan operation mode can therefore test the operation of both the write column redundant multiplexer 320 and the read column redundant multiplexer 410 during the scan operation mode when the match_next signal is false. If the match_next signal is true during the scan operation mode, the operation of the write column redundant multiplexer 320 in column 500 and the read column redundant multiplexer 410 in the previous column are similarly tested. The scan mode for redundant logic circuits and redundant decoders will now be discussed.

[0036] Redundant logic and decoding

[0037] Redundant decoders typically respond to a redundancy enable signal. During scan operation using such a conventional redundant decoder, the assertion of the redundancy enable signal can occur precisely before the assertion of the trigger edge of the scan clock signal used for the DFT scan chain. Referring again to memory 100, the decoded redundant address signal is thus presented to the redundant logic circuitry relatively early, before the scan clock signal edge is asserted. The match_next signals from the various redundant logic circuits then have sufficient time to stabilize. This is problematic because resistive path faults may go undetected. For example, a resistive path fault could exist in one of the NAND gates 205, inverters 210 and 220, or NOR gate 215 in the redundant logic circuitry 200. Such a resistive path fault causes the redundant logic circuitry 200 to spend too much time asserting its match_next signal, which can lead to read or write errors. However, if the redundant decoder is triggered only by the redundancy enable signal, such resistive path faults may be undetectable.

[0038] Figure 6 The redundant decoder 600 shown advantageously allows for testing, such as for detecting resistive path faults, by scanning operating modes (including detection of resistive path faults). Figure 1 and Figure 2The redundant logic circuitry discussed. When enabled during scan operation mode, the redundant decoder 600 decodes the fuse word fuse<0:5> to generate three decoded redundant address signals fa<0:3>, fb<0:3>, and fc<0:3>. In an alternative embodiment, the bit width of the fuse word and the number and bit width of the decoded redundant address signals may vary. A gated logic gate (such as NAND gate 605) controls the enabling of the redundant decoder 600. NAND gate 605 gates a low-level active redundant enable signal fc_en with a low-level active gate signal (shift_n), which is asserted a known time prior to the assertion of the trigger edge of the scan clock signal used for the DFT scan chain. Without loss of generality, the following discussion will assume that the trigger edge of the scan clock signal is a rising edge. The output signal from NAND gate 605 is asserted when the shift_n signal discharges shortly before the assertion of the scan clock signal and the redundant enable signal fc_en has discharged. The asserted NAND gate output can then be level-shifted from the core (CX) power domain to the memory (MX) power domain by level shifter 610 to form a gate enable signal received at the enable input terminal of fuse decoder 615. Fuse decoder 615 is configured to decode the fuse word fuse<0:5> into decoded redundant address signals fa<0:3>, fb<0:3>, and fc<0:3> when asserted by the gate enable signal.

[0039] Referring again to memory 100, when timed by the scan clock signal, scan chain flip-flop 105 registers the match_next signal from the zeroth redundancy logic circuit. Flip-flop 105 shifts the sampled match_next signal out as the redundancy scan output signal (red_scan_out). A timer (not shown) can then determine the delay between the discharge of the gate signal (shift_n) and the assertion of the redundancy scan output signal. If this delay is greater than a threshold delay, a resistive path fault in the redundancy logic circuit is detected. For example, a scan can begin by testing the zeroth redundancy logic circuit. If the zeroth redundancy logic circuit asserts its match_next signal such that the threshold delay is not reached, the scan can continue testing the first redundancy logic circuit, and so on, until the Nth redundancy logic circuit is finally tested.

[0040] exist Figure 7The diagram shows the timing of the redundancy decoder signals fc_en, shift_n, fuse word, scan clock signal, and redundancy scan output signal. Before time t0, the fuse word fuse<5:0> is received at the redundancy decoder, and the redundancy enable signal fc_en is asserted by discharging in a low-level active implementation. The fuse word is encoded such that the addressed redundant logic circuit should assert its match_next signal. To test whether this assertion of the match_next signal is subject to resistive path delay, the low-level active gate signal shift_n is asserted by discharging until time t0. The rising edge of the scan clock is asserted not until time t1, approximately 20 ns later. Generally, the delay between shift_n and the scan clock edge can be greater than or less than 20 ns, depending on the difference between normal processing delay and resistive path delay. If the delay between the falling edge of shift_n and the rising edge of the redundancy scan output signal (Red_scan_out) is too large, a resistive path delay is considered detected in the target redundant logic circuit. The redundancy enable signal is then deasserted by charging to the supply voltage at time t2. This time can also be controlled to be a known time (e.g., 20 ns) before the next rising edge of the scan clock signal at time t3, in order to determine whether the redundant scan output signal takes too long to discharge.

[0041] Now refer to Figure 8 The flowchart illustrates an exemplary method for scanning a redundant multiplexer in a column. The actions in the flowchart respond to the trigger edge of a scan clock signal during a scan operation mode in which the column redundancy signal is false. The method includes action 800, which routes a shift-in signal to a write driver via a write column redundancy multiplexer. Routing the shift-in signal via write column redundancy multiplexer 320 in column 400 is an example of action 800. The method also includes action 805, which processes the shift-in signal via a write driver to form a pair of write driver output signals. Processing the shift-in signal in write driver 325 in column 400 is an example of action 805. The method also includes action 810, which routes the pair of write driver output signals to a sense amplifier via a scan multiplexer. Routing via scan multiplexer 405 in column 400 is an example of action 810. Additionally, the method includes action 815, which senses the pair of write driver output signals in a sense amplifier to form a sensed version of the shift-in signal. Sensing in sense amplifier 330 in column 400 is an example of action 815. Finally, the method includes action 820, which routes the sensed version of the shift-in signal to the data output latch by reading the column redundancy multiplexer. The routing via reading the column redundancy multiplexer 410 in column 400 is an example of action 820.

[0042] This disclosure will now be outlined in the following exemplary terms:

[0043] Clause 1. A memory comprising:

[0044] Multiple columns, each column including:

[0045] Bit line;

[0046] Complementary bit lines;

[0047] A first read multiplexer transistor is coupled to the bit line and has a read terminal;

[0048] A second read multiplexer transistor is coupled to the complementary bit line and has a complementary read terminal;

[0049] A write driver having a write data output terminal and a complementary write data output terminal;

[0050] A scan multiplexer having a first pair of input terminals coupled to the write data output terminal and the complementary write data output terminal, and a second pair of input terminals coupled to the read terminal and the complementary read terminal; and

[0051] A sensing amplifier coupled to the output of the scan multiplexer.

[0052] Clause 2. The memory according to Clause 1, wherein the scan multiplexer is configured to select the first pair of input terminals during a scan mode and to select the second pair of input terminals during a read operation.

[0053] Clause 3. The memory according to any one of Clauses 1 to 2, each column further includes:

[0054] A read column redundancy multiplexer has a first input terminal coupled to the output terminal of the sense amplifier and a second input terminal coupled to the output terminal of a sense amplifier in an adjacent column.

[0055] Clause 4. The memory according to Clause 3, each column further includes a data output latch having an input terminal coupled to the output terminal of the read column redundancy multiplexer.

[0056] Clause 5. The memory according to any one of Clauses 3 to 4, wherein the read column redundancy multiplexer is configured to select its first input terminal in response to a column redundancy signal being false, and to select its second input terminal in response to a column redundancy signal being true.

[0057] Clause 6. The memory according to any one of Clauses 1 to 5, each column further includes:

[0058] A write column redundancy multiplexer has a first output terminal coupled to an input terminal of the write driver and a second output terminal coupled to a write driver in an adjacent column.

[0059] Clause 7. The memory as described in Clause 6, each column further includes:

[0060] A scan trigger, wherein the write column redundancy multiplexer includes an input terminal coupled to the output of the scan trigger.

[0061] Clause 8. The memory as described in Clause 7, wherein the scan trigger includes a master latch and a slave latch.

[0062] Clause 9. The memory according to any one of Clauses 1 to 8, wherein the first read multiplexer transistor and the second read multiplexer transistor each comprise a p-type metal-oxide-semiconductor (PMOS) transistor.

[0063] Clause 10. The memory pursuant to Clause 5 further includes:

[0064] Multiple redundant logic circuits corresponding to the plurality of columns, each redundant logic circuit being configured to process multiple decoded redundant address bits to generate the column redundant signal corresponding to the column.

[0065] Clause 11. The memory according to Clause 10, wherein each redundant logic circuit includes a first logic gate configured to process the column redundancy signal from the preceding redundant logic circuit in the redundant logic circuit.

[0066] Clause 12. The memory as described in Clause 11, wherein each first logic gate is a NOR gate.

[0067] Clause 13. The memory according to Clause 11, wherein each redundant logic circuit further includes a second logic gate configured to process the redundant address bits of the plurality of decoded circuits.

[0068] Clause 14. The memory as described in Clause 13, wherein each second logic gate comprises a NAND gate.

[0069] Clause 15. The memory according to any one of Clauses 1 to 14 further comprises:

[0070] A first write multiplexer transistor is coupled between the bit line and the write data output terminal; and

[0071] A second write multiplexer transistor is coupled between the complementary bit line and the complementary write data output terminal.

[0072] Clause 16. The memory according to any one of Clauses 10 to 13 further comprises:

[0073] Redundant decoder, the redundant decoder comprising:

[0074] A gated logic gate configured to process a column redundancy enable signal with a gated signal, wherein the redundancy decoder is configured to decode a fuse word in response to an assertion from the output signal of the gated logic gate.

[0075] Clause 17. The memory pursuant to Clause 16, wherein the gated logic gates include NAND gates.

[0076] Clause 18. A method for testing columns in a memory, comprising:

[0077] In response to the column redundancy signal being false during the scan operation mode:

[0078] In response to the trigger edge of the scan clock signal, the shift-in signal is routed to the write driver via a write column redundancy multiplexer;

[0079] The write driver processes the shift-in signal to form a pair of write driver output signals;

[0080] The pair of write driver output signals are routed to the sense amplifier via a scan multiplexer;

[0081] Sensing the pair of write driver output signals in the sensing amplifier to form a sensed version of the shift-in signal; and

[0082] The sensed version of the shifted-in signal is routed to the data output latch by reading the column redundancy multiplexer.

[0083] Clause 19. The method described pursuant to Clause 18 further includes:

[0084] In response to the column redundancy signal of the column being true during the scan operation mode:

[0085] The shift-in signal is routed to the first adjacent column via the write column redundancy multiplexer; and

[0086] The sensed version of the shift-in signal is routed from the second adjacent column to the data output latch via the read column redundancy multiplexer.

[0087] Clause 20. The method according to any one of Clauses 18 to 19 further includes:

[0088] Assert the gated signal at the gated delay preceding the trigger edge of the scan clock signal;

[0089] In response to the assertion of the gated signal, the fuse word is decoded to form a plurality of redundant decoded bits; and

[0090] The redundant bits of the multiple decoded data are processed to form the column redundancy signal.

[0091] Clause 21. A memory comprising:

[0092] Multiple columns, each column including:

[0093] Bit line;

[0094] Complementary bit lines;

[0095] A first read multiplexer transistor is coupled to the bit line and has a read terminal;

[0096] A second read multiplexer transistor is coupled to the complementary bit line and has a complementary read terminal;

[0097] A sensing amplifier having a first input terminal coupled to the readout terminal and a second input terminal coupled to the complementary readout terminal;

[0098] A read column redundancy multiplexer, the read column redundancy multiplexer having a first input terminal coupled to the output terminal of the sense amplifier, and a second input terminal coupled to the sense amplifier in an adjacent column; and

[0099] A data output latch having an input terminal that is coupled to the output terminal of the read column redundant multiplexer via a direct electrical connection.

[0100] Clause 22. The memory according to Clause 21, wherein the read column redundancy multiplexer is configured to select its first input terminal in response to a column redundancy signal being false, and to select its second input terminal in response to a column redundancy signal being true.

[0101] Clause 23. The memory according to any one of Clauses 21 to 22, each column further includes:

[0102] Write to the drive; and

[0103] A write column redundancy multiplexer has a first output terminal coupled to an input terminal of the write driver and a second output terminal coupled to a write driver in an adjacent column.

[0104] Clause 24. The memory pursuant to Clause 23, each column further includes:

[0105] A scan trigger, wherein the write column redundancy multiplexer includes an input terminal coupled to the output terminal of the scan trigger.

[0106] Clause 25. A memory comprising:

[0107] A redundant decoder, comprising a gated logic gate and a fuse decoder, the fuse decoder having an enable input terminal coupled to the output terminal of the gated logic gate, and the redundant decoder further comprising multiple output terminals for address signals for multiple decoding;

[0108] Multiple column redundancy logic circuits arranged in series, each column redundancy logic circuit having a set of input terminals for receiving a corresponding set of redundant address bits, and an output terminal for column redundancy signals; and

[0109] A scan trigger, configured to latch the column redundancy signal from the last column redundancy logic circuit in the column redundancy logic circuit.

[0110] Clause 26. The memory pursuant to Clause 25, wherein the gated logic gates include NAND gates.

[0111] Clause 27. The memory according to any one of Clauses 25 to 26, wherein each redundant logic circuit is configured to assert its column redundancy signal in response to an assertion of the column redundancy signal from the preceding redundant logic circuit in the redundant logic circuit.

[0112] Clause 28. The memory according to Clause 26, wherein each redundant logic circuit further includes a first logic gate configured to process the column redundancy signal from the preceding redundant logic circuit in the redundant logic circuit.

[0113] Clause 29. The memory according to Clause 28, wherein each redundant logic circuit further includes a second logic gate configured to process a corresponding set of decoded redundant address bits.

[0114] Clause 30. The memory pursuant to Clause 29, wherein each first logic gate comprises a NOR gate, and wherein each second logic gate comprises a NAND gate.

[0115] As those skilled in the art will understand to date and depending on the specific application at hand, many modifications, substitutions, and variations can be made to the materials, apparatus, configuration, and methods of use of the devices disclosed herein without departing from the spirit and scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments shown and described herein (as they are merely examples of this disclosure), but should be fully equivalent to the appended claims and their functional equivalents.

Claims

1. A memory, comprising: Multiple columns, each column including: Bit line; Complementary bit lines; A first read multiplexer transistor is coupled to the bit line and has a read terminal; A second read multiplexer transistor is coupled to the complementary bit line and has a complementary read terminal; A write driver having a write data output terminal and a complementary write data output terminal; A write column redundancy multiplexer has a first output terminal coupled to an input terminal of the write driver and a second output terminal coupled to a write driver in an adjacent column. A scan multiplexer configured to select, in response to a scan mode signal, between: a first pair of input terminals coupled to the write data output terminal and the complementary write data output terminal, and a second pair of input terminals coupled to the read terminal and the complementary read terminal; A sensing amplifier, coupled to the output of the scan multiplexer; and A read column redundancy multiplexer has a first input terminal coupled to the output terminal of the sense amplifier and a second input terminal coupled to the output terminal of a sense amplifier in an adjacent column.

2. The memory of claim 1, wherein the scan multiplexer is configured to select the first pair of input terminals during a scan mode and select the second pair of input terminals during a read operation.

3. The memory according to claim 1, each column further includes a data output latch having an input terminal coupled to the output terminal of the read column redundancy multiplexer.

4. The memory of claim 3, wherein the read column redundancy multiplexer is configured to select its first input terminal in response to a false column redundancy signal and to select its second input terminal in response to a true column redundancy signal.

5. The memory according to claim 1, wherein each column further comprises: A scan trigger, wherein the write column redundancy multiplexer includes an input terminal coupled to the output terminal of the scan trigger.

6. The memory of claim 5, wherein the scan trigger comprises a master latch and a slave latch.

7. The memory of claim 1, wherein the first read multiplexer transistor and the second read multiplexer transistor each comprise a p-type metal-oxide-semiconductor (PMOS) transistor.

8. The memory according to claim 4, further comprising: Multiple redundant logic circuits corresponding to the plurality of columns, each redundant logic circuit being configured to process multiple decoded redundant address bits to generate the column redundant signal corresponding to the column.

9. The memory of claim 8, wherein each redundant logic circuit includes a first logic gate configured to process the column redundancy signal from the preceding redundant logic circuit in the redundant logic circuit.

10. The memory of claim 9, wherein each first logic gate is a NOR gate.

11. The memory of claim 9, wherein each redundant logic circuit further comprises a second logic gate configured to process the redundant address bits of the plurality of decoded circuits.

12. The memory of claim 11, wherein each second logic gate comprises a NAND gate.

13. The memory according to claim 1, further comprising: A first write multiplexer transistor is coupled between the bit line and the write data output terminal; and A second write multiplexer transistor is coupled between the complementary bit line and the complementary write data output terminal.

14. The memory according to claim 8, further comprising: Redundant decoder, the redundant decoder comprising: A gated logic gate configured to process a column redundancy enable signal with a gated signal, wherein the redundancy decoder is configured to decode a fuse word in response to an assertion from the output signal of the gated logic gate.

15. The memory of claim 14, wherein the gated logic gates include NAND gates.

16. A method for testing columns in a memory, comprising: In response to the column redundancy signal being false during the scan operation mode: In response to the trigger edge of the scan clock signal, the shift-in signal is routed to the write driver via a write column redundancy multiplexer; The write driver processes the shift-in signal to form a pair of write driver output signals; The pair of write driver output signals are routed to the sense amplifier via a scan multiplexer; The pair of write driver output signals in the sensing amplifier are sensed to form a sensed version of the shift-in signal; as well as The sensed version of the shifted-in signal is routed to the data output latch by reading the column redundancy multiplexer.

17. The method of claim 16, further comprising: In response to the column redundancy signal of the column being true during the scan operation mode: The shift-in signal is routed to the first adjacent column via the write column redundancy multiplexer; as well as The sensed version of the shift-in signal is routed from the second adjacent column to the data output latch via the read column redundancy multiplexer.

18. The method of claim 16, further comprising: Assert the gated signal at the gated delay preceding the trigger edge of the scan clock signal; In response to the assertion of the gated signal, the fuse word is decoded to form a plurality of redundant bits for decoding; as well as The redundant bits of the multiple decoded data are processed to form the column redundancy signal.

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