Method for failure prediction of semiconductor device and semiconductor device

Abstract

The semiconductor element (15) constituting the trench gate structure comprises multiple main cells (14) including multiple first cells (141) and second cells (142). The second cells, designed to predict failures in the first cells, have a structure that makes it easier for the gate insulating film to be damaged by current flow than the first cells, and are fewer in number than the first cells. Furthermore, during semiconductor element operation, a common gate drive voltage is applied to the gates of the first cells and the gates of the second cells. Electrical characteristics are measured, and failures in the second cells caused by current flow during operation are detected. To prevent the application of a gate drive voltage to the faulty second cell, the gate of the faulty second cell is electrically isolated from the gate of the first cell. Failures in the first cell are predicted based on the failures in the second cell.

Description

[0001] Citation of relevant applications

[0002] This application is based on Japanese Patent Application No. 2021-102750, filed on June 21, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The disclosure in this specification relates to a method for predicting failures in a semiconductor device and to a semiconductor device. Background Technology

[0004] Patent Document 1 discloses a method for evaluating the lifetime of a trench-structured MOS semiconductor device. The contents of prior art documents are incorporated herein by reference as an explanation of the technical elements herein.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2008-205230 Summary of the Invention

[0008] In Patent Document 1, a MOS semiconductor device is used, employing a sensing element with a thinner film thickness (including both the main element and the gate oxide film) than the main element. The lifetime of the main element is predicted by subjecting the sensing element to accelerated testing. However, the stress introduced by the accelerated testing differs from the stress actually applied in the market. Furthermore, because the accelerated testing applies stress to the sensing element that leads to failure, the sensing element cannot be used in the market, resulting in reduced utilization efficiency of the semiconductor device, i.e., chip area utilization efficiency. Further improvements are required for the failure prediction method and the semiconductor device itself, as described above or in other unmentioned viewpoints.

[0009] One object of this disclosure is to provide a fault prediction method and a semiconductor device that can suppress the reduction in the utilization efficiency of semiconductor elements and can predict faults with high accuracy.

[0010] The fault prediction method for semiconductor devices disclosed herein includes a fault prediction method for semiconductor devices comprising a trench gate structure of semiconductor elements consisting of multiple main cells connected in parallel, wherein,

[0011] The multiple main units include multiple first units and second units. The second units, designed to predict failures of the first units, have a structure that makes it easier for the gate insulating film to be damaged by current than the first units, and are fewer in number than the first units.

[0012] When driving the semiconductor device, a common gate drive voltage is applied to the gate of the first unit and the gate of the second unit.

[0013] The electrical characteristics were measured and faults in the second unit caused by power-on during operation were detected.

[0014] In order to prevent the application of a gate drive voltage to the faulty second cell, the gate of the faulty second cell is electrically disconnected from the gate of the first cell.

[0015] Faults in the first unit can be predicted based on faults in the second unit.

[0016] According to the fault prediction method for the semiconductor device disclosed herein, a common gate drive voltage as the first unit is applied to the second unit during the driving of the semiconductor element. When a fault is detected in the second unit, the gate of the faulty second unit is electrically disconnected from the gate of the first unit. Since the second unit also functions as a main unit constituting the semiconductor element before the fault occurs, the reduction in the utilization efficiency of the semiconductor element can be suppressed.

[0017] In addition, electrical characteristics are measured and faults in the second unit caused by energization during operation are detected. Since the second unit actually fails due to stress applied in the market, faults in the first unit, i.e., faults in the semiconductor element, can be predicted with high accuracy based on the faults in the second unit.

[0018] The semiconductor devices disclosed herein include semiconductor elements with trench gate structures.

[0019] The aforementioned semiconductor element is composed of multiple main units connected in parallel, wherein the aforementioned semiconductor device includes:

[0020] The semiconductor substrate has a main cell region and an outer peripheral region. The main cell region is a region in which multiple main cells are disposed, and has multiple first cells and second cells as main cells. The second cells have a structure that makes it easier to destroy the gate insulating film by energizing the first cells in order to predict the failure of the first cells, and the number of the second cells is less than that of the first cells. The outer peripheral region surrounds the main cell region.

[0021] Multiple gate pads, including a first pad and a second pad, wherein the first pad is connected to the gate of a first unit, and the second pad is separately disposed from the first pad and connected to the gate of a second unit, the multiple gate pads being disposed on one surface of a semiconductor substrate to apply a gate drive voltage to the gate of a main unit; and

[0022] Multiple switches, including a first switch connected to a first pad and a second switch connected to a second pad, are individually configured for the gate pad and allow or disable the application of a gate drive voltage to the gate pad.

[0023] When driving the semiconductor components, if the second unit is functioning correctly, all switches are turned on. If a fault occurs, only the second switch corresponding to the faulty second unit is turned off, and the remaining switches are turned on.

[0024] When the semiconductor element is not driven, the first switch is turned off and the second switch is turned on.

[0025] According to the disclosed semiconductor device, when the semiconductor element is driven, a gate drive voltage common to the first unit is also applied to the second unit. When the second unit fails, the gate drive voltage applied to the failed second unit can be cut off. That is, before the second unit fails, since the second unit also functions as a main unit constituting the semiconductor element, the reduction in the utilization efficiency of the semiconductor element can be suppressed.

[0026] Furthermore, the second unit fails because it operates together with the first unit during the driving of the semiconductor element. That is, it fails due to the stress actually applied in the market. Therefore, it is possible to predict the failure of the first unit, i.e., the failure of the semiconductor element, with high accuracy based on the failure of the second unit.

[0027] Another semiconductor device disclosed herein includes a semiconductor element with a trench gate structure.

[0028] The aforementioned semiconductor element is composed of multiple main units connected in parallel, wherein the other semiconductor device mentioned above includes:

[0029] The semiconductor substrate has a main cell region and an outer peripheral region. The main cell region is a region in which multiple main cells are disposed, and has multiple first cells and second cells as main cells. The second cells have a structure that makes it easier to destroy the gate insulating film by energizing the first cells in order to predict the failure of the first cells, and the number of the second cells is less than that of the first cells. The outer peripheral region surrounds the main cell region.

[0030] Multiple gate pads, including a first pad and a second pad, wherein the first pad is connected to the gate of a first unit, and the second pad is separately disposed from the first pad and connected to the gate of a second unit, the multiple gate pads being disposed on one surface of a semiconductor substrate to apply a gate drive voltage to the gate of a main unit; and

[0031] The aforementioned fuse connects the second pad and the first pad separately.

[0032] With the failure of the second unit, the fuse connected to the second pad corresponding to the failed second unit blows.

[0033] According to the disclosed semiconductor device, during the driving of the semiconductor element, a gate drive voltage common to the first unit can also be applied to the second unit via a fuse. Furthermore, if the second unit fails due to damage to the gate insulating film, the fuse blows, cutting off the gate drive voltage applied to the failed second unit. That is, since the second unit also functions as a main unit constituting the semiconductor element before the second unit fails, the reduction in the utilization efficiency of the semiconductor element can be suppressed.

[0034] Furthermore, the second unit fails because it operates together with the first unit during the driving of the semiconductor element. That is, it fails due to the stress actually applied in the market. Therefore, it is possible to predict the failure of the first unit, i.e., the failure of the semiconductor element, with high accuracy based on the failure of the second unit.

[0035] This specification discloses multiple methods that employ different technical means to achieve various objectives. The claims and the symbols enclosed in parentheses within them illustratively indicate a correspondence with portions of the embodiments described later and are not intended to limit the scope of the technology. The objectives, features, and effects disclosed in this specification will become clearer with reference to the following detailed description and accompanying drawings. Attached Figure Description

[0036] Figure 1 This is a top view showing the semiconductor device in the first embodiment.

[0037] Figure 2 It is along Figure 1 A cross-sectional view along lines I, II, and I.

[0038] Figure 3 This is a diagram showing the area around the gate pad.

[0039] Figure 4 This is a diagram illustrating an example of the opening and closing modes of a switch during operation.

[0040] Figure 5 This is a diagram illustrating an example of the opening and closing modes of a switch when it is not driven.

[0041] Figure 6 This is a diagram illustrating an example of the switching mode when the second unit malfunctions and the switch is in operation.

[0042] Figure 7 This is a flowchart illustrating a fault prediction method.

[0043] Figure 8 This is a flowchart illustrating the process during driver execution.

[0044] Figure 9 This is a flowchart illustrating the processing when not driven.

[0045] Figure 10 This is a diagram showing the periphery of the gate pad in the semiconductor device of the second embodiment.

[0046] Figure 11 This is a diagram showing the periphery of the gate pad in a semiconductor device according to a third embodiment.

[0047] Figure 12 This is a flowchart illustrating a fault prediction method.

[0048] Figure 13 This is a diagram illustrating fault detection.

[0049] Figure 14 This is a graph showing the predicted failure period of the first unit.

[0050] Figure 15 This is a cross-sectional view showing a semiconductor device according to a fourth embodiment.

[0051] Figure 16 This is a cross-sectional view showing a semiconductor device according to the fifth embodiment. Detailed Implementation

[0052] Hereinafter, several embodiments will be described based on the accompanying drawings. Furthermore, in each embodiment, repeated descriptions are sometimes omitted by using the same symbols to denote corresponding constituent elements. When only a portion of the structure is described in each embodiment, structures from other previously described embodiments can be applied to the remaining parts of that structure. Moreover, not only combinations of structures explicitly described in the descriptions of each embodiment are possible, but also combinations of structures from multiple embodiments can be partially combined with each other, provided that such combinations do not particularly hinder them.

[0053] (First Implementation)

[0054] First, the schematic structure of the semiconductor device will be explained.

[0055] Semiconductor Devices

[0056] Next, based on Figure 1 and Figure 2 The structure of the semiconductor device is explained. Figure 1 This is a top view showing a semiconductor device. Figure 1 In order to show the connection between the gate and the gate wiring, the protective film and interlayer insulating film on the semiconductor substrate are omitted, and the source is represented by a dashed line. In addition, the switch provided on the semiconductor substrate is shown in a simplified diagram. Figure 2 It is along Figure 1 A cross-sectional view along lines I, II, and I.

[0057] Hereinafter, the thickness direction of the semiconductor substrate is defined as the Z-direction. The arrangement direction of the trenches orthogonal to the Z-direction is defined as the Y-direction. The direction orthogonal to both the Z and Y directions is defined as the X-direction. Unless otherwise specified, the top view viewed from the Z-direction is simply referred to as a top view.

[0058] like Figure 1 As shown, the semiconductor device 10 includes a semiconductor substrate 11. The semiconductor substrate 11 is sometimes referred to as a semiconductor chip. The semiconductor substrate 11 is made of silicon (Si), a wide-bandgap semiconductor with a wider bandgap than silicon, or the like. Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond.

[0059] The semiconductor substrate 11 has a main cell region 12 and an outer peripheral region 13. The outer peripheral region 13 surrounds the main cell region 12 when viewed from above. The outer peripheral region 13 is the outer periphery of the main cell region 12, i.e., compared to... Figure 1 The area shown by the dashed line is further outward. Although the illustration is omitted, a pressure-resistant structure, such as a protective ring, is formed in the outer peripheral region 13.

[0060] The main cell region 12 is sometimes referred to as the element formation region, element region, main region, active region, etc. Multiple main cells 14 are disposed in the main cell region 12. The main cell 14 is sometimes referred to as a unit cell, unit structure, unit circuit, element, etc. Multiple main cells 14 are connected in parallel to each other to form a trench gate structure semiconductor element 15. The semiconductor device 10 includes the semiconductor element 15.

[0061] The semiconductor element 15 in this embodiment is a MOSFET formed on a semiconductor substrate 11 made of SiC. The trench gate structure semiconductor element 15 is not limited to a MOSFET. For example, an IGBT can be used instead of a MOSFET. MOSFET is short for Metal Oxide Semiconductor Field Effect Transistor. IGBT is short for Insulated Gate Bipolar Transistor.

[0062] like Figure 2As shown, the semiconductor substrate 11 has a drain region 20, a drift region 21, a base region 22, a source region 23, and a base contact region 24. The semiconductor substrate 11 is formed, for example, by epitaxial growth (Japanese: エピタキシャル成長), ion implantation of impurities, etc., to form each semiconductor region made of SiC on the SiC substrate. The semiconductor region is sometimes referred to as a semiconductor layer, a diffusion layer, etc. The semiconductor substrate 11 has a front surface 11a and a back surface 11b as its main surfaces (plate surfaces). The back surface 11b is the surface opposite to the front surface 11a in the Z direction.

[0063] The drain region 20 constitutes the front surface 11a of the semiconductor substrate 11. The drain region 20 is an n-conductive type (n+) semiconductor region with a higher impurity concentration than the drift region 21.

[0064] The drift region 21 is formed on the surface of the drain region 20 opposite to the surface forming the front surface 11a. The drift region 21 is an n-conductive type (n) semiconductor region with a lower impurity concentration than the drain region 20. The drain region 20 and the drift region 21 are provided in substantially the entire region of the semiconductor substrate 11 in a top view.

[0065] The base region 22 is formed on the surface of the drift region 21 opposite to the surface on the drain region 20 side. The base region 22 is a p-conductive type (p) semiconductor region. The base region 22 is mainly provided in the main unit region 12 of the semiconductor substrate 11. The base region 22 is provided in the surface layer on the back surface 11b side of the semiconductor substrate 11. If the n-conductive type is set as the first conductive type, then the p-conductive type is the second conductive type.

[0066] The source region 23 is provided in the surface layer on the back surface 11b side within the base region 22. The source region 23 is an n-conductive type (n+) semiconductor region with a higher impurity concentration than the drift region 21.

[0067] The base contact region 24 is provided in the surface layer on the back surface 11b side within the base region 22. The base contact region 24 is provided adjacent to the source region 23. The base contact region 24 is a p-conductive type (p+) semiconductor region with a higher impurity concentration than the base region 22. The source region 23 and the base contact region 24 are provided in the main unit region 12. The semiconductor substrate 11 of the present embodiment has the base contact region 24 as an example, but it can also be configured not to have the base contact region 24.

[0068] Trench 25 is formed in the semiconductor substrate 11 with the above-described structure. The trench 25 is formed to a predetermined depth with respect to the back surface 11b. The trench 25 penetrates the source region 23 and the base region 22. The leading edge of the trench 25 reaches the drift region 21. The base region 22 and the source region 23 are formed to contact the side surfaces of the trench 25. Multiple trenches 25 are formed in the main cell region 12 of the semiconductor substrate 11. Each trench 25 extends along the X direction. The multiple trenches 25 are arranged at approximately equal intervals in the Y direction and appear as stripes when viewed from above. The trenches 25 are arranged in two rows.

[0069] The trench 25 is mainly formed in the main unit region 12. The trench 25 defines the main unit 14. Each of the main units 14 includes a trench 25, and the multiple main units 14 are arranged along the Y direction.

[0070] A gate insulating film 26 is formed in the wall of the trench 25. Then, a gate 27 is formed on the surface of the gate insulating film 26 to fill the trench 25. The gate 27 penetrates the source region 23 and the base region 22 and reaches the drift region 21. A plurality of gates 27 are formed in the main cell region 12 of the semiconductor substrate 11. Each gate 27 extends along the X direction. The plurality of gates 27 are arranged at approximately equal intervals in the Y direction and appear as stripes when viewed from above. The gates 27 are arranged in two rows.

[0071] A source electrode 28 is formed on the back side 11b of the semiconductor substrate 11. The source electrode 28 is mainly formed on the main cell region 12. The source electrode 28 is electrically connected to the source region 23. The source electrode 28 is electrically connected to the base region 22 via the base contact region 24. The source electrode 28 is electrically separated from the gate electrode 27 through the interlayer insulating film 29. Pads serving as signal electrodes are also formed on the back side 11b of the semiconductor substrate 11. The pads include a plurality of gate pads 30.

[0072] A drain 31 is formed on one side 11a of the semiconductor substrate 11. The drain 31 is formed over the entire area of ​​one side 11a. The drain 31 is electrically connected to the drain region 20.

[0073] Thus, a MOS structure with a gate 27 having a trench structure is formed in each main unit 14 of the semiconductor substrate 11. Furthermore, multiple main units 14 are connected in parallel to each other to form a semiconductor element 15 with a channel gate structure, specifically forming a vertical n-channel MOSFET.

[0074] The semiconductor device 10 can be applied to power conversion circuits such as inverters or converters.

[0075] <Main Unit>

[0076] Next, based on Figure 1 and Figure 2The main unit 14 will be described.

[0077] like Figure 1 and Figure 2 As shown, a plurality of main cells 14 are disposed in the main cell region 12 of the semiconductor substrate 11. The plurality of main cells 14 are connected in parallel to each other. The plurality of main cells 14 include a plurality of first cells 141 and a smaller number of second cells 142 than the number of first cells 141. The majority of the plurality of main cells 14 are first cells 141, and the remainder are second cells 142.

[0078] The first unit 141 is the main part that functions as a semiconductor element 15. The first unit 141 occupies most of the main unit region 12. The first units 141 have a common structure. The first unit 141 is sometimes referred to as a general structure part, a general element part, a standard unit, etc.

[0079] The second unit 142 is a main unit 14 provided for predicting faults in the first unit 141. The second unit 142 has a structure that makes the gate insulating film 26 more easily damaged than the first unit 141 when energized, in order to predict faults in the first unit 141. The second unit 142 is sometimes referred to as a detection structure, detection element, fault detection unit, detection unit, etc. The second unit 142, together with the first unit 141, functions as a semiconductor element 15 until a fault occurs. The main unit 14 includes at least one second unit 142.

[0080] The main unit 14 of this embodiment includes a plurality of second units 142, each with a different vulnerability of the gate insulating film 26. The second units 142 include three types of second units 142a, 142b, and 142c, each with a different thickness of the gate insulating film 26. In the second units 142a, 142b, and 142c, the gate 27 is approximately the same size, but because the trench 25 is different in size, the thickness of the gate insulating film 26 is different.

[0081] The thinner the gate insulating film 26, the higher the electric field applied to it, and the easier it is for insulation failure to occur. For example... Figure 2 As shown, the gate insulating film 26 of the second units 142a, 142b, and 142c is thinner than the gate insulating film 26 of the first unit 141. The gate insulating film 26 of the second unit 142a is the thinnest, followed by the gate insulating film of the second unit 142b. The thickness of the gate insulating film 26 satisfies the relationship: second unit 142a < second unit 142b < second unit 142c < first unit 141.

[0082] In addition, such as Figure 1As shown, the second unit 142 is disposed at the end of the main unit region 12 in the Y direction, which is the arrangement direction of the plurality of main units 14. In this embodiment, the main unit 14 corresponding to the three gates 27, starting from the end of the main unit region 12 on the side farther from the gate pad 30, is called the second unit 142. The second unit 142a is disposed at the position furthest from the gate pad 30 in the Y direction. The second unit 142b is disposed between the second units 142a and 142c. All the main units 14 that are closer to the gate pad 30 than the second unit 142c are the first units 141.

[0083] <Gate pads and their connection structures>

[0084] Next, based on Figure 1 and Figure 3 The gate pad 30 and the connection structure between the gate pad 30 and the gate 27 are described. Figure 3 This is a diagram showing the area around the gate pad.

[0085] Gate pad 30 is a pad connected to gate 27 via gate wiring described later. The plurality of gate pads 30 includes a first pad 301 and a second pad 302. The first pad 301 is electrically connected to the gate 27 of the first cell 141 in the main cell 14. The second pad 302 is electrically connected to the gate 27 of the second cell 142 in the main cell 14.

[0086] The second pad 302 in this embodiment includes second pads 302a, 302b, and 302c. Second pad 302a is electrically connected to the gate 27 of the second unit 142a. Second pad 302b is electrically connected to the gate 27 of the second unit 142b. Second pad 302c is electrically connected to the gate 27 of the second unit 142c.

[0087] The semiconductor device 10 also includes a common pad 32, a plurality of gate wirings 33, and a plurality of switches 34. The common pad 32 is a pad for the plurality of gate pads 30 to share a common connection. A gate drive voltage is applied to the common pad 32 by a drive circuit (driver) not shown.

[0088] The semiconductor device 10 of this embodiment includes a first pad 301, two second pads 302a, two second pads 302b, two second pads 302c, and a common pad 32. The first pad 301 and the second pads 302 are arranged along the X direction. Specifically, starting from one end, they are arranged in the order of second pads 302a, second pads 302b, second pads 302c, first pad 301, second pads 302c, second pads 302b, and second pads 302a. The first pad 301, the second pads 302, and the common pad 32 are arranged along the Y direction. In the Y direction, the common pad 32 is disposed on the end side of the semiconductor substrate 11, and the first pad 301 and the second pads 302 are disposed on the main cell region 12 side.

[0089] Gate wiring 33 electrically connects gate 27 to gate pad 30. Multiple gate wirings 33 include a first wiring 331 and a second wiring 332. First wiring 331 electrically connects the gate 27 of the first cell 141 to the first pad 301. Second wiring 332 electrically connects the gate 27 of the second cell 142 to the second pad 302.

[0090] The second wiring 332 in this embodiment includes second wirings 332a, 332b, and 332c. Second wiring 332a electrically connects the gate 27 of the second unit 142a to the second pad 302a. Second wiring 332b electrically connects the gate 27 of the second unit 142b to the second pad 302b. Second wiring 332c electrically connects the gate 27 of the second unit 142c to the second pad 302c. As described above, since the gate 27 is arranged in two columns, two first wirings 331 and two second wirings 332a, 332b, and 332c are respectively provided.

[0091] Switch 34 allows or disables the application of (input) gate drive voltage to gate pad 30. Switch 34 is configured individually for gate pad 30. In this embodiment, switch 34 is located in the power path of common pad 32 and gate pad 30. One of the main terminals of switch 34, for example, the drain terminal, is connected to common pad 32, and the other main terminal, for example, the source terminal, is connected to gate pad 30.

[0092] Switch 34 is formed on the back side 11b of semiconductor substrate 11. Switch 34 is, for example, a horizontal MOSFET. Switch 34 is formed by multiple layers, including a semiconductor thin film, a gate, and a gate insulating film. In the semiconductor thin film, a base region, a drain region, and a source region are formed by doping with impurities.

[0093] The multiple switches 34 include a first switch 341 and a second switch 342. The first switch 341 is disposed in the power path between the common pad 32 and the first pad 301. When the first switch 341 is turned on, the common pad 32 and the first pad 301 are electrically connected (conducted); when the first switch 341 is turned off, the electrical connection between the common pad 32 and the first pad 301 is cut off.

[0094] A second switch 342 is disposed in the power path of the common pad 32 and the second pad 302. The second switch 342 is disposed separately for the second pad 302. In this embodiment, the second switch 342 includes second switches 342a, 342b, and 342c. Second switch 342a is disposed in the power path of the common pad 32 and the second pad 302a. When the second switch 342a is turned on, the common pad 32 and the second pad 302a are electrically connected; when the second switch 342a is turned off, the electrical connection between the common pad 32 and the second pad 302a is disconnected.

[0095] Similarly, a second switch 342b is disposed in the power path of the common pad 32 and the second pad 302b. By turning on the second switch 342b, the common pad 32 and the second pad 302b are electrically connected; by turning off the second switch 342b, the electrical connection between the common pad 32 and the second pad 302b is disconnected.

[0096] <Switch On / Off Mode>

[0097] Next, based on Figures 3-6 The opening and closing modes of switch 34 will be explained. Figure 4 The opening and closing modes of switch 34 are shown when semiconductor element 15 is driven and the second unit 142 is not malfunctioning. Figure 5 The opening and closing modes of switch 34 are shown when semiconductor element 15 is not driven and the second unit 142 is activated (detection action). Figure 6 The on / off modes of switch 34 are shown when semiconductor element 15 is driven and a portion of the second unit 142 malfunctions. Figures 4-6 In the diagram, switch 34 is shown in a simplified form.

[0098] like Figure 3 As shown, a gate drive voltage for driving the semiconductor element 15, i.e., turning the drive on and off, is supplied from the gate drive power supply 80. The gate drive power supply 80 is a power supply used to apply a gate drive voltage to the gate 27 of the semiconductor element. The gate drive power supply 80 generates the gate drive voltage based on control commands from a control circuit (not shown) and outputs it to the common pad 32 of the semiconductor device 10.

[0099] On the other hand, a gate drive voltage for turning each switch 34 on and off is supplied from the switching power supply 81. The switching power supply 81 is provided individually for each switch 34. The switching power supply 81 is electrically connected to the gate of the corresponding switch 34.

[0100] A current sensor 82 is provided between the gate drive power supply 80 and the common pad 32. The current sensor 82 detects the gate current Igs, which is an electrical characteristic. Faults in the second unit 142 can be detected based on the detection value of the current sensor 82. At least one of the gate drive power supply 80, the switching power supply 81, and the current sensor 82 is formed, for example, in the drive circuit of the semiconductor element 15.

[0101] Semiconductor element 15 supplies power to a load (e.g., an electric motor) not shown by means of a drive. The driving of semiconductor element 15 is the period during which power is supplied to the load. The driving period is sometimes referred to as normal operation, normal use, etc. During the driving of semiconductor element 15 and if the second unit 142 does not malfunction, such as... Figure 4 As shown, the first switch 341 is turned on, and all the second switches 342 are turned on. Thus, a gate drive voltage is applied from the gate drive power supply 80 to the gate 27 of the first cell 141 via the common pad 32, the first switch 341, and the first pad 301. Additionally, a gate drive voltage is applied from the gate drive power supply 80 to the gate 27 of each of the second cells 142 via the common pad 32, the second switch 342, and the second pad 302. Therefore, all the main cells 14 function as semiconductor elements 15.

[0102] In this embodiment, the second unit 142 performs a detection operation during periods when no power is supplied to the load, i.e., when the semiconductor element 15 is not driven. Figure 5 As shown, only the second switch 342 corresponding to the second unit 142 that performs the detection action is turned on, while the other switches 34 are turned off. In this embodiment, multiple types of second units 142a, 142b, and 142c are sequentially activated to perform detection actions. As an example, Figure 5 The opening and closing modes of switch 34 are shown when the second unit 142a performs a detection operation.

[0103] like Figure 5As shown, only the second switch 342a is turned on, while the other second switches 342b, 342c and the first switch 341 are turned off. Thus, a gate drive voltage is applied from the gate drive power supply 80 to the gate 27 of the second unit 142a via the common pad 32, the second switch 342a, and the second pad 302a. Therefore, only the second unit 142a in the main unit 14 operates. The current sensor 82 detects the current flowing through the gate 27 of the second unit 142a in the main unit 14. By comparing the gate current detected by the current sensor 82 with a threshold used to determine insulation failure, a fault in the second unit 142a can be detected. Specifically, when the gate current exceeds the threshold, a fault is determined to have occurred in the second unit 142a.

[0104] The threshold can be set to detect states where insulation failure has occurred in the gate insulating film 26 or where a short circuit has occurred between the gate and source, or it can be set to detect states where there are signs (precursors) of insulation failure.

[0105] Similarly, when only the second switch 342b is turned on and the other second switches 342a, 342c and the first switch 341 are turned off, a gate drive voltage is applied only to the gate 27 of the second unit 142b. This allows for the detection of faults in the second unit 142b. Furthermore, when only the second switch 342c is turned on and the other second switches 342a, 342b and the first switch 341 are turned off, a gate drive voltage is applied only to the gate 27 of the second unit 142c. This allows for the detection of faults in the second unit 142c.

[0106] After detecting a fault in the second unit 142, the on / off mode of the switch 34 in the drive is switched so that no gate drive voltage is applied to the faulty second unit 142 when the semiconductor element 15 is driven. For example, in the case of detecting a fault in the second unit 142a, such as... Figure 6 As shown, the second switch 342a corresponding to the faulty second unit 142a is disconnected, and the remaining second switches 342b, 342c and the first switch 341 are turned on. Thus, the main unit 14 other than the faulty second unit 142a, namely the first unit 141 and the second units 142b, 142c, function as semiconductor elements 15.

[0107] <Fault Prediction Methods>

[0108] Next, based on Figures 7-9 The method for predicting faults in semiconductor device 10 is explained. Figure 7 This is a flowchart illustrating an example of a fault prediction method. Figure 8 This is a flowchart illustrating the process during driver execution. Figure 9This is a flowchart illustrating the processing during non-drive operation. The fault prediction method shown below can be executed at the switching moment between drive and non-drive operation of semiconductor element 15, or it can be executed repeatedly at a predetermined cycle.

[0109] like Figure 7 As shown, first, a determination is made as to whether the process is driven (step S100). If the process is driven, drive-time processing, i.e., normal use processing, is performed (step S200), and the example processing ends. If the process is not driven, non-drive-time processing, i.e., detection-time processing, is performed (step S300), and the series of processes ends.

[0110] like Figure 8 As shown, in the driving-time processing, firstly, it is determined whether a faulty second unit 142 exists (step S201). The faulty second unit 142 is the second unit 142 that is detected as faulty in the non-driving-time processing. Information related to the faulty second unit 142 is stored in memory in the non-driving-time processing described later.

[0111] In the case of a faulty second unit 142, the switch 34 corresponding to the fault-free main unit 14, i.e., the normal unit, is turned on, and the semiconductor element 15 is driven (step S202). Figure 6 As shown, the second switch 342 corresponding to the faulty second unit 142 is disconnected. Thus, the gate 27 of the faulty second unit 142 is electrically isolated from the gates 27 of the other main units 14, including the first unit 141, and no gate drive voltage is applied. The main units 14 other than the faulty second unit 142 function as semiconductor elements 15.

[0112] On the other hand, if the second unit 142 is fault-free, all switches 34 are turned on and the semiconductor element 15 is driven (step S203). Figure 4 As shown, the first switch 341 is turned on, and all the second switches 342 are turned on. Thus, all the main units 14 function as semiconductor elements 15. The drive process ends when the process in step S202 or S203 is completed.

[0113] like Figure 9 As shown, in the non-driving process, firstly, the first switch 341 is turned off (step S301). As a result, no gate drive voltage is applied to the gate 27 of the first unit 141.

[0114] Next, it is determined whether there is a second unit 142 that has not malfunctioned, that is, a normal second unit 142 (step S302).

[0115] When a normal second unit 142 exists, the second switch 342 is selectively turned on, and only the normal second unit 142 corresponding to the turned-on second switch 342 is activated, i.e., a detection operation is performed (step S303). Specifically, the corresponding second switch 342 is turned on so that the second unit 142, which did not perform a detection operation in this process and whose gate insulating film 26 is most easily damaged, is activated (detection operation).

[0116] For example, if none of the second units 142 perform any detection actions and no faults occur, such as Figure 5 As shown, only the second switch 342a is turned on, so that the second unit 142a, whose gate insulating film 26 is most easily damaged, performs a detection operation. By turning on the second switch 342a, only the gate drive voltage is applied to the gate 27 of the second unit 142a, and only the second unit 142a operates to detect faults. In addition, when there is only one normal second unit 142, the second switch 342 corresponding to the normal second unit 142 is turned on.

[0117] Next, during the detection operation, the gate current (current) is measured, and it is determined whether the measured current value exceeds the threshold used to determine insulation failure (step S304). For example, when the second unit 142a is activated for detection, the current value measured by the current sensor 82 is the value of the current flowing through the gate 27 of the second unit 142a.

[0118] If the current exceeds the threshold, a fault is determined to have occurred, and the fault of the second unit 142 that performed the detection action is stored (step S305). Next, the status of the second unit 142 selected in step S303 having completed the detection action is stored (step S306). If the current does not exceed the threshold in step S304, the processing in step S305 is not performed, but the processing in step S306 is performed instead.

[0119] After step S306 is executed, it is determined whether all detection actions have been performed on the normal second unit 142, i.e., whether all detection actions have been completed (step S307). If there are any normal second units 142 that have not performed detection actions, the process returns to step S303 and the subsequent processing is executed again.

[0120] After the detection is completed, the next step is to check whether the number of second units 142 that have detected faults has reached a predetermined number (step S308). If the predetermined number of faults has reached a predetermined number, it is predicted that the risk of the first unit 141 failing is high. That is, a fault prediction is made for the first unit 141. In this embodiment, if all three second units 142a, 142b, and 142c fail, it is predicted that the risk of the first unit 141 failing is high.

[0121] Then, the notification flag is turned on (step S309), and the non-driving process ends. External notifications are executed by turning on the flag. For example, an anomaly is notified via display or sound. The notification may, for example, remind the vehicle user to replace (switch) the semiconductor device 10.

[0122] If the number of faults in step S308 does not reach the specified number, the processing in step S309 is not executed; instead, the non-drive processing ends. Furthermore, if there is no normal second unit 142 in step S302, the processing after step S303 is not executed; instead, the non-drive processing ends.

[0123] In non-driven processing, the order of steps S301 and S302 can also be reversed. That is, step S301 can be executed after step S302 has been executed.

[0124] An example is shown in which the value of the gate current is compared with a threshold in step S304 to determine the fault of the second unit 142, i.e., the damage to the gate insulating film 26, but it is not limited to this. For example, nonlinear methods such as neural networks can also be used to determine the fault.

[0125] The above-mentioned fault prediction method can also be implemented by computer-executable instructions.

[0126] In one embodiment, the non-transitory computer-readable medium is configured to store computer-executable instructions that, when executed by a device such as a processor or computer, cause the device and / or related components to perform a method. It can also be configured as a fault prediction device including a processor and memory, the memory storing a program containing instructions that cause the processor to execute.

[0127] <Summary of the First Implementation>

[0128] As described above, according to the fault prediction method of the semiconductor device 10 of this embodiment, when the semiconductor element 15 is driven, the same gate drive voltage as the first unit 141 is also applied to the second unit 142. Furthermore, when a fault is detected in the second unit 142, the gate 27 of the faulty second unit 142 is electrically disconnected from the gate 27 of the first unit 141. Since the second unit 142 also functions as the main unit 14 constituting the semiconductor element 15 before a fault occurs, the reduction in chip area utilization efficiency, i.e., the reduction in the utilization efficiency of the semiconductor element 15, can be suppressed.

[0129] Furthermore, electrical characteristics are measured and faults in the second unit 142 caused by energization during operation are detected. As described above, the second unit 142 is driven in the same manner as the first unit 141 when the semiconductor element 15 is driven. Therefore, the second unit 142 actually fails due to stress applied in the market. Therefore, faults in the first unit 141, i.e., faults in the semiconductor element 15, can be predicted with high accuracy based on the faults in the second unit 142.

[0130] As described above, the fault prediction method of the semiconductor device 10 according to this embodiment can suppress the reduction in the utilization efficiency of the semiconductor element 15 and can predict faults with high accuracy.

[0131] Furthermore, the gate insulating film can break down due to the concentrated electric field during the operation of the semiconductor device, resulting in a short circuit between the gate and source, which is considered a fault. When a short circuit occurs, the device loses its function as a switching device. Such faults in semiconductor devices tend to occur at the ends where stress tends to concentrate. Semiconductor devices are composed of multiple main units (unit structures) connected in parallel; however, if the current concentration caused by a short circuit leads to a temperature rise and the main units are damaged over a large area, the device cannot be used as a semiconductor device.

[0132] In this embodiment, when a fault is detected in the second unit 142, the gate 27 of the faulty second unit 142 is electrically disconnected from the first unit 141, and no gate drive voltage is applied. This suppresses the possibility of other main units 14 malfunctioning due to a temperature rise caused by the fault in the second unit 142. In other words, it is possible to predict the fault in the first unit 141 with high accuracy while maintaining its function as a semiconductor element 15.

[0133] In this embodiment, the main unit 14 includes a plurality of second units 142 (142a, 142b, 142c) with varying fragility of the gate insulating film 26. Then, the failure of the first unit 141 is predicted based on the failures of the plurality of second units 142. Ideally, the plurality of second units 142 fail sequentially in order of fragility of the gate insulating film 26, for example, in order of thinness of the gate insulating film 26. Therefore, the overall failure progression of the semiconductor device can be estimated based on the failures of the plurality of second units 142. Thus, the accuracy of failure prediction can be further improved.

[0134] In this embodiment, when the number of failures in the second unit 142 reaches a predetermined number, the failure of the first unit 141 is predicted. As described above, since multiple second units 142 fail sequentially over time, the degree of failure progression can be estimated based on the number of failures in the second units 142. That is, the failure of the first unit 141 can be predicted.

[0135] In this embodiment, a notification is issued when a malfunction of the first unit 141 is predicted. This allows the vehicle user to be reminded to replace the semiconductor device 10.

[0136] In this embodiment, when the semiconductor element 15 is driven, the first switch 341 connected to the gate 27 of the first unit 141 is turned on, and the second switch 342 connected to the gate 27 of the second unit 142 is turned on. Thus, a common gate drive voltage is applied to the first unit 141 and the second unit 142. Furthermore, when the semiconductor element 15 is not driven, the first switch 341 is turned off, and the gate drive voltage is applied only to the second unit 142, which has the second switch 342 turned on, and its electrical characteristics are measured. A fault in the second unit 142 caused by the power-on during driving is detected. Then, by turning off the second switch 342 corresponding to the faulty second unit 142, the faulty second unit 142 is electrically isolated from the first unit 141.

[0137] In this way, by selectively switching on and off switches 34 (341, 342), the second unit 142 can also be activated during driving, while only the second unit 142 can be activated and faults detected during non-driving, without applying a gate drive voltage to the faulty second unit 142. Since the first unit 141 is not activated during non-driving, but only the second unit 142 with the second switch 342 turned on is activated, faults in the second unit 142 can be detected with high precision by measuring its electrical characteristics.

[0138] The semiconductor device 10 of this embodiment is configured to perform the fault prediction method described above. Specifically, the main unit 14 includes a plurality of first units 141 and a smaller number of second units 142 than the number of first units 141. Furthermore, the gate pad 30 includes a first pad 301 connected to the gate 27 of the first unit 141 and a second pad 302 separately disposed from the first pad 301 and connected to the gate 27 of the second unit 142. In addition, the semiconductor device 10 includes a plurality of switches 34 individually connected to the gate pad 30. The switches 34 include a first switch 341 connected to the first pad and a second switch 342 connected to the second pad 302.

[0139] Then, when the semiconductor element 15 is driven, if the second unit 142 is not faulty, all switches 34 are turned on. If a fault occurs, only the second switch 342 corresponding to the faulty second unit 142 is turned off, and the remaining switches 34 are turned on. In addition, when the semiconductor element 15 is not driven, the first switch 341 is turned off, and the second switch 342 is turned on.

[0140] In this embodiment, an example is shown of a plurality of second units 142 with different vulnerabilities to each other, including the gate insulating film 26, but this is not a limitation. Only one type of second unit 142 may be included, or two types of second units 142 may be included. Four or more types of second units 142 may also be included.

[0141] Additionally, an example of the semiconductor device 10 including a common pad 32 is shown, but it is not limited to this. It may also be configured without the common pad 32. In this case, the switch 34 is connected separately to the drive circuit via wiring components such as bonding wires.

[0142] (Second Implementation)

[0143] This embodiment is a variation based on the previous embodiment, and the description of the previous embodiment can be referenced. In the previous embodiment, the semiconductor device 10 includes a switch 34. Alternatively, it may be configured without a switch 34.

[0144] Figure 10 The periphery of the gate pad 30 in the semiconductor device 10 of this embodiment is shown. Figure 10 The diagram shows the connection structure between the semiconductor device 10 and the drive circuit 83.

[0145] The driving circuit 83 is formed on the circuit board. The driving circuit 83 is sometimes referred to as a gate driving circuit, driver, gate driver, etc. The driving circuit 83 includes the aforementioned gate driving power supply 80, switching power supply 81, and current sensor 82. The driving circuit 83 also includes a switch 84. The switch 84 is provided separately for the gate pad 30. The switch 84 corresponds to the aforementioned switch 34.

[0146] Switch 84 includes a first switch 841 and a plurality of second switches 842. The plurality of second switches 842 includes second switches 842a, 842b, and 842c. The first switch 841 is equivalent to the first switch 341, and the second switches 842 are equivalent to the second switches 342. Furthermore, the second switches 842a, 842b, and 842c are equivalent to the second switches 342a, 342b, and 342c.

[0147] A switch 84 is disposed between the gate drive power supply 80 and the gate pad 30. Multiple switches 84 are connected in parallel. One of the main terminals of the multiple switches 84, for example, the drain terminal, is connected to the gate drive power supply 80. Another main terminal, for example, the source terminal, is connected to the corresponding gate pad 30 via a wiring component 85 such as a bonding wire. A separate switching power supply 81 is connected to the gate of each switch 84.

[0148] <Summary of the Second Implementation>

[0149] Based on the above structure, the fault prediction method shown in the previous embodiment can be executed. Specifically, when the semiconductor element 15 is driven, a common gate drive voltage is applied to the first unit 141 and the second unit 142 by turning on the first switch 841 and the second switch 842. Furthermore, when the semiconductor element 15 is not driven, the first switch 841 is turned off, and the gate drive voltage is applied only to the second unit 142, which has the second switch 842 turned on, and its electrical characteristics are measured. A fault in the second unit 142 caused by the power-on during driving is detected. Then, the faulty second unit 142 is electrically isolated from the first unit 141 by turning off the second switch 842 corresponding to the faulty second unit 142.

[0150] In this way, by selectively switching on and off the switches 84 (841, 842), the second unit 142 can also be activated during driving, and only the second unit 142 can be activated and faults detected during non-driving, without applying a gate drive voltage to the faulty second unit 142.

[0151] (Third Implementation)

[0152] This embodiment is a variation based on the previous embodiment, and the description of the previous embodiment can be referenced. In the previous embodiment, the gate drive voltage was not applied to the faulty second unit 142 by opening switches 34 and 84. Alternatively, the gate drive voltage can also be prevented from being applied to the faulty second unit 142 by blowing the fuse.

[0153] Semiconductor Devices

[0154] Figure 11 This is a diagram showing the periphery of the gate pad 30 in the semiconductor device 10 of this embodiment. Figure 11 Corresponding to Figure 3 .

[0155] like Figure 11 As shown, the semiconductor device 10 does not include the common pad 32 and the switch 34. Although omitted from the illustration, the main unit 14 of this embodiment also has a first unit 141 and a plurality of second units 142 (142a, 142b, 142c), similar to the previous embodiment. In addition, the gate pad 30 has a first pad 301 and a plurality of second pads 302 (302a, 302b, 302c).

[0156] Semiconductor device 10 includes a fuse 35. Fuse 35 is sometimes referred to as a current fuse. Fuse 35 individually connects a second pad 302 and a first pad 301. The semiconductor device 10 of this embodiment includes a plurality of fuses 35 (35a, 35b, 35c). Fuse 35a connects the second pad 302a to the first pad 301. Fuse 35b connects the second pad 302b to the first pad 301. Fuse 35c connects the second pad 302c to the first pad 301.

[0157] When a current exceeding the rated current flows through the circuit, the fuse 35 locally heats up and melts, thus breaking the circuit. When the gate insulating film 26 in the corresponding second unit 142 is damaged and a short circuit occurs between the gate and source, causing a current exceeding the rated current to flow through the circuit, the fuse 35 melts.

[0158] like Figure 11 As shown, the gate drive power supply 80 is connected to the first pad 301. A current sensor 82 for detecting the gate current Igs is disposed in the power path between the first pad 301 and the gate drive power supply 80. Since no switch 34 is provided, a switching power supply 81 is not required.

[0159] <Fault Prediction Methods>

[0160] Next, based on Figures 12-14 The method for fault prediction is explained. Figure 12 This is a flowchart illustrating an example of a fault prediction method. Figure 13 This is a diagram illustrating fault detection. Figure 14 This is a graph showing the predicted failure period of the first unit.

[0161] In this embodiment, a fault in the second unit 142 is also detected during the driving of the semiconductor element 15. For example... Figure 12 As shown, starting from the drive instruction of semiconductor element 15, a gate drive voltage is first applied to drive semiconductor element 15 (step S400). Specifically, a gate drive voltage is applied from the gate drive power supply 80 to the first pad 301. That is, a gate drive voltage is applied to the gate 27 of the first cell 141. In addition, a gate drive voltage is applied to the gate 27 of the second cell 142, which is the second cell 142 where the corresponding fuse 35 has not blown, i.e., the second cell 142 where no fault has occurred. The first cell 141 and the second cell 142 where no fault has occurred operate and function as semiconductor element 15.

[0162] Next, the gate current Igs is monitored by the current sensor 82 (step S401), and a fault is determined based on the gate current to determine whether the second unit 142 has failed (step S402). Then, if a fault has occurred, the time up to the fault is stored (step S403), and step S402 is repeatedly executed if no fault has occurred.

[0163] like Figure 13 As shown, the gate current increases with the deterioration of the gate insulating film of the second cell 142. Furthermore, when a gate-source short circuit occurs due to damage to the gate insulating film 26, the fuse 35 flows with a current exceeding its rated value and melts, causing the gate current to decrease sharply. In this embodiment, as an example, the time from when the gate current value changes sharply from large to small, i.e., the time from when the fuse 35 melts, is stored as the operating time until the second cell 142 fails. The operating time refers to the cumulative applied time of the gate drive voltage until the second cell 142 fails. Alternatively, the second cell 142 can be determined to be faulty by the gate current exceeding a predetermined threshold. In this case, the time until the threshold is exceeded can also be set as the operating time.

[0164] When the second unit 142 fails, the gate 27 of the failed second unit 142 is electrically isolated from the gates 27 of the other main units 14 due to the blowing of the fuse 35. That is, a gate drive voltage cannot be applied to the gate 27 of the failed second unit 142.

[0165] Next, it is determined whether all second units 142 have failed (step S404). If any second units 142 have failed, the process after step S402 is executed again. In this embodiment, the process after step S402 is executed repeatedly until all three types of second units 142a, 142b, and 142c have failed. If there is only one second unit 142, the process will proceed to step S405.

[0166] As described above, the vulnerability of the gate insulating films of the second units 142a, 142b, and 142c differs from each other. In this embodiment, similarly to the previous embodiment, the thickness of the gate insulating film 26 differs from each other. Therefore, as... Figure 13 As shown, the operating time of the second cell 142a, where the gate insulating film 26 is the thinnest, is t1. The operating time of the second cell 142b, where the gate insulating film 26 is the second thinnest, is t2 (>t1). The operating time of the second cell 142c, where the gate insulating film 26 is the thickest, is t3 (>t2). Thus, the operating times until a fault occurs differ. Times t1, t2, and t3 correspond to the fault period of the second cell 142.

[0167] Next, the failure period of the first unit 141 is predicted based on all the failure periods of the second unit 142 (step S405), and the series of processes ends.

[0168] For example, if the structure is determined, the electric field E that becomes the breakdown voltage limit of the gate insulating film 26 of the first unit 141 and the second unit 142 can be pre-calculated through device simulation. Therefore, the destructive electric fields of the second units 142a, 142b, and 142c are pre-set as E1, E2, and E3, and the destructive electric field of the first unit 141 is set as Ex, and the obtained times t1, t2, and t3 are used as follows: Figure 14 A two-dimensional plot is shown. From this, the time tx at which the insulation fails in the first unit 141 can be predicted. Time tx corresponds to the fault period of the first unit 141.

[0169] <Summary of the Third Implementation>

[0170] According to the fault prediction method of the semiconductor device 10 in this embodiment, similarly to the previous embodiment, when the semiconductor element 15 is driven, a gate drive voltage common to the first unit 141 is applied to the second unit 142 via the fuse 35. Furthermore, electrical characteristics are measured and faults in the second unit 142 are detected. By blowing the fuse 35, the gate 27 of the faulty second unit 142 is electrically separated from the gate 27 of the first unit 141. Before a fault occurs in the second unit 142, since the second unit 142 also functions as the main unit 14 constituting the semiconductor element 15, the reduction in chip area utilization efficiency, i.e., the reduction in the utilization efficiency of the semiconductor element 15, can be suppressed.

[0171] Furthermore, electrical characteristics are measured and faults in the second unit 142 caused by energization during operation are detected. As described above, the second unit 142 is driven in the same manner as the first unit 141 when the semiconductor element 15 is driven. Therefore, the second unit 142 actually fails due to stress applied in the market. Therefore, faults in the first unit 141, i.e., faults in the semiconductor element 15, can be predicted with high accuracy based on the faults in the second unit 142.

[0172] In this embodiment, the fuse 35 blows when the second unit 142 fails, and the gate 27 of the failed second unit 142 is electrically isolated from the first unit 141 without applying a gate drive voltage. This suppresses the possibility of other main units 14 failing due to a temperature rise caused by the failure of the second unit 142. In other words, it is possible to predict the failure of the first unit 141 with high accuracy while maintaining its function as a semiconductor element 15.

[0173] According to the semiconductor device 10 of this embodiment, when the semiconductor element 15 is driven, a gate drive voltage common to the first element 141 can also be applied to the second unit 142 via the fuse 35. Then, as the second unit 142 fails due to damage to the gate insulating film 26, the fuse 35 blows, cutting off the gate drive voltage applied to the failed second unit 142. That is, before the second unit 142 fails, since the second unit 142 also functions as the main unit 14 constituting the semiconductor element 15, the reduction in the utilization efficiency of the semiconductor element 15 can be suppressed.

[0174] Furthermore, the second unit 142 malfunctions when it operates together with the first unit 141 during the driving of the semiconductor element 15. That is, it malfunctions due to stress actually applied in the market. Therefore, it is possible to predict the malfunction of the first unit 141, i.e., the malfunction of the semiconductor element 15, with high accuracy based on the malfunction of the second unit 142.

[0175] In this embodiment, the failure period of the first unit 141 is predicted based on the failure period of the second unit 142. As described above, since the multiple second units 142 fail in a time sequence, the failure period of the first unit 141 can be predicted based on the failure periods of the second units 142. In particular, in this embodiment, since the failure periods of the multiple second units 142 are used, the failure period of the first unit 141 can be predicted.

[0176] <Variation Example>

[0177] In this embodiment, an example is shown of predicting the failure period of the first unit 141 based on the failure periods of a plurality of second units 142 (142a, 142b, 142c), but it is not limited thereto. The failure period of the first unit 141 may also be predicted based on the failure period of one of the second units 142.

[0178] The prediction (estimation) of the fault period of the first unit 141 is not limited to the method described above. For example, when the thicknesses of the gate insulating films 26 are different from each other, the fault period of the first unit 141 can also be calculated based on the ratio of the thicknesses of the gate insulating films 26 and the aforementioned operating time. Alternatively, a nonlinear regression method can also be used for prediction.

[0179] In the configuration using fuse 35, an example is shown of predicting the failure period of the first unit 141 based on the failure period of the second unit 142, but this is not a limitation. In the configuration using fuse 35, similarly to the previous embodiment, the failure of the first unit 141 can also be predicted by the number of failures of the second unit 142 reaching a predetermined number. In this case, notification can also be given when the failure of the first unit 141 is predicted.

[0180] In the structure using switches 34, 84 as shown in the previous embodiment, as described in this embodiment, the failure period of the first unit 141 can also be predicted based on the failure period of the second unit 142. For example, in Figure 9 In the non-driving process shown, the fault period of the second unit 142, i.e. the time until the fault occurs, can also be stored in step S305, and instead of step S308, the fault period of the first unit 141 can be predicted based on the fault period of the second unit 142.

[0181] Alternatively, after predicting the failure period of the first unit 141 based on the failure period of the second unit 142, notification can be given according to the predicted failure period of the first unit 141. For example, notification can be given when the predicted failure period is reached, or notification can be given when a specified time before the failure period is reached.

[0182] (Fourth Implementation)

[0183] This embodiment is a variation based on the previous embodiment, and the description of the previous embodiment can be referenced. In the previous embodiment, by thinning the thickness of the gate insulating film 26, the gate insulating film 26 of the second unit 142 is made easier to damage than that of the first unit 141. Alternatively, the gate insulating film 26 of the second unit 142 can also be made easier to damage than that of the first unit 141 by adjusting the depth region periodically provided within the drift region 21.

[0184] Figure 15 This is a cross-sectional view showing the semiconductor device 10 of this embodiment. Figure 15 It is Figure 1 The cross-sectional view shown is an extension of line I II I to the outer peripheral region 13. (See figure) Figure 15 As shown, in addition to the structure shown in the previous embodiments, the semiconductor device 10 also has a depth region 36 and a protective ring 37.

[0185] A depth region 36 is periodically disposed within the drift region 21 in the main cell region 12. The depth region 36 extends downward from the base region 22, i.e., to the drain region 20 side. The depth region 36 extends to a position deeper than the trench 25.

[0186] The depth region 36 is a p-conductivity (p++) semiconductor region with a higher impurity concentration than the base region 22 and the base contact region 24. The depth region 36 is electrically connected to the source 28 via the base region 22 and the base contact region 24. The depth region 36 is disposed between adjacent trenches 25 in the main cell region 12. The depth region 36 extends along the X direction and is arranged with the trenches 25 in the Y direction.

[0187] A guard ring 37 is disposed within the drift region 21 in the outer peripheral region 13. The guard ring 37 is a p-conductivity semiconductor region with a higher impurity concentration than the base region 22. The lower end position of the guard ring 37 is approximately equal to, for example, the lower end position of the depth region 36. Multiple guard rings 37 are disposed. The innermost guard ring 37A among the multiple guard rings 37 is a p-conductivity (p++) semiconductor region with a higher impurity concentration than the other guard rings 37 (p+).

[0188] A guard ring 37A is connected to the end of the base region 22 located in the outer peripheral region 13. The guard ring 37A is configured to have a predetermined distance D1 between it and the trench 25 disposed at the end in the Y direction. The guard ring 37A is electrically connected to the source 28 via the base region 22 and the base contact region 24. Other guard rings 37 besides the guard ring 37A do not contact the base region 22 and are configured to have a predetermined depth between them and the back surface 11b of the semiconductor substrate 11. Other guard rings 37 are not electrically connected to the source 28.

[0189] The depletion layer (Japanese: 空乏層) extends starting from the junction (Japanese: ジャンクション). Additionally, the higher the impurity concentration, the more difficult it is for the depletion layer to extend. If a deep region 36 with a relatively high impurity concentration that extends below the trench 25 is provided within the main cell region 12, it is difficult to generate electric field concentration at the lower part of the trench 25. Further, if the impurity concentration of the innermost guard ring 37A is increased, it is difficult to generate electric field concentration at the end trench 25.

[0190] In the present embodiment, by intentionally controlling the above-mentioned distance D1 and / or the impurity concentration of the guard ring 37A, it is possible to make the gate insulating film 26 of the second cell 142 more likely to be damaged than that of the first cell 141. That is, by controlling the distance D1 and / or the impurity concentration of the guard ring 37A, it is configured to easily concentrate the electric field on the gate insulating film 26 of the second cell 142. For example, the longer the distance D1, the stronger the electric field applied to the end gate insulating film 26, and the more likely it is to cause dielectric breakdown. Additionally, the lower the impurity concentration of the guard ring 37A, the stronger the electric field applied to the end gate insulating film 26, and the more likely it is to cause dielectric breakdown. Other structures are the same as those described in the previous embodiment.

[0191] <Summary of the Fourth Embodiment>

[0192] According to the above structure, even if the trench structure including the gate insulating film 26 and the gate 27 is common to the first cell 141 and the second cell 142, it is possible to make the gate insulating film 26 of the second cell 142 more likely to be damaged than that of the first cell 141.

[0193] (Fifth Embodiment)

[0194] This embodiment is a modification based on the previous embodiment, and the description of the previous embodiment can be cited. In the previous embodiment, by making the overall thickness of the gate insulating film 26 thinner, the gate insulating film 26 of the second cell 142 is made more likely to be damaged than that of the first cell 141. As an alternative, it is also possible to make the gate insulating film 26 of the second cell 142 more likely to be damaged than that of the first cell 141 by locally thinning the thickness of the gate insulating film 26.

[0195] Figure 16 It is a cross-sectional view showing the semiconductor device 10 of this embodiment. Figure 16 It is a cross-sectional view along the Figure 1 line II-II shown. As Figure 16As shown, in this embodiment, in the second unit 142, the corners of the bottom wall and sidewalls of the trench 25 are cut out. The shape of the cut out is sometimes referred to as a chamfered shape, a tapered shape, etc. As a result, the thickness of the gate insulating film 26 of the second unit 142 is thinner than that of the first unit 141 in the cut-out portion, and approximately the same as that of the first unit 141 in other portions. Other structures are the same as those described in the previous embodiments.

[0196] <Summary of the Fifth Implementation>

[0197] If the above structure is adopted, the deviation of the threshold voltage Vth caused by the difference in thickness of the gate insulating film 26 of the first unit 141 and the second unit 142 can be reduced or eliminated. On the other hand, since the electric field is concentrated in the notch portion, the gate insulating film 26 of the second unit 142 can be damaged more easily than that of the first unit 141.

[0198] (Other implementation methods)

[0199] The disclosure in this specification and accompanying drawings is not limited to the illustrated embodiments. This disclosure includes illustrated embodiments and modifications made by those skilled in the art based thereon. For example, this disclosure is not limited to the combinations of components and / or elements shown in the embodiments. This disclosure can be implemented in various combinations. This disclosure may have additional portions that can be added to the embodiments. This disclosure includes embodiments in which components and / or elements of the embodiments are omitted. This disclosure includes substitutions or combinations of components and / or elements between one embodiment and another. The technical scope of this disclosure is not limited to the description of the embodiments. Several technical scopes of this disclosure should be understood to be expressed by the description of the claims, and also include all modifications within the meaning and scope of equivalence to the description of the claims.

[0200] The disclosures in the specification and drawings are not limited by the claims. The disclosures in the specification and drawings include the technical ideas described in the claims, and involve more diverse and broader technical ideas than those described in the claims. Therefore, it is possible to extract various technical ideas from the disclosures in the specification and drawings without being limited by the claims.

Claims

1. A method for predicting faults in a semiconductor device, The semiconductor device includes a semiconductor element with a trench gate structure, wherein the semiconductor element is composed of multiple main units connected in parallel. The plurality of main units include a plurality of first units and a plurality of second units. The plurality of second units have a structure that makes it easier for the gate insulating film to be damaged by power-on than the first units in order to predict failures of the first units, and are fewer in number than the first units. The vulnerability of the gate insulating film of each of the multiple second units differs from that of the others. When the semiconductor element is driven, a common gate drive voltage is applied to the gate of the first unit and the gate of the second unit. The electrical characteristics were measured and faults in the second unit caused by the energization during the drive were detected. In order to prevent the gate drive voltage from being applied to the faulty second cell, the gate of the faulty second cell is electrically disconnected from the gate of the first cell. Faults in the first unit are predicted based on multiple faults in the second unit.

2. The fault prediction method for a semiconductor device as described in claim 1, characterized in that, The failure period of the first unit is predicted based on the failure period of the second unit.

3. The fault prediction method for a semiconductor device as described in claim 1, characterized in that, The failure of the first unit is predicted by the number of failures in the second unit reaching a predetermined number.

4. The fault prediction method for a semiconductor device as described in claim 1, characterized in that, Notifications are issued based on the predicted failure of the first unit.

5. The fault prediction method for a semiconductor device as described in any one of claims 1 to 4, characterized in that, During the driving process, a common gate drive voltage is applied to both the first and second units by turning on a first switch connected to the gate of the first unit and a second switch connected to the gate of the second unit. When the semiconductor element is not driven, the first switch is disconnected, and the gate drive voltage is applied only to the second unit that turns on the second switch, and the electrical characteristics are measured. Furthermore, a fault in the second unit caused by the power-on during driving is detected. By disconnecting the second switch corresponding to the faulty second unit, the faulty second unit is electrically isolated from the first unit.

6. The fault prediction method for a semiconductor device as described in any one of claims 1 to 4, characterized in that, During the driving process, the gate drive voltage is applied to the gate of the second unit via a fuse, and the gate drive voltage is not applied to the gate of the first unit via the fuse. Faults in the second unit caused by energization during the drive are detected by measuring the electrical characteristics during the drive. The fuse blows due to a fault in the second unit, thereby electrically separating the faulty second unit from the first unit.

7. A semiconductor device comprising a semiconductor element with a trench gate structure, the semiconductor element being configured by connecting a plurality of main units in parallel. The semiconductor device includes: A semiconductor substrate having a main cell region and an outer peripheral region, wherein the main cell region is a region having a plurality of main cells, wherein each main cell has a plurality of first cells and second cells, wherein the second cells have a structure that makes it easier to destroy the gate insulating film by energizing the first cells in order to predict the failure of the first cells, and the number of the second cells is less than that of the first cells, and the outer peripheral region surrounds the main cell region. Multiple gate pads, including a first pad and a second pad, wherein the first pad is connected to the gate of the first unit, and the second pad is separately disposed from the first pad and connected to the gate of the second unit, the multiple gate pads are disposed on one surface of the semiconductor substrate to apply a gate driving voltage to the gate of the main unit; as well as Multiple switches, including a first switch connected to the first pad and a second switch connected to the second pad, are individually configured for the gate pad and allow or disable the application of the gate drive voltage to the gate pad. When the semiconductor element is driven, if the second unit is not faulty, all the switches are turned on; if a fault occurs, only the second switch corresponding to the faulty second unit is turned off, and the remaining switches are turned on. When the semiconductor element is not driven, the first switch is turned off and the second switch is turned on.

8. A semiconductor device, the semiconductor device comprising a semiconductor element with a trench gate structure, the semiconductor element being composed of a plurality of main units connected in parallel. The semiconductor device includes: A semiconductor substrate having a main cell region and an outer peripheral region, wherein the main cell region is a region having a plurality of main cells, wherein each main cell has a plurality of first cells and second cells, wherein the second cells have a structure that makes it easier to destroy the gate insulating film by energizing the first cells in order to predict the failure of the first cells, and the number of the second cells is less than that of the first cells, and the outer peripheral region surrounds the main cell region. Multiple gate pads, including a first pad and a second pad, wherein the first pad is connected to the gate of the first unit, and the second pad is separately disposed from the first pad and connected to the gate of the second unit, the multiple gate pads are disposed on one surface of the semiconductor substrate to apply a gate driving voltage to the gate of the main unit; as well as A fuse that individually connects the second pad and the first pad. As the second unit fails, the fuse connected to the second pad corresponding to the failed second unit blows.

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