A method and apparatus for testing the bonding quality of semiconductor discrete device chips.

Abstract

This invention provides a method and apparatus for testing the bonding quality of semiconductor discrete devices. It obtains two semiconductor discrete devices in advance, one with acceptable bonding and the other with unacceptable bonding (but very close to acceptable). The transient thermal resistance of the bonding layer is used to determine the transient thermal resistance test time based on the transient thermal resistance test time and the transient thermal resistance of the unacceptable semiconductor discrete device at the same test time. The bonding quality of the semiconductor discrete device under test is then tested based on this transient thermal resistance test time. This invention can quickly and effectively screen out semiconductor discrete devices with unacceptable bonding, has good practical value and economic benefits, and is suitable for widespread application.

Description

Technical Field

[0001] This invention relates to the field of thermal performance technology for semiconductor discrete devices, and in particular to a method and apparatus for testing the bonding qualification of semiconductor discrete device chips. Background Technology

[0002] Electrical thermal resistance testing (hereinafter referred to as "thermal resistance") is the best non-destructive method for evaluating the thermal performance of devices. Thermal resistance testing is divided into steady-state thermal resistance and transient thermal resistance. Steady-state thermal resistance has higher requirements in terms of testing cost and efficiency compared to transient thermal resistance, making transient thermal resistance a more economical method for thermal performance screening. Specifically, because the presence of voids in the chip-substrate interface bonding material of semiconductor discrete devices prevents heat conduction from the chip to the substrate (package), the transient thermal resistance of semiconductor discrete devices is sensitive to voids in the chip-substrate interface bonding material. The transient thermal resistance (TRT) curve of discrete semiconductor devices gradually increases with heating time (tH), progressing through stages of chip TRT, adhesive layer TRT, case TRT, and finally stabilizing total TRT. Since the chip's thermal response time is several orders of magnitude shorter than the case's, the width of the heating power pulse (i.e., the heating time) can be selected to be greater than the chip's thermal response time but less than the case's. This places the discrete semiconductor device in a state where both the chip and adhesive layer are heated, allowing for the measurement of the TRT's transient thermal resistance, thus determining the quality (void conditions) of the adhesive layer. Furthermore, because heat conduction does not reach the device's case during transient TRT measurement, it eliminates the need for heat sink and case temperature testing, significantly simplifying the procedure and improving accuracy. Therefore, transient TRT measurement can be effectively used in large-scale device screening, process control, and incoming inspection to inspect the quality of the chip adhesive layer (primarily in terms of thermal performance), effectively rejecting devices with poor chip bonding.

[0003] The existing semiconductor discrete device chip bonding qualification test method generally consists of the following steps: (1) Select a batch of samples with the same test piece specifications and adjust the required heating power according to the heating power of the semiconductor discrete device and its junction temperature change per unit time; (2) Preliminarily test the transient thermal resistance of this batch of samples and record the two samples with the largest and smallest transient thermal resistance; (3) Plot the transient thermal resistance curves of these two samples and find the inflection point (bifurcation point) as the heating time; (4) Evaluate whether the heating time is feasible. If not, repeat the above steps; (5) Remove unqualified samples from this batch of samples based on the heating time and generate a transient thermal resistance normal distribution map based on the transient thermal resistance value of qualified samples; (6) Construct a chip bonding qualification test criterion based on the transient thermal resistance normal distribution map, and use the criterion to conduct chip bonding qualification test of the test piece. However, this method has the following two drawbacks: First, the process of determining the heating time is relatively complex, and it is also necessary to evaluate whether the heating time is feasible; second, the process of determining the criterion is complex, and it is necessary to conduct transient thermal resistance tests on this batch of samples before performing mathematical statistics; moreover, it is impossible to assess whether this batch of samples is properly tested during the transient thermal resistance test, and it is very easy to generate incorrect criteria due to test abnormalities.

[0004] Therefore, there is an urgent need to provide a test method for the bonding qualification of semiconductor discrete device chips that can overcome the above-mentioned defects. Summary of the Invention

[0005] To overcome the above-mentioned defects, the present invention provides a method and apparatus for testing the bonding qualification of semiconductor discrete devices, enabling rapid and effective screening of semiconductor discrete devices with unqualified chip bonding.

[0006] In a first aspect, the present invention provides a method for testing the bonding conformity of semiconductor discrete device chips, the method comprising:

[0007] The transient thermal resistance curves of the first semiconductor discrete device and the second semiconductor discrete device were tested respectively.

[0008] Based on the transient thermal resistance curves of the first and second semiconductor discrete devices, the transient thermal resistance test time of the bonding layer of the semiconductor discrete devices is determined.

[0009] Based on the transient thermal resistance test time and the transient thermal resistance of the first semiconductor discrete device during the transient thermal resistance test time, the chip bonding qualification test is performed on the target semiconductor discrete device.

[0010] Among them, the chip bonding of the first semiconductor discrete device is unqualified and infinitely close to qualified;

[0011] The chip bonding of the second semiconductor discrete device is qualified.

[0012] According to the semiconductor discrete device chip bonding qualification test method provided by the present invention, the transient thermal resistance curve represents time on the horizontal axis and transient thermal resistance on the vertical axis, and the chip specifications of the first semiconductor discrete device and the second semiconductor discrete device are the same.

[0013] The step of determining the transient thermal resistance test time of the bonding layer of the semiconductor discrete devices based on the transient thermal resistance curves of the first and second semiconductor discrete devices includes:

[0014] Determine the curve separation point of the transient thermal resistance curve of the first semiconductor discrete device and the transient thermal resistance curve of the second semiconductor discrete device in the same coordinate system;

[0015] The time corresponding to the separation point of the curve is taken as the transient thermal resistance test time.

[0016] According to the semiconductor discrete device chip bonding qualification test method provided by the present invention, the step of performing chip bonding qualification test on the target semiconductor discrete device based on the transient thermal resistance test time and the transient thermal resistance of the first semiconductor discrete device during the transient thermal resistance test time includes:

[0017] Based on the transient thermal resistance test time and the transient thermal resistance, a chip bonding qualification test criterion is constructed;

[0018] Based on the chip bonding qualification test criteria, the chip bonding qualification test is performed on the target semiconductor discrete device.

[0019] According to the semiconductor discrete device chip bonding qualification test method provided by the present invention, the chip bonding qualification test criterion is as follows:

[0020] For any semiconductor discrete device, if the transient thermal resistance of the semiconductor discrete device during the transient thermal resistance test time is greater than the transient thermal resistance, then the chip bonding of the semiconductor discrete device is unqualified.

[0021] Otherwise, the bonding of the semiconductor discrete device chip is qualified.

[0022] According to the semiconductor discrete device chip bonding qualification test method provided by the present invention, whether the chip bonding of the first semiconductor discrete device and the second semiconductor discrete device is qualified is determined according to the first rule;

[0023] The first rule states that chip bonding is unqualified when the total void area in the contact area of ​​the bonding layer of a semiconductor discrete device exceeds a first preset percentage of the total contact area; otherwise, it is qualified.

[0024] According to the semiconductor discrete device chip bonding qualification test method provided by the present invention, the first preset percentage is 15%.

[0025] According to the semiconductor discrete device chip bonding qualification test method provided by the present invention, the first semiconductor discrete device and the second semiconductor discrete device are obtained by customization or X-ray selection.

[0026] In a second aspect, the present invention provides a semiconductor discrete device chip bonding conformity testing apparatus, the apparatus comprising:

[0027] The transient thermal resistance curve testing module is used to test the transient thermal resistance curves of the first semiconductor discrete device and the second semiconductor discrete device, respectively.

[0028] The transient thermal resistance test time determination module is used to determine the transient thermal resistance test time of the bonding layer of the semiconductor discrete device based on the transient thermal resistance curves of the first semiconductor discrete device and the second semiconductor discrete device.

[0029] The chip bonding qualification test module is used to perform chip bonding qualification test on the target semiconductor discrete device based on the transient thermal resistance test time and the transient thermal resistance of the first semiconductor discrete device under the transient thermal resistance test time.

[0030] Among them, the chip bonding of the first semiconductor discrete device is unqualified and infinitely close to qualified;

[0031] The chip bonding of the second semiconductor discrete device is qualified.

[0032] Thirdly, the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the semiconductor discrete device chip bonding conformity test method as described in the first aspect.

[0033] Fourthly, the present invention provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the semiconductor discrete device chip bonding conformity test method as described in the second aspect.

[0034] This invention provides a method and apparatus for testing the bonding quality of semiconductor discrete devices, comprising: testing the transient thermal resistance curves of a first semiconductor discrete device and a second semiconductor discrete device respectively; wherein the bonding of the first semiconductor discrete device is unqualified but infinitely close to qualified; the bonding of the second semiconductor discrete device is qualified; determining the transient thermal resistance test time of the bonding layer of the semiconductor discrete device based on the transient thermal resistance curves of the first and second semiconductor discrete devices; and performing a bonding quality test on the target semiconductor discrete device based on the transient thermal resistance test time and the transient thermal resistance of the first semiconductor discrete device at the transient thermal resistance test time. This invention can quickly and effectively screen out semiconductor discrete devices with unqualified chip bonding, has good practical value and economic benefits, and is suitable for widespread application. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0036] Figure 1 This is a flowchart illustrating the semiconductor discrete device chip bonding qualification test method provided by the present invention;

[0037] Figure 2 This is a schematic diagram of the transient thermal resistance curve provided by the present invention;

[0038] Figure 3 This is a schematic diagram illustrating the generation process of the chip bonding qualification test criterion provided by the present invention;

[0039] Figure 4 This is an X-ray image of chip bonding provided by the present invention;

[0040] Figure 5 This is a schematic diagram of the semiconductor discrete device chip bonding qualification test device provided by the present invention;

[0041] Figure 6 This is a schematic diagram of the structure of the electronic device provided by the present invention;

[0042] Figure label:

[0043] 610: Processor; 620: Communication interface; 630: Memory; 640: Communication bus. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0045] The following is combined Figures 1-6 The present invention describes a method and apparatus for testing the bonding conformity of semiconductor discrete device chips.

[0046] Firstly, the steady-state thermal resistance of discrete semiconductor devices typically consists of chip thermal resistance, adhesive layer thermal resistance, package thermal resistance, and heat sink thermal resistance. Adhesive layer thermal resistance, determined by factors such as chip area, adhesive materials, and sintering processes, is a critical component of the device's thermal resistance and is more difficult to control and guarantee compared to chip and package thermal resistance. Analysis of the transient thermal resistance curves of discrete semiconductor devices shows that as the heating time (tH) increases, the transient thermal resistance gradually increases, and can be categorized as chip thermal resistance, adhesive layer thermal resistance, package thermal resistance, heat sink thermal resistance, and total thermal resistance. When tH is small, heat conduction occurs through the chip. As tH increases and exceeds the chip's thermal response time, heat is transferred through the chip to the chip adhesive region. Further increases in tH result in heat transfer to the device package, eventually flattening the thermal response curve, which represents the total thermal resistance. The adhesive layer thermal resistance exhibits the greatest variation in thermal resistance among discrete semiconductor devices. The quality of the adhesive layer directly affects the thermal resistance of the discrete semiconductor device, thus impacting its heat dissipation. Current methods for testing chip bonding conformity are not fast or accurate due to the complexity and unreliability of the heating time and the determination process of chip bonding conformity test criteria. Therefore, this invention provides a method for testing the bonding conformity of semiconductor discrete devices, such as... Figure 1 As shown, the method includes:

[0047] S11: Test the transient thermal resistance curves of the first semiconductor discrete device and the second semiconductor discrete device respectively;

[0048] The transient thermal resistance curve of the semiconductor discrete device of this invention is tested using existing methods, which will not be elaborated here.

[0049] S12: Determine the transient thermal resistance test time of the bonding layer of the semiconductor discrete device based on the transient thermal resistance curves of the first semiconductor discrete device and the second semiconductor discrete device.

[0050] The purpose of this invention is to quickly screen out semiconductor discrete devices with substandard chip bonding. Since the pass / fail status of chip bonding in semiconductor discrete devices is reflected in the transient thermal resistance of the bonding layer, it is necessary to find the transient thermal resistance test time (typically in the millisecond range) corresponding to this transient thermal resistance. It can be said that the accuracy of the transient thermal resistance test time is a prerequisite for the pass / fail testing of chip bonding in semiconductor discrete devices, directly determining the validity of the results. This invention locates the transient thermal resistance test time by analyzing the transient thermal resistance curves of two semiconductor discrete devices with pass and fail (very close to pass) chip bonding. Furthermore, the test time for steady-state thermal resistance of semiconductor discrete devices is generally in the minutes range, while the transient thermal resistance test time (typically in the millisecond range) is the fundamental reason why using the transient thermal resistance test time allows for rapid screening.

[0051] S13: Based on the transient thermal resistance test time and the transient thermal resistance of the first semiconductor discrete device during the transient thermal resistance test time, perform a chip bonding qualification test on the target semiconductor discrete device.

[0052] It is understandable that the transient thermal resistance of any semiconductor discrete device during the transient thermal resistance test time is the transient thermal resistance of its own adhesive layer (caused by voids in the adhesive layer). The comparison between this transient thermal resistance and the transient thermal resistance of the first semiconductor discrete device during the transient thermal resistance test time reflects whether any semiconductor discrete device is qualified.

[0053] Among them, the chip bonding of the first semiconductor discrete device is unqualified and infinitely close to qualified;

[0054] The chip bonding of the second semiconductor discrete device is qualified.

[0055] The present invention provides a method for testing the bonding conformity of semiconductor discrete devices. It obtains two semiconductor discrete devices in advance, one with conforming bonding and the other with conforming bonding (but very close to conforming). By testing and analyzing the transient thermal resistance curves of these two semiconductor discrete devices, the transient thermal resistance test time for the bonding layer of the semiconductor discrete devices is determined. Based on this transient thermal resistance test time and the transient thermal resistance of the conforming semiconductor discrete device at the same test time, the bonding conformity test of the target semiconductor discrete device can be achieved. This invention can quickly and effectively screen out semiconductor discrete devices with unconforming bonding, has good practical value and economic benefits, and is suitable for widespread application.

[0056] Furthermore, 3. The present invention has a simple testing principle, no specific requirements for the installation of testing devices or testing fixtures, and is easy to operate.

[0057] Based on the above embodiments, as an optional embodiment, the transient thermal resistance curve represents time on the horizontal axis and transient thermal resistance on the vertical axis, and the chip specifications of the first semiconductor discrete device and the second semiconductor discrete device are the same.

[0058] S12 includes:

[0059] S12.1: Determine the curve separation point of the transient thermal resistance curve of the first semiconductor discrete device and the transient thermal resistance curve of the second semiconductor discrete device in the same coordinate system;

[0060] S12.2: The time corresponding to the separation point of the curve is taken as the transient thermal resistance test time.

[0061] Specifically, if the heating time tH of two discrete semiconductor devices is not greater than the thermal time constant of the chip, the thermal characteristics of identical chips should be the same, meaning the two curves are identical in the low-value region of tH. Note that if two discrete semiconductor devices use different chips (e.g., different thicknesses or cross-sectional areas), the two curves will differ in the low-value region of tH. Therefore, in this invention, the two discrete semiconductor devices have identical chip specifications. As tH increases, exceeding the chip's thermal time constant, heat will be transferred through the chip to the chip bonding area. Due to the difference in thermal characteristics between the two discrete semiconductor devices in the chip bonding area, the curves will bifurcate when tH increases to the transient thermal resistance test time. Therefore, the transient thermal resistance test time can be easily located from the point where the two curves separate.

[0062] Figure 2 This is a schematic diagram of the transient thermal resistance curve, as shown below. Figure 2 As shown, the two transient thermal resistance curves initially overlap and then separate, and the time corresponding to the separation point is the transient thermal resistance test time.

[0063] Based on the above embodiments, as an optional embodiment, S13 includes:

[0064] S13.1: Based on the transient thermal resistance test time and the transient thermal resistance, construct a chip bonding qualification test criterion;

[0065] S13.2: Based on the chip bonding qualification test criteria, perform chip bonding qualification test on the target semiconductor discrete device.

[0066] Figure 3 This is a schematic diagram of the process of generating chip bonding qualification test criteria. The present invention constructs chip bonding qualification test criteria based on transient thermal resistance test time and the transient thermal resistance. This criterion can be formulated according to industrial scenarios.

[0067] Preferably, the criterion for chip bonding qualification test is:

[0068] For any semiconductor discrete device, if the transient thermal resistance of the semiconductor discrete device during the transient thermal resistance test time is greater than the transient thermal resistance, then the chip bonding of the semiconductor discrete device is unqualified.

[0069] Otherwise, the bonding of the semiconductor discrete device chip is qualified.

[0070] Alternatively, the chip bonding qualification test criterion is as follows:

[0071] For any semiconductor discrete device, if the difference between the transient thermal resistance of the semiconductor discrete device during the transient thermal resistance test time and the transient thermal resistance is less than a preset threshold, then the chip bonding of the semiconductor discrete device is unqualified.

[0072] It can be said that the formulation of chip bonding qualification test criteria directly determines the accuracy of semiconductor discrete device chip bonding qualification test.

[0073] Based on the above embodiments, as an optional embodiment, whether the chip bonding of the first semiconductor discrete device and the second semiconductor discrete device is qualified is determined according to the first rule;

[0074] The first rule states that chip bonding is unqualified when the total void area in the contact area of ​​the bonding layer of a semiconductor discrete device exceeds a first preset percentage of the total contact area; otherwise, it is qualified.

[0075] Preferably, the first preset percentage is 15%.

[0076] According to Clause 3.10.2.3.1 of Method 2076.1 "X-ray Radiography" in GJB 128B-2021 "Test Methods for Semiconductor Discrete Devices", void-type structures are unacceptable.

[0077] A. From a mechanical strength perspective, the voids in the contact area exceed 1 / 2 of the total contact area.

[0078] B. For heat dissipation purposes, unless otherwise specified, the total area of ​​the contact area voids of all power and case rated devices shall not exceed 15% of the total contact area, and the total area of ​​the contact area voids of other devices shall not exceed 30% of the total contact area.

[0079] This invention primarily targets heat dissipation, and the transient thermal resistance test objects are generally devices with power and package ratings. Therefore, the first preset percentage is generally selected as 15%. Furthermore, although the chip bonding of the first semiconductor discrete device is not up to standard, it is infinitely close to being up to standard (or it can be selected as being right on the line of pass). To ensure a significant difference in thermal characteristics between the first and second semiconductor discrete devices in the chip bonding area (to better determine the separation point), the chip bonding of the second semiconductor discrete device is preferably selected as extremely high, for example, a void ratio of 3%.

[0080] Figure 4 These are X-ray images of chip bonding with void ratios of 15% and 3%.

[0081] Based on the above embodiments, as an optional embodiment, the first semiconductor discrete device and the second semiconductor discrete device are obtained by customization or X-ray selection.

[0082] As can be seen from the above embodiments, the selection of the first semiconductor discrete device and the second semiconductor discrete device is the cornerstone of the performance of the present invention, and usually needs to be customized or selected by X-ray scanning.

[0083] Secondly, the semiconductor discrete device chip bonding qualification test apparatus provided by the present invention will be described. The semiconductor discrete device chip bonding qualification test apparatus described below and the semiconductor discrete device chip bonding qualification test method described above can be referred to in correspondence with each other. Figure 5 This is a schematic diagram of the semiconductor discrete device chip bonding qualification testing device provided by the present invention, as shown below. Figure 5 As shown, the device includes:

[0084] The transient thermal resistance curve test module 21 is used to test the transient thermal resistance curves of the first semiconductor discrete device and the second semiconductor discrete device, respectively.

[0085] The transient thermal resistance test time determination module 22 is used to determine the transient thermal resistance test time of the bonding layer of the semiconductor discrete device based on the transient thermal resistance curves of the first semiconductor discrete device and the second semiconductor discrete device.

[0086] The chip bonding qualification test module 23 is used to perform chip bonding qualification test on the target semiconductor discrete device based on the transient thermal resistance test time and the transient thermal resistance of the first semiconductor discrete device under the transient thermal resistance test time.

[0087] Among them, the chip bonding of the first semiconductor discrete device is unqualified and infinitely close to qualified;

[0088] The chip bonding of the second semiconductor discrete device is qualified.

[0089] The semiconductor discrete device chip bonding qualification testing device provided by this invention obtains two semiconductor discrete devices in advance: one with qualified chip bonding and the other with unqualified (but very close to qualified) bonding. By testing and analyzing the transient thermal resistance curves of these two semiconductor discrete devices, the transient thermal resistance test time of the bonding layer of the semiconductor discrete device is determined. Based on this transient thermal resistance test time and the transient thermal resistance of the unqualified semiconductor discrete device at the same transient thermal resistance test time, the chip bonding qualification test of the target semiconductor discrete device can be achieved. This invention can quickly and effectively screen out semiconductor discrete devices with unqualified chip bonding, has good practical value and economic benefits, and is suitable for widespread application.

[0090] Based on the above embodiments, as an optional embodiment, the transient thermal resistance curve represents time on the horizontal axis and transient thermal resistance on the vertical axis, and the chip specifications of the first semiconductor discrete device and the second semiconductor discrete device are the same.

[0091] The transient thermal resistance test time determination module includes:

[0092] The curve separation point determination unit is used to determine the curve separation point of the transient thermal resistance curve of the first semiconductor discrete device and the transient thermal resistance curve of the second semiconductor discrete device in the same coordinate system.

[0093] The transient thermal resistance test time determination unit takes the time corresponding to the curve separation point as the transient thermal resistance test time.

[0094] Based on the above embodiments, as an optional embodiment, the chip bonding qualification test module includes:

[0095] A chip bonding pass / fail test criterion construction unit is used to construct a chip bonding pass / fail test criterion based on the transient thermal resistance test time and the transient thermal resistance.

[0096] A chip bonding qualification test unit is used to perform chip bonding qualification tests on the target semiconductor discrete device based on the chip bonding qualification test criteria.

[0097] Based on the above embodiments, as an optional embodiment, the chip bonding qualification test criterion is as follows:

[0098] For any semiconductor discrete device, if the transient thermal resistance of the semiconductor discrete device during the transient thermal resistance test time is greater than the transient thermal resistance, then the chip bonding of the semiconductor discrete device is unqualified.

[0099] Otherwise, the bonding of the semiconductor discrete device chip is qualified.

[0100] Based on the above embodiments, as an optional embodiment, whether the chip bonding of the first semiconductor discrete device and the second semiconductor discrete device is qualified is determined according to the first rule;

[0101] The first rule states that chip bonding is unqualified when the total void area in the contact area of ​​the bonding layer of a semiconductor discrete device exceeds a first preset percentage of the total contact area; otherwise, it is qualified.

[0102] Based on the above embodiments, as an optional embodiment, the first preset percentage is 15%.

[0103] Based on the above embodiments, as an optional embodiment, the first semiconductor discrete device and the second semiconductor discrete device are obtained by customization or X-ray selection.

[0104] Thirdly, Figure 6 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 6 As shown, the electronic device may include: a processor 610, a communication interface 620, a memory 630, and a communication bus 640, wherein the processor 610, the communication interface 620, and the memory 630 communicate with each other through the communication bus 640. The processor 610 can call logic instructions in the memory 630 to execute a semiconductor discrete device chip bonding qualification test method. This method includes: testing the transient thermal resistance curves of a first semiconductor discrete device and a second semiconductor discrete device respectively; determining the transient thermal resistance test time of the semiconductor discrete device bonding layer based on the transient thermal resistance curves of the first and second semiconductor discrete devices; and performing a chip bonding qualification test on the target semiconductor discrete device based on the transient thermal resistance test time and the transient thermal resistance of the first semiconductor discrete device at the transient thermal resistance test time.

[0105] Among them, the chip bonding of the first semiconductor discrete device is unqualified but infinitely close to qualified; the chip bonding of the second semiconductor discrete device is qualified.

[0106] Furthermore, the logical instructions in the aforementioned memory 630 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0107] Fourthly, the present invention also provides a computer program product, the computer program product including a computer program, the computer program being able to be stored on a non-transitory computer-readable storage medium, the computer program being executed by a processor, the computer being able to execute the semiconductor discrete device chip bonding qualification test method provided by the above methods, the method including: testing the transient thermal resistance curves of a first semiconductor discrete device and a second semiconductor discrete device respectively; determining the transient thermal resistance test time of the semiconductor discrete device bonding layer based on the transient thermal resistance curves of the first semiconductor discrete device and the second semiconductor discrete device; and performing a chip bonding qualification test on the target semiconductor discrete device based on the transient thermal resistance test time and the transient thermal resistance of the first semiconductor discrete device at the transient thermal resistance test time;

[0108] Among them, the chip bonding of the first semiconductor discrete device is unqualified but infinitely close to qualified; the chip bonding of the second semiconductor discrete device is qualified.

[0109] Fifthly, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the semiconductor discrete device chip bonding qualification test method provided by the methods described above. The method includes: testing the transient thermal resistance curves of a first semiconductor discrete device and a second semiconductor discrete device respectively; determining a transient thermal resistance test time for the bonding layer of the semiconductor discrete device based on the transient thermal resistance curves of the first semiconductor discrete device and the second semiconductor discrete device; and performing a chip bonding qualification test on the target semiconductor discrete device based on the transient thermal resistance test time and the transient thermal resistance of the first semiconductor discrete device at the transient thermal resistance test time.

[0110] Among them, the chip bonding of the first semiconductor discrete device is unqualified but infinitely close to qualified; the chip bonding of the second semiconductor discrete device is qualified.

[0111] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0112] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for testing the bonding quality of semiconductor discrete device chips, characterized in that, The method includes: The transient thermal resistance curves of the first semiconductor discrete device and the second semiconductor discrete device were tested respectively. Based on the transient thermal resistance curves of the first and second semiconductor discrete devices, the transient thermal resistance test time of the bonding layer of the semiconductor discrete devices is determined, including: determining the curve separation point of the transient thermal resistance curves of the first and second semiconductor discrete devices in the same coordinate system; taking the time corresponding to the curve separation point as the transient thermal resistance test time; wherein the chip specifications of the first and second semiconductor discrete devices are the same. Based on the transient thermal resistance test time and the transient thermal resistance of the first semiconductor discrete device during the transient thermal resistance test time, the chip bonding qualification test is performed on the target semiconductor discrete device. The chip bonding of the first semiconductor discrete device and the second semiconductor discrete device is qualified according to the first rule. The first rule is that the chip bonding is unqualified when the total area of ​​the voids in the contact area of ​​the bonding layer of the semiconductor discrete device exceeds a first preset percentage of the total contact area, and qualified otherwise. The total area of ​​voids in the contact region of the adhesive layer of the first semiconductor discrete device is equal to the first preset percentage. The total void area in the contact region of the adhesive layer of the second semiconductor discrete device is less than the first preset percentage; The first semiconductor discrete device and the second semiconductor discrete device have significant differences in thermal characteristics in the chip bonding area.

2. The semiconductor discrete device chip bonding qualification test method according to claim 1, characterized in that, The transient thermal resistance curve uses time on the horizontal axis and transient thermal resistance on the vertical axis.

3. The semiconductor discrete device chip bonding qualification test method according to claim 1, characterized in that, The chip bonding qualification test of the target semiconductor discrete device is performed based on the transient thermal resistance test time and the transient thermal resistance of the first semiconductor discrete device during the transient thermal resistance test time, including: Based on the transient thermal resistance test time and the transient thermal resistance, a chip bonding qualification test criterion is constructed; Based on the chip bonding qualification test criteria, the chip bonding qualification test is performed on the target semiconductor discrete device.

4. The semiconductor discrete device chip bonding qualification test method according to claim 3, characterized in that, The criteria for the chip bonding qualification test are as follows: For any semiconductor discrete device, if the transient thermal resistance of the semiconductor discrete device during the transient thermal resistance test time is greater than that of the first semiconductor discrete device during the transient thermal resistance test time, then the chip bonding of the semiconductor discrete device is unqualified. Otherwise, the bonding of the semiconductor discrete device chip is qualified.

5. The semiconductor discrete device chip bonding qualification test method according to claim 1, characterized in that, The first preset percentage is 15%.

6. The semiconductor discrete device chip bonding conformity test method according to any one of claims 1 to 5, characterized in that, The first semiconductor discrete device and the second semiconductor discrete device are obtained through customization or X-ray selection.

7. A semiconductor discrete device chip bonding qualification testing device, characterized in that, The device includes: The transient thermal resistance curve testing module is used to test the transient thermal resistance curves of the first semiconductor discrete device and the second semiconductor discrete device, respectively. A transient thermal resistance test time determination module is used to determine the transient thermal resistance test time of the bonding layer of the semiconductor discrete device based on the transient thermal resistance curves of the first semiconductor discrete device and the second semiconductor discrete device. This includes: determining the curve separation point of the transient thermal resistance curves of the first semiconductor discrete device and the second semiconductor discrete device in the same coordinate system; and using the time corresponding to the curve separation point as the transient thermal resistance test time; wherein the chip specifications of the first semiconductor discrete device and the second semiconductor discrete device are the same. The chip bonding qualification test module is used to perform chip bonding qualification test on the target semiconductor discrete device based on the transient thermal resistance test time and the transient thermal resistance of the first semiconductor discrete device under the transient thermal resistance test time. The chip bonding of the first semiconductor discrete device and the second semiconductor discrete device is qualified according to the first rule. The first rule is that the chip bonding is unqualified when the total area of ​​the voids in the contact area of ​​the bonding layer of the semiconductor discrete device exceeds a first preset percentage of the total contact area, and qualified otherwise. The total area of ​​voids in the contact region of the adhesive layer of the first semiconductor discrete device is equal to the first preset percentage. The total void area in the contact region of the adhesive layer of the second semiconductor discrete device is less than the first preset percentage; The first semiconductor discrete device and the second semiconductor discrete device have significant differences in thermal characteristics in the chip bonding area.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the semiconductor discrete device chip bonding qualification test method as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the semiconductor discrete device chip bonding conformity test method as described in any one of claims 1 to 6.

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