A general test structure and test system for digital chips

Abstract

The application relates to the technical field of digital chip testing, and discloses a general testing structure and testing system of a digital chip, which comprises a working mode detection unit, a BIST analysis unit, a scan chain testing interface unit and N BIST testing interface units; in use, the working mode detection unit is used to set the current working mode, the BIST analysis unit is used to select an IP module for testing according to the current working mode, and the two mode setting pins of the working mode detection unit are multiplexed, so that the number of pins used for testing can be reduced, the CP testing cost can be reduced, and the testing risk can be reduced; in addition, the external data is analyzed by the BIST analysis unit, and the analyzed external data is sent to the BIST testing interface unit or the scan chain testing interface unit, so that the application can be connected with a testing machine only by using one working mode detection unit to realize two kinds of testing, the testing interfaces are unified, and general testing is realized.

Description

Technical Field

[0001] This invention relates to the field of digital chip testing technology, and more specifically to a general testing structure and testing system for digital chips. Background Technology

[0002] After the wafer is fabricated, the surface of the entire wafer will be covered with thousands of unpackaged chips that are regularly distributed. Before these chips are packaged, they need to be tested for CP (Chip Probing), which is to test the function and performance of each unpackaged chip. Only chips that pass the CP test can be packaged, thereby reducing unnecessary chip packaging tooling.

[0003] After the chip is packaged, it needs to undergo FT (Final Test) testing to check whether the packaged chip functions properly and whether any new defects were generated during the packaging process. Only chips that pass the FT test can meet the requirements of actual applications.

[0004] Currently, the technologies used for CP testing and FT testing include BIST (Build in selftest) testing, scan chain testing, and JTAG (Joint Test Action Group) testing.

[0005] BIST testing, also known as built-in self-test, is a technology that embeds relevant circuits into the chip circuitry during chip design to provide self-test functionality, thereby reducing the reliance of device testing on automated test equipment (ATE).

[0006] Scan chain testing uses observable and controllable scan flip-flops to replace the original general flip-flops in the circuit for testing. These scan flip-flops are connected in series to form a scan chain. In test mode, external data can be serially shifted in and out through the scan chain to achieve control and observation of the entire circuit.

[0007] JTAG testing primarily uses the JTAG interface, an international standard testing protocol mainly used for internal chip testing. Its basic principle is to define a TAP (Test Access Port) inside the device and then use a dedicated JTAG testing tool to test the internal nodes.

[0008] For existing testing technologies, each IP module of the chip (power module LDO, clock module OSC, Flash module, etc.) has its own BIST test interface. Unlike scan link ports, the lack of a unified BIST test interface significantly increases the cost of developing test programs on automated test equipment (ATE). Although JTAG testing technology provides a unified test interface, it still requires software support to truly implement the testing functions.

[0009] Furthermore, for CP testing, since it requires connecting to the test equipment via probes attached to the chip pins, the more test pins there are, the higher the risk of inaccurate probe placement, resulting in lower CP test accuracy. At the same time, a higher number of pins also reduces the number of chips that can be tested in parallel on the wafer, increasing the cost of CP testing. Therefore, using fewer test pins during the testing process yields better test results.

[0010] For scan chain testing, four test pins are required: CK (clock) pin, SE (scan enable) pin, SI (scan input) pin, and SO (scan output) pin.

[0011] For JTAG testing, five pins are required: TCK (clock), TMS (mode select), TDI (data input), TDO (data output), and the optional TRST (test reset).

[0012] For BIST testing, since each module is designed separately, the interface is not standardized, but at least four pins are required: clock pin, test enable pin, input pin, and output pin. In addition, the more complex the IP module, the more pins it may need. Summary of the Invention

[0013] In view of the shortcomings of the background technology, the present invention provides a general test structure and test system for digital chips. The technical problem to be solved is that there is currently a lack of a unified interface structure for BIST test and scan chain test, and the number of test pins is relatively large, requiring at least four pins.

[0014] To solve the above technical problems, the present invention provides the following technical solution in the first aspect: a general test structure for digital chips, including a working mode detection unit, a BIST parsing unit, a scan chain test interface unit, and N BIST test interface units, where N is a positive integer;

[0015] The working mode detection unit includes a clock pin for receiving a clock, M mode setting pins for setting the working mode, a test clock output pin, a test data input pin, a test data output pin, and a working mode output pin, where M is a positive integer greater than 1, and two of the M mode setting pins are multiplexed pins used for inputting external data and outputting detection data, respectively.

[0016] The working mode detection unit outputs a test clock through the test clock output pin based on the clock, and outputs a working mode selection signal through the working mode output pin based on the input signal level status of the M mode setting pins. The test data input pin and the test data output pin are electrically connected to two multiplexed pins.

[0017] The BIST parsing unit includes a parsing output interface, and is electrically connected to N BIST test interface units and scan chain test interface units through the parsing output interface. Each BIST test interface unit is used to connect to a test IP module.

[0018] The BIST parsing unit is electrically connected to the test clock output pin, test data input pin, test data output pin and working mode output pin respectively. It receives the test clock through the test clock output pin, and is electrically connected to two multiplexed pins through the test data input pin and test data output pin to receive external data and output test data. It receives the working mode selection signal through the working mode output pin.

[0019] The BIST parsing unit selects a BIST test interface unit for testing based on the working mode selection signal, and inputs a test clock and performs data interaction to the selected BIST test interface unit through the parsing output interface. The data interaction includes inputting parsed external data to the selected BIST test interface unit and receiving detection data output by the selected BIST test interface unit.

[0020] In one implementation of the first aspect, the value of M needs to satisfy the following formula:

[0021] 2 M ≥N+1.

[0022] In one embodiment of the first aspect, the operating mode detection unit is used to latch the operating mode and output an operating mode selection signal based on the signal level states of M mode setting pins when powered on.

[0023] In one embodiment of the first aspect, the operating mode detection unit further includes a reset pin, which latches the operating mode and outputs an operating mode selection signal based on the signal level states of M mode setting pins when a reset signal of a set duration is input to the reset pin.

[0024] In one embodiment of the first aspect, after the operating mode is latched, the two multiplexed pins of the operating mode detection unit are used to input external data and output detection data.

[0025] In one embodiment of the first aspect, the external data includes start bit data, data bit data, command bit data, and end bit data;

[0026] The detection data includes start bit data, data bit data, and end bit data.

[0027] In one embodiment of the first aspect, the BIST test interface unit includes a BIST test clock pin, a BIST operating mode setting pin, a BIST command pin, x BIST test input pins, and y BIST test output pins. The parsing output interface of the BIST parsing unit is used to input a test clock to the BIST test clock pin. The parsing output interface of the BIST parsing unit is used to input a first-level signal to the BIST operating mode setting pin of the selected BIST test interface unit to put it into test operating mode. When the BIST operating mode setting pin inputs a second-level signal, it is in normal operating mode. The first level and the second level are two opposite level states. The x BIST test input pins are used to input parsed external data, and the y BIST test output pins are used to output external data. x and y are positive integers. When the BIST test interface unit is in test operating mode, it inputs the parsed external data input by the x BIST test input pins to the IP module electrically connected to it.

[0028] In one embodiment of the first aspect, the BIST test interface unit further includes x normal input pins for inputting normal operation data. When the BIST test interface unit is in normal operation mode, it sends the normal operation data input from the x normal input pins to the IP module electrically connected thereto.

[0029] In one embodiment of the first aspect, the scan chain test interface unit includes a scan clock pin, a scan input pin, a scan output pin, and a scan enable pin. The BIST parsing unit inputs an enable signal to the scan enable pin based on the operating mode selection signal. The BIST parsing unit inputs a clock signal to the scan clock pin, inputs external data to the scan input pin, receives test data through the scan output pin, and sends the test data to the test data output pin.

[0030] Secondly, the present invention also provides a testing system, including the general testing structure of a digital chip as described above, and further including a testing machine, which is electrically connected to the working mode detection unit and is used to send external data to the working mode detection unit and receive detection data output by the working mode detection unit.

[0031] The beneficial effects of this invention compared with the prior art are as follows: This invention sets the current working mode by setting the working mode detection unit, and allows the BIST parsing unit to select an IP module for testing based on the current working mode. In addition, the two mode setting pins of the working mode detection unit are multiplexed, thereby reducing the number of pins used for testing, thereby reducing CP testing costs and lowering testing risks.

[0032] Furthermore, since the external data is parsed by the BIST parsing unit and the parsed external data is sent to the BIST test interface unit or the scan chain test interface unit, this invention can achieve two tests by using only one working mode detection unit connected to the test machine, thereby achieving a unified test interface and realizing universal testing. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of the present invention in the embodiment;

[0034] Figure 2 This is a pin diagram of the BIST test interface unit.

[0035] Figure 3 This is a pin diagram of the scan chain test interface unit;

[0036] Figure 4 This is a schematic diagram of the structure of external data;

[0037] Figure 5 This is a schematic diagram of the structure of the detection data. Detailed Implementation

[0038] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0039] like Figure 1 As shown, a general test structure for a digital chip includes a working mode detection unit 1, a BIST parsing unit 2, a scan chain test interface unit 4, and multiple BIST test interface units 3; the number of BIST test interface units 3 can be set according to the number of IP modules that need to be tested, that is, it can be expanded according to actual needs, and there is no limitation here.

[0040] exist Figure 1 In the middle, the working mode detection unit 1 includes a clock pin CLK0 for receiving the clock, multiple mode setting pins for setting the working mode, a test clock output pin CLK10, a test data input pin IN10, a test data output pin OUT10, and a working mode output pin MODE. Two of the multiple mode setting pins are multiplexed pins used for inputting external data and outputting detection data, respectively.

[0041] The working mode detection unit 1 outputs the test clock through the test clock output pin CLK10 based on the clock. Based on the input signal level status of the M mode setting pins, the working mode selection signal is output through the working mode output pin MODE. The test data input pin IN10 and the test data output pin OUT10 are electrically connected to two multiplexed pins.

[0042] BIST parsing unit 2 includes a parsing output interface, and is electrically connected to N BIST test interface units 3 and scan chain test interface units 4 through the parsing output interface. Each BIST test interface unit 3 is used to connect to a test IP module.

[0043] BIST parsing unit 1 is electrically connected to the test clock output pin CLK10, the test data input pin IN10, the test data output pin OUT10, and the working mode output pin MODE. It receives the test clock through the test clock output pin CLK10, and is electrically connected to two multiplexed pins through the test data input pin IN10 and the test data output pin OUT10 to receive external data and output test data. It receives the working mode selection signal through the working mode output pin.

[0044] BIST parsing unit 1 selects a BIST test interface unit 3 for testing based on the working mode selection signal, and inputs the test clock and performs data interaction to the selected BIST test interface unit 3 through the parsing output interface. The data interaction includes inputting parsed external data to the selected BIST test interface unit 3 and receiving the detection data output by the selected BIST test interface unit 3.

[0045] Specifically, in this embodiment, the number of BIST test interface units 3 can be set according to the actual number of IP modules to be tested, that is, it can be expanded according to actual needs, and there is no limitation here; for more complex chips, there are more IP modules. In this case, the present invention only needs to connect to the external testing institution through the working mode detection unit 1, and then parse the external data through the BIST parsing unit and select the specific IP module for testing, thereby reducing the number of pins connected to the external testing institution and reducing the testing cost.

[0046] Specifically, in this embodiment, the number of mode setting pins can be determined based on the sum of the actual number of IP modules to be tested and the number of scan chain test interface units 4; there is no limitation here. Figure 1 In the mode setting pins, there are pins IN0 / TST0, OUT0 / TST1 and TSTN, among which pins IN0 / TST0 and OUT0 / TST1 are multiplexed pins.

[0047] In this embodiment, the relationship between the BIST test interface unit 3, the scan chain test interface unit 4, and the mode setting pin is as follows: Assuming the number of BIST test interface units 3 is N, where N is a positive integer, and the number of mode setting pins is M, where M is a positive integer, then the values ​​of N and M need to satisfy the following formula:

[0048] 2 M ≥N+1.

[0049] For example, assuming there are only three BIST test interface units 3 and one scan chain test interface unit 4, only two mode setting pins are needed to set the operating modes of the three IP modules. Let's say the three IP modules are IP0, IP1, and IP2. The operating mode is set based on the signal level of the two mode setting pins. For instance, when the signal level of the two mode setting pins is "00", IP1 can be selected for testing; when it's "01", IP2 can be selected; when it's "10", IP3 can be selected; and when it's "11", scan chain test interface unit 4 can be selected. This example shows that the operating mode checking unit 1 of this invention can interact with external devices using at least three pins, reducing the number of pins required for chip testing.

[0050] In this embodiment, the process of setting the working mode through the working mode detection unit 1 is as follows:

[0051] Firstly, the working mode detection unit 1 can latch the working mode and output the working mode selection signal based on the signal level state of the mode setting pin when powered on.

[0052] Secondly, the working mode detection unit 1 also includes a reset pin. When a reset signal of a set duration is input to the reset pin, the working mode is latched based on the signal level state of the mode setting pin, and a working mode selection signal is output.

[0053] In addition, in this embodiment, for the multiplexed mode setting pins, after the working mode detection unit 1 latches the working mode, the two multiplexed pins begin to be used for inputting external data and outputting detection data. In actual use, after the working mode is set, external data is input to pin IN0 / TST0, and then input to BIST parsing unit 2 for parsing through test data input pin IN10. After receiving the detection data, BIST parsing unit 2 sends the test data to the external testing agency through test data output pin OUT10 and pin OUT0 / TST1.

[0054] In this embodiment, the formats of external data and detection data are as follows: Referring to Figure 4, external data includes start bit data, data bit data, command bit data and end bit data. The number of bits of the start bit data, data bit data, command bit data and end bit data of external data can be set according to actual needs. There is no limitation here. For example, the start bit data and end bit data are both four bits, and the four bits of the start bit data and end bit data of external data are both high-level signals.

[0055] For example, a 20-bit external data set would have the following format: 1111_yyyy_xxxxxxxx_1111;

[0056] The 1111 on the right is the start bit, the 1111 on the left is the end bit, yyyy is the command bit (defined as 4 bits), and xxxxxxxx is the data bit (defined as 8 bits).

[0057] Reference Figure 5 The detection data includes start bit data, data bit data, and end bit data. For example, the number of bits in the start bit data, data bit data, and end bit data of the detection data can be set according to actual needs. For example, the start bit data and end bit data of the detection data are both 4 bits, and the four start bit data and end bit data of the detection data are both high-level signals.

[0058] For example, 16-bit external data has the following format: 1111_xxxxxxxx_1111;

[0059] The 1111 on the right is the start bit, the 1111 on the left is the end bit, and xxxxxxxx represents the data bits (defined as 8 bits).

[0060] It is important to note that when defining the length of the data bits for external data and detection data, the number of data bits must meet the bit requirements of all IP modules.

[0061] In practical use, BIST parsing unit 2 parses the B-bit data and C-bit command data, and then sends the parsed data to the designated BIST test interface unit 3. In addition, after the working mode is set, BIST parsing unit 2 can parse external data according to a predefined external data format, and send the data to working mode detection unit 1 according to the predefined format. The working mode detection unit 1 then sends the data to the external testing agency through the OUT0 / TST1 pin. In this way, the parsing of external data can be achieved solely through hardware without the need for software intervention.

[0062] Reference Figure 2 In this embodiment, the BIST test interface unit 3 includes a BIST test clock pin TST_CLK, a BIST working mode setting pin IP1_TST_EN, a BIST command pin IP1_BIST_CMD, x BIST test input pins and y BIST test output pins. The x BIST test input pins are pins ip1_in1, ip1_in2 and ip1_inx, and the y BIST test output pins are pins ip1_out1, ip1_out2 and ip1_outy.

[0063] The parsing output interface of BIST parsing unit 2 is used to input the test clock to the BIST test clock pin TST_CLK. The parsing output interface of BIST parsing unit 2 is used to input a first-level signal to the BIST working mode setting pin IP1_TST_EN of the selected BIST test interface unit 3 to put it into test working mode. When the second-level signal is input to the BIST working mode setting pin IP1_TST_EN, it is in normal working mode. The first level state and the second level state are two opposite level states. In this embodiment, the first level state is a high level device and the second level state is a low level state. x BIST test input pins are used to input parsed external data, and y BIST test output pins are used to output external data. x and y are positive integers. When BIST test interface unit 3 is in test working mode, it inputs the parsed external data input by x BIST test input pins to the IP module electrically connected to it.

[0064] In practical use, BIST parsing unit 2 enters test mode by inputting a high-level signal to the BIST operating mode setting pin IP1_TST_EN of the corresponding BIST test interface unit 3. This allows for selection testing of all BIST test interface units 3 simply by setting the corresponding mode setting pin, thereby reducing the number of connection pins to external testing mechanisms. Furthermore, the number of BIST test input pins and BIST test output pins can be increased or decreased for different IP modules; no restrictions are imposed here.

[0065] In this embodiment, the BIST test interface unit 3 further includes x normal input pins, which are used to input normal working data. When the BIST test interface unit 3 is in normal working mode, it sends the normal working data input by the x normal input pins to the IP module electrically connected to it.

[0066] For example, Figure 4 The pin function definitions of BIST test interface unit 3 shown can be found in Table 1, which is as follows:

[0067] Table 1

[0068]

[0069]

[0070]

[0071] Reference Figure 3 In this embodiment, the scan chain test interface unit 4 includes a scan clock pin SCAN_CLK, a scan input pin SCAN_IN, a scan output pin SCAN_OUT, and a scan enable pin SCAN_EN. The BIST parsing unit 2 inputs an enable signal to the scan enable pin SCAN_EN based on the working mode selection signal. The BIST parsing unit 2 inputs a clock signal to the scan clock pin SCAN_CLK, inputs external data to the scan input pin SCAN_IN, receives test data through the scan output pin SCAN_OUT, and sends the test data to the test data output pin OUT10.

[0072] In summary, this invention sets the current working mode by setting the working mode detection unit 1, and allows the BIST parsing unit 2 to select an IP module for testing based on the current working mode. Furthermore, it allows the two mode setting pins of the working mode detection unit 1 to be reused, thereby reducing the number of pins used for testing, thus reducing CP testing costs and lowering testing risks.

[0073] Furthermore, since the external data is parsed by the BIST parsing unit 2 and the parsed external data is sent to the BIST test interface unit 3 or the scan chain test interface unit 4, the present invention can achieve two tests by using only one working mode detection unit 1 connected to the test machine, thereby achieving the unification of the test interface and realizing universal testing.

[0074] Secondly, the present invention also provides a testing system, including the general testing structure of a digital chip as described above, and further including a tester (ATE), which is electrically connected to the working mode detection unit 1 and is used to send external data to the working mode detection unit 1 and receive the detection data output by the working mode detection unit 1.

[0075] Based on the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A universal test structure for digital chips, characterized in that, It includes a working mode detection unit, a BIST parsing unit, a scan chain test interface unit, and N BIST test interface units, where N is a positive integer; The working mode detection unit includes a clock pin for receiving a clock, M mode setting pins for setting the working mode, a test clock output pin, a test data input pin, a test data output pin, and a working mode output pin, where M is a positive integer greater than 1, and two of the M mode setting pins are multiplexed pins used for inputting external data and outputting detection data, respectively. The working mode detection unit outputs a test clock through the test clock output pin based on the clock, and outputs a working mode selection signal through the working mode output pin based on the input signal level status of the M mode setting pins. The test data input pin and the test data output pin are electrically connected to two multiplexed pins. The BIST parsing unit includes a parsing output interface, and is electrically connected to N BIST test interface units and scan chain test interface units through the parsing output interface. Each BIST test interface unit is used to connect to a test IP module. The BIST parsing unit is electrically connected to the test clock output pin, test data input pin, test data output pin and working mode output pin respectively. It receives the test clock through the test clock output pin, and is electrically connected to two multiplexed pins through the test data input pin and test data output pin to receive external data and output test data. It receives the working mode selection signal through the working mode output pin. The BIST parsing unit selects a BIST test interface unit for testing based on the working mode selection signal, and inputs a test clock and performs data interaction to the selected BIST test interface unit through the parsing output interface. The data interaction includes inputting parsed external data to the selected BIST test interface unit and receiving detection data output by the selected BIST test interface unit. The BIST test interface unit includes a BIST test clock pin, a BIST operating mode setting pin, a BIST command pin, x BIST test input pins, and y BIST test output pins. The parsing output interface of the BIST parsing unit is used to input a test clock to the BIST test clock pin. The parsing output interface of the BIST parsing unit is used to input a first-level signal to the BIST operating mode setting pin of the selected BIST test interface unit to put it into test operating mode. When the BIST operating mode setting pin inputs a second-level signal, it is in normal operating mode. The first level and the second level are two opposite level states. The x BIST test input pins are used to input parsed external data, and the y BIST test output pins are used to output detection data. x and y are positive integers. When the BIST test interface unit is in test operating mode, it inputs the parsed external data input from the x BIST test input pins to the IP module electrically connected to it.

2. The universal test structure for a digital chip according to claim 1, characterized in that, The value of M needs to satisfy the following formula: 。 3. The universal test structure for a digital chip according to claim 1, characterized in that, The operating mode detection unit is used to latch the operating mode and output the operating mode selection signal based on the signal level status of M mode setting pins when powered on.

4. A universal test structure for a digital chip according to any one of claims 1-3, characterized in that, The working mode detection unit also includes a reset pin. When a reset signal of a set duration is input to the reset pin, the working mode is latched based on the signal level states of the M mode setting pins and a working mode selection signal is output.

5. The universal test structure for a digital chip according to claim 4, characterized in that, After the working mode is latched, the two multiplexed pins of the working mode detection unit are used to input external data and output detection data.

6. The universal test structure for a digital chip according to claim 1, characterized in that, The external data includes start bit data, data bit data, command bit data, and end bit data; The detection data includes start bit data, data bit data, and end bit data.

7. The universal test structure for a digital chip according to claim 1, characterized in that, The BIST test interface unit also includes x normal input pins, which are used to input normal operation data. When the BIST test interface unit is in normal operation mode, it sends the normal operation data input from the x normal input pins to the IP module electrically connected to it.

8. The universal test structure for a digital chip according to claim 1, characterized in that, The scan chain test interface unit includes a scan clock pin, a scan input pin, a scan output pin, and a scan enable pin. The BIST parsing unit inputs an enable signal to the scan enable pin based on the working mode selection signal. The BIST parsing unit inputs a clock signal to the scan clock pin, inputs external data to the scan input pin, receives test data through the scan output pin, and sends the test data to the test data output pin.

9. A testing system, characterized in that, The invention includes a general test structure for a digital chip as described in any one of claims 1-8, and further includes a test machine, which is electrically connected to the operating mode detection unit and is used to send external data to the operating mode detection unit and receive detection data output by the operating mode detection unit.

Images