Array substrate and display panel

Abstract

This application provides an array substrate and a display panel. The array substrate includes multiple scan lines extending along a first direction and data lines extending along a second direction. The scan lines and data lines intersect to define multiple pixel regions. Each pixel region is provided with a sub-pixel. The multiple sub-pixels are arranged in multiple columns along the first direction and in multiple rows along the second direction. Each sub-pixel includes a pixel electrode and a transistor. The vertical orthographic projection of each pixel electrode covers at least a portion of the vertical orthographic projection of the corresponding scan line, so that the pixel electrode expands outward in the direction of the scan line, thereby increasing the aperture ratio of each sub-pixel and thus improving the transmittance, thereby alleviating the technical problem of low transmittance in existing tri-gate liquid crystal display panels. At the same time, the transistor of each sub-pixel is electrically connected to the pixel electrode of a sub-pixel in an adjacent row, which can reduce the impact of the coupling capacitance generated by the overlap of the pixel electrode and the scan line on the sub-pixel in the same row.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] With the development of Liquid Crystal Display (LCD) technology, a tri-gate LCD panel has emerged in the industry to reduce the cost of LCD panels. A tri-gate LCD panel has multiple pixel units arranged in rows and columns, and each pixel unit is driven by three adjacent scan lines. Each pixel unit consists of three sub-pixel units of different colors arranged vertically; for example, each pixel unit includes a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit. The sub-pixel units in the same row are electrically connected to a single scan line. Furthermore, the sub-pixel units in any row are of the same color; for example, all the sub-pixel units arranged in one row are either red, green, or blue.

[0003] However, in traditional tri-gate liquid crystal display panels, the areas corresponding to the thin-film transistors, scan lines, and pixel electrode trunks are all opaque, resulting in a small aperture ratio and low transmittance. Summary of the Invention

[0004] This application provides an array substrate and a display panel to alleviate the technical problem of low transmittance in existing tri-gate liquid crystal display panels.

[0005] To solve the above problems, the technical solution provided in this application is as follows:

[0006] This application provides an array substrate comprising multiple scan lines extending along a first direction and data lines extending along a second direction. The scan lines and data lines intersect to define multiple pixel regions. Each pixel region is provided with a sub-pixel. The multiple sub-pixels are arranged in multiple columns along the first direction and in multiple rows along the second direction. Each sub-pixel includes a pixel electrode and a transistor. The vertical orthographic projection of each pixel electrode covers at least a portion of the vertical orthographic projection of the corresponding scan line. In the same column of sub-pixels, the transistor of each sub-pixel is electrically connected to the pixel electrode of a sub-pixel in an adjacent row.

[0007] In the array substrate provided in the embodiments of this application, each transistor includes a gate, a source, and a drain. The gate is electrically connected to the scan line of the corresponding row, one of the source and the drain is electrically connected to the corresponding data line, and the other is electrically connected to the pixel electrode of a sub-pixel in an adjacent row.

[0008] In the array substrate provided in the embodiments of this application, each pixel electrode includes a main electrode extending along the first direction and branch electrodes extending from the main electrode in different directions; the pixel electrode also includes a border electrode surrounding the main electrode and the branch electrodes and an extension electrode protruding from the border electrode, the border electrode having a first opening on the side away from the extension electrode, the extension electrode passing through the first opening of the sub-pixel in the adjacent row and being electrically connected to the drain of the sub-pixel in the adjacent row.

[0009] In the array substrate provided in this application embodiment, the extended electrode extends along the second direction, and the pixel electrode is axially symmetrical about the extension line of the extended electrode.

[0010] In the array substrate provided in the embodiments of this application, the array substrate further includes a plurality of first connection traces extending along the first direction, and the source is electrically connected to the data line through the first connection traces.

[0011] In the array substrate provided in this application embodiment, the first connection trace overlaps with the main electrode.

[0012] In the array substrate provided in this application embodiment, the main electrode divides the pixel electrode into a first display domain and a second display domain. The first display domain is located on one side of the main electrode, and the second display domain is located on the other side of the main electrode. The first display domain includes a first sub-display domain and a second sub-display domain. The branch electrodes in the first sub-display domain and the second sub-display domain extend in different directions, and there is a first gap between the first sub-display domain and the second sub-display domain. The second display domain includes a third sub-display domain and a fourth sub-display domain. The branch electrodes in the third sub-display domain and the fourth sub-display domain extend in different directions, and there is a second gap between the third sub-display domain and the fourth sub-display domain. The transistor is located below the pixel electrode and is disposed corresponding to the first gap and / or the second gap.

[0013] In the array substrate provided in the embodiments of this application, in the sub-pixels in the same column, any three adjacent sub-pixels constitute a pixel, the three sub-pixels of each pixel are different in color, and the sub-pixels in the same row are the same in color; each data line connects the pixels in the odd-numbered rows in the same column and the pixels in the even-numbered rows in the adjacent columns, and each scan line connects the sub-pixels in the same row.

[0014] In the array substrate provided in the embodiments of this application, in the sub-pixels in the same row, the vertical orthographic projection of the pixel electrode of each sub-pixel covers a portion of the vertical orthographic projection of the scan line of the corresponding row, and covers a portion of the vertical orthographic projection of the scan line of the adjacent row.

[0015] This application also provides a display panel that includes an array substrate of one of the foregoing embodiments.

[0016] The beneficial effects of this application are as follows: In the array substrate and display panel provided by this application, the array substrate includes multiple scan lines extending along a first direction and data lines extending along a second direction. The scan lines and data lines intersect to define multiple pixel areas. Each pixel area is provided with a sub-pixel. The multiple sub-pixels are arranged in multiple columns along the first direction and in multiple rows along the second direction. Each sub-pixel includes a pixel electrode and a transistor. The vertical orthographic projection of each pixel electrode covers at least a portion of the vertical orthographic projection of the corresponding scan line, so that the pixel electrode expands outward in the direction of the scan line, thereby increasing the aperture ratio of each sub-pixel and thus improving the transmittance, solving the technical problem of low transmittance in existing tri-gate liquid crystal display panels. At the same time, in the same column of sub-pixels, the transistor of each sub-pixel is electrically connected to the pixel electrode of a sub-pixel in an adjacent row, which can reduce the influence of the coupling capacitance generated by the overlap of the pixel electrode and the scan line on the sub-pixel in the same row. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a partial top view of a tri-gate liquid crystal display panel in related technologies.

[0019] Figure 2 This is a top view of an array substrate provided in an embodiment of this application.

[0020] Figure 3 for Figure 2 A schematic diagram showing the detailed structure of the middle sub-pixels.

[0021] Figure 4 for Figure 3 A magnified schematic diagram of the middle sub-pixels.

[0022] Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure along the M-M' direction.

[0023] Figure 6 for Figure 4 A schematic diagram of the cross-sectional structure along the N-N' direction.

[0024] Figure 7 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application. Detailed Implementation

[0025] The following descriptions of the embodiments are based on the accompanying illustrations, illustrating specific embodiments in which this application can be implemented. Directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustration and understanding of this application, and not for limiting this application. In the figures, structurally similar units are denoted by the same reference numerals. In the figures, the thickness of some layers and regions is exaggerated for clarity and ease of description. That is, the dimensions and thicknesses of each component shown in the figures are arbitrarily shown, but this application is not limited thereto.

[0026] To address the issue of low transmittance in tri-gate liquid crystal display panels in related technologies, the inventors of this application discovered during their research that: (Referring to...) Figure 1 , Figure 1 This is a partial top-view structural diagram of a tri-gate liquid crystal display panel in related technologies. In a tri-gate liquid crystal display panel, the areas corresponding to the thin-film transistors (TFTs), scan lines (GL), and the trunk of the pixel electrodes (PE) are all opaque, resulting in a small aperture ratio and low transmittance. Furthermore, GBS traces are positioned above the scan lines (GL) and DBS traces are positioned above the data lines (DL), further reducing the aperture ratio of the tri-gate liquid crystal display panel.

[0027] Therefore, this application provides an array substrate and a display panel to solve the aforementioned problem of poor viewing angle.

[0028] Please refer to Figures 2 to 6 , Figure 2 This is a top view schematic diagram of an array substrate provided in an embodiment of this application. Figure 3 for Figure 2 A schematic diagram showing the detailed structure of the middle sub-pixels. Figure 4 for Figure 3 A magnified schematic diagram of the middle sub-pixels. Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure along the M-M' direction. Figure 6 for Figure 4 A schematic diagram of the cross-sectional structure along the N-N' direction. (Refer to...) Figure 2 The array substrate 100 includes a substrate 10 and multiple scan lines (e.g., ...) arranged on the substrate 10. Figure 2 The schematic diagram shows scan lines G(n-3), G(n-2), G(n-1), Gn, G(n+1), G(n+2), G(n+3) and multiple data lines (such as...). Figure 2 The schematically shown data lines are D(n-3), D(n-2), D(n-1), Dn, D(n+1), D(n+2), D(n+3), where n is greater than or equal to 3. Multiple scan lines extend along a first direction X and are spaced apart along a second direction Y. Multiple data lines DL extend along the second direction Y and are spaced apart along the first direction X. The first direction X and the second direction Y are different; for example, the first direction X is a row direction, and the second direction Y is a column direction.

[0029] The scan lines and data lines intersect to define multiple pixel regions PD, each pixel region PD having a sub-pixel SP, such that the array substrate 100 includes multiple sub-pixels SP, and the multiple sub-pixels SP are arrayed on the array substrate 100. The multiple sub-pixels SP are arranged in multiple columns along the first direction X (e.g., ...). Figure 2 The schematically shown sub-pixel columns L(n-3), L(n-2), L(n-1), Ln, L(n+1), L(n+2) are arranged in multiple rows along the second direction Y (e.g., Figure 2 The schematic diagram shows the sub-pixel rows H(n-3), H(n-2), H(n-1), Hn, H(n+1), H(n+2)).

[0030] In the second direction Y, any three adjacent sub-pixels SP in the same column constitute a pixel P. The three sub-pixels SP of each pixel P are of different colors; that is, any two adjacent sub-pixels SP are of different colors, and any three adjacent sub-pixels SP of different colors form a pixel P. Specifically, each pixel P includes three sub-pixels SP arranged sequentially in the second direction Y. These three sequentially arranged sub-pixels SP are of different colors, for example, they may include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The three sub-pixels SP of different colors of each pixel P are connected to the same data line. Each data line connects the pixels P in the odd-numbered rows of the same column and the pixels P in the even-numbered rows of adjacent columns. Taking data line Dn as an example, data line Dn is electrically connected to the pixels P in the odd-numbered rows of sub-pixel column Ln, and data line Dn is also electrically connected to the pixels P in the even-numbered rows of sub-pixel column L(n-1).

[0031] In the first direction X, all sub-pixels SP in the same row have the same color, and all sub-pixels SP with the same color are connected to the same scan line. Taking sub-pixel row Hn as an example, all sub-pixels SP in sub-pixel row Hn are red sub-pixels R, and all red sub-pixels R are electrically connected to scan line Gn. Of course, the colors of the sub-pixels SP in the same row can also be different. When the colors of the sub-pixels SP in each row are different, the color shift that occurs when displaying a two-color mixed image can be improved. This application embodiment uses the example of all sub-pixels SP in each row having the same color, and for ease of description, the scan line mentioned below is described using Gn as an example, and the data line is described using Dn as an example.

[0032] Reference Figure 3 Each sub-pixel SP includes a pixel electrode 20 and a transistor 30. Each pixel electrode 20 includes a main electrode 21 extending along the first direction X and branch electrodes 22 extending from the main electrode 21 in different directions. The pixel electrode 20 also includes a border electrode 23 surrounding the main electrode 21 and the branch electrodes 22. The vertical orthographic projection of each pixel electrode 20 covers at least a portion of the vertical orthographic projection of the corresponding scan line. That is, the orthographic projection of the pixel electrode 20 on the substrate 10 overlaps with the orthographic projection of the corresponding scan line on the substrate 10. Thus, the pixel electrode 20 can expand outward in the direction of the corresponding scan line, thereby increasing the aperture ratio of each sub-pixel SP and improving the transmittance, solving the technical problem of low transmittance in existing tri-gate liquid crystal display panels.

[0033] Specifically, in conjunction with reference Figure 3 , Figure 4 and Figure 5 The orthographic projection of the border electrode 23 of the pixel electrode 20 onto the substrate 10 overlaps with the orthographic projection of the corresponding scan line onto the substrate 10. Taking the pixel electrode 20 of the sub-pixel SP located in sub-pixel row Hn and sub-pixel column L(n-1) as an example, the orthographic projection of the border electrode 23 of the pixel electrode 20 onto the substrate 10 overlaps with the orthographic projection of the corresponding scan line Gn onto the substrate 10. Thus, the pixel electrode 20 can expand outwards in the direction of the scan line Gn, thereby increasing the aperture ratio of the sub-pixel SP and improving the transmittance.

[0034] Optionally, in the same row of sub-pixels SP, the vertical orthographic projection of the pixel electrode 20 of each sub-pixel SP covers a portion of the vertical orthographic projection of the scan line in the corresponding row, and also covers a portion of the vertical orthographic projection of the scan line in the adjacent row, to further increase the aperture ratio of each sub-pixel SP and improve transmittance. Similarly, taking the pixel electrode 20 of the sub-pixel SP located in sub-pixel row Hn and sub-pixel column L(n-1) as an example, the orthographic projection of the border electrode 23 of the pixel electrode 20 on the substrate 10 overlaps with the orthographic projection of the scan line Gn corresponding to the sub-pixel row Hn on the substrate 10, and the orthographic projection of the border electrode 23 on the substrate 10 also overlaps with the orthographic projection of the scan line G(n+1) corresponding to the adjacent sub-pixel row H(n+1) on the substrate 10. In this way, the pixel electrode 20 can expand outward in the direction of the scan line Gn and the scan line G(n+1), thereby further increasing the aperture ratio of the sub-pixel SP and further improving transmittance.

[0035] However, the pixel electrode 20 overlaps with the scan line Gn. While this improves transmittance, it also creates a coupling capacitance between the pixel electrode 20 and the scan line Gn. When charging the sub-pixel SP, this large coupling capacitance affects the voltage on the pixel electrode 20, thus impacting the charging rate and display quality of the sub-pixel SP. To address this, the inventors of this application, through in-depth research, have found a method to resolve the issue of the pixel electrode 20 overlapping with the scan line Gn, which affects the charging rate and display quality of the sub-pixel SP: In the same column of sub-pixels SP, the transistor 30 of each sub-pixel SP is electrically connected to the pixel electrode 20 of one sub-pixel SP in an adjacent row.

[0036] Specifically, in conjunction with reference Figure 3 , Figure 4 and Figure 6The transistor 30 is located on the side of the pixel electrode 20 closer to the substrate 10, that is, the transistor 30 is located below the pixel electrode 20, and the pixel electrode 20 is located on the side of the transistor 30 away from the substrate 10. Each transistor 30 includes a gate 31, a source 32, and a drain 33. The gate 31 is electrically connected to the scan line of the corresponding row. One of the source 32 and the drain 33 is electrically connected to the corresponding data line, and the other is electrically connected to the pixel electrode 20 of a sub-pixel SP in an adjacent row. In this embodiment, the source 32 is electrically connected to the data line, and the drain 33 is electrically connected to the pixel electrode 20 in an adjacent row as an example.

[0037] The pixel electrode 20 includes a main electrode 21 extending along the first direction X and branch electrodes 22 extending from the main electrode 21 in different directions. The pixel electrode 20 also includes a border electrode 23 surrounding the main electrode 21 and the branch electrodes 22, and an extension electrode 24 protruding from the border electrode 23. The border electrode 23 has a first opening 230 on the side away from the extension electrode 24. The extension electrode 24 passes through the first opening 230 of the sub-pixel SP in the adjacent row and is electrically connected to the drain 33 of the sub-pixel SP in the adjacent row. For example, taking the pixel electrode 20 of the sub-pixel SP located in sub-pixel row H(n+1) and sub-pixel column L(n-1) as an example, refer to... Figure 4 The extension electrode 24 of the pixel electrode 20 in the sub-pixel row H(n+1) passes through the first opening 230 of the pixel electrode 20 in the sub-pixel row Hn and is electrically connected to the drain 33 of the transistor 30 in the sub-pixel row Hn.

[0038] Furthermore, continue to refer to Figure 3 , Figure 4 and Figure 6 Each sub-pixel SP further includes a storage capacitor 40, which is located on the side of the transistor 30 away from the extended electrode 24, for example, the transistor 30 is positioned close to the extended electrode 24, and the storage capacitor 40 is positioned close to the first opening 230. The storage capacitor 40 includes a first electrode 41 and a second electrode 42 disposed opposite to each other. The first electrode 41 is located on the side of the second electrode 42 away from the substrate 10. The first electrode 41 is electrically connected to the drain 33 of the transistor 30 and also to the extended electrode 24. That is, the pixel electrode 20 of each sub-pixel SP is electrically connected to the drain 33 of the transistor 30 of the adjacent row of sub-pixel SPs through the first electrode 41 of the storage capacitor 40 of the adjacent row of sub-pixel SPs.

[0039] Reference Figure 4 and Figure 6 The first electrode 41 of the storage capacitor 40 is disposed on the same layer as the source 32 and the drain 33 of the transistor 30, and the second electrode 42 is disposed on the same layer as the gate 31 of the transistor 30. It should be noted that "disposed on the same layer" in this application means that in the fabrication process, at least two different structures are obtained by patterning a film layer formed of the same material, and the at least two different structures are disposed on the same layer. For example, in this embodiment, the second electrode 42 and the gate 31 are obtained by patterning the same conductive film layer, and therefore the second electrode 42 and the gate 31 are disposed on the same layer.

[0040] The transistor 30 is disposed on the substrate 10, and the pixel electrode 20 is disposed on the side of the transistor 30 away from the substrate 10. The substrate 10 may include a rigid substrate such as a glass substrate, a quartz substrate, or a silicon wafer. The gate 31 of the transistor 30 is disposed on the substrate 10, the active layer 34 of the transistor 30 is disposed on the side of the gate 31 away from the substrate 10, and the source 32 and drain 33 of the transistor 30 are disposed on the side of the active layer 34 away from the gate 31. Both the source 32 and the drain 33 are electrically connected to the active layer 34. The pixel electrode 20 is disposed on the side of the source 32 and the drain 33 away from the gate 31 and is electrically connected to the drain 33.

[0041] Of course, the array substrate 100 also includes a plurality of insulating layers disposed between the layers of the transistor 30 and between the transistor 30 and the pixel electrode 20. For example, the array substrate 100 also includes a gate insulating layer 11 disposed between the gate 31 and the active layer 34, an interlayer insulating layer 12 disposed between the active layer 34 and the source 32 and the drain 33, a passivation layer 13 disposed between the source 32, the drain 33 and the pixel electrode 20, and a planarization layer 14.

[0042] Optionally, the gate 31, the source 32, and the drain 33 may all be made of conductive metals such as copper, aluminum, molybdenum, and titanium. The active layer 34 may be made of semiconductor materials such as amorphous silicon and polycrystalline silicon. The gate insulating layer 11, the interlayer insulating layer 12, and the passivation layer 13 may all be made of inorganic materials such as silicon oxide and silicon nitride, and the planarization layer 14 may be made of organic materials such as organic photoresist.

[0043] In this embodiment, by electrically connecting the transistor 30 of each sub-pixel SP to the pixel electrode 20 of an adjacent row of sub-pixel SP, cross-row charging of the sub-pixel SP is achieved, thereby mitigating the impact of the large coupling capacitance generated between the pixel electrode 20 and the scan line on the charging of the sub-pixel SP. Specifically, referring to... Figure 3 Taking four sub-pixel rows H(n-1), Hn, H(n+1), and H(n+2) as an example, when the scan line G(n+1) corresponding to sub-pixel row H(n+1) starts scanning, scan line G(n+1) charges the sub-pixel SP of sub-pixel row H(n+2). At this time, the signal change of scan line G(n+1) will generate coupling capacitance with the pixel electrodes 20 of sub-pixel rows H(n+1) and Hn, which will affect the pixel voltage of sub-pixel rows H(n+1) and Hn. When the scan line Gn corresponding to sub-pixel row Hn starts scanning, scan line Gn charges the sub-pixel SP of sub-pixel row H(n+1), thus... The effect of pixel voltage changes in sub-pixel row H(n+1) caused by charging sub-pixel row H(n+2) is quickly eliminated. Furthermore, the signal change of scan line Gn at this time will generate coupling capacitance with the pixel electrodes 20 of sub-pixel row H(n-1) and sub-pixel row Hn, thus affecting the pixel voltages of sub-pixel row H(n-1) and sub-pixel row Hn. When scan line G(n-1) corresponding to sub-pixel row H(n-1) starts scanning, scan line G(n-1) charges sub-pixel SP of sub-pixel row Hn, thus quickly eliminating the effect of pixel voltage changes in sub-pixel row Hn caused by charging sub-pixel row H(n+2) and sub-pixel row H(n+1). Therefore, the pixel voltage of sub-pixel SP in each row is affected twice by the signal change of the scan line, but by charging across rows, the effect of the coupling capacitance generated by the overlap of the pixel electrode and the scan line on the sub-pixel in this row can be quickly eliminated.

[0044] In other embodiments, within the same row of sub-pixels SP, the vertical orthographic projection of the pixel electrode 20 of each sub-pixel SP completely covers the vertical orthographic projection of the scan line in the corresponding row; that is, the orthographic projection of the pixel electrode 20 on the substrate 10 completely covers the orthographic projection of the scan line Gn on the substrate 10. Simultaneously, there is no overlap between the vertical orthographic projection of the pixel electrode 20 of each sub-pixel SP and the vertical orthographic projection of the scan line in the adjacent row. This also increases the aperture ratio of the sub-pixels and improves transmittance. Furthermore, since the pixel voltage of each row of sub-pixels SP is affected once by the signal change of the scan line, the effect of the coupling capacitance generated by the overlap of the pixel electrode and the scan line on the sub-pixels in this row can be quickly eliminated through cross-row charging.

[0045] In one embodiment, in conjunction with reference to Figure 3 , Figure 4 and Figure 5 In order to further increase the aperture ratio of the sub-pixel SP, in each sub-pixel SP, the transistor 30 is disposed in the middle region corresponding to the pixel electrode 20. Specifically, the main electrode 21 divides the pixel electrode 20 into a first display domain C1 and a second display domain C2. The first display domain C1 is located on one side of the main electrode 21, and the second display domain C2 is located on the other side of the main electrode 21. The first display domain C1 includes a first sub-display domain Dm1 and a second sub-display domain Dm2. The branch electrodes 22 within the first sub-display domain Dm1 and the second sub-display domain Dm2 have different extension directions, and a first gap 211 exists between the first sub-display domain Dm1 and the second sub-display domain Dm2. The second display domain C2 includes a third sub-display domain Dm3 and a fourth sub-display domain Dm4. The branch electrodes 22 within the third sub-display domain Dm3 and the fourth sub-display domain Dm4 have different extension directions, and a second gap 212 exists between the third sub-display domain Dm3 and the fourth sub-display domain Dm4. The transistor 30 is located below the pixel electrode 20 and is configured corresponding to the first gap 211 and / or the second gap 212. Figure 3 As shown, the transistor 30 is positioned corresponding to the first gap 211, and the storage capacitor 40 is positioned corresponding to the second gap 212. The extended electrode 24 is close to the first gap 211, and the first opening 230 is close to the second gap 212 and passes through the second gap 212.

[0046] Understandably, to improve viewing angle, the pixel electrode PE of a sub-pixel in related technologies typically includes two mutually perpendicular trunk electrodes, both located in the middle region of the pixel electrode PE, such as... Figure 1 As shown. The area corresponding to the trunk electrode cannot be used for display. However, by setting the transistor 30 in the middle area of ​​the pixel electrode 20, this application is equivalent to setting the transistor 30 in an area where the sub-pixel SP would not be displayed, thereby saving the space for additional transistor 30. This can further improve the aperture ratio of the sub-pixel SP.

[0047] Furthermore, the array substrate 100 also includes multiple first connection traces 50 extending along the first direction X, and the source electrode 32 is electrically connected to the corresponding data line through the first connection traces 50. The first connection traces 50 coincide with the main electrode 21, that is, the orthographic projection of the first connection traces 50 on the substrate 10 falls within the range of the orthographic projection of the main electrode 21 on the substrate 10, so as to avoid the first connection traces 50 affecting the aperture ratio of the sub-pixel SP.

[0048] Optionally, the extended electrode 24 within each sub-pixel SP extends along the second direction Y, and the pixel electrode 20 is axially symmetrical about the extension line of the corresponding extended electrode 24, and the extension line of the extended electrode 24 also passes through the first opening 230. Thus, by also positioning the extended electrode 24 and the first opening 230 in the middle region of the pixel electrode 20, the extended electrode 24 is electrically connected to the corresponding transistor 30.

[0049] Based on the same inventive concept, this application also provides a display panel, please refer to... Figures 2 to 7 , Figure 7 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application. The display panel includes an array substrate 100 as described in one of the foregoing embodiments. The display panel is a liquid crystal display panel, etc., and this embodiment is described using a liquid crystal display panel as an example. Specifically, refer to... Figure 7 The display panel 1000 includes a first substrate and a second substrate disposed opposite to each other, wherein one of the first substrate and the second substrate is an array substrate 100 as described in one of the foregoing embodiments. In this embodiment, the array substrate 100 is used as the first substrate, and the second substrate is a color filter substrate 200. The display panel 1000 also includes liquid crystal molecules 300 sandwiched between the array substrate 100 and the color filter substrate 200.

[0050] As can be seen from the above embodiments:

[0051] This application provides an array substrate and a display panel. The array substrate includes multiple scan lines extending along a first direction and data lines extending along a second direction. The scan lines and data lines intersect to define multiple pixel regions. Each pixel region is provided with a sub-pixel. The multiple sub-pixels are arranged in multiple columns along the first direction and in multiple rows along the second direction. Each sub-pixel includes a pixel electrode and a transistor. The vertical orthographic projection of each pixel electrode covers at least a portion of the vertical orthographic projection of the corresponding scan line, so that the pixel electrode expands outward in the direction of the scan line, thereby increasing the aperture ratio of each sub-pixel and improving the transmittance. This solves the technical problem of low transmittance in existing tri-gate liquid crystal display panels. At the same time, in the same column of sub-pixels, the transistor of each sub-pixel is electrically connected to the pixel electrode of a sub-pixel in an adjacent row, which can reduce the impact of the coupling capacitance generated by the overlap of the pixel electrode and the scan line on the sub-pixel in the same row.

[0052] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0053] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, characterized in that, It includes multiple scan lines extending along a first direction and data lines extending along a second direction. The scan lines and data lines intersect to define multiple pixel areas. Each pixel area is provided with a sub-pixel. The multiple sub-pixels are arranged in multiple columns along the first direction and in multiple rows along the second direction. Each of the sub-pixels includes a pixel electrode and a transistor, the vertical orthographic projection of each pixel electrode covers at least a portion of the vertical orthographic projection of the corresponding scan line, and in the same column of the sub-pixels, the transistor of each sub-pixel is electrically connected to the pixel electrode of a sub-pixel in an adjacent row; Each of the transistors includes a gate, a source, and a drain. The gate is electrically connected to the scan line of the corresponding row, one of the source and the drain is electrically connected to the corresponding data line, and the other is electrically connected to the pixel electrode of a sub-pixel in an adjacent row. Each of the pixel electrodes includes a main electrode extending along the first direction and branch electrodes extending from the main electrode in different directions; The pixel electrode also includes a border electrode surrounding the main electrode and the branch electrode, and an extension electrode protruding from the border electrode. The border electrode has a first opening on the side away from the extension electrode. The extension electrode passes through the first opening of the sub-pixel in the adjacent row and is electrically connected to the drain of the sub-pixel in the adjacent row.

2. The array substrate according to claim 1, characterized in that, The extended electrode extends along the second direction, and the pixel electrode is axially symmetrical about the extension line of the extended electrode.

3. The array substrate according to claim 1, characterized in that, The array substrate also includes multiple first connection traces extending along the first direction, and the source electrode is electrically connected to the data line through the first connection traces.

4. The array substrate according to claim 3, characterized in that, The first connection trace overlaps with the main electrode.

5. The array substrate according to claim 1, characterized in that, The main electrode divides the pixel electrode into a first display domain and a second display domain. The first display domain is located on one side of the main electrode, and the second display domain is located on the other side of the main electrode. The first display domain includes a first sub-display domain and a second sub-display domain. The branch electrodes in the first sub-display domain and the second sub-display domain extend in different directions, and there is a first gap between the first sub-display domain and the second sub-display domain. The second display domain includes a third sub-display domain and a fourth sub-display domain. The branch electrodes in the third sub-display domain and the fourth sub-display domain extend in different directions, and there is a second gap between the third sub-display domain and the fourth sub-display domain. The transistor is located below the pixel electrode and is configured corresponding to the first gap and / or the second gap.

6. The array substrate according to any one of claims 1 to 5, characterized in that, In the same column of sub-pixels, any three adjacent sub-pixels constitute a pixel, the three sub-pixels of each pixel are different in color, and the sub-pixels in the same row are the same in color; each data line connects the pixels in the odd-numbered rows of the same column and the pixels in the even-numbered rows of the adjacent column, and each scan line connects the sub-pixels in the same row.

7. The array substrate according to claim 6, characterized in that, In the same row of sub-pixels, the vertical orthographic projection of the pixel electrode of each sub-pixel covers a portion of the vertical orthographic projection of the scan line of the corresponding row, and also covers a portion of the vertical orthographic projection of the scan line of the adjacent row.

8. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 7.

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