Array substrate, test tool, wiring splicing method and liquid crystal display panel

Abstract

This application discloses an array substrate, a testing fixture, a wiring splicing method, and a liquid crystal display panel, including: a test connection line; a first test trace, the first test trace being located at least on one side of the test connection line; a lead, one end of which passes through the first test trace and is electrically connected to the test connection line; and a connecting line, located on the side of the first test trace away from the test connection line; wherein the other end of the lead is electrically connected to the connecting line. The method of this application provides different exposure methods to obtain different traces between array substrates, enabling the connection of multiple array substrates with a large area, solving the problem that different connection locations cannot be exposed in one exposure, thus facilitating the testing of multiple array substrates and improving the production efficiency of the array substrate.

Description

Technical Field

[0001] The embodiments of this application relate to the field of liquid crystal display panel technology, and particularly to an array substrate, a testing fixture, a wiring splicing method, and a liquid crystal display panel. Background Technology

[0002] With the rapid development of LCD technology, the size of LCD displays has also increased significantly. LCD displays incorporate an array substrate, which undergoes numerous tests during manufacturing to ensure it meets requirements. However, the small distance between adjacent array substrates during fabrication makes it difficult to establish connections and facilitate testing between them. Summary of the Invention

[0003] The embodiments of this application provide an array substrate, a test fixture, a wiring splicing method, and a liquid crystal display panel to solve the technical problem in the prior art that it is difficult to connect multiple array substrates and difficult to test the array substrates.

[0004] To address the aforementioned technical problems, embodiments of this application disclose the following technical solutions:

[0005] In a first aspect, an array substrate is provided, comprising:

[0006] Test the connection cable;

[0007] The first test trace is located at least on one side of the test connection line;

[0008] A lead wire, one end of which passes through the first test trace and is electrically connected to the test connection wire;

[0009] A connecting line, wherein the connecting line is located on the side of the first test trace away from the test connecting line;

[0010] The other end of the lead wire is electrically connected to the connecting wire.

[0011] In conjunction with the first aspect, it also includes a second test trace, wherein there is a gap between the first test trace and the connecting line, the second test trace is located in the gap, and the lead wire passes through the second test trace.

[0012] In conjunction with the first aspect, it also includes a third test trace, which is located at least on one side of the test connection line.

[0013] Secondly, an array substrate testing fixture is provided for testing array substrates, including:

[0014] A glass substrate, wherein the array substrate is located on the glass substrate;

[0015] Test connection line, the two ends of which are electrically connected to the adjacent array substrate respectively;

[0016] The array substrate includes a connection line and a first test trace. The first test trace is located at least on one side of the connection line, and the test connection line passes through the first test trace and is electrically connected to the connection line.

[0017] In conjunction with the second aspect, the test connection line includes a first trace and a second trace, one end of the first trace is electrically connected to the connection line, the other end of the first trace is electrically connected to one end of the second trace, and the other end of the second trace is electrically connected to the connection line of the adjacent array substrate.

[0018] In conjunction with the second aspect, both the first trace and the second trace are electrically connected to the connecting line via leads, and the leads pass through the first test trace.

[0019] In conjunction with the second aspect, the connection between the first trace and the second trace has a splicing area.

[0020] Thirdly, a method for splicing traces on an array substrate is provided, for splicing traces on an array substrate, including:

[0021] A first trace is obtained by exposing a first area to a first light source, and one end of the first trace is electrically connected to a connecting line.

[0022] The first light source is shielded by a photomask, and the second area is exposed by the second light source to obtain the second trace. One end of the second trace is electrically connected to another connecting line, and the other end of the second trace is electrically connected to the other end of the first trace.

[0023] The second trace is spliced ​​with the first trace to connect the multiple array substrates.

[0024] In conjunction with the third aspect, when the first trace is obtained by exposure using the first light source, the second light source is turned off; when the second trace is obtained by exposure using the second light source, the first light source is turned on.

[0025] Wherein, when the photomask covers the first area, at least a portion of the first trace is exposed, so that the second trace and the first trace are spliced ​​together.

[0026] Fourthly, a liquid crystal display panel includes an array substrate as described in any one of the first aspects.

[0027] One of the above technical solutions has the following advantages or beneficial effects:

[0028] Compared with the prior art, the array substrate of this application includes: an array substrate comprising: a test connection line; a first test trace, the first test trace being located at least on one side of the test connection line; a lead, one end of the lead passing through the first test trace and electrically connected to the test connection line; and a connecting line located on the side of the first test trace away from the test connection line; wherein the other end of the lead is electrically connected to the connecting line. The array substrate provided by this application facilitates testing during the fabrication process, thus improving the testing efficiency of the array substrate and consequently improving the production efficiency of the array substrate.

[0029] This application discloses a testing fixture for an array substrate, comprising: a glass substrate, with the array substrate located on the glass substrate; and test connection lines, both ends of which are electrically connected to adjacent array substrates. The array substrate includes the connection lines and a first test trace, the first test trace being located at least on one side of the connection lines, and the test connection lines passing through the first test traces and electrically connected to the connection lines. This application facilitates testing of the array substrates on the glass substrate by setting test connection lines between multiple array substrates, thereby improving the testing efficiency of the array substrates and consequently increasing the production efficiency of the array substrates.

[0030] This application discloses a method for splicing traces on an array substrate, comprising: exposing a first region with a first light source to obtain a first trace, one end of which is electrically connected to a connecting line; shielding the first light source with a photomask; exposing a second region with a second light source to obtain a second trace, one end of which is electrically connected to another connecting line, and the other end of which is electrically connected to the other end of the first trace; splicing the second trace with the first trace to connect multiple array substrates. This method provides different exposure methods to obtain different traces between array substrates, enabling the connection of multiple array substrates over a large area. It solves the problem that different connection locations cannot be exposed in a single exposure, thus facilitating testing of multiple array substrates and improving the production efficiency of array substrates. Attached Figure Description

[0031] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0032] Figure 1 This is a schematic diagram of the structure of the array substrate provided in the embodiments of this application;

[0033] Figure 2 This is a schematic diagram of the structure of the array substrate provided in other embodiments of this application;

[0034] Figure 3 This is a schematic diagram of the structure of the test fixture provided in the embodiments of this application;

[0035] Figure 4This is a partial structural schematic diagram of the test fixture provided in an embodiment of this application;

[0036] Figure 5 Examples of this application Figure 4 A magnified schematic diagram of the local structure at point A;

[0037] Figure 6 A schematic diagram of the process steps for the wiring splicing method provided in the embodiments of this application;

[0038] Figure 7 A schematic diagram of the splicing system is provided for the embodiments of this application.

[0039] The attached figures are labeled as follows:

[0040] 100 - Array substrate, 120 - Third test trace, 130 - Lead, 140 - Connector, 150 - Second test trace, 160 - First test trace, 200 - Glass substrate, 230 - Splicing area, 300 - Test connector, 310 - First trace, 320 - Second trace, 400 - First light source, 500 - Photomask, 600 - Second light source. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0042] In exposure processes, it is common to encounter situations where multiple panels need to be interconnected. However, it is impossible to connect them in a single exposure, and multiple exposures can affect components in other areas. Therefore, an efficient and safe interconnection method is needed to connect multiple panels.

[0043] The specific implementation methods of this application are illustrated below through examples:

[0044] like Figure 1 and Figure 2 As shown, this application embodiment provides an array substrate 100, including: a test connection line 300; a first test trace 160, the first test trace 160 being located at least on one side of the test connection line 300; a lead 130, one end of the lead 130 passing through the first test trace 160 and electrically connected to the test connection line 300; and a connecting line 140, the connecting line 140 being located on the side of the first test trace 160 away from the test connection line 300; wherein, the other end of the lead 130 is electrically connected to the connecting line 140. Specifically, the array substrate 100 includes at least two metal structures, upper and lower, each containing a chip. A test connection line 300 is located in the upper metal structure and connects the two chips in the upper and lower layers. A first test trace 160 is located in the lower metal structure and is used for testing the chips in the lower metal structure. The first test trace 160 can be arranged around one or more sides of the chip according to testing needs. A lead 130 is located in the upper metal structure and connects to the chips in the upper structure. The lead 130 must cross the first test trace 160, meaning the first test trace 160 and the lead 130 have overlapping portions but are not connected to each other. A connection line 140 is located in the upper metal structure and connects to the lead 130. The test connection line 300 is connected to the connection line 140 by crossing the first test trace 160 through the lead 130, thus facilitating chip testing.

[0045] like Figure 1 and Figure 2 As shown in the embodiment of this application, a second test trace 150 is also included. A gap exists between the first test trace 160 and the connecting line 140, and the second test trace 150 is located within this gap. A lead 130 passes through the second test trace 150. Specifically, the second test trace 150 is located in the lower metal structure and is connected to the chip or the first test trace 160 for connecting to test equipment when testing the chip.

[0046] like Figure 1 and Figure 2 As shown, in this embodiment, a third test trace 120 is also included, which is located at least on one side of the test connection line 300. Specifically, the third test trace 120 is located in the lower metal structure. The third test trace 120 can be arranged around one or more sides of the chip according to testing needs, or the third test trace 120 can also be arranged on one or more sides of the metal trace 110. The third test trace 120 is connected to the chip or the first test trace 160 and is used to connect to the test equipment when testing the chip.

[0047] like Figures 1 to 5As shown, based on the same inventive concept, this application also provides an array substrate testing fixture, including: a glass substrate 200, with an array substrate 100 located on the glass substrate 200; a test connection line 300, with both ends of the test connection line 300 electrically connected to adjacent array substrates 100; wherein, the array substrate 100 includes a connection line 140 and a first test trace 160, the first test trace 160 being located at least on one side of the connection line 140, and the test connection line 300 passing through the first test trace 160 and electrically connected to the connection line 140. Specifically, as the size of liquid crystal displays increases, the demand for array substrates 100 also increases. In order to improve the yield and pass rate of array substrates 100, it is necessary to test the array substrates 100 after the fabrication is completed. However, since the array substrates 100 are arranged too densely on the glass substrate 200, it is difficult to connect and test multiple array substrates 100. Multiple array substrates 100 are located in different rows of glass substrate 200. The different array substrates 100 are connected by test connection lines 300, realizing communication between different array substrates 100, so as to facilitate testing of array substrates 100.

[0048] like Figures 1 to 5 As shown in this embodiment, the test connection line 300 includes a first trace 310 and a second trace 320. One end of the first trace 310 is electrically connected to the connection line 140, and the other end of the first trace 310 is electrically connected to one end of the second trace 320. The other end of the second trace 320 is electrically connected to the connection line 140 of the adjacent array substrate 100. Specifically, both the first trace 310 and the second trace 320 are metal lines. The glass substrate 200 has a multi-layer metal structure, and the first trace 310 and the second trace 320 can achieve interconnection between different array substrates 100 through different layer structures. Furthermore, detection and phase-matching signals can be transmitted between the array substrates 100 through the first trace 310 and the second trace 320, thereby enabling testing of multiple array substrates 100.

[0049] like Figures 1 to 5As shown in this embodiment, both the first trace 310 and the second trace 320 are electrically connected to the connecting line 140 via a lead 130, which passes through the first test trace 160. Specifically, both the first trace 310 and the second trace 320 are obtained through light source exposure. Due to the presence of the first test trace 160, the first trace 310 and the second trace 320 cannot directly connect to the connecting line 140 through exposure when they are close to it. Therefore, by setting a lead 130 on the test connecting line 300 to cross the first test trace 160, the connection between the first trace 310 and the second trace 320 and the connecting line 140 is achieved. By setting the lead 130, the misconnection of the first trace 310 and the second trace 320 to the first test trace 160 during exposure can be avoided, which would prevent the array substrate 100 from completing the test.

[0050] like Figures 1 to 5 As shown in this embodiment, the connection between the first trace 310 and the second trace 320 has a splicing area 230. Specifically, the first trace 310 and the second trace 320 are obtained through different exposure steps. Therefore, the splicing area 230 is the connection between the first trace 310 and the second trace 320. In the splicing area 230, a portion of the structure of the first trace 310 and the second trace 320 overlaps with each other. The overlapping splicing area 230 strengthens the connection between the first trace 310 and the second trace 320, thereby preventing the connection between the first trace 310 and the second trace 320 from easily breaking or detaching.

[0051] like Figure 6 and Figure 7 As shown in the embodiments of this application, a method for splicing traces on an array substrate includes:

[0052] S1: A first trace 310 is obtained by illuminating a first region with a first light source 400. One end of the first trace 310 is electrically connected to a connecting line 140. Specifically, when exposing the first trace 310 by light, the glass substrate 200 is first divided into a first region and a second region. The glass substrate 200 has multiple array substrates. In order to facilitate the transmission of detection and phase matching signals between multiple array substrates 100, the multiple array substrates 100 need to be connected by metal wires. The multiple array substrates 100 are generally connected by light exposure traces. However, as the size of liquid crystal displays becomes larger and larger, ordinary exposure connection methods can no longer cover multiple array substrates 100. Therefore, the glass substrate 200 is divided into at least a first region and a second region, and different operations are performed on the two regions to avoid the situation where the glass substrate 200 is too large and cannot be covered by exposure. It should be noted that before exposure, a lead 130 is led outward from the in-plane of one of the array substrates 100. During exposure, firstly, the first region is illuminated by the first light source 400, thereby exposing the area near the array substrate 100 in the first region to obtain the first trace 310. It is important to note that the endpoints of the first trace 310 are connected to the endpoints of the lead 130, thus enabling the first trace 310 to be connected to the plane of the array substrate 100 via the lead 130. To control the traces in the first region, the light sources illuminating other regions are turned off, leaving only the first light source 400 covering a portion of the first region. The area and number of first light sources illuminating the first region are not fixed and can be adjusted according to the size and range of the first region. When the first region is large, the number of first light sources 400 can be increased or the illumination range expanded; when the first region is small, the number of first light sources 400 can be appropriately reduced or the illumination range narrowed, thereby reducing unnecessary resource waste and minimizing the impact on other regions.

[0053] In some other embodiments of this application, the glass substrate 200 may be divided into more regions, such as three, four or five regions, and the panels in each region may be connected using the same or different exposure methods, thereby achieving the effect of connecting the panels in each region.

[0054] S2: A photomask 500 is used to shield the first light source 400, and the second region is exposed by the second light source 600 to obtain the second trace 320. One end of the second trace 320 is electrically connected to the connection line 140 of another array substrate 100, and the other end of the second trace 320 is electrically connected to the other end of the first trace 310. Specifically, after the first region and the second region are divided, the second light source 600 is used to irradiate the second region in order to expose the second trace 320 in the second region. In order to avoid affecting the first trace 310 that has already been exposed in the first region, a photomask can be used to shield the first light source 400, thereby avoiding any impact on the first region when irradiating the second region. In some other embodiments of this application, a photomask 500 can also be used to cover the first region, thereby isolating the first region from the first light source 400 and the second light source 600. Understandably, in order to achieve the splicing of the second trace 320 and the first trace 310, when the photomask 500 blocks the first area, at least a portion of the first trace 310 needs to be exposed. This allows the second trace 320 to extend along the exposed portion of the first trace 310 when the second trace 320 is exposed, serving both a guiding function and enabling the connection between the second trace 320 and the first trace 310.

[0055] S3: The second trace 320 is spliced ​​with the first trace 310 to connect multiple array substrates 100. Specifically, by splicing the second trace 320 and the first trace 310, multiple array substrates 100 are connected, which facilitates testing of multiple array substrates 100. Through testing, it is possible to know in advance whether the array substrate 100 is damaged, thereby improving the yield of the array substrate 100 and improving the fabrication efficiency of the array substrate 100.

[0056] like Figure 6 and Figure 7As shown in this embodiment, when the first light source 400 exposes to obtain the first trace 310, the second light source 600 is turned off; when the second light source 600 exposes to obtain the second trace 320, the first light source 400 is turned on; wherein, when the photomask 500 shields the first area, at least a portion of the first trace 310 is exposed, so that the second trace 320 and the first trace 310 are spliced ​​together. It can be understood that the second light source 600 is the portion of the light source that is turned off when illuminating the first area. When illuminating the second area, the state of the first light source 400 does not need to be controlled. Therefore, to obtain a larger illumination range, the first light source 400 can be fully turned on, and combined with the illumination range of the second light source 600, a larger illumination range can be obtained, thereby illuminating the entire second area. In some other embodiments of this application, only the second light source 600 or only the first light source 400 can be used to illuminate the second area, depending on the distribution of the first and second areas.

[0057] In this embodiment, to connect the first trace 310 and the second trace 320, the connection end of the first trace 310 needs to be exposed when exposing the second trace 320. This results in a portion of the first region being irradiated twice during the irradiation of the second region, i.e., a portion of the region is an overlapping irradiated area. Generally, the overlapping irradiated area is the splicing area 230 of the first trace 310 and the second trace 320. Forming the splicing area 230 can strengthen the connection between the first trace 310 and the second trace 320, preventing breakage or poor contact between the first trace 310 and the second trace 320.

[0058] In this embodiment, both the first light source 400 and the second light source 600 are parallel lights. Parallel light ensures more uniform illumination across all areas during exposure, preventing uneven lighting in some areas from causing varying exposure speeds. Although some edge areas may be overexposed due to light diffraction, dividing the area into zones can prevent important parts from being overexposed, thus avoiding the negative effects of overexposure.

[0059] like Figure 7As shown, based on the same inventive concept, this application also provides a wiring splicing system, including: a first light source 400 and a second light source 600, the first light source 400 and the second light source 600 being arranged side-by-side in sections; a photomask 500, the photomask 500 being adjustablely disposed below the first light source 400 or the second light source 600; and a switch module, the switch module being connected to the first light source 400 and the second light source 600, used to control the on / off state of the first light source 400 and the second light source 600. It can be understood that the wiring splicing system is a corresponding device capable of implementing a wiring splicing method, including the first light source 400 and the second light source 600 disposed on an integrated component. The first light source 400 and the second light source 600 modules originally belonged to the same component, but in this application, they are divided into different functional roles. Simultaneously, the photomask 500 is disposed below the first light source 400 and the second light source 600. The photomask 500 can be rotated as needed to block light. When the first light source 400 needs to be blocked, the photomask 500 can be rotated to be below the first light source 400 to block it. When the second light source 600 needs to be blocked, the photomask 500 can be rotated to be below the second light source 600 to block it. Simultaneously, the photomask 500 can also be adjusted according to the area to be blocked, thereby satisfying the blocking requirements for the corresponding area. In this embodiment, the switch module is used for controlling the on / off state of the first light source 400 and the second light source 600. Each light source has an individual switch control, facilitating the design of the illumination intensity and range of the illuminated area.

[0060] Based on the same inventive concept, embodiments of this application also provide a liquid crystal display panel, including an array substrate as provided in any of the above claims.

[0061] The above provides a detailed description of an array substrate, testing fixture, wiring splicing method, and liquid crystal display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, characterized in that, include: An upper metal structure and a lower metal structure, both of which contain chips; The test connection line (300) is located in the upper metal structure and is used to connect the chip in the upper metal structure and the chip in the lower metal structure. The first test trace (160) is located in the lower metal structure, and the first test trace (160) is located at least on one side of the test connection line (300); The lead wire (130) is located in the upper metal structure. One end of the lead wire (130) passes through the first test trace (160) and is electrically connected to the test connection line (300). The lead wire (130) and the first test trace (160) have an overlapping portion but are not connected to each other. The connecting line (140) is located in the upper metal structure, and the connecting line (140) is located on the side of the first test trace (160) away from the test connecting line (300); The other end of the lead (130) is electrically connected to the connecting line (140), and the test connecting line (300) is connected to the connecting line (140) by crossing the first test trace (160) through the lead (130) to test the chip.

2. The array substrate as described in claim 1, characterized in that, It also includes a second test trace (150), with a gap between the first test trace (160) and the connecting line (140), the second test trace (150) being located in the gap, and the lead wire (130) passing through the second test trace (150).

3. The array substrate as described in claim 1, characterized in that, It also includes a third test trace (120), which is located at least on one side of the test connection line (300).

4. An array substrate testing fixture for testing the array substrate (100) as described in any one of claims 1 to 3, characterized in that, include: A glass substrate (200), on which the array substrate (100) is located; Test connection line (300), the two ends of which are electrically connected to the adjacent array substrate (100); The array substrate (100) includes a connection line (140) and a first test trace (160). The first test trace (160) is located at least on one side of the connection line (140). The test connection line (300) passes through the first test trace (160) and is electrically connected to the connection line (140).

5. The array substrate testing fixture as described in claim 4, characterized in that, The test connection line (300) includes a first trace (310) and a second trace (320). One end of the first trace (310) is electrically connected to the connection line (140), and the other end of the first trace (310) is electrically connected to one end of the second trace (320). The other end of the second trace (320) is electrically connected to the connection line (140) of the adjacent array substrate (100).

6. The array substrate testing fixture as described in claim 5, characterized in that, The first trace (310) and the second trace (320) are both electrically connected to the connecting line (140) via a lead (130), and the lead (130) passes through the first test trace (160).

7. The array substrate testing fixture as described in claim 5, characterized in that, The connection between the first trace (310) and the second trace (320) has a splicing area (230).

8. A method for splicing traces on an array substrate, used for splicing traces on an array substrate (100) as described in any one of claims 1 to 3, characterized in that, include: The first trace (310) is obtained by exposing the first area by the first light source (400), and one end of the first trace (310) is electrically connected to the connecting line (140); The first light source (400) is shielded by a photomask (500), and the second area is exposed by the second light source (600) to obtain the second trace (320). One end of the second trace (320) is electrically connected to another connecting line (140), and the other end of the second trace (320) is electrically connected to the other end of the first trace (310). The second trace (320) is spliced ​​with the first trace (310) to connect the plurality of array substrates (100).

9. The wiring splicing method as described in claim 8, characterized in that, When the first trace (310) is obtained by exposure using the first light source (400), the second light source (600) is turned off; when the second trace (320) is obtained by exposure using the second light source (600), the first light source (400) is turned on. When the photomask (500) covers the first area, at least a portion of the first trace (310) is exposed so that the second trace (320) and the first trace (310) are spliced ​​together.

10. A liquid crystal display panel, characterized in that, Includes the array substrate as described in any one of claims 1-3.

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