A wiring layout photoetching process window optimization method, device, equipment and medium

Abstract

The application provides a wiring layout photoetching process window optimization method, device, equipment and medium, input a first version picture segment into a Transformer encoder model, output position information of a target sub-region in the first version picture segment and a first process window evaluation parameter corresponding to the first version picture segment; the target sub-region includes a first pattern; the first process window evaluation parameter is less than a preset parameter; the first pattern is optimized by using a back propagation algorithm and a post-processing algorithm to obtain a second pattern; the second pattern is input into a transposed convolution network to obtain a third pattern; the target sub-region in a second version picture segment includes the third pattern; a second process window evaluation parameter corresponding to the second version picture segment is greater than the first process window evaluation parameter. The process window evaluation parameter can be improved, the effect of expanding the process window is realized, and the manufacturability of the layout is improved, which is convenient for chip manufacturing.

Description

Technical Field

[0001] This application relates to the semiconductor field, and in particular to a method, apparatus, equipment, and medium for optimizing the window of a wiring layout photolithography process. Background Technology

[0002] Among the many manufacturing processes for integrated circuits, photolithography is the most critical. The photolithography process is responsible for transforming the design board... Figure 1 Layer by layer, the pattern is fabricated onto the wafer. The advancement of integrated circuit technology nodes requires the density of patterns on the layout to double every eighteen months to two years (Moore's Law), and it is the development of photolithography technology that supports this increase in layout density. However, due to the existence of light diffraction and interference phenomena, the actual pattern transferred to the wafer is not exactly the same as the designed layout, resulting in a certain error and affecting the accuracy of imaging. In addition, the photolithography system also experiences defocusing during actual operation, meaning that the focusing plane does not completely overlap with the wafer surface; defocusing also affects the quality of photolithographic imaging. These are all key factors affecting the manufacturability of the design, resulting in a relatively small photolithography process window (PW).

[0003] If manufacturability is improved solely through process modifications, the improvement becomes less noticeable as process nodes shrink. In such cases, while manufacturers improve processes, designers also need to consider manufacturing issues during the design phase and create a layout that is easy to manufacture based on the specific requirements of the process.

[0004] In other words, as technology nodes continue to shrink and process complexity increases, certain areas of the layout may experience insufficient lithography process windows, and some areas may even become hotspots, which can significantly impact the manufacturability of the layout. Therefore, providing a method for optimizing the lithography process windows of wiring layouts has become an urgent technical problem to be solved. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a method, apparatus, equipment, and medium for optimizing the photolithography process window of a wiring layout. This method can improve the evaluation parameters of the process window, thereby expanding the process window and improving the manufacturability of the layout, thus facilitating chip fabrication. The specific solution is as follows:

[0006] On the one hand, this application provides a method for optimizing the photolithography process window of the wiring layout, including:

[0007] The first image segment is input into the Transformer encoder model, and the location information of the target sub-region in the first image segment and the first process window evaluation parameters corresponding to the first image segment are output; the target sub-region includes the first pattern; the first process window evaluation parameters are less than preset parameters;

[0008] The process window is optimized using the backpropagation algorithm and post-processing algorithm on the first pattern to obtain the second pattern;

[0009] The second pattern is input into the transposed convolutional network to obtain the third pattern; the target sub-region in the second version of the image segment includes the third pattern; the evaluation parameter of the second process window corresponding to the second version of the image segment is greater than the evaluation parameter of the first process window.

[0010] In another aspect, embodiments of this application also provide a wiring layout photolithography process window optimization apparatus, comprising:

[0011] The determining unit is used to input the first version of the image segment into the Transformer encoder model, output the position information of the target sub-region in the first version of the image segment, and the first process window evaluation parameters corresponding to the first version of the image segment; the target sub-region includes a first pattern; the first process window evaluation parameters are less than preset parameters;

[0012] An optimization unit is used to optimize the process window of the first pattern using a backpropagation algorithm and a post-processing algorithm to obtain a second pattern.

[0013] The output unit is used to input the second pattern into the transposed convolutional network to obtain the third pattern; the target sub-region in the second image segment includes the third pattern; the second process window evaluation parameter corresponding to the second image segment is greater than the first process window evaluation parameter.

[0014] In another aspect, embodiments of this application provide a computer device, the computer device including a processor and a memory:

[0015] The memory is used to store program code and transmit the program code to the processor;

[0016] The processor is used to execute the methods described above according to the instructions in the program code.

[0017] In another aspect, embodiments of this application provide a computer-readable storage medium for storing a computer program for performing the methods described above.

[0018] This application provides a method, apparatus, device, and medium for optimizing the lithography process window of a wiring layout. A first image segment is input into a Transformer encoder model, which outputs the location information of a target sub-region within the first image segment, as well as the first process window evaluation parameters corresponding to the first image segment. The target sub-region includes a first pattern. The first process window evaluation parameters are less than preset parameters. The first pattern is optimized using a backpropagation algorithm and a post-processing algorithm to obtain a second pattern. The second pattern is input into a transposed convolutional network to obtain a third pattern. The target sub-region in the second image segment includes the third pattern. The second process window evaluation parameters corresponding to the second image segment are greater than the first process window evaluation parameters. In this embodiment, the Transformer encoder model can be used to identify the target sub-region that needs to be optimized for the lithography process window. The first pattern in the target sub-region is processed. The backpropagation algorithm can enhance the optimization space, accelerate the optimization process, and improve the process window evaluation parameters. The post-processing algorithm can further optimize the first pattern. The process window of the resulting second pattern is larger. The image size can be restored through the transposed convolutional network to obtain the third pattern. Compared with the first pattern, the third pattern can improve the process window evaluation parameters, thereby expanding the process window and improving the manufacturability of the layout, which is convenient for chip manufacturing. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This paper illustrates a flowchart of a wiring layout photolithography process window optimization method provided in an embodiment of this application.

[0021] Figure 2 A schematic diagram of a photolithography process window provided in an embodiment of this application is shown;

[0022] Figure 3 This paper illustrates a flowchart of another wiring layout photolithography process window optimization method provided in an embodiment of this application;

[0023] Figure 4 This illustration shows a schematic diagram of a model architecture provided in an embodiment of this application;

[0024] Figure 5 This illustration shows a schematic diagram of a pattern in a page segment provided in an embodiment of this application;

[0025] Figure 6 A schematic diagram of a PWE algorithm provided in an embodiment of this application is shown;

[0026] Figure 7 A structural block diagram of a wiring layout photolithography process window optimization device provided in this application embodiment;

[0027] Figure 8 This is a structural diagram of a computer device provided in an embodiment of this application. Detailed Implementation

[0028] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0029] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0030] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0031] For ease of understanding, the following detailed description, in conjunction with the accompanying drawings, provides a method, apparatus, equipment, and medium for optimizing the lithography process window of a wiring layout according to an embodiment of this application.

[0032] refer to Figure 1 The diagram shown is a flowchart illustrating a wiring layout photolithography process window optimization method provided in an embodiment of this application. The method may include the following steps.

[0033] S101, input the first version of the image segment into the Transformer encoder model, and output the location information of the target sub-region in the first version of the image segment, as well as the evaluation parameters of the first process window corresponding to the first version of the image segment.

[0034] Specifically, the digital circuit design process of a chip includes several stages: logic design, layout design, mask design, and manufacturing. Traditionally, optimization can be performed during the mask design stage by employing techniques such as Optical Proximity Correction (OPC) and Subresolution Assist Feature (SRAF) to improve manufacturability. However, since the placement and routing layout is already determined at this design stage, the optimization space is very limited. The solution provided in this application is applied to the layout design stage, that is, it provides a layout optimization architecture for photolithography window enlargement (PWE) in the post-routing stage, which can optimize photolithography printability and improve manufacturability in the early design stage.

[0035] In this embodiment of the application, the first image segment can be a part of the layout. The first image segment has a corresponding first process window evaluation parameter, which is used to evaluate the size of the process window. The process window will be briefly described below.

[0036] In projection lithography systems, for a given feature size, the range of deviations from the optimal focal plane that allows for maintaining line quality is defined as the depth of focus (DOF). For lithography processes, a larger DOF is more favorable for exposing the lithographic pattern. The relationship between DOF and exposure wavelength and the numerical aperture of the projection lens is as follows:

[0037]

[0038] In the formula, k2 is the depth-of-focus process factor. As the position of the focal plane changes, the quality of the exposure lines also changes. Thus, there must exist a position with the best exposure line quality, which is called the optimal focal plane. The value by which the actual imaging plane deviates from the optimal focal plane is called the defocusing amount.

[0039] In other words, depth of focus is the range within which the imaging position is allowed to deviate from the optimal focal plane position, while defocus is the range within which the actual imaging position deviates from the optimal focal plane position.

[0040] The purpose of photolithography is to copy the pattern on the photomask into a photoresist of a certain thickness. In order to obtain lines with steep sidewalls, the imaging intensity should be as consistent as possible within the thickness range of the photoresist. This requires that the depth of focus of projection lithography be greater than the thickness of the photoresist.

[0041] Relating to the formula for lithographic resolution, the expression for depth of focus can be rewritten as:

[0042]

[0043] The feature size CD of a photolithographic pattern fluctuates significantly with variations in exposure dose and defocusing amount. In actual photolithography processes, the electrical performance of integrated circuit chips allows for a certain degree of error in the feature size of the photolithographic pattern; this permissible error range is typically ±10% CD. Based on this standard, points meeting the conditions can be plotted on the Poisson curve of the photolithographic image, and connecting these points yields the following result: Figure 2 The process window shown.

[0044] Figure 2 The portion of the curve shown that allows for the largest possible rectangular or elliptical enclosed area is called the process window. Elliptical process windows are generally used in photolithography, where only the largest possible ellipse can be obtained within the closed area. It should be noted that the rectangles or circles shown in the figure are drawn within a closed area formed by two curves, representing the exposure dose at different focal plane positions, satisfying both CD(1+10%) and CD(1-10%) conditions.

[0045] In practical photolithography processes, the standard for measuring the process window is generally the depth of focus (DOF) value when the exposure dose varies by 5% (i.e., the Y-axis length of the ellipse is fixed, and the X-axis length of the ellipse is measured). A larger DOF value indicates a larger process window; therefore, the first evaluation parameter for the process window can be the depth of focus (DOF). Alternatively, a fixed depth of focus range can be used, and the size of the process window can be measured by the exposure dose; in this case, the first evaluation parameter for the process window can also be the exposure dose. For ease of description, the following examples use the DOF value to measure the size of the process window; that is, the first evaluation parameter for the process window is the depth of focus (DOF).

[0046] Since actual processes have a certain degree of instability, such as fluctuations in exposure energy and focus value in lithography machines, the lithography process must provide linewidth values ​​that meet the requirements within this range of variation. To solve this problem, it is essential to analyze the process window of the layout.

[0047] In this embodiment, a first version of the image segment can be input into the Transformer encoder model. The first version of the image segment includes multiple sub-regions. The sub-region that needs to be optimized is defined as the target sub-region. The model can output the location information of the target sub-region and the first process window evaluation parameter. The location information of the target sub-region can indicate the specific location of the target sub-region in the first version of the image segment. The target sub-region includes a first pattern. The first process window evaluation parameter is the process window evaluation parameter corresponding to the first version of the image segment. If the first process window evaluation parameter is less than a preset parameter, it indicates that the first version of the image segment needs to be optimized by the process window.

[0048] In practical applications, the first image segment can be evaluated and modeled. In the evaluation and modeling step, the Transformer encoder model can be used for fast PW evaluation. Then, the lithography process window expansion algorithm can be used for processing. Specifically, two algorithms are used to improve the process window evaluation parameters. Then, restoration modeling is performed, and the optimal solution obtained by the algorithm optimization is restored using transposed convolution, thereby restoring it to the original layout image.

[0049] Specifically, the Transformer encoder model has shown great superiority in many sequence-to-sequence tasks. Due to the diversity of two-dimensional shapes in the layout, there is a large optimization space for layout modification, which can be handled by the Transformer-based Vision (ViT) method.

[0050] refer to Figure 3 The diagram shown illustrates a flowchart of another wiring layout photolithography process window optimization method provided in this application embodiment, including evaluation modeling, PWE algorithm processing, and restoration modeling processing. (See reference...) Figure 4 The diagram shown is a schematic of a model architecture provided in an embodiment of this application, including information such as the input, output, kernel, and step size of each layer.

[0051] Specifically, the first image clip, or original image clip, can be input into the Transformer encoder model. First, image encoding (Patch Embedding) processing is performed, which extracts important image features from the first image clip. This part includes Conv1 convolutional layers, Flatten1 smoothing layers, and Linear1 fully connected layers. The Conv1 convolutional layer can extract image features, the Flatten1 smoothing layer can convert the multidimensional data output by the Conv1 convolutional layer into one-dimensional data, and the Linear1 fully connected layer can perform linear transformation processing.

[0052] Next, positional embedding can be performed to add positional information to the image-encoded data so that the positional information of the specific region affecting the DOF value, i.e., the target sub-region, can be determined later.

[0053] The data after location information encoding is input into the Transformer Encoder. As the core mechanism of Transformer, it avoids the traditional convolution structure and creatively utilizes the attention mechanism based on linear operation and parallel processing methods, enabling the framework's prediction model to uniformly process global information. After processing by the Transformer Encoder, the first version of the image segment's encoded information matrix can be obtained.

[0054] Then, the data is input into a multilayer perceptron (MLP) for processing. The MLP can calculate the attention score of each sub-region in the first image segment. The attention score measures the influence of the sub-region on the process window evaluation parameters of the first image segment. The sub-region with the highest attention score can be selected as the target sub-region, and subsequent optimization processes focus on this target sub-region to determine the PW (Power Window) used for the optically sensitive layout, without the need for extensive mathematical modeling on the first image segment to identify the regions that need optimization. The output includes two values: Resultpos, which represents the location information of the region with the highest attention score, i.e., the location information of the target sub-region; and ResultDOF, which represents the first process window evaluation parameter corresponding to the first image segment, such as the DOF value corresponding to the first image segment.

[0055] S102, the process window is optimized using the backpropagation algorithm and post-processing algorithm for the first pattern to obtain the second pattern.

[0056] In this embodiment of the application, the process window can be optimized using the PWE algorithm for the first pattern. The PWE algorithm includes a backpropagation algorithm and a post-processing algorithm. The backpropagation algorithm can expand the process window, and the post-processing algorithm can further optimize the shape and position of the pattern, determine whether the design rule check (DRC) is satisfied, perform connectivity verification, and determine whether the pixels in the pattern are retained.

[0057] Specifically, design rule checks can include minimum spacing checks, minimum critical dimension checks, etc. For example, optimized line segments should not overlap with other line segments to meet the minimum spacing requirements of the DRC rules. If line segments in the second pattern separate, it is necessary to use post-processing techniques to extend them until they are reconnected, thereby ensuring that there are no open circuits. Connectivity checks mean that if the first pattern includes vias, the second pattern should also include vias to constrain the optimization space. Conversely, if the second pattern does not contain vias, the optimization is invalid.

[0058] Specifically, if the DRC and connectivity checks pass, the map area is further processed. The post-processing algorithm can also determine whether the pixels in the pattern should be retained, and check the surrounding 3×3 pixels with the pixel as the center.

[0059] Specifically, the optimized first pattern can be denoted as the second pattern. After the process window is optimized, the process window evaluation parameter corresponding to the first version of the second image is greater than the first process window evaluation parameter.

[0060] In this embodiment of the application, S102 may specifically include the following steps.

[0061] S1021-S1022 can be executed cyclically until the optimal solution for horizontal scan line segmentation is determined. The optimal solution corresponds to the largest process window evaluation parameter. S1023-S1024 can be executed cyclically until the optimal solution for vertical scan line segmentation is determined. Then, the two optimal solutions can be compared, and the optimized solution with the largest process window evaluation parameter is determined to optimize the first pattern to obtain the second pattern.

[0062] S1021, the first pattern is divided using horizontal scan lines to obtain the fourth pattern.

[0063] In this embodiment, the first pattern can be segmented using horizontal scan lines, prioritizing the extraction of horizontal line segments (rectangles) to cover vertical line segments, resulting in a fourth pattern. This facilitates effective processing of polygonal shapes in the first pattern. (Refer to...) Figure 5 As shown in (b), this is for... Figure 5 (a) is obtained by horizontal scan line segmentation.

[0064] S1022, the process window is optimized for the fourth pattern using the backpropagation algorithm and the post-processing algorithm to obtain the fifth pattern.

[0065] Specifically, after scan line segmentation, the fourth pattern can be optimized using backpropagation and post-processing algorithms. By moving horizontal lines to change the shape of the first pattern, the process window is expanded to obtain the fifth pattern. The third image segment composed of the fifth pattern has third process window evaluation parameters.

[0066] In one possible implementation, the fourth pattern can be processed by expanding the process window using a backpropagation algorithm to obtain the eighth pattern. Then, the eighth pattern can be optimized using a post-processing algorithm to obtain the fifth pattern.

[0067] In this embodiment, when determining whether to retain a pixel in a pattern, the post-processing algorithm can check a 3×3 pixel circle around the pixel. Specifically, the eighth pattern may include a first pixel, and pixels adjacent to the first pixel are designated as second pixels. There can be a maximum of eight second pixels, i.e., eight pixels surrounding the first pixel. The eighth pattern is then optimized using the post-processing algorithm to obtain a fifth pattern. Specifically, if the pixel value of multiple second pixels is 255, and at least one second pixel is connected to the first pixel, then the first pixel is retained in the fifth pattern; otherwise, the first pixel is deleted from the fifth pattern.

[0068] Specifically, if the pixel value of the second pixel is 255, it means that the pixel is black. When multiple second pixels are black, it means that there is a pattern around the first pixel. If the black second pixel and the first pixel are adjacent in the horizontal or vertical direction, it is considered that the second pixel and the first pixel are connected. That is to say, if the black second pixel and the first pixel are adjacent in the diagonal direction, it is considered that the second pixel and the first pixel are not connected.

[0069] In this way, if multiple second pixels around the first pixel are black, and at least one second pixel is connected to the first pixel in the horizontal or vertical direction, then the first pixel is not an isolated pixel and can be retained. Otherwise, the first pixel is an isolated pixel and needs to be deleted.

[0070] S1023, the first pattern is divided using vertical scan lines to obtain the sixth pattern.

[0071] Specifically, the first pattern can be segmented using vertical scan lines, prioritizing the extraction of vertical line segments. The vertical line segment rectangles can partially cover the horizontal line segments, resulting in the sixth pattern. (Refer to...) Figure 5 (c) in the middle.

[0072] S1024, the process window of the sixth pattern is optimized using the backpropagation algorithm and the post-processing algorithm to obtain the seventh pattern; the fourth version of the image segment composed of the seventh pattern has the fourth process window evaluation parameters.

[0073] Specifically, the sixth pattern can be processed using the backpropagation algorithm to expand the process window, followed by post-processing to obtain the seventh pattern. The fourth version of the image segment composed of the seventh pattern has the fourth process window evaluation parameters.

[0074] S1025, if the evaluation parameter of the third process window is greater than the evaluation parameter of the fourth process window, then the fifth pattern is used as the second pattern; otherwise, the seventh pattern is used as the second pattern.

[0075] Specifically, the evaluation parameters of the process windows under the two segmentation methods can be compared, and the pattern corresponding to the larger value can be selected as the second pattern. That is, if the evaluation parameter of the third process window is greater than the evaluation parameter of the fourth process window, the fifth pattern is selected as the second pattern; otherwise, the seventh pattern is selected as the second pattern, thus obtaining the optimized second pattern.

[0076] refer to Figure 6 The diagram shown is a schematic of a PWE algorithm provided in an embodiment of this application. F represents the output generated by the lithography model to approximate the actual DOF. S represents the layout scheme of moving a portion of the line segment rectangle in the original layout. The moved layout pattern must satisfy the routing rules in the physical design stage. Ω represents the set of all possible S. Next, we can... Figure 6 A brief explanation is provided.

[0077] 1: S←Original map X

[0078] 2: Preprocess the original layout X by dividing the layout using horizontal scan lines to obtain the processed layout Xhor.

[0079] 3: Execute the following loop (the purpose is to find the optimal solution S):

[0080] 4: Perform backpropagation algorithm on the layout Xi after scan line segmentation to obtain layout Xi'.

[0081] 5: Perform a post-processing algorithm on layout Xi' to obtain layout Xi''.

[0082] 6-11: Determine if the DOF value of layout Xi” is greater than the DOF value of the layout in the previous scheme. If the DOF value of layout Xi” is greater, then layout Xi” is selected as the optimized scheme; otherwise, return to step 3 and determine the next scheme S.

[0083] 12: Original map X ← Optimized solution S (maximum DOF value)

[0084] 13: Preprocess the original layout X by dividing the layout using vertical scan lines to obtain the processed layout Xver.

[0085] 14: Repeat 3-12

[0086] 15: Optimal Solution S max ←Original map X

[0087] In other words, the original map is divided into horizontal and vertical scan lines to find all possible movement schemes S. Then, the algorithm iterates through all schemes S, performs backpropagation and post-processing on S, and selects the optimal scheme S with the highest DOF value.max .

[0088] S103, the second pattern is input into the transposed convolutional network to obtain the third pattern; the target sub-region in the second image segment includes the third pattern; the evaluation parameters of the second process window corresponding to the second image segment are greater than the evaluation parameters of the first process window.

[0089] In this embodiment of the application, the second pattern can be input into the transposed convolutional network. The transposed convolutional network can rescale the matrix obtained from the PWE algorithm to restore the original image size, thereby generating an image that is very similar to the actual layout after deconvolution, i.e., obtaining the third pattern.

[0090] The image segment composed of the third pattern is designated as the second image segment. The evaluation parameter of the second process window corresponding to the second image segment is greater than that of the first process window, thus achieving process window optimization. Furthermore, since both the input and output images are single-channel images, single-channel normalization must be performed before final resizing. If a single-channel value exceeds a certain threshold, it is set to 255; otherwise, it is erased.

[0091] By using the Transformer encoder model to identify the target sub-region that needs to be optimized for the lithography process window, the first pattern in the target sub-region is processed. The backpropagation algorithm can enhance the optimization space, accelerate the optimization process, and improve the process window evaluation parameters. The post-processing algorithm can further optimize the first pattern, resulting in a second pattern with a larger process window. The image size can be restored through a transposed convolutional network to obtain a third pattern. Compared with the first pattern, the third pattern can improve the process window evaluation parameters, thereby expanding the process window and improving the manufacturability of the layout, which facilitates chip manufacturing.

[0092] This application provides a method for optimizing the lithography process window of a wiring layout. A first image segment is input into a Transformer encoder model, which outputs the location information of the target sub-region in the first image segment and the first process window evaluation parameters corresponding to the first image segment. The target sub-region includes a first pattern. The first process window evaluation parameters are less than preset parameters. The first pattern is optimized using a backpropagation algorithm and a post-processing algorithm to obtain a second pattern. The second pattern is input into a transposed convolutional network to obtain a third pattern. The target sub-region in the second image segment includes the third pattern. The second process window evaluation parameters corresponding to the second image segment are greater than the first process window evaluation parameters. In this embodiment, the Transformer encoder model can be used to identify the target sub-region that needs to be optimized for the lithography process window. The first pattern in the target sub-region is processed. The backpropagation algorithm can enhance the optimization space, accelerate the optimization process, and improve the process window evaluation parameters. The post-processing algorithm can further optimize the first pattern. The process window of the resulting second pattern is larger. The image size can be restored through the transposed convolutional network to obtain the third pattern. Compared with the first pattern, the third pattern can improve the process window evaluation parameters, thereby expanding the process window and improving the manufacturability of the layout, which is convenient for chip manufacturing.

[0093] Based on the above-described wiring layout lithography process window optimization method, this application embodiment also provides a wiring layout lithography process window optimization apparatus, referencing... Figure 7 The diagram shown is a structural block diagram of a wiring layout photolithography process window optimization device provided in an embodiment of this application. The device may include:

[0094] The determining unit 201 is used to input the first version of the image segment into the Transformer encoder model, output the position information of the target sub-region in the first version of the image segment, and the first process window evaluation parameter corresponding to the first version of the image segment; the target sub-region includes a first pattern; the first process window evaluation parameter is less than a preset parameter;

[0095] Optimization unit 202 is used to optimize the process window of the first pattern using a backpropagation algorithm and a post-processing algorithm to obtain a second pattern;

[0096] Output unit 203 is used to input the second pattern into a transposed convolutional network to obtain a third pattern; the target sub-region in the second image segment includes the third pattern; the second process window evaluation parameter corresponding to the second image segment is greater than the first process window evaluation parameter.

[0097] Specifically, the optimization unit is used for:

[0098] The first pattern is divided using horizontal scan lines to obtain a fourth pattern;

[0099] The process window of the fourth pattern is optimized using the backpropagation algorithm and the post-processing algorithm to obtain the fifth pattern; the third image segment composed of the fifth pattern has the third process window evaluation parameters;

[0100] The first pattern is divided using vertical scan lines to obtain the sixth pattern;

[0101] The process window of the sixth pattern is optimized using the backpropagation algorithm and the post-processing algorithm to obtain the seventh pattern; the fourth image segment composed of the seventh pattern has the fourth process window evaluation parameters.

[0102] If the evaluation parameter of the third process window is greater than the evaluation parameter of the fourth process window, then the fifth pattern is used as the second pattern; otherwise, the seventh pattern is used as the second pattern.

[0103] Specifically, the optimization unit is used for:

[0104] The process window of the fourth pattern is expanded using the backpropagation algorithm to obtain the eighth pattern;

[0105] The eighth pattern is optimized using the post-processing algorithm to obtain the fifth pattern.

[0106] Specifically, the eighth pattern includes a first pixel and a plurality of second pixels adjacent to the first pixel, and the optimization unit is used for:

[0107] If the pixel value of multiple second pixels is 255, and at least one second pixel is connected to the first pixel, then the first pixel is retained in the fifth pattern; otherwise, the first pixel is deleted from the fifth pattern.

[0108] Specifically, the evaluation parameters for the first process window include depth of focus or exposure dose.

[0109] This application provides a wiring layout photolithography process window optimization device. A first image segment is input into a Transformer encoder model, which outputs the location information of a target sub-region in the first image segment and the first process window evaluation parameters corresponding to the first image segment. The target sub-region includes a first pattern. The first process window evaluation parameters are less than preset parameters. The first pattern is optimized using a backpropagation algorithm and a post-processing algorithm to obtain a second pattern. The second pattern is input into a transposed convolutional network to obtain a third pattern. The target sub-region in the second image segment includes the third pattern. The second process window evaluation parameters corresponding to the second image segment are greater than the first process window evaluation parameters. In this embodiment, the Transformer encoder model can be used to identify the target sub-region that needs to be optimized for the lithography process window. The first pattern in the target sub-region is processed. The backpropagation algorithm can enhance the optimization space, accelerate the optimization process, and improve the process window evaluation parameters. The post-processing algorithm can further optimize the first pattern. The process window of the resulting second pattern is larger. The image size can be restored through the transposed convolutional network to obtain the third pattern. Compared with the first pattern, the third pattern can improve the process window evaluation parameters, thereby expanding the process window and improving the manufacturability of the layout, which is convenient for chip manufacturing.

[0110] In another aspect, embodiments of this application provide a computer device, with reference to Figure 8 The diagram shown is a structural diagram of a computer device provided in an embodiment of this application. The computer device includes a processor 310 and a memory 320.

[0111] The memory 320 is used to store program code and transmit the program code to the processor 310;

[0112] The processor 310 is used to execute the method provided in the above embodiments according to the instructions in the program code.

[0113] The computer device may include a terminal device or a server, and the aforementioned apparatus may be configured in the computer device.

[0114] In another aspect, embodiments of this application also provide a storage medium for storing a computer program for executing the methods provided in the above embodiments.

[0115] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by program instructions in hardware. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium can be at least one of the following media: read-only memory (ROM), RAM, magnetic disk, or optical disk, etc., and other media capable of storing program code.

[0116] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0117] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for optimizing the photolithography process window of a wiring layout, characterized in that, include: The first image segment is input into the Transformer encoder model, and the location information of the target sub-region in the first image segment and the first process window evaluation parameters corresponding to the first image segment are output; the target sub-region includes the first pattern; the first process window evaluation parameters are less than preset parameters; The process window is optimized using the backpropagation algorithm and post-processing algorithm on the first pattern to obtain the second pattern; The second pattern is input into the transposed convolutional network to obtain the third pattern; The target sub-region in the second version image segment includes the third pattern; the evaluation parameter of the second process window corresponding to the second version image segment is greater than the evaluation parameter of the first process window. The process window optimization of the first pattern using backpropagation and post-processing algorithms to obtain the second pattern includes: The first pattern is divided using horizontal scan lines to obtain a fourth pattern; The process window of the fourth pattern is optimized using the backpropagation algorithm and the post-processing algorithm to obtain the fifth pattern; the third image segment composed of the fifth pattern has the third process window evaluation parameters; The first pattern is divided using vertical scan lines to obtain the sixth pattern; The process window of the sixth pattern is optimized using the backpropagation algorithm and the post-processing algorithm to obtain the seventh pattern; the fourth image segment composed of the seventh pattern has the fourth process window evaluation parameters. If the evaluation parameter of the third process window is greater than the evaluation parameter of the fourth process window, then the fifth pattern is used as the second pattern; otherwise, the seventh pattern is used as the second pattern.

2. The method according to claim 1, characterized in that, The process window of the fourth pattern is optimized using the backpropagation algorithm and the post-processing algorithm to obtain the fifth pattern, which includes: The process window of the fourth pattern is expanded using the backpropagation algorithm to obtain the eighth pattern; The eighth pattern is optimized using the post-processing algorithm to obtain the fifth pattern.

3. The method according to claim 2, characterized in that, The eighth pattern includes a first pixel and a plurality of second pixels adjacent to the first pixel. The step of optimizing the eighth pattern using the post-processing algorithm to obtain the fifth pattern includes: If the pixel value of multiple second pixels is 255, and at least one second pixel is connected to the first pixel, then the first pixel is retained in the fifth pattern; otherwise, the first pixel is deleted from the fifth pattern.

4. The method according to any one of claims 1-3, characterized in that, The evaluation parameters for the first process window include depth of focus or exposure dose.

5. A wiring layout photolithography process window optimization device, characterized in that, include: The determining unit is used to input the first version of the image segment into the Transformer encoder model, output the position information of the target sub-region in the first version of the image segment, and the first process window evaluation parameters corresponding to the first version of the image segment; the target sub-region includes a first pattern; the first process window evaluation parameters are less than preset parameters; An optimization unit is used to optimize the process window of the first pattern using a backpropagation algorithm and a post-processing algorithm to obtain a second pattern. The output unit is used to input the second pattern into the transposed convolutional network to obtain the third pattern; The target sub-region in the second version image segment includes the third pattern; the evaluation parameter of the second process window corresponding to the second version image segment is greater than the evaluation parameter of the first process window. The optimization unit is used for: The first pattern is divided using horizontal scan lines to obtain a fourth pattern; The process window of the fourth pattern is optimized using the backpropagation algorithm and the post-processing algorithm to obtain the fifth pattern; The third image segment composed of the fifth pattern has a third process window evaluation parameter; The first pattern is divided using vertical scan lines to obtain the sixth pattern; The process window of the sixth pattern is optimized using the backpropagation algorithm and the post-processing algorithm to obtain the seventh pattern; the fourth image segment composed of the seventh pattern has the fourth process window evaluation parameters. If the evaluation parameter of the third process window is greater than the evaluation parameter of the fourth process window, then the fifth pattern is used as the second pattern; otherwise, the seventh pattern is used as the second pattern.

6. The apparatus according to claim 5, characterized in that, The optimization unit is used for: The process window of the fourth pattern is expanded using the backpropagation algorithm to obtain the eighth pattern; The eighth pattern is optimized using the post-processing algorithm to obtain the fifth pattern.

7. A computer device, characterized in that, The computer device includes a processor and memory: The memory is used to store program code and transmit the program code to the processor; The processor is configured to execute the method described in any one of claims 1-4 according to the instructions in the program code.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program for performing the method described in any one of claims 1-4.

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