A process network graph modeling method for complex electronic equipment

Abstract

The application provides a process network diagram modeling method for complex electronic equipment, comprising the following steps: step 1, extending a classic AND / OR network diagram so that the classic AND / OR network diagram can completely characterize a complex process flow of complex electronic equipment; step 2, defining structured elements and connotations of a process; step 3, forming a process network by an implementation process of a specific product, and structurally expressing the elements and connotations; step 4, structurally defining a configuration of a production workshop to form a workshop resource supply model; and step 5, based on step 3 and step 4, matching the workshop resource supply and process resource demand, forming an optional combination of multi-dimensional resources, and linking resource-process states, so that the construction of the process network diagram model of the complex electronic equipment is finally realized. The application can solve the problem that a traditional process model cannot accurately characterize the complex electronic equipment due to a long process link, strong process flexibility and complex resource combination.

Description

Technical Field

[0001] This invention relates to the field of process modeling technology for complex electronic devices, and more specifically, to a method for modeling process network diagrams for complex electronic devices. Background Technology

[0002] Traditional two-dimensional card-based processes are unstructured and cannot support the process data requirements for planning management and production execution. Serial PBOM models provide a structured description of process data, but their process routes are singular and lack flexibility. Classic network diagrams contain multi-dimensional process routes, but only have AND / OR logic nodes. Complex electronic devices are characterized by high precision, high density, cross-scale integration, and strong electromechanical-thermal-magnetic coupling. Research and development, prototyping, and mass production occur in parallel and overlapping phases, representing a typical multi-variety, variable-batch production mode, specifically characterized as follows:

[0003] (1) Long process chain: There are hundreds of thousands of parts, dozens of BOM layers, and hundreds of process nodes;

[0004] (2) High process flexibility: In the process chain, in addition to process nodes such as optional (OR) process and no-order (AND) process, there are also process nodes such as parallel processing process, probability selection process and condition selection process, and the combination of processes is complex and varied.

[0005] (3) Complex resource combination: The manufacturing resources required for the process cover all dimensions such as people, machines, materials, methods, environment, and measurement, with the number of resource combinations reaching tens of thousands.

[0006] (4) Uncertainty of the state of resources and processes: The state of manufacturing factors, represented by resources and processes, is highly dynamic.

[0007] Therefore, traditional two-dimensional card technology, serial PBOM model, and classic AND / OR network diagram cannot accurately describe the process route of complex electronic devices produced across generations, multiple types, and multiple series on the same line. They also fail to present information such as process resource combination and key resource-process status, resulting in insufficient process guidance, insufficient support for planning and scheduling, and production efficiency that cannot meet the needs of rapid mass production of equipment. Summary of the Invention

[0008] This invention aims to provide a process network diagram modeling method for complex electronic devices, in order to solve the problem that traditional process models cannot accurately represent the long process links, high process flexibility, and complex resource combinations of complex electronic devices.

[0009] This invention provides a method for modeling process network diagrams for complex electronic devices, comprising the following steps:

[0010] Step 1: Expand the logic and nodes of the classic AND / OR network diagram to fully represent the complex process flow of complex electronic devices.

[0011] Step 2: Define the structural elements and connotations of the process;

[0012] Step 3: Based on Step 1 and Step 2, the implementation process of the specific product is woven into a process network through multiple logical nodes, and the multi-dimensional elements and connotations of each process are expressed in a structured way.

[0013] Step 4: Define the configuration in the production workshop in a structured manner to form a workshop resource supply model;

[0014] Step 5: Based on the work network and structured representation in Step 3 and the workshop resource supply model in Step 4, match the workshop resource supply with the process resource demand to form a multi-dimensional resource optional combination, and link the resource-process status to finally realize the construction of the process network diagram model of complex electronic equipment.

[0015] Furthermore, step 1 includes the following sub-steps:

[0016] Step 1.1: Inherit the five types of nodes and one type of logical expression of the classic AND / OR network diagram: start node, end node, process node, unordered node, optional node, and preceding and following logic;

[0017] Step 1.2: Summarize and generalize complex electronic devices, and add 3 types of nodes and 1 type of logic expression based on the classic AND / OR network diagram: parallel nodes, conditional selection nodes, probability selection nodes and adjacent logic.

[0018] Step 1.3 combines the 8 types of nodes and 2 types of logic from steps 1.1 and 1.2 to form the basic elements of the expanded network diagram. For using network diagrams to describe process routes, basic rules are defined.

[0019] Furthermore, in step 1.1, the five types of nodes and one type of logical expression are as follows:

[0020] (1) Start node, indicating the start of the process flow;

[0021] (2) Termination node, indicating the end of the process flow;

[0022] (3) Process node, which represents a specific process;

[0023] (4) Unordered nodes indicate that the subsequent process branches are serial paths, but there are no order constraints on each branch;

[0024] (5) Optional node means that the subsequent process branch can be selected arbitrarily, but only one branch can be selected;

[0025] (6) Precedence logic, indicating the order of connection between nodes.

[0026] Furthermore, in step 1.2, the three types of nodes and one type of logical expression are as follows:

[0027] (1) Parallel node, indicating that the subsequent process branches can be carried out in parallel;

[0028] (2) Conditional selection node indicates that the subsequent process branch must meet specific conditions before it will be executed;

[0029] (3) Selecting a node with a fixed probability means that the probability of its subsequent process branch being executed is fixed;

[0030] (4) Adjacency logic indicates the immediate preceding and immediate following relationship between connected processes.

[0031] Furthermore, in step 1.3, the basic rules are defined as follows:

[0032] (1) It must contain one start node and one end node; the start node is the first node of the network graph and the end node is the last node of the network graph.

[0033] (2) It must contain at least one process node;

[0034] (3) Each node is connected by sequential or adjacent logic to represent the sequential relationship between the nodes;

[0035] (4) Adjacent logic can only connect process nodes and can only exist in process branches described by unordered nodes.

[0036] Furthermore, step 2 includes the following sub-steps:

[0037] Step 2.1 defines in detail the elements and connotations of the process nodes described in Step 1; the process nodes cover four dimensions of elements: basic elements, process time, resource requirements, and resource-process status;

[0038] Step 2.2: Define the basic elements in a structured manner, including the process number and process name;

[0039] Step 2.3, define the process time in a structured manner, including value time, manufacturing time, and maximum parallelism: where:

[0040] (1) Value time: describes the value time of a process, including human time, standard time and machine time;

[0041] (2) Manufacturing time: describes the actual operation time of a process, including actual operation time, preparation time and cycle;

[0042] (3) Maximum number of parallel operations: describes the number of items that can be completed in the same job time;

[0043] Step 2.4: Define the resource requirements for the execution process in a structured manner.

[0044] (1) People: Describes the human resource requirements of the process, including personnel roles, number, ability level and output unit;

[0045] (2) Machine: Describes the requirements of the process for the workstation, including the function, type and quantity of the workstation;

[0046] (3) Materials: Describe the material requirements for the process, including name, model, quantity and unit;

[0047] (4) Method: The method for describing the operation process, including process segment, process overview, technological method, maximum parallelism and automation capability;

[0048] (5) Environment: Describes the environmental requirements of the process, including temperature, humidity, cleanliness and anti-static level;

[0049] (6) Measurement: Describe the process’s requirements for instruments, equipment and tooling, including type, name, sub-category, model and quantity.

[0050] Step 2.5, define the resource-process status in a structured way, including the status of key materials and key processes:

[0051] (1) Status of key materials: describes the probability of key materials being available on time and links to the material requirements table;

[0052] (2) Quality status of critical materials: Describe the probability of the critical materials meeting the requirements for function and performance, and link it to the material requirements table;

[0053] (3) Maturity of key processes: The probability that key processes will not experience any abnormalities and will be completed on time within the cycle, which is linked to the process method table;

[0054] (4) Deviation of working hours of key processes: The degree of deviation of working hours of key processes that are completed beyond the deadline is linked to the process method table.

[0055] Furthermore, step 3 includes the following sub-steps:

[0056] Step 3.1 involves constructing the process network and explaining the construction rules for the process network of each discipline in complex electronic equipment.

[0057] Step 3.2, define the elements of each process node:

[0058] (1) The basic elements are defined in the process network construction described in step 3.1;

[0059] (2) Resource requirements definition: Based on the product drawings, technical data, test outline and acceptance specifications, and in accordance with the resource requirements defined in step 2.4, describe the process method, plan the process materials, and define the requirements for personnel, workstations and instrument tooling equipment in sequence;

[0060] (3) Process time quota: The value time and manufacturing time quota for each process are based on the time quota standard;

[0061] (4) The resource-process status is linked in step 5.

[0062] Furthermore, step 3.1 includes the following sub-steps:

[0063] Step 3.1.1, Assembly process network construction rules:

[0064] (1) Based on the product structure characteristics, construct a serial path in the order from inside to outside and from bottom to top;

[0065] (2) For processes with clear division of labor and separation, such as structural component assembly, device fixing, and cable assembly fabrication, parallel nodes should be planned;

[0066] (3) For processes that do not interfere with each other, such as the installation of pluggable components, the pasting of signs, and the installation of cable assemblies, disordered nodes should be planned;

[0067] Step 3.1.2, Rules for constructing the process network:

[0068] (1) Construct a serial main path according to the process of static testing, no-load testing, device adjustment, system configuration and performance testing;

[0069] (2) For the test procedures of indicators that do not affect each other and are independent of each other, plan disordered nodes;

[0070] (3) If there are different testing methods for the same indicator, plan optional nodes for selection;

[0071] Step 3.1.3, Rules for constructing the experimental process network:

[0072] (1) When the test order is clearly adjustable in the test specifications, plan unordered nodes;

[0073] (2) For specific platforms or special test project requirements, condition-selected nodes are used for constraints;

[0074] (3) For cases where the test specifications clearly state that sampling tests are allowed for mass production, a fixed probability selection node characterization is adopted.

[0075] Step 3.1.4, Inspection process network construction rules: The network shall be constructed sequentially according to the order of appearance preparation, appearance acceptance, electrical performance acceptance, quality record filing and product packaging and warehousing. No changes are allowed unless there are special requirements.

[0076] Furthermore, in step 4, the workshop resource supply model includes:

[0077] (1) Personnel, including: work ID number, name, gender, production line, team, job type, role, professional category, competency level, contact information and on-the-job status;

[0078] (2) Workstation, including: number, name, type, function, production line, responsible person and occupancy status;

[0079] (3) Equipment, instruments and tooling, including: number, name, model, type, sub-category, production line, responsible person, occupancy status and validity period.

[0080] Furthermore, step 5 includes the following sub-steps:

[0081] Step 5.1: Match the resource requirements of each process node described in Step 3.2 with the workshop resource supply model described in Step 4 to form a resource combination of optional personnel, workstations, equipment, instruments and tooling.

[0082] Step 5.2: Read the kitting status and quality status of key materials, as well as the maturity and deviation prediction information of key processes from the quality database, and link them to the material requirements table and process method table of the corresponding processes to provide prior information for subsequent planning and scheduling.

[0083] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0084] The process network diagram modeling method for complex electronic devices provided by this invention effectively addresses the problem that traditional process models cannot accurately represent complex electronic devices due to their long process links, high process flexibility, and complex resource combinations. By defining a network diagram paradigm suitable for complex electronic devices, the multidimensional process routes of the product are woven into a process network through multiple logical nodes. Furthermore, based on the production plan and production line resource status, the method matches the optional process resource combinations with the predicted status of key resources and processes, thereby constructing a process network diagram model for complex electronic devices. Compared with existing technologies, this invention accurately represents the multidimensional process routes of complex electronic devices, presents the multi-process resource combinations and statuses in real time, provides prior information for planning and scheduling, and supports the efficient and high-quality production of complex electronic devices. Attached Figure Description

[0085] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0086] Figure 1 This is a flowchart of a process network diagram modeling method for complex electronic devices in an embodiment of the present invention.

[0087] Figure 2 This is a schematic diagram illustrating how the implementation process of a specific product is woven into a process network through multiple logical nodes in an embodiment of the present invention.

[0088] Figure 3 This is a schematic diagram showing the structured expression of the multi-dimensional elements and connotations of each process in an embodiment of the present invention, presented in tabular form. Detailed Implementation

[0089] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0090] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0091] Example

[0092] like Figure 1 As shown in the figure, this embodiment proposes a method for modeling process network diagrams for complex electronic devices, including the following steps:

[0093] Step 1: Expand the logic and nodes of the classic AND / OR network diagram to fully represent the complex process flow of complex electronic devices; specifically:

[0094] Step 1.1: Inherit the 5 types of nodes and 1 type of logical expression from the classic AND / OR network diagram:

[0095] (1) Start node (S), which indicates the start of the process flow;

[0096] (2) Termination node (E) indicates the end of the process flow;

[0097] (3) Process node (N), representing a specific process;

[0098] (4) Unordered node (AND) indicates that the subsequent process branches are serial paths, but there is no order constraint between the branches;

[0099] (5) Optional node (OR) means that the subsequent process branch can be selected arbitrarily, but only one branch can be selected;

[0100] (6) The preceding and following logic (→) indicates the sequential relationship between connected nodes (not necessarily adjacent).

[0101] Step 1.2 summarizes and categorizes the complexity of multi-disciplinary integration (assembly, debugging, testing, inspection, etc.) of complex electronic equipment, the concurrent operation of multiple business processes (research, production, repair, etc.), and the complexity of multiple platforms, multiple projects, and multiple derived processes. Based on the classic AND / OR network diagram, three new types of nodes and one type of logical expression are added:

[0102] (1) Parallel node (PA) indicates that the subsequent process branches can be carried out in parallel;

[0103] (2) Conditional Selection Node (COR) indicates that the subsequent process branch must meet specific conditions before it will be executed;

[0104] (3) Probability of choice (POR) node means that the probability of its subsequent process branch being executed is fixed;

[0105] (4) Adjacent logic (→) indicates the immediate preceding and immediate following relationship between the connected processes.

[0106] Step 1.3, combining steps 1.1 and 1.2, the above 8 types of nodes and 2 types of logic constitute the basic elements of the expanded network diagram. For using a network diagram to describe a process route, the following basic rules must be met:

[0107] (1) It must contain one start node (S) and one end node (E). The start node (S) is the first node of the network graph, and the end node (E) is the last node of the network graph.

[0108] (2) It must contain at least one process node;

[0109] (3) Each node is connected by a preceding-following logic (→) or an adjacent logic (→) to represent the sequential relationship between the nodes;

[0110] (4) The adjacent logic (→) can only connect process nodes and can only exist in the process branches described by unordered nodes (AND).

[0111] Step 2: Define the structured elements and connotations of the process from the dimensions of process stage, time, resources, and status; specifically:

[0112] Step 2.1 defines in detail the elements and connotations of the process node (N) described in Step 1. Due to the massive scale of resource combinations in complex electronic equipment, which is mainly presented as combinations of instruments or equipment, it differs significantly from traditional single equipment or machine tools. Furthermore, the production process of complex electronic equipment is highly complex, with extremely high uncertainty in the states of manufacturing elements such as material status and processing time. Therefore, the process node (N) encompasses elements in four dimensions: basic elements, process time, resource requirements, and resource-process status.

[0113] Step 2.2: Define the basic elements in a structured manner, including the process number and process name;

[0114] Step 2.3, define the process time in a structured manner, including value time, manufacturing time, and maximum parallelism: where:

[0115] (1) Value time: describes the value time of a process, including human time, standard time, and machine time;

[0116] (2) Manufacturing time: describes the actual operation time of a process, including actual operation time, preparation time, and cycle time;

[0117] (3) Maximum number of parallel operations: describes the number of items that can be completed in the same job time.

[0118] Step 2.4: Define the resource requirements for personnel, machines, materials, methods, environment, and measurement needed to execute the process in a structured manner.

[0119] (1) People: Describes the human resource requirements of the process, including personnel roles, number, ability level, output unit and other elements;

[0120] (2) Machine: Describes the requirements of the process for the workstation, including the function, type and quantity of the workstation;

[0121] (3) Materials: Describe the material requirements for the process, including elements such as name, model, quantity, and unit;

[0122] (4) Method: The method for describing the operation process, including elements such as process segment, process overview, technological method, maximum parallelism, and automation capability;

[0123] (5) Environment: Describes the environmental requirements of the process, including factors such as temperature and humidity, cleanliness, and anti-static level;

[0124] (6) Measurement: Describe the requirements of the process for instruments, equipment and tooling, including elements such as type, name, sub-classification, model and quantity.

[0125] Step 2.5, define the resource-process status in a structured way, including the status of key materials and key processes:

[0126] (1) Status of key materials: describes the probability of key materials being available on time, and can be linked to the material requirements table;

[0127] (2) Quality status of critical materials: describes the probability of the critical materials meeting functional and performance requirements, and can be linked to the material requirements table;

[0128] (3) Maturity of key processes: The probability that key processes will not experience any abnormalities and will be completed on time within the cycle can be linked to the process method table;

[0129] (4) Deviation of working hours for key processes: The degree of deviation of working hours for key processes that are completed late can be linked to the process method table.

[0130] Step 3: Based on the network diagram constructed in Steps 1 and 2, the implementation process of a specific product is woven into a process network through multiple logical nodes, such as... Figure 2 As shown, the multi-dimensional elements and connotations of each process are expressed in a structured way and presented in tabular form as follows. Figure 3 As shown; specifically:

[0131] Step 3.1 involves constructing the process network. Since the implementation logic of assembly, debugging, testing, trial, and inspection of complex electronic equipment varies significantly across different disciplines, the process network construction rules for each discipline will be explained in detail. Specifically:

[0132] Step 3.1.1, Assembly process network construction rules:

[0133] (1) Based on the product structure characteristics, construct a serial path in the order from inside to outside and from bottom to top;

[0134] (2) For processes with clear division of labor and separation, such as structural component assembly, device fixing, and cable assembly fabrication, parallel nodes (PA) should be planned.

[0135] (3) For processes such as plug-in component installation, label pasting, and cable assembly installation that do not interfere with each other, unordered nodes (AND) should be planned.

[0136] Step 3.1.2, Rules for constructing the process network:

[0137] (1) Construct a serial main path according to the process of static testing, no-load testing, device adjustment, system configuration, and indicator testing;

[0138] (2) For test procedures that do not affect each other's adjustment points and are independent of each other, unordered nodes (AND) should be planned;

[0139] (3) If there are different testing methods for the same indicator, an optional node (OR) can be planned for selection;

[0140] Step 3.1.3, Rules for constructing the experimental process network:

[0141] (1) When the test order is clearly adjustable in the test specification, unordered nodes (AND) should be planned;

[0142] (2) For specific platforms or special test project requirements, Conditional Selection Nodes (COR) should be used for constraints;

[0143] (3) For cases where the test specifications clearly state that sampling tests are allowed for mass production, the probability of choosing a node (POR) should be used to characterize the process.

[0144] Step 3.1.4, verify the process network construction rules:

[0145] The process should be compiled sequentially according to the following steps: appearance preparation, appearance inspection, electrical performance inspection, quality record filing, and product packaging and warehousing. No changes are allowed unless there are special requirements.

[0146] Step 3.2, define the elements of each process node:

[0147] (1) The basic elements are defined in the process network construction described in step 3.1;

[0148] (2) Definition of resource requirements: Based on the product drawings, technical data, test outlines, acceptance specifications, etc., according to the resource requirements defined in step 2.4, the process method description, process material planning, personnel, workstation, instrument tooling and equipment requirements are defined in sequence.

[0149] (3) Process time quota: The value time and manufacturing time quota for each process are based on the time quota standard.

[0150] (4) The resource-process status is linked in step 5.

[0151] Step 4 involves structurally defining the personnel, workstations, equipment, instruments, and tooling in the production workshop to form a workshop resource supply model; specifically:

[0152] (1) Personnel include: work ID number, name, gender, production line, team, job type, role, professional category, ability level, contact information, on-the-job status, etc.

[0153] (2) The workstation includes the following elements: number, name, type, function, production line, responsible person, and occupancy status;

[0154] (3) Equipment, instruments and tooling include: number, name, model, type, sub-category, production line, responsible person, occupancy status, validity period and other elements;

[0155] Step 5 involves matching workshop resource supply with process resource demand to form a multi-dimensional resource combination, and linking resource-process status to ultimately construct the process network diagram model for complex electronic equipment; specifically:

[0156] Step 5.1: Match the resource requirements of each process node described in Step 3.2 with the workshop resource supply model described in Step 4 to form a combination of available personnel, workstations, equipment, instruments, tooling and other resources;

[0157] Step 5.2: Read the kitting status and quality status of key materials, as well as the maturity and deviation prediction information of key processes from the quality database, and link them to the material requirements table and process method table of the corresponding processes to provide prior information for subsequent planning and scheduling.

[0158] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for modeling process network diagrams for complex electronic devices, characterized in that, Includes the following steps: Step 1: Expand the logic and nodes of the classic AND / OR network diagram to fully represent the complex process flow of complex electronic devices. Step 2: Define the structural elements and connotations of the process; Step 3: Based on Step 1 and Step 2, the implementation process of the specific product is woven into a process network through multiple logical nodes, and the multi-dimensional elements and connotations of each process are expressed in a structured way. Step 4: Define the configuration of the production workshop in a structured manner to form a workshop resource supply model; Step 5, based on the work network and structured representation from Step 3 and the workshop resource supply model from Step 4, matches workshop resource supply with process resource demand to form optional combinations of multi-dimensional resources, and links resource-process states, ultimately realizing the construction of the process network diagram model for complex electronic devices, including the following sub-steps: Step 5.1: Match the resource requirements of each process node with the workshop resource supply model described in Step 4 to form a resource combination of optional personnel, workstations, equipment, instruments and tooling. The resource requirements for each process node are defined as follows: based on the product drawings, technical data, test outlines and acceptance specifications, the process method is described in sequence according to the resource requirements required for the execution process, the process material planning is carried out, and the requirements for personnel, workstations and instrument tooling equipment are defined. The structured definition of the resource requirements for the execution process includes: (1) People: Describes the human resource requirements of the process, including personnel roles, number, ability level and output unit; (2) Machine: Describes the requirements of the process for the workstation, including the function, type and quantity of the workstation; (3) Materials: Describe the material requirements for the process, including name, model, quantity and unit; (4) Method: The method for describing the operation process, including process segment, process overview, technological method, maximum parallelism and automation capability; (5) Environment: Describes the environmental requirements of the process, including temperature, humidity, cleanliness and anti-static level; (6) Measurement: Describe the process's requirements for instruments, equipment and tooling, including type, name, sub-category, model and quantity; Step 5.2: Read the kitting status and quality status of key materials, as well as the maturity and deviation prediction information of key processes from the quality database, and link them to the material requirements table and process method table of the corresponding processes to provide prior information for subsequent planning and scheduling.

2. The method for modeling process network diagrams for complex electronic devices according to claim 1, characterized in that, Step 1 includes the following sub-steps: Step 1.1: Inherit the five types of nodes and one type of logical expression of the classic AND / OR network diagram: start node, end node, process node, unordered node, optional node, and preceding and following logic; Step 1.2: Summarize and generalize complex electronic devices, and add 3 types of nodes and 1 type of logic expression based on the classic AND / OR network diagram: parallel nodes, conditional selection nodes, probability selection nodes and adjacent logic. Step 1.3 combines the 8 types of nodes and 2 types of logic from steps 1.1 and 1.2 to form the basic elements of the expanded network diagram. For using network diagrams to describe process routes, basic rules are defined.

3. The method for modeling process network diagrams for complex electronic devices according to claim 2, characterized in that, In step 1.1, the 5 types of nodes and 1 type of logical expression are as follows: (1) Start node, indicating the start of the process flow; (2) Termination node, indicating the end of the process flow; (3) Process node, which represents a specific process; (4) Unordered nodes indicate that the subsequent process branches are serial paths, but there are no order constraints on each branch; (5) Optional node means that the subsequent process branch can be selected arbitrarily, but only one branch can be selected; (6) Precedence logic, indicating the order of connection between nodes.

4. The method for modeling process network diagrams for complex electronic devices according to claim 3, characterized in that, In step 1.2, the three types of nodes and one type of logical expression are as follows: (1) Parallel node, indicating that the subsequent process branches can be carried out in parallel; (2) Conditional selection node indicates that the subsequent process branch must meet specific conditions before it will be executed; (3) Selecting a node with a fixed probability means that the probability of its subsequent process branch being executed is fixed; (4) Adjacency logic indicates the immediate preceding and immediate following relationship between connected processes.

5. The method for modeling process network diagrams for complex electronic devices according to claim 4, characterized in that, In step 1.3, the basic rules are defined as follows: (1) It must contain one start node and one end node; the start node is the first node of the network graph and the end node is the last node of the network graph. (2) It must contain at least one process node; (3) Each node is connected by sequential or adjacent logic to represent the sequential relationship between the nodes; (4) Adjacent logic can only connect process nodes and can only exist in process branches described by unordered nodes.

6. The method for modeling process network diagrams for complex electronic devices according to claim 5, characterized in that, Step 2 includes the following sub-steps: Step 2.1 defines in detail the elements and connotations of the process nodes described in Step 1; the process nodes cover four dimensions of elements: basic elements, process time, resource requirements, and resource-process status; Step 2.2: Define the basic elements in a structured manner, including the process number and process name; Step 2.3, define the process time in a structured manner, including value time, manufacturing time, and maximum parallelism: where: (1) Value time: describes the value time of a process, including human time, standard time and machine time; (2) Manufacturing time: describes the actual operation time of a process, including actual operation time, preparation time and cycle; (3) Maximum number of parallel operations: describes the number of items that can be completed in the same job time; Step 2.4: Define the resource requirements for the execution process in a structured manner; Step 2.5, define the resource-process status in a structured way, including the status of key materials and key processes: (1) Status of key materials: describes the probability of key materials being available on time and links to the material requirements table; (2) Quality status of critical materials: Describe the probability of the critical materials meeting the requirements for function and performance, and link it to the material requirements table; (3) Maturity of key processes: The probability that key processes will not experience any abnormalities and will be completed on time within the cycle, which is linked to the process method table; (4) Deviation of working hours of key processes: The degree of deviation of working hours of key processes that are completed beyond the deadline is linked to the process method table.

7. The method for modeling process network diagrams for complex electronic devices according to claim 6, characterized in that, Step 3 includes the following sub-steps: Step 3.1 involves constructing the process network and explaining the construction rules for the process network of each discipline in complex electronic equipment. Step 3.2, define the elements of each process node: (1) The basic elements are defined in the process network construction described in step 3.1; (2) Definition of resource requirements; (3) Process time quota: The value time and manufacturing time quota for each process are based on the time quota standard; (4) The resource-process status is linked in step 5.

8. The method for modeling process network diagrams for complex electronic devices according to claim 7, characterized in that, Step 3.1 includes the following sub-steps: Step 3.1.1, Assembly process network construction rules: (1) Based on the product structure characteristics, construct a serial path in the order from inside to outside and from bottom to top; (2) For processes with clear division of labor and separation, such as structural component assembly, device fixing, and cable assembly fabrication, parallel nodes should be planned; (3) For processes that do not interfere with each other, such as the installation of pluggable components, the pasting of signs, and the installation of cable assemblies, disordered nodes should be planned; Step 3.1.2, Rules for constructing the process network: (1) Construct a serial main path according to the process of static testing, no-load testing, device adjustment, system configuration and performance testing; (2) For the test procedures of indicators that do not affect each other and are independent of each other, plan disordered nodes; (3) If there are different testing methods for the same indicator, plan optional nodes for selection; Step 3.1.3, Rules for constructing the experimental process network: (1) When the test order is clearly adjustable in the test specifications, plan unordered nodes; (2) For specific platforms or special test project requirements, condition-selected nodes are used for constraints; (3) For cases where the test specifications clearly state that sampling tests are allowed for mass production, a probability-based node selection method is used for characterization. Step 3.1.4, Inspection process network construction rules: The network shall be constructed sequentially according to the order of appearance preparation, appearance acceptance, electrical performance acceptance, quality record filing and product packaging and warehousing. No changes are allowed unless there are special requirements.

9. The method for modeling process network diagrams for complex electronic devices according to claim 8, characterized in that, In step 4, the workshop resource supply model includes: (1) Personnel, including: work ID number, name, gender, production line, team, job type, role, professional category, competency level, contact information and on-the-job status; (2) Workstation, including: number, name, type, function, production line, responsible person and occupancy status; (3) Equipment, instruments and tooling, including: number, name, model, type, sub-category, production line, responsible person, occupancy status and validity period.

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