Power state detection and brownout signal automatic isolation circuit

Abstract

The application discloses a power state detection and power-off signal automatic isolation circuit, which comprises: a detection enable control register arranged in a first power domain and powered by a first power voltage, used for outputting a first enable control signal to a power detection circuit; or arranged in a second power domain and powered by a second power voltage, used for outputting a second enable control signal to the power detection circuit; the power detection circuit comprises a voltage conversion unit arranged in the first power domain and a power detection unit arranged in the second power domain, the power detection circuit generates a power state signal based on the first enable control signal or the second enable control signal, and outputs the power state signal to a signal isolation circuit; the signal isolation circuit is arranged in the first power domain, isolates a floating signal in the second power domain based on the power state signal and outputs an isolated signal. The power state signal of the power detection circuit is used for isolating the signal of the power-off power domain, so that the chip can work in a correct mode or leakage can be avoided.

Description

Technical Field

[0001] This invention relates to the field of multi-power domain chip technology, and in particular to a power status detection and automatic isolation circuit for power-down signals. Background Technology

[0002] With the increasing prevalence of low-power chips, multi-power-domain chips are becoming more common. For example, the power supply for chip digital I / O, core units, and different functional blocks within the chip may all use different power supplies due to different externally connected modules. In different states, some power supplies may be not powered on or be turned off. In this case, the signals in that power domain become uncertain floating signals. These floating signals, when connected to other power domains, will cause the circuits in those other power domains to operate in random states and experience random leakage. To solve this problem, the power management module is typically kept powered on. The power management module controls the switching of each power supply and also controls other circuits that are not powered on to isolate the signals from the powered-off power domains.

[0003] The aforementioned power isolation scheme relies on a normally-on power management module and the power isolation control is performed by the system. Therefore, the register configuration section must also be powered on and functioning normally; otherwise, these isolations cannot be handled. However, if the user cannot determine which module has lost power, or if the module that lost power is in the power domain where the configuration register is located, signal isolation cannot be achieved through user-configured registers.

[0004] Therefore, given the shortcomings of the existing technology, there is an urgent need for a circuit that can avoid chip leakage or operating mode errors and achieve low system power consumption.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a power status detection and automatic power-down signal isolation circuit that can isolate only the power-down power domain signal by independently detecting each power domain, without relying on ensuring the normal operation of the detection enable control register configuration function. When the detected power supply is powered on, the detection function for this part of the power domain can be independently turned off, enabling the power detection circuit to achieve zero static power consumption.

[0007] To achieve the above objectives, embodiments of the present invention provide a power status detection and automatic power-down signal isolation circuit, the circuit comprising: a detection enable control register, a power detection circuit, and a signal isolation circuit;

[0008] The detection enable control register is set in the first power domain and powered by the first power supply voltage of the first power domain, and is used to output a first enable control signal to the power detection circuit; or the detection enable control register is set in the second power domain and powered by the second power supply voltage of the second power domain, and is used to output a second enable control signal to the power detection circuit.

[0009] The power detection circuit includes a voltage conversion unit disposed in a first power domain and a power detection unit disposed in a second power domain. The power detection circuit is used to generate a power status signal based on the first enable control signal or the second enable control signal, and output the power status signal to a signal isolation circuit.

[0010] The signal isolation circuit is located in the first power domain and is used to isolate the floating signal in the second power domain based on the power status signal and output an isolation signal.

[0011] In one or more embodiments of the present invention, the power supply detection unit includes a pull-down resistor and a first MOSFET, wherein a first end of the pull-down resistor is connected to a second power supply voltage, and a second end of the pull-down resistor is connected to the drain of the first MOSFET; the source of the first MOSFET is grounded, and the gate of the first MOSFET is used to input a first enable control signal.

[0012] In one or more embodiments of the present invention, the voltage conversion unit includes a second MOSFET, a third MOSFET, and a pull-up resistor;

[0013] The gate of the second MOS transistor is used to input the second power supply voltage signal, the source of the second MOS transistor is grounded, and the drain of the second MOS transistor is connected to the first end of the pull-up resistor; the second end of the pull-up resistor is connected to the drain of the third MOS transistor; and the source of the third MOS transistor is connected to the first power supply voltage.

[0014] In one or more embodiments of the present invention, the voltage conversion unit further includes a NAND gate logic circuit and a NOT gate logic circuit; the first input terminal of the NAND gate logic circuit is used to receive a first enable control signal, the second input terminal of the NAND gate logic circuit is connected to the drain of the second MOS transistor, and the output terminal of the NAND gate logic circuit is connected to a signal isolation circuit to output a power status signal.

[0015] In one or more embodiments of the present invention, the voltage conversion unit further includes a NOT gate logic circuit; the input terminal of the NOT gate logic circuit is used to receive a first enable control signal, and the output terminal of the NOT gate logic circuit is connected to the gate of a third MOS transistor.

[0016] In one or more embodiments of the present invention, the signal isolation circuit is an OR gate voltage conversion circuit or an AND gate voltage conversion circuit.

[0017] In one or more embodiments of the present invention, the AND gate voltage conversion circuit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

[0018] The source of the first PMOS transistor is connected to the source of the second PMOS transistor, the source of the third PMOS transistor, and the source of the fourth PMOS transistor, all connected to a first power supply voltage. The gate of the first PMOS transistor is connected to the drain of the second PMOS transistor and the drain of the second NMOS transistor. The drain of the first PMOS transistor is connected to the gate of the second PMOS transistor, the drain of the third PMOS transistor, the gate of the fourth PMOS transistor, the drain of the first NMOS transistor, and the gate of the third NMOS transistor. The gate of the third PMOS transistor and the gate of the fourth NMOS transistor are connected to the output terminal of the power supply detection circuit. The drain of the fourth PMOS transistor and the drain of the third NMOS transistor are connected to the output terminal of the AND gate voltage conversion circuit. The gate of the first NMOS transistor is used to receive a first differential signal from the second power supply domain. The gate of the second NMOS transistor is used to receive a second differential signal from the second power supply domain. The common source of the third and fourth NMOS transistors is grounded.

[0019] In one or more embodiments of the present invention, the OR gate voltage conversion circuit includes: a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor;

[0020] The source of the fifth PMOS transistor and the source of the eighth PMOS transistor are connected to the first power supply voltage. The gate of the fifth PMOS transistor and the gate of the seventh NMOS transistor are connected to the output terminal of the power supply detection circuit. The drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor and the source of the seventh PMOS transistor. The gate of the sixth PMOS transistor is connected to the drain of the seventh PMOS transistor and the drain of the sixth NMOS transistor. The drain of the sixth PMOS transistor is connected to the gate of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the gate of the eighth NMOS transistor, the drain of the seventh NMOS transistor, and the drain of the fifth NMOS transistor. The drain of the eighth PMOS transistor and the drain of the eighth NMOS transistor are connected to the output terminal of the OR gate voltage conversion circuit. The gate of the fifth NMOS transistor is used to receive the first differential signal of the second power supply domain. The gate of the sixth NMOS transistor is used to receive the second differential signal of the second power supply domain. The source of the fifth NMOS transistor, the source of the sixth NMOS transistor, the source of the seventh NMOS transistor, and the source of the eighth NMOS transistor are all grounded.

[0021] In one or more embodiments of the present invention, the power supply detection unit includes a pull-down resistor, wherein a first terminal of the pull-down resistor is grounded and a second terminal is connected to a detection enable control register; the voltage conversion unit includes a second MOSFET, a third MOSFET, and a pull-up resistor, wherein the gate of the second MOSFET is used to input a second enable control signal, the source of the second MOSFET is grounded, and the drain of the second MOSFET is connected to the first terminal of the pull-up resistor; the second terminal of the pull-up resistor is connected to the drain of the third MOSFET; and the source of the third MOSFET is connected to a first power supply voltage.

[0022] In one or more embodiments of the present invention, the voltage conversion unit further includes a NAND gate logic circuit and a NOT gate logic circuit; the first input terminal of the NAND gate logic circuit is connected to a first power supply voltage, the second input terminal is connected to the drain of a second MOS transistor, and the output terminal is connected to a signal isolation circuit to output the detection result; the input terminal of the NOT gate logic circuit is connected to the first power supply voltage, and the output terminal is connected to the gate of a third MOS transistor. In one or more embodiments of the present invention, the power supply detection circuit is used to detect the detected power supply signal. When the detected power supply domain is powered off, the signal isolation circuit isolates all digital signals of the detected power supply domain into a digital signal with a defined state, wherein the detected power supply signal is either a power supply voltage signal within the detected power supply domain or a high-level signal within the detected power supply domain, and the voltage of the high-level signal is equal to the power supply voltage of the detected power supply domain.

[0023] Compared with existing technologies, a power state detection and automatic power-down signal isolation circuit according to an embodiment of the present invention is suitable for power state detection of multi-power-domain chips. It controls power state detection by issuing an enable control signal through a detection enable control register, and automatically isolates signals from the power-down power domain using the power state signal from the power detection circuit, preventing the chip from operating in an incorrect mode or experiencing leakage. The detection enable control register can be configured to disable the power detection function or set the high-level signal of the detected power domain's power state low, achieving the chip's lowest power consumption mode. Attached Figure Description

[0024] Figure 1 This is a circuit design of the detection enable control register in the detection circuit section according to an embodiment of the present invention;

[0025] Figure 2 This is a circuit design of the detection enable control register in the detected power domain portion according to an embodiment of the present invention;

[0026] Figure 3 It is a signal isolation circuit with an AND gate function according to an embodiment of the present invention;

[0027] Figure 4 It is a signal isolation circuit with an OR gate function according to an embodiment of the present invention.

[0028] Explanation of key figure labels:

[0029] 11-First MOSFET, 12-Pull-down resistor, 13-Pull-up resistor, 14-Second MOSFET, 15-Third MOSFET;

[0030] 21-First PMOS transistor, 22-Second PMOS transistor, 23-Third PMOS transistor, 24-Fourth PMOS transistor, 25-First NMOS transistor, 26-Second NMOS transistor, 27-Third NMOS transistor, 28-Fourth NMOS transistor;

[0031] 31-Fifth PMOS transistor, 32-Sixth PMOS transistor, 33-Seventh PMOS transistor, 34-Eighth PMOS transistor, 35-Fifth NMOS transistor, 36-Sixth NMOS transistor, 37-Seventh NMOS transistor, 38-Eighth NMOS transistor. Detailed Implementation

[0032] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0033] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0034] Example 1:

[0035] like Figure 1 As shown, this application proposes a power status detection and automatic power-down signal isolation circuit. The circuit includes a power detection circuit, a signal isolation circuit, and a detection enable control register. The detection enable control register is used to output an enable control signal to the power detection circuit.

[0036] The detection enable control register can be set in the first power domain and powered by the first power supply voltage in the first power domain. In a preferred but non-limiting embodiment of this application, the first power domain is a normally open power domain, that is, a power domain that does not lose power; the second power domain is the power domain to be detected, that is, a power domain that may lose power.

[0037] The power detection circuit includes a voltage conversion unit disposed in a first power domain and a power detection unit disposed in a second power domain. The power detection circuit is used to detect the second power voltage based on a first enable control signal and output a power status signal to a signal isolation circuit. The signal isolation circuit receives the power status signal and controls the isolation of the detected power domain signal and outputs an isolation signal.

[0038] The power detection circuit includes a voltage conversion unit disposed in a first power domain and a power detection unit disposed in a second power domain. The power detection circuit detects a second power supply voltage based on a first enable control signal and outputs the detection result to a signal isolation circuit. Specifically, the power detection unit includes a pull-down resistor 12 and a first MOSFET 11. The first end of the pull-down resistor 12 is connected to the second power supply voltage, and the second end of the pull-down resistor 12 is connected to the drain of the first MOSFET 11. The source of the first MOSFET 11 is grounded, and its gate is used to input the first enable control signal. The pull-down resistor 12 is used to pull down the power supply voltage signal in the second power domain. Specifically, in this embodiment, the pull-down resistor 12 is a controllable switch used to pull down the second power supply voltage or a high-level signal in the second power domain. When the second power domain is powered down, the pull-down resistor 12 can pull the power status signal to "0"; when the detected power domain is powered on, the pull-down resistor 12 is ignored, and the power status signal is "1". Through this clear low / high level, it can be determined whether the detected power domain is powered down. It is understood that the circuit structure proposed in this application can not only detect the second power supply voltage in the second power domain, i.e., the power supply domain to be detected, but also detect other high-level signals in the second power domain. The embodiments of this application only illustrate the second power supply voltage. Those skilled in the art can use the power state detection and automatic isolation circuit for power failure signals provided in this application to detect various signals in the power supply domain to be detected based on actual needs.

[0039] It is understood that the second power supply voltage or the voltage of the high-level signal within the second power supply domain may be inconsistent with the first power supply voltage connected to the power detection circuit. Therefore, this embodiment also proposes a voltage conversion unit to avoid leakage current in the power detection circuit caused by the inconsistency between the detected signal voltage and the power detection circuit voltage. The voltage conversion unit includes a second MOSFET 14, a third MOSFET 15, and a pull-up resistor 13. The gate of the second MOSFET 14 is used to input the second power supply voltage signal, the source of the second MOSFET 14 is grounded, and the drain of the second MOSFET 14 is connected to the first terminal of the pull-up resistor 13. The second terminal of the pull-up resistor 13 is connected to the drain of the third MOSFET 14. The source of the third MOSFET 14 is connected to the first power supply voltage. When the converted signal is high, the second MOSFET 14 is turned on and outputs a low level. When the converted signal is low, the second MOSFET 14 is turned off, and the pull-up resistor 13 pulls the converted signal to a high level.

[0040] The voltage conversion unit also includes a NAND gate logic circuit, a NOT gate logic circuit, and a third MOSFET 15. The first input terminal of the NAND gate logic circuit is used to input a first enable control signal, the second input terminal is connected to the drain of the second MOSFET 14, and the output terminal of the NAND gate logic circuit is connected to a signal isolation circuit to output the detection result.

[0041] The input of the NAND gate logic circuit is connected to the detection enable control register, and its output is connected to the gate of the third MOSFET 15. The drain of the third MOSFET 15 is connected to the pull-up resistor 13, and the source of the third MOSFET 15 is connected to the first power supply voltage. The input of the NOT gate logic circuit is used to input the first enable control signal, and its output is connected to the gate of the third MOSFET 15. In this embodiment, the voltage conversion unit built into the power supply detection circuit enables the voltage conversion function to be achieved without differential conversion of the converted signal.

[0042] The power detection circuit proposed in this embodiment can easily disable the pull-down resistor 12 and pull-up resistor 13, ensuring that the static current is zero after the first power supply VDD1 and the second power supply VDD2 of the second power domain connected to the power detection circuit are powered on. The pull-down resistor 12 is controlled by the first MOSFET 11, so voltage conversion is not required. When the pull-down resistor 12 is disabled, the power detection circuit cannot operate correctly and requires isolation of the power status signal via a NAND gate logic circuit to prevent leakage and incorrect signal isolation. Therefore, the operation of the power detection circuit includes: controlling the pull-down resistor 12 to pull down the second power supply voltage or a high-level signal within the second power domain using a first enable control signal. The pull-down resistor 12 can be any type of resistor, such as a MOSFET resistor. When the enable control signal det_en = 1, the MOSFET resistor is turned on, pulling down the detected signal. The detected signal, driven by a weak pull-down resistor, appears as a digital signal of either 0 or 1 in the detection circuit. This signal can directly turn the MOSFET in the voltage conversion unit of the power supply detection circuit on or off. When the second power domain is powered off, the second MOSFET 14 of the power supply detection circuit is turned off, and the level is pulled high by the pull-up resistor 13. When the second power domain is powered on, and the detected power signal is 1, the second MOSFET 14 of the power supply detection circuit is turned on. The drive is much greater than that of the pull-up resistor 13, and the level cannot be pulled high, remaining at a low level. This process converts the second power supply voltage into the first power supply voltage.

[0043] In this embodiment, the signal isolation circuit receives the power status signal and controls the isolation of the detected power domain signal, outputting an isolation signal. The power status detection and automatic power-down signal isolation circuit detects whether the detected power domain, i.e., the second power domain, is powered down. If it is powered down, the signal isolation circuit automatically isolates all digital signals in that power domain from an uncertain state to a definite state. The power detection circuit detects the detected power signal, which is either the second power voltage signal or a high-level signal within the second power domain, where the voltage of the high-level signal is equal to the second power voltage. Through the signal isolation circuit, once the second power domain is powered down, isolation is initiated for signals from this power domain, preventing the circuit from entering an incorrect operating state and preventing circuit leakage. After the detected power is powered on, the static power consumption of the power detection circuit is disabled by detecting the enable control register, putting the chip in standby mode with no additional static power consumption.

[0044] The signal isolation circuit is a voltage conversion circuit with AND or OR gates. By detecting the output signal det_out of the detection circuit, the signal isolation circuit is controlled to achieve automatic signal isolation when power is lost.

[0045] like Figure 3 In one embodiment shown, the signal isolation circuit can be a voltage conversion circuit with an AND gate function: when the detected power supply is powered off, the output terminal det_out of the power supply detection circuit outputs a low-level signal, i.e., the power status signal, i.e., isoB as shown in the figure. The AND gate voltage conversion circuit proposed in this embodiment takes this low-level signal and the second power domain signal as inputs, and isolates the second power domain signal to "0". The power-off power domain signal is a differential signal d and dB.

[0046] Specifically, the AND gate voltage conversion circuit includes multiple MOS transistors: a first PMOS transistor 21, a second PMOS transistor 22, a third PMOS transistor 23, a fourth PMOS transistor 24, a first NMOS transistor 25, a second NMOS transistor 26, a third NMOS transistor 27, and a fourth NMOS transistor 28. The sources of the first PMOS transistor 21, the second PMOS transistor 22, the third PMOS transistor 23, and the fourth PMOS transistor 24 are connected to the power supply voltage of the detection circuit's power supply domain; the gates of the first PMOS transistor 21, the drains of the second PMOS transistor 22, and the drains of the second NMOS transistor 26 are connected; the drains of the first PMOS transistor 21, the gates of the second PMOS transistor 22, the drains of the third PMOS transistor 23, the gates of the fourth PMOS transistor 24, the drains of the first NMOS transistor 25, and the drains of the third NMOS transistor 28 are connected. The gate of transistor 27 is connected; the gate of the third PMOS transistor 23 and the gate of the fourth NMOS transistor 28 are connected to the output terminal of the power supply detection circuit, i.e., the iosB signal; the drain of the fourth PMOS transistor 24 and the drain of the third NMOS transistor 27 are connected to the output terminal out of the AND gate voltage conversion circuit; the gate of the first NMOS transistor 25 is the first differential signal input terminal of the second power domain; the gate of the second NMOS transistor 26 is the second differential signal input terminal of the second power domain; the common source of the third NMOS transistor 27 and the fourth NMOS transistor 28 is grounded.

[0047] like Figure 4 The diagram shows a voltage conversion circuit with an OR gate function. When the detected power supply is powered off, the inverted signal of det_out outputs a high level, which, through the OR gate voltage conversion circuit, isolates the power-off signal into "1".

[0048] like Figure 4 In one embodiment shown, the signal isolation circuit can be a voltage conversion circuit with an OR gate function: when the second power domain is powered down, the output terminal det_out of the power detection circuit outputs a high-level signal in reverse, i.e., iso as shown in the figure. The AND gate voltage conversion circuit proposed in this embodiment uses this low-level signal and the power-down power domain signal as inputs to isolate the second power domain signal into "1". The second power domain signal is a differential signal d and dB.

[0049] Specifically, the OR gate voltage conversion circuit includes multiple MOSFETs: PMOS transistor 31 (fifth), PMOS transistor 32 (sixth), PMOS transistor 33 (seventh), PMOS transistor 34 (eighth), NMOS transistor 35 (fifth), NMOS transistor 36 (sixth), NMOS transistor 37 (seventh), and NMOS transistor 38 (eighth). The source of PMOS transistor 31 and the source of PMOS transistor 34 are connected to the power supply voltage of the detection circuit's power supply domain; the gate of PMOS transistor 31 and the gate of NMOS transistor 37 are connected to the output terminal of the power supply detection circuit, i.e., the ISO signal; the drain of PMOS transistor 31, the source of PMOS transistor 32, and the source of PMOS transistor 33 are connected; the gate of PMOS transistor 32, the drain of PMOS transistor 33, and the drain of NMOS transistor 36 are connected; the drain of PMOS transistor 32, the gate of PMOS transistor 33, and the gate of NMOS transistor 38 are connected... The gate of PMOS transistor 34, the gate of the eighth NMOS transistor 38, the drain of the seventh NMOS transistor 37, and the drain of the fifth NMOS transistor 35 are connected together; the drain of the eighth PMOS transistor 34 and the drain of the eighth NMOS transistor 38 are connected together to the output terminal of the OR gate voltage conversion circuit; the gate of the fifth NMOS transistor 35 is the first differential signal input terminal of the second power domain; the gate of the sixth NMOS transistor 36 is the second differential signal input terminal of the second power domain; the source of the fifth NMOS transistor 35, the source of the sixth NMOS transistor 36, the source of the seventh NMOS transistor 37, and the source of the eighth NMOS transistor 38 are all grounded.

[0050] In summary, when the detection enable control register is set in the first power domain, the power status detection and automatic power-down signal isolation circuit proposed in this invention is suitable for multi-power domain chips. Under normal operating conditions, if some detected power domains are powered down or not powered on, the digital signals of these detected power domains will be automatically isolated by other power domains to prevent the chip from operating in an incorrect mode or experiencing leakage. In standby mode, the power detection function can be disabled by configuring the detection enable control register, so that the chip does not consume additional static current.

[0051] Example 2

[0052] like Figure 2As shown, the difference from Embodiment 1 is that the detection enable control register is set in the second power domain and powered by the second power supply voltage. In this case, the power detection circuit includes a voltage conversion unit set in the first power domain and a power detection unit set in the second power domain. The power detection unit includes a pull-down resistor 12, the first end of which is grounded and the second end is used to receive the second enable control signal. In this case, the voltage conversion unit includes a second MOSFET 14, a third MOSFET 15 and a pull-up resistor 13. The gate of the second MOSFET 14 is used to input the second enable control signal, the source of the second MOSFET 14 is grounded, and the drain of the second MOSFET 14 is connected to the first end of the pull-up resistor 13. The second end of the pull-up resistor 13 is connected to the drain of the third MOSFET 15. The source of the third MOSFET 15 is connected to the first power supply voltage.

[0053] At this time, the voltage conversion unit also includes a NAND gate logic circuit and a NOT gate logic circuit; the first input terminal of the NAND gate logic circuit is connected to the first power supply voltage, the second input terminal of the NAND gate logic circuit is connected to the drain of the second MOS transistor 14, and the output terminal of the NAND gate logic circuit is connected to the signal isolation circuit to output the detection result; the input terminal of the NOT gate logic circuit is connected to the first power supply voltage, and the output terminal of the NOT gate logic circuit is connected to the gate of the third MOS transistor 15.

[0054] In summary, when the detection enable control register is located in the detection circuit section, the signal being detected is the power supply of the detected power domain. The detection enable control register can be configured to disable the detection function to reduce standby power consumption. If both the detected power domain and the detection power domain are powered on, configuring the enable control signal to 0 disables the detection function, thus shutting down the quiescent current of the detection circuit. Figure 1 Under normal power supply conditions (VDD1), and with the enable control register located in VDD1, the power detection circuit in the power domain of VDD1 detects whether the power domain of VDD2 is down. Users can configure the enable control signal VDD2_det_en from the enable control register to be either 0 or 1, depending on the scenario. When configured to 1, a pull-down resistor is required.

[0055] A ground connection of 12 is required for power detection. When the configuration is set to 0, disconnecting it will prevent static current.

[0056] like Figure 2As shown, when the enable control register is in the second power domain, the enable control signal changes level with the power-on and power-off of the second power domain. Even if the enable control signal state is the same as the signal in the second power domain, the power detection circuit uses the enable control signal as the detected signal. The enable control register is connected to the power supply voltage of the second power domain, i.e., VDD1 shown in the figure. The user may not be able to configure the enable control register to issue the enable control signal VDD1_det_en. When VDD1 is powered on, the enable control signal issued by the enable control register is high, making the power detection always effective. When all power domains are powered on and the chip enters standby mode, the static power consumption of the detection circuit needs to be turned off to save more power. This can be achieved by configuring the enable control register to VDD1_det_en = 0, making both ends of pull-down resistor 12 low, resulting in no static power consumption. At the same time, the second MOSFET 14 is in the off state, and the voltage across pull-up resistor 13 is also the same, resulting in no static power consumption.

[0057] The circuit proposed in this application can achieve a zero standby static power consumption mode. Besides disabling the power detection function, zero static power consumption can also be achieved by changing the second power supply voltage signal in the second power domain to a low level. When the power domain where the detection enable control register is located is the second power domain, and the detection circuit has no reset signal, the power detection circuit needs to be placed in a normally open state. Otherwise, when the detection enable control register cannot be configured, the power detection circuit may fail to work, leak current, or operate incorrectly. In the normally open state, the power detection circuit will detect other power domains whenever power is applied, and will automatically isolate the signal in the power-down power domain once a power failure is detected. If both the power supply VDD1 of the power detection circuit and the power supply VDD2 of the second power domain are powered on, to obtain the lowest standby power consumption, the static current of the power detection circuit needs to be turned off. This requires changing the high-level signal in the second power domain to a low-level signal, so that the pull-down resistor 12 and pull-up resistor 13 of the power detection circuit will have no static power consumption.

[0058] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A power status detection and automatic power-down signal isolation circuit, characterized in that, The circuit includes: a detection enable control register, a power detection circuit, and a signal isolation circuit; The detection enable control register is set in the first power domain and powered by the first power supply voltage of the first power domain, and is used to output a first enable control signal to the power detection circuit; or, the detection enable control register is set in the second power domain and powered by the second power supply voltage of the second power domain, and is used to output a second enable control signal to the power detection circuit. The power detection circuit includes a voltage conversion unit disposed in a first power domain and a power detection unit disposed in a second power domain. The power detection circuit is used to generate a power status signal based on the first enable control signal or the second enable control signal, and output the power status signal to a signal isolation circuit. The signal isolation circuit is located in the first power domain and is used to isolate floating signals in the second power domain based on the power status signal and output an isolation signal.

2. The power status detection and automatic power failure signal isolation circuit as described in claim 1, characterized in that, The power detection unit includes a pull-down resistor and a first MOSFET, wherein the first end of the pull-down resistor is connected to a second power supply voltage, and the second end of the pull-down resistor is connected to the drain of the first MOSFET; the source of the first MOSFET is grounded, and the gate of the first MOSFET is used to receive a first enable control signal.

3. The power status detection and automatic power failure signal isolation circuit as described in claim 1, characterized in that, The detection enable control register is set in the first power domain and powered by the first power supply voltage of the first power domain. The voltage conversion unit includes a second MOSFET, a third MOSFET, and a pull-up resistor. The gate of the second MOS transistor is used to input the second power supply voltage signal, the source of the second MOS transistor is grounded, and the drain of the second MOS transistor is connected to the first end of the pull-up resistor; the second end of the pull-up resistor is connected to the drain of the third MOS transistor; and the source of the third MOS transistor is connected to the first power supply voltage.

4. The power status detection and automatic power failure signal isolation circuit as described in claim 3, characterized in that, The voltage conversion unit further includes a NAND gate logic circuit and a NOT gate logic circuit; the first input terminal of the NAND gate logic circuit is used to input a first enable control signal, the second input terminal of the NAND gate logic circuit is connected to the drain of the second MOS transistor, and the output terminal of the NAND gate logic circuit is connected to a signal isolation circuit to output a power status signal to the signal isolation circuit. The input terminal of the NOT gate logic circuit is used to receive the first enable control signal, and the output terminal of the NOT gate logic circuit is connected to the gate of the third MOS transistor.

5. The power status detection and automatic power failure signal isolation circuit as described in claim 3, characterized in that, The signal isolation circuit includes an OR gate voltage conversion circuit or an AND gate voltage conversion circuit.

6. The power status detection and automatic power failure signal isolation circuit as described in claim 5, characterized in that, The AND gate voltage conversion circuit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The source of the first PMOS transistor is connected to the source of the second PMOS transistor, the source of the third PMOS transistor, and the source of the fourth PMOS transistor, all connected to a first power supply voltage. The gate of the first PMOS transistor is connected to the drain of the second PMOS transistor and the drain of the second NMOS transistor. The drain of the first PMOS transistor is connected to the gate of the second PMOS transistor, the drain of the third PMOS transistor, the gate of the fourth PMOS transistor, the drain of the first NMOS transistor, and the gate of the third NMOS transistor. The gate of the third PMOS transistor and the gate of the fourth NMOS transistor are connected together to the output terminal of the power supply detection circuit. The drain of the fourth PMOS transistor and the drain of the third NMOS transistor are connected together to the output terminal of the AND gate voltage conversion circuit. The gate of the first NMOS transistor is used to receive a first differential signal from the second power supply domain. The gate of the second NMOS transistor is used to receive a second differential signal from the second power supply domain. The common source of the third and fourth NMOS transistors is grounded.

7. The power status detection and automatic power failure signal isolation circuit as described in claim 5, characterized in that, The OR gate voltage conversion circuit includes: a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; The source of the fifth PMOS transistor and the source of the eighth PMOS transistor are connected to the first power supply voltage. The gate of the fifth PMOS transistor and the gate of the seventh NMOS transistor are connected to the output terminal of the power supply detection circuit. The drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor and the source of the seventh PMOS transistor. The gate of the sixth PMOS transistor is connected to the drain of the seventh PMOS transistor and the drain of the sixth NMOS transistor. The drain of the sixth PMOS transistor is connected to the gate of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the gate of the eighth NMOS transistor, the drain of the seventh NMOS transistor, and the drain of the fifth NMOS transistor. The drain of the eighth PMOS transistor and the drain of the eighth NMOS transistor are connected to the output terminal of the OR gate voltage conversion circuit. The gate of the fifth NMOS transistor is used to receive the first differential signal of the second power supply domain. The gate of the sixth NMOS transistor is used to receive the second differential signal of the second power supply domain. The source of the fifth NMOS transistor, the source of the sixth NMOS transistor, the source of the seventh NMOS transistor, and the source of the eighth NMOS transistor are all grounded.

8. The power status detection and automatic power failure signal isolation circuit as described in claim 1, characterized in that, The detection enable control register is set in the second power domain and is powered by the second power supply voltage of the second power domain. The power detection unit includes a pull-down resistor, the first end of which is grounded and the second end of which is used to connect to the detection enable control register.

9. The power status detection and automatic power failure signal isolation circuit as described in claim 1, characterized in that, The voltage conversion unit includes a second MOSFET, a third MOSFET, and a pull-up resistor. The gate of the second MOSFET is used to input a second enable control signal. The source of the second MOSFET is grounded. The drain of the second MOSFET is connected to the first terminal of the pull-up resistor. The second terminal of the pull-up resistor is connected to the drain of the third MOSFET. The source of the third MOSFET is connected to the first power supply voltage.

10. The power status detection and automatic power failure signal isolation circuit as described in claim 9, characterized in that, The voltage conversion unit further includes a NAND gate logic circuit and a NOT gate logic circuit; the first input terminal of the NAND gate logic circuit is connected to the first power supply voltage, the second input terminal of the NAND gate logic circuit is connected to the drain of the second MOS transistor, and the output terminal of the NAND gate logic circuit is connected to a signal isolation circuit to output the detection result. The input terminal of the NOT gate logic circuit is connected to the first power supply voltage, and the output terminal of the NOT gate logic circuit is connected to the gate of the third MOS transistor.

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