Implementation method of physically unclonable function based on complementary resistive switching memristor

Abstract

The application discloses an implementation method of a physically unclonable function based on a complementary resistive switching memristor, and belongs to the technical field of semiconductor and CMOS hybrid integrated circuits. Since the complementary resistive switching memristor in a high resistance state has two different states, and the high resistance devices in different states have different responses to external excitation, one high resistance state can only be operated by applying a forward voltage, and the other high resistance state can only be operated by applying a negative voltage, and when the physically unclonable function is constructed based on the complementary resistive switching memristor, the high resistance devices are in the same state, and the physically unclonable function can be reconstructed, hidden or recovered by using a forward pulse voltage or a negative pulse voltage according to the state of the device. Therefore, the physically unclonable function constructed based on the complementary resistive switching memristor has higher security, and is expected to be widely applied to a high-security hardware security protection system.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor and CMOS hybrid integrated circuit technology, specifically relating to a method for implementing a physically unclonable function based on a complementary resistive memristor. Background Technology

[0002] The continuous advancement of information technology has driven the rapid development of fields such as the Internet of Things (IoT) and cloud computing, promoting an unprecedented expansion of the scale of interconnected networks and smart electronic devices. However, electronic devices with internet access are highly vulnerable to hardware piracy, counterfeiting, and malware implantation, leading to the leakage of sensitive information and causing incalculable economic losses. SonicWall's annual report indicates that in the first half of 2022 alone, more than 1.2 million malicious attack software programs targeting the IoT were launched, an increase of 77% compared to the previous year. Therefore, the importance of hardware security systems is increasingly prominent.

[0003] As an emerging hardware security primitive, physically unclonable functions are designed and implemented based on the inherent variations in the physical properties of devices caused by random deviations in the manufacturing process of hardware circuits, making them easy to fabricate. Furthermore, due to the existence of unpredictable random process deviations, even with the same manufacturing conditions, the original manufacturer cannot clone an identical hardware system. Therefore, physically unclonable functions are widely used in the field of hardware security protection.

[0004] Transition metal-oxide (TMO) memristors have attracted considerable attention due to their simple structure, small area, high durability, and low power consumption, as well as their compatibility with CMOS fabrication processes. However, due to variations in fabrication processes and the resistive switching mechanism of filament-based memristors, inherent eigenvalue fluctuations are unavoidable in terms of switching time and operating voltage. These fluctuations can serve as ideal random sources for implementing hardware security systems. Compared to traditional hardware security systems, memristor-based security systems offer significant advantages in terms of area and power consumption. To further enhance the security of physically unclonable functions (FOCs) in memristors, researchers have utilized the excellent durability and randomness of bipolar memristors to realize reconfigurable FOCs, effectively improving their security.

[0005] However, the data stored in traditional physically unclonable functions is physically accessible. With the development of attack techniques, attackers can use advanced microprograms and sophisticated analysis methods to steal the data stored in physically unclonable functions using leaked side-channel information, thus compromising their functionality. Therefore, a novel approach is needed to endow physically unclonable functions with the ability to be hidden and recovered. The function can be recovered only when needed, and its stored data can be hidden when idle. This effectively prevents attackers from stealing the stored data and enhances the attack resistance of physically unclonable functions. Summary of the Invention

[0006] To address the problems existing in the prior art, this invention proposes a method for realizing physically unclonable functions based on complementary resistive switching memristors (CRS). Because the oxygen vacancy distribution inside the high-resistivity state of a CRS varies in different states, the CRS can store different states depending on the excitation received. Furthermore, the high-resistivity device in different states responds differently to external stimuli. This characteristic endows the physically unclonable function with the ability to be hidden and recovered, while also effectively eliminating the original conductive filaments in the device and achieving a redistribution of oxygen vacancies inside the device, thus giving the physically unclonable function reconfigurable characteristics. Therefore, the physically unclonable function constructed based on this memristor has higher security.

[0007] The technical solution of the present invention is as follows:

[0008] A method for implementing a physically unclonable function based on a complementary resistive-switching memristor is characterized by employing a memristor array with a 1R, 1T1R structure. The word lines and bit lines of this array intersect perpendicularly, with complementary resistive-switching memristors at the intersection points. The electrical characteristics of the complementary resistive-switching memristors include four states: S1, S2, S3, and S4, where S1 and S3 are high-resistance states, and S2 and S4 are low-resistance states. The specific steps of the method are as follows:

[0009] A. Constructing physically unclonable functions

[0010] A1. Select the complementary resistive rheostat to be written in the memristor array, apply a pulse signal to change the device resistance value;

[0011] A2. Statistically analyze the resistance distribution of devices in the memristor array. Set a reference resistance value as the median value in the resistance distribution. When the memristor resistance is greater than the reference resistance value, set the device to a high-resistance state S1 or S3; when the memristor resistance is less than the reference resistance value, set the device to a low-resistance state S2 or S4. The set reference resistance value ensures that the complementary resistive-variable memristors in the memristor array are in 50% high-resistance and 50% low-resistance states. All high-resistance devices in the memristor array are in the same state. Based on the different states of the complementary resistive-variable memristors in the memristor array, the physically non-cloning functions are divided into two categories, M1 and M2. In the M1 array, all high-resistance devices are in state S1, and all low-resistance devices are in state S2. In the M2 array, all high-resistance devices are in state S3, and all low-resistance devices are in state S4.

[0012] A3. When the memristor array has M word lines and N bit lines, the challenge of the physical no-cloning function is M+N bits, where the first M bits are used for word line selection, with M / 2 bits being 1 and M / 2 bits being 0, and the last N bits are used for bit line selection, with 1 bit being 1 in the first N / 2 bits and 1 bit being 1 in the last N / 2 bits.

[0013] A4. For any challenge, use M / 2 cycles to generate all responses, generating a total of M / 2 response bits. In each cycle, select one "1" challenge from the first M bits to select the corresponding row; at the same time, select the corresponding two columns based on the two "1" challenges from the last N bits.

[0014] A5. Read the current I1 of the complementary resistive-variable memristor in the m-th row and n1-th column and the current I2 of the complementary resistive-variable memristor in the m-th row and n2-th column respectively. Compare the magnitudes of I1 and I2. When I1 = I2, the output response is 1; when I1 ≠ I2, the output response is 0. And so on, to obtain all the M / 2-bit response values, thus realizing the construction of a physically unclonable function.

[0015] B. For the physically unclonable functions M1 or M2 implemented in step A, when reconstructing M1, a negative pulse signal is used for reconstruction, and when reconstructing M2, a positive pulse signal is used for reconstruction. The specific steps are as follows:

[0016] B1. For all devices in the memristor array, select the complementary resistive rheostat to be written, selecting one device at a time;

[0017] B2. Apply a reading voltage to read the resistance value of the device. If the device has a high resistance value, skip it; if it has a low resistance value, apply a negative or positive pulse signal to make the device have a high resistance value.

[0018] B3. For all high-resistance devices in the memristor array in state S1 (M1 type of physical no-cloning function), use a negative pulse voltage to write to all devices in the array, rewriting the devices to the S3 high-resistance state; when all high-resistance devices are in state S3 (M2 type of physical no-cloning function), use a positive pulse voltage to write to all devices in the array, rewriting the devices to the S1 high-resistance state.

[0019] B4. Reconstruct the new physically unclonable function according to the method for constructing physically unclonable functions described in A.

[0020] C. Hidden Physical Unclonable Functions

[0021] C1. Hiding physically unclonable functions of type M1: Select each low-resistance device in the memristor array and reset the low-resistance device to a high-resistance state using a negative pulse voltage to achieve the hiding of physically unclonable functions M1.

[0022] C2. Hiding physically unclonable functions of type M2: Select each low-resistance device in the memristor array and reset the low-resistance device to a high-resistance state using a positive pulse voltage to hide the physically unclonable function M2.

[0023] D. Recovering physically unclonable functions

[0024] D1. Recovery of physical non-clonable functions of type M1: Select one device at a time and operate using a positive pulse. For devices that can undergo resistive switching, set them to a low-resistance state. This process continues until all devices have been operated on, thus achieving the recovery of M1.

[0025] D2. Recovery of physical non-clonable functions of type M2: Select one device at a time and operate using a negative pulse. For devices that can undergo resistance change, set them to a low-resistance state. This process continues until all devices have been operated on, thus achieving the recovery of M2.

[0026] Furthermore, the complementary resistive memristor includes a top electrode, a dielectric layer, a dielectric layer, and a bottom electrode, wherein the two dielectric layers are composed of the same transition metal oxide with different oxygen contents stacked one on top of the other, and its structure is a metal-insulator-insulator-metal capacitor structure or a metal-semiconductor-semiconductor-metal capacitor structure.

[0027] Furthermore, the top electrode or bottom electrode is made of Pt, Al, Au, W, Cu or TiN material.

[0028] Furthermore, the transition metal oxide material of the dielectric layer is TaO. x HfO x or AlO x .

[0029] This invention provides a method for implementing physically unclonable functions (PUCs) based on complementary resistive switching (CRS) memristors. Utilizing the unique resistive-switching characteristics of CRSs, the PUC is endowed with the ability to be hidden and recovered. Simultaneously, it effectively eliminates the original conductive filaments in the device, achieving a redistribution of oxygen vacancies within the device, thereby giving the PUC a reconfigurable characteristic. Therefore, the PUC constructed based on this memristor has higher security and can effectively resist external data theft, making it promising for widespread application in high-security hardware security protection systems. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the complementary resistive-variable memristor of the present invention; wherein 1—top electrode; 2—upper dielectric layer A; 3—lower dielectric layer B; 4—bottom electrode;

[0031] Figure 2 These are the typical electrical characteristics of the complementary resistive-variable memristor of this invention;

[0032] Figure 3 This is a schematic diagram of a complementary resistive-memristor array in a specific embodiment of the present invention. Detailed Implementation

[0033] The present invention will be further clearly and completely described below with reference to the accompanying drawings and specific embodiments.

[0034] Figure 1 This is a typical structural diagram and material description of the complementary resistive-variable memristor used in this invention. The two dielectric layers of this type of typical device are made of the same transition metal oxide (such as TaO) with different oxygen contents. x and TaO y The complementary resistive-variable memristor (x≠y) is constructed. Typical electrical characteristics of the complementary resistive-variable memristor are as follows: Figure 2 As shown. When the device is in the S3 state with high resistance, it is not affected by a negative voltage. Only when a positive voltage is applied will a resistance change occur, as shown. Figure 2 The right half is shown. With the application of a positive voltage, the device's resistance first gradually decreases, reaching state S4. With a further increase in the positive voltage, the device's resistance increases again, eventually reaching a high-resistance state, which is state S1. The high-resistance state in S1 is unaffected by the positive voltage; resistance change only occurs when a negative voltage is applied. With the application of a negative voltage, the device's resistance first gradually decreases, reaching state S2 (the same as state S4). With a further increase in the negative voltage, the device's resistance increases again, eventually reaching a high-resistance state, which is state S3. It is worth noting that memristor devices with similar electrical characteristics are all included within the scope of the complementary resistive-variable memristor described in this invention. Figure 3This applies to the array structure used in this invention, including memristor arrays with 1R structure and 1T1R structure.

[0035] Based on the different states of complementary resistive-variable memristors in the memristor array, physically unclonable functions are divided into two categories, M1 and M2. In the M1 array, all high-resistivity devices are in state S1, and all low-resistivity devices are in state S2. In the M2 array, all high-resistivity devices are in state S3, and all low-resistivity devices are in state S4. This invention uses an M1-type physically unclonable function constructed with a 32x32 array as an example to specifically illustrate the proposed implementation method.

[0036] 1. Construction

[0037] 1) For all devices in the array, use row and column selectors or other circuits to select one device at a time;

[0038] 2) Apply a negative pulse signal to the selected device to change its resistance value;

[0039] 3) Statistically analyze the distribution of resistance values ​​of devices in the memristor array, and set a reference resistance value as the median value of the resistance distribution. When the resistance value of a memristor is greater than the reference resistance value, the device is set to a high resistance state S1; when the resistance value of a memristor is less than the reference resistance value, the device is set to a low resistance state S2. The set reference resistance value ensures that the complementary resistive variable memristors in the memristor array are in a 50% high resistance state and a 50% low resistance state.

[0040] 3) The memristor array has 32 word lines and 32 bit lines. The physical no-cloning function challenge is 64 bits. The first 32 bits are used for word line selection, with 16 bits as "1" and 16 bits as "0". The last 32 bits are used for bit line selection, with 1 bit as "1" in the first 16 bits and 1 bit as "0" in the last 16 bits. "1" indicates that a voltage is applied; "0" indicates that no read voltage is applied.

[0041] 4) For any challenge, all responses are generated in 16 cycles, resulting in 16 response bits. In each cycle, one "1" challenge from the first 32 bits is selected and voltage is applied to select the corresponding row (denoted as row m); at the same time, voltage is applied to select the corresponding two columns (denoted as columns n1 and n2) based on the two "1" challenges from the last N bits.

[0042] 5) Read the current I1 of the self-complementary resistive rheostat in the m-th row and n1-th column and the current I2 of the complementary resistive rheostat in the m-th row and n2-th column respectively. Compare the magnitudes of I1 and I2. When I1 = I2, the output response is 1; when I1 ≠ I2, the output response is 0. And so on, to obtain all 16-bit response values, thus realizing the physically unclonable function.

[0043] 2. Restructuring

[0044] 1) For all devices in the array, use row and column selectors or other circuits to select one device at a time;

[0045] 2) Apply a reading voltage to read the resistance value of the device. If the device has a high resistance value, skip it; if it has a low resistance value, apply a positive pulse signal to make the device have a high resistance value.

[0046] 3) After all devices are set to high resistance, a negative pulse voltage is used to write all devices in the array to a new high resistance state.

[0047] 4) Reconstruct a new physically unclonable function according to the method for constructing physically unclonable functions described in section 1.

[0048] 3. Hide

[0049] 1) For all devices in the array, use row and column selectors or other circuits to select one device at a time;

[0050] 2) Apply a reading voltage to read the resistance value of the device. If the device has a high resistance value, skip it; if it has a low resistance value, apply a negative pulse signal to make the device have a high resistance value.

[0051] 3) By setting all devices to high resistance, the physical unclonable function M1 is hidden.

[0052] 4. Recovery

[0053] 1) For all devices in the array, use row and column selectors or other circuits to select one device at a time;

[0054] 2) Use a positive pulse to operate. For devices that can undergo resistance change, set them to a low-resistance state; if resistance change cannot occur, skip the operation.

[0055] 3) After operating all the devices, the physical non-clonable function M1 was recovered.

[0056] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A method for implementing a physically unclonable function based on a complementary resistive switching memristor, characterized in that, Adopting 1R, A 1T1R structure memristor array is used, where the word lines and bit lines intersect perpendicularly. The intersection points are where complementary resistive-variable memristors are located. The electrical characteristics of these complementary resistive-variable memristors include four states: S1, S2, S3, and S4. S1 and S3 represent high-resistance states, while S2 and S4 represent low-resistance states. The specific steps of the method are as follows: A. Constructing a physically unclonable function A1. Select the complementary resistive rheostat to be written in the memristor array, apply a pulse signal to change the device resistance value; A2. Statistically analyze the resistance distribution of devices in the memristor array. Set a reference resistance value as the median value in the resistance distribution. When the memristor resistance is greater than the reference resistance value, set the device to a high-resistance state S1 or S3; when the memristor resistance is less than the reference resistance value, set the device to a low-resistance state S2 or S4. All high-resistance devices in the memristor array are in the same state. Based on the different states of the complementary resistance-variable memristors in the memristor array, divide the physically non-cloning functions into two categories, M1 and M2. In the M1 array, all high-resistance devices are in state S1, and all low-resistance devices are in state S2; in the M2 array, all high-resistance devices are in state S3, and all low-resistance devices are in state S4. A3. When the memristor array has M word lines and N bit lines, the challenge of the physical no-cloning function is M+N bits, where the first M bits are used for word line selection, with M / 2 bits being 1 and M / 2 bits being 0, and the last N bits are used for bit line selection, with 1 bit being 1 in the first N / 2 bits and 1 bit being 1 in the last N / 2 bits. A4. For any challenge, use M / 2 cycles to generate all responses, generating a total of M / 2 response bits. In each cycle, select one "1" challenge from the first M bits to select the corresponding row; at the same time, select the corresponding two columns based on the two "1" challenges from the last N bits. A5. Read the current I1 of the complementary resistive rheostat in the m-th row and n1-th column and the current I2 of the complementary resistive rheostat in the m-th row and n2-th column respectively. Compare the magnitudes of I1 and I2. When I1 = I2, the output response is 1; when I1 ≠ I2, the output response is 0. And so on, to obtain all the M / 2-bit response values, thus realizing the construction of a physically unclonable function. B. For the physically unclonable functions M1 or M2 implemented in step A, when reconstructing M1, a negative pulse signal is used for reconstruction, and when reconstructing M2, a positive pulse signal is used for reconstruction. The specific steps are as follows: B1. For all devices in the memristor array, select the complementary resistive rheostat to be written, selecting one device at a time; B2. Apply a reading voltage to read the resistance value of the device. If the device has a high resistance value, skip it; if it has a low resistance value, apply a negative or positive pulse signal to make the device have a high resistance value. B3. For all high-resistance devices in the memristor array in state S1 (M1 type of physical no-cloning function), use a negative pulse voltage to write to all devices in the array, rewriting the devices to the S3 high-resistance state; when all high-resistance devices are in state S3 (M2 type of physical no-cloning function), use a positive pulse voltage to write to all devices in the array, rewriting the devices to the S1 high-resistance state. B4. Reconstruct the new physically unclonable function according to the method for constructing physically unclonable functions described in A. C. Hidden Physically Unclonable Functions C1. Hiding physically unclonable functions of type M1: Select each low-resistance device in the memristor array and reset the low-resistance device to a high-resistance state using a negative pulse voltage to achieve the hiding of physically unclonable functions M1. C2. Hiding physically unclonable functions of type M2: Select each low-resistance device in the memristor array and reset the low-resistance device to a high-resistance state using a positive pulse voltage to hide the physically unclonable function M2. D. Recovering physically unclonable functions D1. Recovery of physical non-clonable functions of type M1: Select one device at a time and operate using a positive pulse. For devices that can undergo resistive switching, set them to a low-resistance state. This process continues until all devices have been operated on, thus achieving the recovery of M1. D2. Recovery of physical non-clonable functions of type M2: Select one device at a time and operate using a negative pulse. For devices that can undergo resistance change, set them to a low-resistance state. This process continues until all devices have been operated on, thus achieving the recovery of M2.

2. The method for realizing physically unclonable function based on complementary resistive switching memristor of claim 1, wherein, The reference resistance value set in the step of constructing the physically unclonable function is such that the complementary resistive rheostats in the memristor array are in a 50 / 50 ratio of high resistance and low resistance.

3. The method for realizing physically unclonable function based on complementary resistive switching memristor of claim 1, wherein, The complementary resistive memristor includes a top electrode, a dielectric layer, a dielectric layer, and a bottom electrode. The two dielectric layers are composed of the same transition metal oxide with different oxygen contents stacked one on top of the other. Its structure is either a metal-insulator-insulator-metal capacitor structure or a metal-semiconductor-semiconductor-metal capacitor structure.

4. The method for implementing a physically unclonable function based on a complementary resistive-variable memristor as described in claim 3, characterized in that, The top or bottom electrode is made of Pt, Al, Au, W, Cu or TiN material.

5. The method for implementing a physically unclonable function based on a complementary resistive-variable memristor as described in claim 3, characterized in that, The transition metal oxide material of the dielectric layer is TaO x , HfO x , or AlO x .

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