A reference model generation method, device, apparatus and storage medium
By establishing a mapping relationship between register transfer level internal variables and stimulus internal variables in chip verification, a target reference model is generated, which solves the problem of low efficiency in chip verification and saves time and manpower costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
- Filing Date
- 2023-11-28
- Publication Date
- 2026-07-21
AI Technical Summary
During chip verification, as chip design specifications iterate and functional requirements increase, verification personnel need to frequently modify or supplement reference model components, resulting in low verification efficiency.
By establishing a target mapping relationship between register transfer level internal variables and stimulus internal variables based on functional coverage points, the target register transfer level file is obtained and analyzed to determine the target operational logic algorithm and generate the target reference model required for the verification platform.
This reduces the time and manpower costs of writing reference models and improves the efficiency of chip verification.
Smart Images
Figure CN117521568B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip verification technology, and in particular to a reference model generation method, apparatus, device, and storage medium. Background Technology
[0002] Chip verification mainly involves functional verification of the RTL (Register Transfer Level) code designed for the chip to ensure the reliability and usability of the designed code.
[0003] With the increasingly widespread application of chips in recent years, the performance requirements and complexity of chips have also become higher and higher. In the actual project research and development process, the chip requirements are not static. As customer needs change, the functional requirements of the chip increase. The design and verification of the chip need to add corresponding code for the added functional points. For chip verification, the increase in requirements means that the functional points that need to be verified increase. In order to ensure the sufficiency and completeness of chip verification, the types of stimuli issued by the corresponding verification platform need to be modified accordingly, that is, adding variables and constraints to the previous stimuli.
[0004] For chip verification platforms, the generated stimuli need to be transmitted to a reference model for logical operations in a high-level software language. The results are then compared with the actual RTL values on the scoring board to determine the correctness and completeness of the chip design's functionality. As chip design specifications are continuously iterated and improved, verification personnel need to simultaneously modify or supplement the relevant logic of the established verification platform, especially the reference model components, to ensure that the operational logic of the input variables matches the design RTL. If the chip design logic is complex and has many potential logic jumps, chip verification personnel will invest a significant amount of effort in increasing the logical matching between the stimuli and the reference model, thereby reducing the efficiency of chip verification. Summary of the Invention
[0005] In view of this, the purpose of this invention is to provide a reference model generation method, apparatus, device, and storage medium, which can save the time and manpower costs required for writing reference models during module verification and improve the efficiency of chip verification. The specific solution is as follows:
[0006] In a first aspect, the present invention discloses a reference model generation method, comprising:
[0007] Establish a target mapping relationship between register transfer level internal variables and stimulus internal variables based on the functional coverage points of the chip to be verified;
[0008] Acquire the target register transfer level internal variables and target stimulus internal variables required for module-level verification of the chip to be verified;
[0009] Based on the target register transfer level internal variables, the corresponding target register transfer level file is retrieved within the register transfer level, and the target register transfer level file is analyzed to determine the target operation logic algorithm in which the target register transfer level internal variables participate.
[0010] The relationship between the target incentive internal variables and the target computation logic algorithm is determined based on the target mapping relationship;
[0011] The target reference model required by the verification platform is generated based on the externally input target information and the relationship between the target stimulus internal variables and the target operation logic algorithm; the target information includes the stimulus type, the stimulus acquisition and transmission method, and the bus protocol used.
[0012] Optionally, before establishing the target mapping relationship between register transfer level internal variables and stimulus internal variables based on the functional coverage points of the chip to be verified, the method further includes:
[0013] Determine the functional coverage of the chip to be verified;
[0014] Obtain the register-transfer level code designed for the chip to be verified, and analyze the register-transfer level code to count the variables inside the register-transfer level, so as to obtain the corresponding internal variables of the register-transfer level;
[0015] Determine the intrinsic incentive variables of the verification platform; the intrinsic incentive variables are the variables required in the predefined incentive.
[0016] Accordingly, establishing the target mapping relationship between register transfer level internal variables and stimulus internal variables based on the functional coverage points of the chip to be verified includes:
[0017] The functional coverage points and register transfer level internal variables of the chip to be verified are classified to obtain the corresponding first classification results;
[0018] Based on the first classification result, a mapping relationship is established between the functional coverage point and the internal variables of the register transfer level to obtain the corresponding first mapping relationship;
[0019] The functional coverage points and the internal stimulus variables of the chip to be verified are classified to obtain the corresponding second classification results;
[0020] Based on the second classification result, a mapping relationship is established between the functional coverage point and the internal stimulus variable to obtain the corresponding second mapping relationship;
[0021] Based on the first mapping relationship and the second mapping relationship, a mapping relationship is established between the register transfer level internal variables and the excitation internal variables to obtain the corresponding target mapping relationship.
[0022] Optionally, obtaining the target register transfer level internal variables and target stimulus internal variables required for module-level verification of the chip to be verified includes:
[0023] When performing module-level verification on the chip to be verified, obtain the target register transfer level internal variables within the register transfer level; the target register transfer level internal variables are variables that participate in the preset main logic operations within the register transfer level.
[0024] Obtain the target stimulus internal variable sent to the stimulus by the verification platform when performing module-level verification on the chip to be verified; the target stimulus internal variable is the variable required to activate the normal operation of the register transfer stage.
[0025] Optionally, the step of analyzing the target register transfer level file to determine the target operation logic algorithm in which the internal variables of the target register transfer level participate includes:
[0026] The target register transfer level file is analyzed to determine any one of the logic statements (case, if-else, or for loop) involved by the internal variables of the target register transfer level, thereby obtaining the target operation logic algorithm.
[0027] Optionally, after analyzing the target register transfer level file to determine the target operation logic algorithm in which the internal variables of the target register transfer level participate, the method further includes:
[0028] Establish the connection between the target computational logic algorithm and the target register transfer level internal variables.
[0029] Optionally, determining the relationship between the target excitation internal variables and the target computation logic algorithm based on the target mapping relationship includes:
[0030] Based on the relationship between the target computation logic algorithm and the target register transfer level internal variables, as well as the target mapping relationship, the target computation logic algorithm is matched with the target stimulus internal variables to establish the relationship between the target stimulus internal variables and the target computation logic algorithm.
[0031] Optionally, the bus protocol is an advanced microcontroller bus architecture bus protocol or a non-standard bus protocol.
[0032] Secondly, the present invention discloses a reference model generation apparatus, comprising:
[0033] The mapping relationship establishment module is used to establish a target mapping relationship between register transfer level internal variables and stimulus internal variables based on the functional coverage points of the chip to be verified.
[0034] The variable acquisition module is used to acquire the target register transfer level internal variables and target stimulus internal variables required for module-level verification of the chip to be verified.
[0035] The file reading module is used to search within the register transfer level according to the internal variables of the target register transfer level in order to read the corresponding target register transfer level file.
[0036] The file analysis module is used to analyze the target register transfer level file to determine the target operation logic algorithm in which the internal variables of the target register transfer level participate.
[0037] The connection determination module is used to determine the connection between the target excitation internal variables and the target operation logic algorithm based on the target mapping relationship;
[0038] The reference model generation module is used to generate a target reference model required by the verification platform based on the target information input from the outside and the relationship between the target stimulus internal variables and the target operation logic algorithm; the target information includes the stimulus type, the stimulus acquisition and transmission method, and the bus protocol used.
[0039] Thirdly, the present invention discloses an electronic device, comprising:
[0040] Memory, used to store computer programs;
[0041] A processor is configured to execute the computer program to implement the steps of the aforementioned disclosed reference model generation method.
[0042] Fourthly, the present invention discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the aforementioned disclosed reference model generation method.
[0043] As can be seen, the present invention provides a reference model generation method, comprising: establishing a target mapping relationship between register transfer level internal variables and stimulus internal variables based on the functional coverage points of the chip to be verified; obtaining the target register transfer level internal variables and target stimulus internal variables required for module-level verification of the chip to be verified; retrieving the corresponding target register transfer level file within the register transfer level according to the target register transfer level internal variables, and analyzing the target register transfer level file to determine the target operation logic algorithm in which the target register transfer level internal variables participate; determining the relationship between the target stimulus internal variables and the target operation logic algorithm according to the target mapping relationship; generating a target reference model required by the verification platform according to the externally input target information and the relationship between the target stimulus internal variables and the target operation logic algorithm; the target information includes the stimulus type, the stimulus acquisition and transmission method, and the bus protocol used. Therefore, this invention establishes a target mapping relationship between register-transfer level internal variables and stimulus internal variables based on functional coverage points. Then, it automatically generates a reference model by combining stimulus information, target mapping relationship, and related algorithms. In other words, a reference model is generated by establishing a connection between stimulus, register-transfer level, and reference model, that is, by mapping stimulus internal variables with register-transfer level internal variables. This reduces the amount of code work and saves the time and manpower required to write a reference model during module-level verification, thereby improving the efficiency of chip verification. Attached Figure Description
[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0045] Figure 1 This is a flowchart of a reference model generation method disclosed in this invention;
[0046] Figure 2 This is a flowchart of establishing a chip verification variable mapping relationship as disclosed in this invention;
[0047] Figure 3 This is a flowchart of a specific reference model generation method disclosed in this invention;
[0048] Figure 4 This is a schematic diagram of a specific chip verification reference model generation framework disclosed in this invention;
[0049] Figure 5 This is a schematic diagram of a reference model generation device disclosed in this invention;
[0050] Figure 6 This is a structural diagram of an electronic device disclosed in this invention. Detailed Implementation
[0051] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0052] Currently, for chip verification platforms, the generated stimuli need to be transmitted to a reference model for logical operations in a high-level software language. The results are then compared with the actual RTL values on the scoring board to determine the correctness and completeness of the chip design's functionality. As chip design specifications are continuously iterated and improved, verification personnel need to simultaneously modify or supplement the relevant logic of the established verification platform, especially the reference model components, to ensure that the operational logic of the input variables matches the design RTL. If the chip design logic is complex and has many potential logic jumps, chip verification personnel will invest a significant amount of effort in increasing the logical matching between the stimuli and the reference model, thus reducing the efficiency of chip verification. Therefore, this invention provides a reference model generation scheme that can save the time and manpower costs required to write reference models during module verification and improve the efficiency of chip verification.
[0053] This invention discloses a method for generating a reference model, see [link to relevant documentation]. Figure 1 As shown, the method includes:
[0054] Step S11: Establish the target mapping relationship between register transfer level internal variables and stimulus internal variables based on the functional coverage points of the chip to be verified.
[0055] In this embodiment, the RTL internal variables (register transfer level internal variables) are linked with the variables inside the verification platform stimulus through functional coverage points, establishing a target mapping relationship between the register transfer level internal variables and the stimulus internal variables, thereby creating the basic conditions for subsequent variable acquisition and matching.
[0056] In this embodiment, before establishing the target mapping relationship between register-transfer level internal variables and stimulus internal variables based on the functional coverage points of the chip to be verified, the method further includes: determining the functional coverage points of the chip to be verified; obtaining the register-transfer level code designed for the chip to be verified, and analyzing the register-transfer level code to statistically analyze the variables within the register-transfer level to obtain the corresponding register-transfer level internal variables; determining the stimulus internal variables of the verification platform; the stimulus internal variables are the variables required in the predefined stimulus. It should be noted that chip verification personnel will decompose the points to be verified according to the chip functions supported by the design as described in the design specification (chip specification document), that is, cover the functional points, and compile a checklist (verification functional point document, that is, a document composed of functional points decomposed by the verification personnel according to the design specification) to define the variables required in the stimulus (code files written by the verification personnel to configure and start RTL).
[0057] In this embodiment, establishing the target mapping relationship between register-transfer level internal variables and stimulus internal variables based on the functional coverage points of the chip under test specifically includes: classifying the functional coverage points and register-transfer level internal variables of the chip under test to obtain a corresponding first classification result; establishing a mapping relationship between the functional coverage points and register-transfer level internal variables based on the first classification result to obtain a corresponding first mapping relationship; classifying the functional coverage points and stimulus internal variables of the chip under test to obtain a corresponding second classification result; establishing a mapping relationship between the functional coverage points and stimulus internal variables based on the second classification result to obtain a corresponding second mapping relationship; and establishing a mapping relationship between the register-transfer level internal variables and stimulus internal variables based on the first and second mapping relationships to obtain a corresponding target mapping relationship. It can be understood that, based on the first mapping relationship between functional coverage points and register-transfer level internal variables and the second mapping relationship between functional coverage points and stimulus internal variables, the functional coverage points connect the RTL internal variables with the stimulus internal variables of the verification platform, and classification is used to further establish the mapping relationship to obtain the target mapping relationship. For example, see... Figure 2 As shown, firstly, a mapping relationship is established between functional coverage points and RTL internal variables. Secondly, the variables required in the stimulus are defined, and the stimulus variables and coverage points are classified to establish a mapping relationship between functional coverage points and stimulus internal variables. Finally, based on the established mapping relationship, the RTL internal variables are linked to the variables inside the validation platform stimulus through the functional coverage points to establish a target mapping relationship between RTL internal variables and stimulus internal variables.
[0058] Step S12: Obtain the target register transfer level internal variables and target stimulus internal variables required for module-level verification of the chip to be verified.
[0059] In this embodiment, after establishing the target mapping relationship between RTL internal variables and stimulus internal variables, the target register transfer level internal variables and target stimulus internal variables required for module-level verification of the chip under test are obtained. Specifically, the target register transfer level internal variables within the register transfer level are obtained when performing module-level verification of the chip under test; these target register transfer level internal variables are variables that participate in the preset main logic operations within the register transfer level. The target stimulus internal variables sent by the verification platform to the stimulus internals when performing module-level verification of the chip under test are also obtained; these target stimulus internal variables are variables required to activate the normal operation of the register transfer level. For example, the variables within the RTL are obtained, and the variables within the stimulus internals sent by the verification platform are also obtained.
[0060] Step S13: Based on the target register transfer level internal variables, search within the register transfer level to read the corresponding target register transfer level file, and analyze the target register transfer level file to determine the target operation logic algorithm in which the target register transfer level internal variables participate.
[0061] In this embodiment, after obtaining the target RTL internal variables, the target RTL file is retrieved by searching within the RTL based on the target register transfer level internal variables. The target RTL file is then analyzed to determine the target computation logic algorithm in which the target RTL internal variables participate. Specifically, the target register transfer level file is analyzed to determine any one of the following logic statements—case statements, if-else statements, or for loop statements—in which the target register transfer level internal variables participate, thereby obtaining the target computation logic algorithm.
[0062] Step S14: Determine the relationship between the target excitation internal variables and the target operation logic algorithm based on the target mapping relationship.
[0063] In this embodiment, after analyzing the target register transfer level file to determine the target operation logic algorithm in which the target register transfer level internal variables participate, the connection between the target stimulus internal variables and the target operation logic algorithm can be determined based on the established target mapping relationship between the RTL internal variables and the stimulus internal variables.
[0064] Step S15: Generate the target reference model required by the verification platform based on the externally input target information and the relationship between the target stimulus internal variables and the target operation logic algorithm; the target information includes the stimulus type, the stimulus acquisition and transmission method, and the bus protocol used.
[0065] In this embodiment, after determining the relationship between the target stimulus internal variables and the target computational logic algorithm, a target reference model required for the verification platform can be generated based on target information including stimulus type, stimulus acquisition and transmission method, and the bus protocol used, as well as the relationship between the target stimulus internal variables and the target computational logic algorithm. The bus protocol is either an advanced microcontroller bus architecture bus protocol or a non-standard bus protocol. It is understood that by establishing a connection between the stimulus, RTL, and reference model, the efficiency of chip verification is improved, allowing chip verification personnel to focus more on the entire platform rather than a specific component. This enables chip verification staff to generate a reference model framework through the mapping of stimulus to variables in the RTL, thereby reducing coding workload. Chip verification staff only need to perform some complex logic adaptation and debugging based on this reference model framework, thus saving the time and manpower costs required to write reference models during module verification.
[0066] As can be seen, in this embodiment of the invention, a target mapping relationship between register transfer level internal variables and stimulus internal variables is established based on functional coverage points. Then, a reference model is automatically generated by combining stimulus information, target mapping relationship and related algorithms. In other words, a reference model is generated by establishing a connection between stimulus, register transfer level and reference model, that is, by mapping stimulus internal variables with register transfer level internal variables. This reduces the amount of code work and saves the time and manpower cost required to write a reference model during module-level verification, thereby improving the efficiency of chip verification.
[0067] See Figure 3 As shown, this embodiment of the invention discloses a specific method for generating a reference model. Compared with the previous embodiment, this embodiment further explains and optimizes the technical solution.
[0068] Step S21: Establish the target mapping relationship between register transfer level internal variables and stimulus internal variables based on the functional coverage points of the chip to be verified.
[0069] Step S22: Obtain the target register transfer level internal variables and target stimulus internal variables required for module-level verification of the chip to be verified.
[0070] Step S23: Based on the target register transfer level internal variables, perform a search within the register transfer level to read the corresponding target register transfer level file, and analyze the target register transfer level file to determine the target operation logic algorithm in which the target register transfer level internal variables participate.
[0071] Step S24: Establish the connection between the target operation logic algorithm and the target register transfer level internal variables.
[0072] In this embodiment, after determining the relationship between the target stimulus internal variables and the target computational logic algorithm, the relationship between the target computational logic algorithm and the target register transfer level internal variables is established.
[0073] Step S25: Match the target operation logic algorithm with the target stimulus internal variables according to the relationship between the target operation logic algorithm and the target register transfer level internal variables and the target mapping relationship, so as to establish the relationship between the target stimulus internal variables and the target operation logic algorithm.
[0074] In this embodiment, after establishing the connection between the target computation logic algorithm and the target register transfer level internal variables, the target computation logic algorithm is matched with the target stimulus internal variables based on the connection between the target computation logic algorithm and the target register transfer level internal variables, as well as the target mapping relationship between the RTL internal variables and the stimulus internal variables, so as to establish the connection between the target stimulus internal variables and the target computation logic algorithm.
[0075] Step S26: Generate the target reference model required by the verification platform based on the externally input target information and the relationship between the target stimulus internal variables and the target operation logic algorithm; the target information includes the stimulus type, the stimulus acquisition and transmission method, and the bus protocol used.
[0076] For details regarding steps S31 to S33 and S36, please refer to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.
[0077] Based on functional coverage points, a target mapping relationship is established between register-transfer level internal variables and stimulus internal variables. Then, by combining stimulus information, target mapping relationship and related algorithms, a reference model is automatically generated. In other words, a reference model is generated by establishing a connection between stimulus, register-transfer level and reference model, that is, by mapping stimulus internal variables with register-transfer level internal variables. This reduces the amount of code work and saves the time and manpower cost required to write reference models during module-level verification, thereby improving the efficiency of chip verification.
[0078] For example, see Figure 4As shown, the established target mapping relationship between RTL internal variables and stimulus internal variables is input. The RTL variable acquisition module retrieves the variables within the RTL, i.e., the variables participating in the main logical operations within the RTL, thus obtaining the target RTL internal variables. The stimulus variable acquisition module retrieves the variables created within the stimulus sent by the verification platform, i.e., the variables required for the normal operation of the RTL, thus obtaining the target stimulus internal variables. The algorithm reading module, algorithm analysis module, and algorithm storage module are closely connected. Specifically, the retrieved target RTL internal variables are input into the algorithm reading module, which then searches within the RTL and reads the corresponding RTL file, i.e., the DUT (Design Under Test). The test (design under test) is then performed in the algorithm analysis module. This module analyzes the RTL file to determine the computational logic algorithms involved by the target RTL internal variables. For example, if the target RTL internal variables participate in case statements, if-else statements, or for loops, these algorithms are linked to the target RTL internal variables and stored in the algorithm storage module. Then, based on the target stimulus internal variables obtained from the stimulus variable module and the information from the algorithm storage module, the data is input into the matching module. The matching module performs algorithm matching based on the target mapping relationship between the RTL internal variables and the stimulus internal variables, establishing a connection between the target stimulus internal variables and the corresponding algorithms. In addition to the output information from the matching module, information including the stimulus type, the stimulus acquisition and transmission method, and the bus protocol used should also be input into the file generation module. For example, the type of bus transmission used, such as the APB (Advanced Peripheral Bus) protocol in the AMBA bus protocol, and the TLM (Transaction Level Management) protocol... In Modeling (Transaction-Level Modeling), which ports are used to acquire and send stimuli? Among them, the TLM port is mainly used for signal line-level communication between various modules in the DUT, as well as for inputting target information of the bus protocol used into the file generation module.When generating a complete reference model file, besides the internal computational logic, obtaining these variables is also a crucial issue. Therefore, it's necessary to understand how stimuli are attached to sequences (containers containing multiple stimuli that flow within the verification platform) and how they are sent to the reference model. Finally, a Python script is used to generate the corresponding SV (Single File System) file, serving as the reference model required by the verification platform. This reference model contains the necessary stimulus variables, methods for acquiring and sending stimuli, and declarations of corresponding TLM ports. Furthermore, it provides a basic logical framework for the functions and tasks related to these stimulus variables. Based on this, developers only need to add or remove logic according to the algorithm's complexity and requirements, flexibly adapting the model. This reduces the coding workload for chip verification staff, freeing them from the effort of matching the verification platform's reference model logic to increasing chip functional requirements, thus improving their work efficiency.
[0079] Accordingly, embodiments of the present invention also disclose a reference model generation apparatus, see [link to relevant documentation]. Figure 5 As shown, the device includes:
[0080] The mapping relationship establishment module 11 is used to establish a target mapping relationship between register transfer level internal variables and stimulus internal variables based on the functional coverage points of the chip to be verified.
[0081] The variable acquisition module 12 is used to acquire the target register transfer level internal variables and target stimulus internal variables required for module-level verification of the chip to be verified.
[0082] The file reading module 13 is used to search within the register transfer level according to the internal variables of the target register transfer level in order to read the corresponding target register transfer level file.
[0083] File analysis module 14 is used to analyze the target register transfer level file to determine the target operation logic algorithm in which the internal variables of the target register transfer level participate.
[0084] The connection determination module 15 is used to determine the connection between the target excitation internal variables and the target operation logic algorithm based on the target mapping relationship;
[0085] The reference model generation module 16 is used to generate a target reference model required by the verification platform based on the target information input from the outside and the relationship between the target stimulus internal variables and the target operation logic algorithm; the target information includes the stimulus type, the stimulus acquisition and transmission method and the bus protocol used.
[0086] As can be seen from the above, in this embodiment of the invention, a target mapping relationship between register transfer level internal variables and stimulus internal variables is established based on functional coverage points. Then, a reference model is automatically generated by combining stimulus information, target mapping relationship and related algorithms. In other words, a reference model is generated by establishing a connection between stimulus, register transfer level and reference model, that is, by mapping stimulus internal variables with register transfer level internal variables. This reduces the amount of code work and saves the time and manpower cost required to write a reference model during module-level verification, thereby improving the efficiency of chip verification.
[0087] In some specific embodiments, the reference model generation apparatus may further include:
[0088] The functional coverage point determination module is used to determine the functional coverage points of the chip to be verified.
[0089] The code acquisition module is used to acquire register transfer level code designed for the chip to be verified;
[0090] The register-transfer-level internal variable determination module is used to analyze the register-transfer-level code to count the variables inside the register-transfer-level, so as to obtain the corresponding register-transfer-level internal variables.
[0091] The incentive internal variable determination module is used to determine the incentive internal variables of the verification platform; the incentive internal variables are predefined variables required in the incentive.
[0092] In some specific embodiments, the mapping relationship establishment module 11 may specifically include:
[0093] The first classification submodule is used to classify the functional coverage points and the register transfer level internal variables of the chip to be verified to obtain the corresponding first classification result;
[0094] The first mapping relationship establishment submodule is used to establish a mapping relationship between the functional coverage point and the internal variables of the register transfer level based on the first classification result, so as to obtain the corresponding first mapping relationship.
[0095] The second classification submodule is used to classify the functional coverage points and the internal stimulus variables of the chip to be verified to obtain the corresponding second classification results;
[0096] The second mapping relationship establishment submodule is used to establish a mapping relationship between the functional coverage point and the internal stimulus variable based on the second classification result, so as to obtain the corresponding second mapping relationship.
[0097] The target mapping relationship establishment submodule is used to establish the mapping relationship between the register transfer level internal variables and the excitation internal variables based on the first mapping relationship and the second mapping relationship, so as to obtain the corresponding target mapping relationship.
[0098] In some specific embodiments, the variable acquisition module 12 may specifically include:
[0099] The first variable acquisition submodule is used to acquire the target register transfer level internal variables in the register transfer level when performing module-level verification on the chip to be verified; the target register transfer level internal variables are variables that participate in the preset main logic operations in the register transfer level.
[0100] The second variable acquisition submodule is used to acquire the target stimulus internal variables sent to the stimulus by the verification platform when performing module-level verification on the chip to be verified; the target stimulus internal variables are the variables required to activate the normal operation of the register transfer stage.
[0101] In some specific embodiments, the file analysis module 14 may specifically include:
[0102] The file analysis submodule is used to analyze the target register transfer level file to determine any one of the logic statements, if-else statements, or for loop statements involved in the target register transfer level internal variables, and to obtain the target operation logic algorithm.
[0103] In some specific embodiments, the reference model generation apparatus may further include:
[0104] The connection establishment module is used to establish the connection between the target computational logic algorithm and the target register transfer level internal variables.
[0105] In some specific embodiments, the contact determination module 15 may specifically include:
[0106] The connection establishment submodule is used to match the target computation logic algorithm with the target stimulus internal variables based on the connection between the target computation logic algorithm and the target register transfer level internal variables and the target mapping relationship, so as to establish the connection between the target stimulus internal variables and the target computation logic algorithm.
[0107] Furthermore, embodiments of the present invention also provide an electronic device. Figure 6 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of the invention.
[0108] Figure 6This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present invention. Specifically, the electronic device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the reference model generation method disclosed in any of the foregoing embodiments. Furthermore, the electronic device 20 in this embodiment may specifically be an electronic computer.
[0109] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this invention, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.
[0110] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.
[0111] The operating system 221 is used to manage and control the various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the reference model generation method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.
[0112] Furthermore, embodiments of the present invention also disclose a computer-readable storage medium storing a computer program, which, when loaded and executed by a processor, implements the reference model generation method steps disclosed in any of the foregoing embodiments.
[0113] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0114] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0115] The foregoing has provided a detailed description of a reference model generation method, apparatus, device, and storage medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A method for generating a reference model, characterized in that, include: Establish a target mapping relationship between register transfer level internal variables and stimulus internal variables based on the functional coverage points of the chip to be verified; Acquire the target register transfer level internal variables and target stimulus internal variables required for module-level verification of the chip to be verified; Based on the target register transfer level internal variables, the corresponding target register transfer level file is retrieved within the register transfer level, and the target register transfer level file is analyzed to determine the target operation logic algorithm in which the target register transfer level internal variables participate. The relationship between the target incentive internal variables and the target computation logic algorithm is determined based on the target mapping relationship; The target reference model required by the verification platform is generated based on the externally input target information and the relationship between the target stimulus internal variables and the target operation logic algorithm; the target information includes the stimulus type, the stimulus acquisition and transmission method, and the bus protocol used.
2. The reference model generation method according to claim 1, characterized in that, Before establishing the target mapping relationship between register transfer level internal variables and stimulus internal variables based on the functional coverage points of the chip to be verified, the following steps are also included: Determine the functional coverage of the chip to be verified; Obtain the register-transfer level code designed for the chip to be verified, and analyze the register-transfer level code to count the variables inside the register-transfer level, so as to obtain the corresponding internal variables of the register-transfer level; Determine the intrinsic incentive variables of the verification platform; the intrinsic incentive variables are the variables required in the predefined incentive. Accordingly, establishing the target mapping relationship between register transfer level internal variables and stimulus internal variables based on the functional coverage points of the chip to be verified includes: The functional coverage points and register transfer level internal variables of the chip to be verified are classified to obtain the corresponding first classification results; Based on the first classification result, a mapping relationship is established between the functional coverage point and the internal variables of the register transfer level to obtain the corresponding first mapping relationship; The functional coverage points and the internal stimulus variables of the chip to be verified are classified to obtain the corresponding second classification results; Based on the second classification result, a mapping relationship is established between the functional coverage point and the internal stimulus variable to obtain the corresponding second mapping relationship; Based on the first mapping relationship and the second mapping relationship, a mapping relationship is established between the register transfer level internal variables and the excitation internal variables to obtain the corresponding target mapping relationship.
3. The reference model generation method according to claim 1, characterized in that, The acquisition of the target register transfer level internal variables and target stimulus internal variables required for module-level verification of the chip under test includes: When performing module-level verification on the chip to be verified, obtain the target register transfer level internal variables within the register transfer level; the target register transfer level internal variables are variables that participate in the preset main logic operations within the register transfer level. Obtain the target stimulus internal variable sent to the stimulus by the verification platform when performing module-level verification on the chip to be verified; the target stimulus internal variable is the variable required to activate the normal operation of the register transfer stage.
4. The reference model generation method according to claim 1, characterized in that, The step of analyzing the target register transfer level file to determine the target operation logic algorithm in which the internal variables of the target register transfer level participate includes: The target register transfer level file is analyzed to determine any one of the logic statements (case, if-else, or for loop) involved by the internal variables of the target register transfer level, thereby obtaining the target operation logic algorithm.
5. The reference model generation method according to claim 1, characterized in that, After analyzing the target register transfer level file to determine the target operation logic algorithm in which the internal variables of the target register transfer level participate, the method further includes: Establish the connection between the target computational logic algorithm and the target register transfer level internal variables.
6. The reference model generation method according to claim 5, characterized in that, Determining the relationship between the target excitation internal variables and the target computation logic algorithm based on the target mapping relationship includes: Based on the relationship between the target computation logic algorithm and the target register transfer level internal variables, as well as the target mapping relationship, the target computation logic algorithm is matched with the target stimulus internal variables to establish the relationship between the target stimulus internal variables and the target computation logic algorithm.
7. The reference model generation method according to any one of claims 1 to 6, characterized in that, The bus protocol is either an advanced microcontroller bus architecture bus protocol or a non-standard bus protocol.
8. A reference model generation apparatus, characterized in that, include: The mapping relationship establishment module is used to establish a target mapping relationship between register transfer level internal variables and stimulus internal variables based on the functional coverage points of the chip to be verified. The variable acquisition module is used to acquire the target register transfer level internal variables and target stimulus internal variables required for module-level verification of the chip to be verified. The file reading module is used to search within the register transfer level according to the internal variables of the target register transfer level in order to read the corresponding target register transfer level file. The file analysis module is used to analyze the target register transfer level file to determine the target operation logic algorithm in which the internal variables of the target register transfer level participate. The connection determination module is used to determine the connection between the target excitation internal variables and the target operation logic algorithm based on the target mapping relationship; The reference model generation module is used to generate a target reference model required by the verification platform based on the target information input from the outside and the relationship between the target stimulus internal variables and the target operation logic algorithm; the target information includes the stimulus type, the stimulus acquisition and transmission method, and the bus protocol used.
9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the reference model generation method as described in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, Used to store a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the reference model generation method as described in any one of claims 1 to 7.