Method and system for inserting scan chains in intermediate representation layer based on modular strategy

Abstract

The application provides a method and system for inserting a scan chain into an intermediate representation layer based on a modular strategy, which comprises the following steps: obtaining an original design including a design circuit to be tested; constructing a directed acyclic graph according to the structural module relationship of the original design, wherein a vertex in the directed acyclic graph represents a module in the intermediate representation layer, and each directed edge represents a logical relationship in which a higher-level module instantiates a lower-level target sub-module; performing a reverse topological sorting on the directed acyclic graph, starting from the lowest-level module in the directed acyclic graph instantiation relationship, inserting a scan chain, creating a pair of input and output ports for the scan chain, and inserting the scan chain into a higher-level module step by step until the scan chain is inserted into the highest-level module in the directed acyclic graph instantiation relationship; and inserting the scan chain into a netlist in the intermediate representation layer which has not been flattened. The application simplifies the scan chain insertion process and significantly improves the efficiency.

Description

Technical Field

[0001] This invention relates to the field of accelerated simulation and prototype verification of FPGA-based digital logic design, and particularly to an intermediate representation layer scan chain insertion method and system based on a modular strategy. Background Technology

[0002] Scan chain-based observation and debugging techniques are important methods used in Design for Testability (DFT) of digital logic chips after silicon. The scan chain method essentially involves replacing or enriching sequential circuit elements (typically D flip-flops, on-chip memory, etc.) with scannable sequential circuit elements during chip design. Through scan interfaces reserved on the chip pins, a scan chain can be driven to read the states from each flip-flop and on-chip memory, thereby observing whether the chip is operating normally and determining whether there are problems in the chip manufacturing process.

[0003] As the scale and complexity of digital circuits increase, the number of flip-flops and on-chip memory used in circuit design also increases significantly. In FPGA design practice, scan chains typically need to be inserted into the gate-level netlist design after synthesis by logic synthesis tools. However, the synthesis steps of logic synthesis tools often modify the signal names in the netlist in batches (the synthesis process requires optimization of the original design code, involving numerous transformation operations, including changing net names, merging structures, recoding, and cross-module signal optimization, resulting in significant differences between the netlist and the original design's RTL code, making it difficult to map the saved circuit states back to the original design code, causing difficulties for later work). The significant differences between the signal names in the output gate-level netlist and the original design's RTL signal names create inconvenience for scan chain insertion. How to more effectively integrate into the logic synthesis tool's processing flow to address the difficulties caused by changes in netlist signal names has become a key technical issue.

[0004] Considering that for most logic synthesis tools, the RTL in the original design is processed primarily using the Intermediate Representation (IR) level, where signal names remain substantially unchanged. Furthermore, the IR level provides a unified description for various flip-flops and on-chip RAM, making it easy to identify and locate the target component to be inserted into the scan chain. Therefore, this invention proposes a method for inserting a scan chain at the IR level.

[0005] However, the implementation of directly inserting scan chains at the intermediate representation level exhibits significant performance degradation when applied to scan chain insertion in large-scale logic designs. Analysis revealed that the performance degradation stems from the fact that directly inserting the intermediate representation layer netlist, which is processed by the logic synthesis tool's default flattening layer, leads to unnecessary duplicate instantiation of the same module, which is instantiated layer by layer using a copying method. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention proposes an intermediate representation layer scan chain insertion method based on a modular strategy, which includes:

[0007] Step 1: Obtain the original design including the circuit to be tested. Based on the structural module relationship of the original design, construct a directed acyclic graph. In the directed acyclic graph, the vertices represent the intermediate representation layer modules involved, and each directed edge represents the logical relationship of the upper module instantiating the lower target sub-module.

[0008] Step 2: Perform a reverse topological sort on the directed acyclic graph. Starting from the lowest-level module in the instantiation relationship of the directed acyclic graph, insert a scan chain. Create a pair of input and output ports for each scan chain, and insert scan chains into the upper-level modules level by level until the top-level module in the instantiation relationship of the directed acyclic graph is inserted into the scan chain.

[0009] The intermediate representation layer scan chain insertion method based on the modular strategy takes into account that the intermediate representation layer netlist after flattening no longer contains the original design's structural hierarchy information, and the scan chain will be inserted into the intermediate representation layer netlist that has not been flattened.

[0010] The intermediate representation layer scan chain insertion method based on the modular strategy, wherein step 2 of the scan chain insertion process includes:

[0011] Construct and insert a scan chain oriented towards triggers;

[0012] Construct and insert scan chains for on-chip memory.

[0013] The intermediate representation layer scan chain insertion method based on the modular strategy is described, wherein the scan chains are connected in series or in parallel.

[0014] This invention also proposes an intermediate representation layer scan chain insertion system based on a modular strategy, which includes:

[0015] The directed acyclic graph (DAG) construction module is used to obtain the original design including the circuit under test. Based on the structural module relationship of the original design, a DAG is constructed. In the DAG, the vertices represent the intermediate representation layer modules involved, and each directed edge represents the logical relationship between the upper module and the lower target sub-module.

[0016] The scan chain insertion module is used to perform reverse topological sorting on the directed acyclic graph. Starting from the lowest-level module in the instantiation relationship of the directed acyclic graph, a scan chain is inserted. A pair of input and output ports is created for each scan chain, and scan chains are inserted into the upper-level modules level by level until the top-level module in the instantiation relationship of the directed acyclic graph is inserted into the scan chain.

[0017] The intermediate representation layer scan chain insertion system based on the modular strategy takes into account that the intermediate representation layer netlist after flattening no longer contains the original design's structural hierarchy information, and the scan chain will be inserted into the intermediate representation layer netlist that has not been flattened.

[0018] The intermediate representation layer scan chain insertion system based on a modular strategy, wherein the process of inserting a scan chain in the scan chain insertion module includes:

[0019] Construct and insert a scan chain oriented towards triggers;

[0020] Construct and insert scan chains for on-chip memory.

[0021] The intermediate representation layer scan chain insertion system based on a modular strategy is described above, wherein the scan chains are connected in series or in parallel.

[0022] The present invention also proposes a server, including the aforementioned intermediate presentation layer scan chain insertion device.

[0023] The present invention also proposes a storage medium for storing a computer program of the intermediate representation layer scan chain insertion method.

[0024] As can be seen from the above solutions, the advantages of the present invention are:

[0025] The method for inserting scan chains at intermediate representation levels proposed in this invention integrates more effectively into the logic synthesis tool's processing flow, addressing the issue of netlist signal name differences arising during the synthesis process. Based on key point 1, a general modular strategy is proposed. Through a bottom-up insertion method based on DAG inverse topology sorting, it ensures that each module instantiation only needs to be processed once. This avoids the unnecessary repetitive work that would occur when logic synthesis tools directly insert IR netlists processed by default at flattened levels, which would otherwise lead to layered instantiation of the same module using a copying method. This improves the efficiency of scan chain insertion. Attached Figure Description

[0026] Figure 1 This is a hierarchical diagram of the original design (Design Under Test, DUT).

[0027] Figure 2 This is the abstracted directed acyclic graph;

[0028] Figure 3 A schematic diagram of a method for modularizing scan chain insertion. Detailed Implementation

[0029] To address the aforementioned issues, this invention proposes a general modular strategy based on the idea of ​​inserting scan chains at the intermediate representation level. In this strategy, the scan chain insertion process is performed on the unmodified intermediate representation layer netlist.

[0030] This invention first obtains the original design, which can be as follows: Figure 1 As shown, for example: A is a network module inside an FPGA; B is a MAC layer data processing module; C is a PHY layer data processing module; D is a DMA module; and E is a FIFO buffer module. The MAC layer data processing module, PHY layer data processing module, and DMA module all require FIFO buffers internally, and these three together form the entire network module. It can be considered that A contains modules B, C, and D, and each of modules B, C, and D contains module E, ultimately forming... Figure 1 The module hierarchy is shown.

[0031] Secondly, the original design is abstracted into a Directed Acyclic Graph (DAG), where vertices represent intermediate representation layer modules involved, and each directed edge represents the logical relationship between the upper-level module and the lower-level target sub-module instantiation (e.g., ...). Figure 2 (As shown).

[0032] Furthermore, we propose a bottom-up scanning chain insertion algorithm based on DAG inverse topological sorting (e.g., Figure 3 (As shown), this ensures that each module instantiation only needs to be processed once. When traversing the module vertices, the scan chains of triggers and on-chip memory in the module are inserted first. The scan chains inserted in each instantiated submodule are connected together based on all outgoing edges of the current vertex.

[0033] Finally, a pair of input and output ports is created for each scan chain in the current module.

[0034] Through the above steps, the top-down construction process is completed, with the final stage of the traversal reaching the top-level module. After the traversal is finished, a scan chain containing all sequential logic units in the design is built into the top-level module.

[0035] By applying the intermediate representation layer scan chain insertion method based on the modular strategy described in this invention, after performing a scan chain insertion operation on an intermediate representation layer that has not been flattened, the intermediate representation layer code can be sent back to the logic synthesis tool to continue other subsequent processing flows.

[0036] To make the above-mentioned features and effects of the present invention clearer and easier to understand, specific embodiments are described below in conjunction with the accompanying drawings. This specification discloses one or more embodiments incorporating the features of the present invention. The disclosed embodiments are merely illustrative. The scope of protection of the present invention is not limited to the disclosed embodiments, but is defined by the appended claims.

[0037] The implementation method of directly inserting scan chains into the intermediate representation layer exhibits significant performance degradation when applied to scan chain insertion in large-scale logic designs. Analysis revealed that the performance degradation is caused by the fact that directly inserting IR netlists, which are processed by the logic synthesis tool at its default flattening level, results in unnecessary repetitive work being performed on the same module instantiated in a copy-based manner.

[0038] To address the aforementioned problems, this invention proposes a general modular strategy based on the idea of ​​inserting scan chains into the intermediate representation layer. In this strategy, the process of inserting scan chains is performed on the unmodified intermediate representation layer netlist.

[0039] First, we will look at the original design (such as...) Figure 1 As shown, assuming the top-level module is A, and A instantiates three sub-modules B, C, and D, which in turn instantiate the same sub-module E, this can be abstracted as a Directed Acyclic Graph (DAG). Vertices represent intermediate representation modules (nodes in the DAG), and each directed edge represents the logical relationship between the source module and the target sub-module (e.g., ...). Figure 2 (as shown);

[0040] Then, we propose a bottom-up insertion algorithm based on DAG inverse topological sorting to ensure that the instantiation of each module only needs to be processed once (e.g., Figure 3 As shown, by performing a reverse topological sort on the DAG, the hierarchy and instantiation relationships of each module in the design can be clearly defined. Therefore, processing begins with module E at the lowest level of the instantiation relationship, iterating upwards through modules B, C, and D, and finally processing the top-level module A. When traversing module vertices, the scan chains of triggers and on-chip memory within the module are inserted first. The scan chains inserted into each instantiated submodule are connected together based on all outgoing edges from the current vertex.

[0041] Finally, a pair of input and output ports is created for each scan chain in the current module.

[0042] After the traversal is complete, a scan chain containing all the sequential logic units in the design is built into the top-level module.

[0043] The following are system embodiments corresponding to the above method embodiments. This embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0044] This invention also proposes an intermediate representation layer scan chain insertion system based on a modular strategy, including:

[0045] The directed acyclic graph (DAG) construction module is used to obtain the original design including the circuit under test. Based on the structural module relationship of the original design, a DAG is constructed. In the DAG, the vertices represent the intermediate representation layer modules involved, and each directed edge represents the logical relationship between the upper module and the lower target sub-module.

[0046] The scan chain insertion module is used to perform reverse topological sorting on the directed acyclic graph. Starting from the lowest-level module in the instantiation relationship of the directed acyclic graph, a scan chain is inserted. A pair of input and output ports is created for each scan chain, and scan chains are inserted into the upper-level modules level by level until the top-level module in the instantiation relationship of the directed acyclic graph is inserted into the scan chain.

[0047] The intermediate representation layer scan chain insertion system based on the modular strategy, wherein when performing the flattening level operation during the logic synthesis tool process, considering that the intermediate representation layer netlist that has completed the flattening process no longer contains the structural hierarchy information of the original design, the scan chain will be inserted into the intermediate representation layer netlist that has not undergone flattening.

[0048] The intermediate representation layer scan chain insertion system based on a modular strategy, wherein the process of inserting a scan chain in the scan chain insertion module includes:

[0049] Construct and insert a scan chain oriented towards triggers;

[0050] Construct and insert scan chains for on-chip memory.

[0051] The intermediate representation layer scan chain insertion system based on a modular strategy is described above, wherein the scan chains are connected in series or in parallel.

[0052] The present invention also proposes a server, including the aforementioned intermediate presentation layer scan chain insertion device.

[0053] The present invention also proposes a storage medium for storing a computer program of the intermediate representation layer scan chain insertion method.

[0054] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A method for inserting an intermediate representation layer scan chain based on a modular strategy, characterized in that, include: Step 1: Obtain the original design including the circuit to be tested. Based on the structural module relationship of the original design, construct a directed acyclic graph. In the directed acyclic graph, the vertices represent the intermediate representation layer modules involved, and each directed edge represents the logical relationship of the upper module instantiating the lower target sub-module. Step 2: Perform reverse topological sorting on the directed acyclic graph. Starting from the lowest-level module in the instantiation relationship of the directed acyclic graph, insert a scan chain. Create a pair of input and output ports for each scan chain, and insert scan chains into the upper-level modules level by level until the top-level module in the instantiation relationship of the directed acyclic graph is inserted into the scan chain. In step 2, the scan chain will be inserted into the intermediate representation layer netlist that has not been flattened. The process of inserting the scan chain includes: constructing and inserting a scan chain oriented towards triggers; and constructing and inserting a scan chain oriented towards on-chip memory.

2. The intermediate representation layer scan chain insertion method based on a modular strategy as described in claim 1, characterized in that, The scanning chains are connected in series or in parallel.

3. A modular strategy-based intermediate representation layer scan chain insertion system, characterized in that, include: The directed acyclic graph (DAG) construction module is used to obtain the original design including the circuit under test. Based on the structural module relationship of the original design, a DAG is constructed. In the DAG, the vertices represent the intermediate representation layer modules involved, and each directed edge represents the logical relationship between the upper module and the lower target sub-module. The scan chain insertion module is used to perform reverse topological sorting on the directed acyclic graph. Starting from the lowest level module in the instantiation relationship of the directed acyclic graph, a scan chain is inserted. A pair of input and output ports is created for each scan chain, and scan chains are inserted into the upper-level modules level by level until the top-level module in the instantiation relationship of the directed acyclic graph is inserted into the scan chain. The scan chain insertion module inserts the scan chain into the intermediate representation layer netlist that has not been flattened. The process of inserting the scan chain in the scan chain insertion module includes: constructing and inserting a scan chain oriented towards triggers; Construct and insert scan chains for on-chip memory.

4. The intermediate representation layer scan chain insertion system based on a modular strategy as described in claim 3, characterized in that, The scanning chains are connected in series or in parallel.

5. A server, characterized in that, Including the intermediate representation layer scan chain insertion system based on a modular strategy as described in claim 3 or 4.

6. A storage medium for storing a computer program that performs the intermediate representation layer scan chain insertion method based on a modular strategy as described in claim 1 or 2.

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