Method and system for physical implementation of two-level synchronous register based on clustering

Abstract

The application discloses a kind of two-stage synchronous register based on clustering physical implementation method and system, the present application includes grabbing all registers;Filter out two-stage synchronous register;For each group of two-stage synchronous register: determine the new position of second stage register;Second stage register clock pin is re-mounted to the clock pin source of first stage register;The moving distance between the original position of second stage register, new position is greater than the two-stage synchronous register of preset threshold value is optimized in sequence;Two-stage synchronous register eliminates unit overlap, and the clock pin connection of two-stage synchronous register is clustered optimization, finally check, repair completion processing.The present application intervenes in the process of layout and wiring, the position of two-stage synchronous register and clock signal connection are placed and intervened, ensure that two-stage synchronous register is not interfered with by other signals when working, while not affecting other logic.

Description

Technical Field

[0001] This invention relates to the field of very large-scale integrated circuit design, and specifically to a physical implementation method and system for a two-level synchronization register based on clustering. Background Technology

[0002] In integrated circuit design, using multiple clock signals with different frequencies can lead to metastability issues. This means that signals transmitted across clock domains may experience unstable or unknown data states after register sampling due to insufficient setup or hold times. To mitigate metastability, a two-stage register synchronization process is typically employed. In cross-clock domain data transmission circuits, using a synchronization register with an additional synchronization signal from the first clock domain ensures stable and reliable data sampling with minimal logic resources. Therefore, during placement and routing, to ensure consistent sampling between the two-stage synchronization registers, their positions must be relatively close, and their clock (CK) inputs must originate from the same source. However, in actual placement and routing, excessive local density and the interference of related logic connections can cause the positions of the two-stage synchronization registers to be affected by other related logic, resulting in larger distances between registers in the same group and premature clock forking. Summary of the Invention

[0003] The technical problem to be solved by this invention is to provide a physical implementation method and system for two-level synchronous registers based on clustering, which addresses the above-mentioned problems in the prior art. This invention aims to provide a standardized design process for dynamically intervening in the placement and routing of two-level synchronous registers according to timing conditions. Through the design process, the placement, clock mounting, inspection and repair of two-level synchronous registers are realized, so that the two-level synchronous registers meet the conditions of close proximity and clock consistency.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A physical implementation method for a two-level synchronization register based on clustering includes: S101: Capture all registers in the physical design state file after cell layout is completed and before clock tree optimization. S102, select two-level synchronization registers from all captured registers; S103, for each group of two-level synchronization registers: determine the new position of the second-level register based on the position of the first-level register and the original position of the second-level register; check whether the clock pin sources of the first-level register and the second-level register are consistent. If they are inconsistent, reattach the clock pin of the second-level register to the clock pin source of the first-level register; determine whether the movement distance between the original position and the new position of the second-level register is greater than a preset threshold. If it is, perform timing optimization on the two-level synchronization registers. S104, eliminates cell overlap between the two-stage synchronization registers, and checks whether the number of fan-outs on the clock pin connection of each two-stage synchronization register exceeds a preset threshold. If it exceeds the preset threshold, it is optimized based on a clustering algorithm. S105, in the physical design status file after the placement and routing process is completed, check whether the positions of each group of two-level synchronization registers are close and whether the sources of the clock pins are consistent, and write the check results into the check report. S106: Determine whether there are two-level synchronization registers that failed the inspection in the inspection report. If there are two-level synchronization registers that failed the inspection, repair them.

[0005] Optionally, step S102 includes: searching for registers with a specified tag from all captured registers, adding the first-level register to the first-level register list syn_reg_lev1, and adding the second-level register to the second-level register list syn_reg_lev2; traversing the registers in all captured registers that do not contain the specified tag, and for the current register cur_reg1 and its corresponding previous-level register cur_reg0 and next-level register cur_reg2 obtained from the traversal, if there is no functional logic between the output of the current register cur_reg1 and the input of the next-level register cur_reg2, and the clock signal sources of the current register cur_reg1 and the next-level register cur_reg2 are the same, while the clock signal sources of the previous-level register cur_reg0 and the current register cur_reg1 are different, then it is determined that the current register cur_reg1 and the next-level register cur_reg2 belong to two-level synchronous registers, and the current register cur_reg1 is added as a first-level register to the first-level register list syn_reg_lev1, and the next-level register cur_reg2 is added as a second-level register to the second-level register list syn_reg_lev2.

[0006] Optionally, step S103, which involves determining the new location of the second-level register based on the location of the first-level register and the original location of the second-level register, includes: S201, obtain the position (x1, y1), length len1, and height h1 of the first-level register reg1; S202, based on the index of the first-level register reg1 in the first-level register list syn_reg_lev1, obtain the corresponding second-level register reg2, and then obtain the position (x2, y2), length len2, and height h2 of the second-level register reg2; S203, the position (x1, y1), length len1, and height h1 of the first-level register reg1, and the position (x2, y2), length len2, and height h2 of the second-level register reg2 determine the initial range of the second-level register reg2's position: box0. The lower left corner coordinates of the range box0 are (box0_llx, box0_lly), and the upper right corner coordinates are (box0_urx, box0_ury). Where: if x2>= If x1 is true, the value of the bottom left x-coordinate box0_llx is x1; otherwise, the value of the bottom left x-coordinate box0_llx is x1-len2. If y2>=y1 is true, the value of the bottom left y-coordinate box0_lly is y1; otherwise, the value of the bottom left y-coordinate box0_lly is y1-h2. The value of the top right x-coordinate box0_urx is the sum of the bottom left x-coordinate box0_llx, length len1, and length len2. The value of the top right y-coordinate box0_ury is the sum of the bottom left y-coordinate box0_lly, height h1, and height h2. S204. Determine whether there is an immovable unit in the initial range box0 of the second-level register reg2. If there is an immovable unit, determine the value of the new position (x2', y2') of the second-level register as (box0_llx, box0_lly). Otherwise, determine the value of the new position (x2', y2') of the second-level register as (box0_llx, box0_lly+h1).

[0007] Optionally, step S103, which checks whether the clock pin sources of the first-level register and the second-level register are consistent, and if they are inconsistent, reattaching the clock pin of the second-level register to the clock pin source of the first-level register, includes: capturing the connection names of the clock pin sources of the first-level register reg1 and the second-level register reg2 respectively, determining whether the connection names of the clock pin sources of the first-level register reg1 and the second-level register reg2 are the same, and if they are not the same, disconnecting the clock pin of the second-level register reg2 from the original connection name, and then connecting the clock pin of the second-level register reg2 to the connection name of the clock pin source of the first-level register reg1.

[0008] Optionally, when determining whether the movement distance between the original and new positions of the second-level register is greater than a preset threshold in step S103, the calculation function expression for the movement distance between the original and new positions of the second-level register is: d2=|x2-x2'|+|y2-y2'|; the timing optimization of the two-level synchronization register in step S103 includes: determining whether there are redundant buffers or paired inverters between the first-level register and the second-level register of the two-level synchronization register; if there are redundant buffers or paired inverters, then the redundant buffers or paired inverters are deleted.

[0009] Optionally, step S104 includes: S301 sets all two-level synchronization registers to a movable state, moves two-level synchronization registers with overlapping cells to eliminate cell overlap, and sets all two-level synchronization registers to a non-movable state. S302, obtain the connections of the clock pins of all two-level synchronization registers and add them to the connection set; S303, iterate through each connection in the connection set, and for each connection obtained through iteration: determine whether the fan-out count on the connection exceeds the preset threshold Fout_max. If it exceeds the preset threshold, optimize based on a clustering algorithm. The number of groups (num) and the group size (Fout_half_max) are calculated using the following formula: num = roundup(Fout_net / Fout_max), Fout_half_max = rounddown (Fout_max / 2), In the above formula, `roundup` represents rounding up, `Fout_net` is the number of fan-outs on the connection, `Fout_max` is a preset threshold, and `rounddown` represents rounding down. Based on all the first-level registers `cur_reg1s` fan-out on the connection, obtain the coordinate set of these first-level registers `cur_reg1s`, and find the minimum and maximum values ​​of the x-coordinates `x0_min` and `x0_max`, as well as the minimum and maximum values ​​of the y-coordinates `y0_min` and `y0_max`. Based on the minimum and maximum values ​​of the x-coordinates `x0_min` and `x0_max`, and the minimum and maximum values ​​of the y-coordinates `y0_min` and `y0_max`, randomly generate a group of `num` coordinate sets (`xc_init`, ...) within the rectangular area defined by `(x0_min, y0_min)` and `(x0_max, y0_max)`. yc_init) serves as the initialization center point for the clustering algorithm; the clustering algorithm is used to divide all the first-level registers cur_reg1s fanned out on this connection into num groups according to the group size Fout_half_max, and obtains the register list of each group and its final geometric center coordinate set (xc_final, yc_final); num buffers are inserted on this connection, and each buffer drives the first-level registers in num groups and their corresponding second-level registers; S304: Reacquire the clock pin connections of all two-level synchronization registers and add them to a new connection set. Set the properties of all connections in the new connection set to immobile state, and also set the directly associated units of all connections in the new connection set to immobile state.

[0010] Optionally, step S105 includes: S401, in the physical design status file after the placement and routing process is completed, obtain the full names of all two-level synchronization registers and put them into the register list ff_reg_list. Starting from the first group of two-level synchronization registers put into the register list ff_reg_list, denote the first-level register in the two-level synchronization registers as reg1 and the second-level register as reg2. The coordinates of the lower left corner of the first-level register reg1 are (x1, y1) and the coordinates of the second-level register reg2 are (x2, y2). S402, traverse each group of two-level synchronization registers in the register list ff_reg_list. For each group of two-level synchronization registers obtained through traversal: take the lower left corner coordinates (x1, y1) of the first-level register reg1 as the center, and the required distance d between the first-level register reg1 and the second-level register reg2 as the radius to obtain a rectangular area range_box. The coordinates of the lower left corner of the rectangular area range_box are (x1-d, y1-d), and the coordinates of the upper right corner are (x1+d, y1+d). If the second-level register reg2 is within the rectangular area range_box, and the clock pin connections of the first-level register reg1 and the second-level register reg2 are consistent, then the check result of this group of two-level synchronization registers is determined to be passed. If the second-level register reg2 is not within the rectangular area range_box, or the clock pin connections of the first-level register reg1 and the second-level register reg2 are inconsistent, then the check result of this group of two-level synchronization registers is determined to be failed. Write the check result into the check report.

[0011] Optionally, step S106 includes: S501: Determine if there are any failed two-level synchronization registers in the inspection report. If so, repair them: If the failure is due to inconsistent clock pin connections for the first-level register reg1 and the second-level register reg2, reconnect the clock pin connection for the second-level register reg2 to the clock pin connection for the first-level register reg1; if the failure is due to the second-level register reg2 not being within the rectangular area range_box, first determine the new position of the second-level register based on its original position and the position of the first-level register. Then, determine if the movement distance between the original and new positions of the second-level register is greater than a preset threshold. If so, perform timing optimization on the two-level synchronization registers. S502, export the netlist and perform an equivalence check to ensure functional consistency; if it passes, proceed to step S503; otherwise, find the inconsistencies, make the necessary modifications, and execute step S502 again. S503 uses the commands provided by the tool to optimize the routing.

[0012] Furthermore, the present invention also provides a physical implementation system for a cluster-based two-level synchronization register, comprising an interconnected microprocessor and a memory, wherein the microprocessor is programmed or configured to execute the physical implementation method of the cluster-based two-level synchronization register.

[0013] Furthermore, the present invention also provides a computer-readable storage medium storing a computer program for being programmed or configured by a microprocessor to execute the physical implementation method of the clustering-based two-level synchronization register.

[0014] Compared with the prior art, the present invention has the following advantages: The physical implementation method of the two-level synchronous register based on clustering provides a standardized design process for dynamically intervening in the position layout of the two-level synchronous registers according to the timing situation during the placement and routing process. The design process realizes the placement, clock mounting, inspection and repair of the two-level synchronous registers. By intervening in the position placement and clock signal connection of the two-level synchronous registers during the placement and routing process, it is ensured that the two-level synchronous registers are not interfered with by other signals when they are working, and at the same time, they do not affect other logic, so that the two-level synchronous registers meet the conditions of close position and consistent clock. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the basic process of the method in an embodiment of the present invention.

[0016] Figure 2 This is a schematic diagram illustrating the principle of clustering and grouping in the embodiment of the present invention. Detailed Implementation

[0017] like Figure 1 As shown, the physical implementation method of the two-level synchronization register based on clustering in this embodiment includes: S101: Capture all registers in the physical design state file after cell layout is completed and before clock tree optimization. S102, select two-level synchronization registers from all captured registers; S103, for each group of two-level synchronization registers: determine the new position of the second-level register based on the position of the first-level register and the original position of the second-level register; check whether the clock pin sources of the first-level register and the second-level register are consistent. If they are inconsistent, reattach the clock pin of the second-level register to the clock pin source of the first-level register; determine whether the movement distance between the original position and the new position of the second-level register is greater than a preset threshold. If it is, perform timing optimization on the two-level synchronization registers. S104, Fan-out optimization: Eliminate cell overlap in the two-stage synchronization registers and check whether the fan-out on the clock pin connection of each two-stage synchronization register exceeds a preset threshold. If it exceeds the preset threshold, optimization is performed based on a clustering algorithm. S105, Check: In the physical design status file after the placement and routing process is completed, check whether the positions of each group of two-stage synchronization registers are close and whether the sources of the clock pins are consistent, and write the check results into the check report. S106, Repair: Determine whether there are two-level synchronization registers that failed the inspection in the inspection report. If there are two-level synchronization registers that failed the inspection, then repair the two-level synchronization registers that failed the inspection.

[0018] Step S101 is used to capture all registers in the physical design state file (db) after the cell layout is completed and before the clock tree optimization, and obtain the full name (full_name) of all instantiated registers in this design. In order to facilitate subsequent processing, this embodiment puts all captured registers into a custom list reg_list.

[0019] In this embodiment, step S102 includes: searching for registers containing a specified tag (such as "syn_ff") from all captured registers; adding the first-level register to the first-level register list syn_reg_lev1; and adding the second-level register to the second-level register list syn_reg_lev2. For registers in all captured registers that do not contain the specified tag, traverse the current register cur_reg1 and its corresponding previous-level register cur_reg0 and next-level register cur_reg2. If the output (Q-terminal) of the current register cur_reg1 is less than the output (Q-terminal) of the next-level register cur_reg2... If there is no functional logic between the input terminals (D terminals) of g2, and the clock signal sources of the current register cur_reg1 and the next-level register cur_reg2 are the same, while the clock signal sources of the previous-level register cur_reg0 and the current register cur_reg1 are different, then it is determined that the current register cur_reg1 and the next-level register cur_reg2 belong to two-level synchronous registers. The current register cur_reg1 is added as the first-level register to the first-level register list syn_reg_lev1, and the next-level register cur_reg2 is added as the second-level register to the second-level register list syn_reg_lev2.

[0020] In this embodiment, step S103, determining the new location of the second-level register based on the location of the first-level register and the original location of the second-level register, includes: S201, obtain the position (x1, y1), length len1, and height h1 of the first-level register reg1; S202, based on the index of the first-level register reg1 in the first-level register list syn_reg_lev1, obtain the corresponding second-level register reg2, and then obtain the position (x2, y2), length len2, and height h2 of the second-level register reg2; S203, the position (x1, y1), length len1, and height h1 of the first-level register reg1, and the position (x2, y2), length len2, and height h2 of the second-level register reg2 determine the initial range of the second-level register reg2's position: box0. The lower left corner coordinates of the range box0 are (box0_llx, box0_lly), and the upper right corner coordinates are (box0_urx, box0_ury). Where: if x2>= If x1 is true, the value of the bottom-left x-coordinate box0_llx is x1; otherwise, the value of the bottom-left x-coordinate box0_llx is x1-len2. If y2>=y1, the value of the bottom-left y-coordinate box0_lly is y1; otherwise, the value of the bottom-left y-coordinate box0_lly is y1-h2. The value of the top-right x-coordinate box0_urx is the sum of the bottom-left x-coordinate box0_llx, length len1, and length len2. The value of the top-right y-coordinate box0_ury is the sum of the bottom-left y-coordinate box0_lly, height h1, and height h2. This can be represented as: box0_llx = (x2>= x1) ? x1: x1-len2; box0_lly = (y2>=y1) ? y1 : y1-h2; box0_urx = box0_llx + len1 + len2; box0_ury = box0_lly + h1 + h2; In this case, (x2>= x1) ? x1 : x1-len2 is a ternary operator, x2>= x1 is the condition, x1 is the result of the condition being true (box0_llx= x1), and x1-len2 is the result of the condition being false (box0_llx= x1-len2). Similarly, in (y2>=y1) ? y1 : y1-h2, y2>=y1 is the condition, y1 is the result of the condition being true (box0_lly = y1), and y1-h2 is the result of the condition being false (box0_lly = y1-h2). S204. Determine whether there is an immovable unit in the initial range box0 of the second-level register reg2. If there is an immovable unit, determine the value of the new position (x2', y2') of the second-level register as (box0_llx, box0_lly). Otherwise, determine the value of the new position (x2', y2') of the second-level register as (box0_llx, box0_lly+h1).

[0021] In this embodiment, step S103, checking whether the clock pins (clk1 and clk2) of the first-level register and the second-level register have the same source, and if they do not, reattaching the clock pin of the second-level register to the clock pin source of the first-level register includes: grabbing the connection names (denoted as net1 and net2) of the clock pin source of the first-level register reg1 and the second-level register reg2 respectively, and determining whether the connection names of the clock pin source of the first-level register reg1 and the second-level register reg2 are the same (i.e., whether net1 and net2 are the same). If they are not the same, disconnecting the clock pin of the second-level register reg2 from the original connection name, and then connecting the clock pin of the second-level register reg2 to the connection name of the clock pin source of the first-level register reg1 (disconnecting the clk terminal of reg2 from net2 and connecting the clk terminal of reg2 to net1).

[0022] In this embodiment, when determining whether the movement distance between the original and new positions of the second-level register is greater than a preset threshold in step S103, the calculation function expression for the movement distance between the original and new positions of the second-level register is: d2=|x2-x2'|+|y2-y2'|; the timing optimization of the two-level synchronization register in step S103 includes: determining whether there are redundant buffers or paired inverters between the first-level register and the second-level register of the two-level synchronization register; if there are redundant buffers or paired inverters, then the redundant buffers or paired inverters are deleted. Furthermore, tools can be used to further optimize the position of the logic unit connected to the output of the second-level register.

[0023] In this embodiment, step S104 includes: S301 sets all two-stage synchronization registers to the placed state, moves two-stage synchronization registers with cell overlap to eliminate cell overlap, and sets all two-stage synchronization registers to the fixed state to avoid changing the position of these synchronization registers in subsequent placement and routing steps. S302, obtain the connections of the clock pins of all two-level synchronization registers and add them to the connection set all_syn_clk_nets; S303, iterate through each connection in the set all_syn_clk_nets, and for each connection obtained, determine whether the fan-out count of the connection exceeds the preset threshold Fout_max. If it exceeds the preset threshold, optimize based on a clustering algorithm. The number of groups (num) and the group size (Fout_half_max) are calculated using the following formula: num = roundup(Fout_net / Fout_max), Fout_half_max = rounddown (Fout_max / 2), In the above formula, `roundup` represents rounding up, `Fout_net` is the number of fan-outs on the connection, `Fout_max` is a preset threshold, and `rounddown` represents rounding down. Based on all the first-level registers `cur_reg1s` fan-out on the connection, obtain the coordinate set of these first-level registers `cur_reg1s`, and find the minimum and maximum values ​​of the x-coordinates `x0_min` and `x0_max`, as well as the minimum and maximum values ​​of the y-coordinates `y0_min` and `y0_max`. Based on the minimum and maximum values ​​of the x-coordinates `x0_min` and `x0_max`, and the minimum and maximum values ​​of the y-coordinates `y0_min` and `y0_max`, randomly generate a group of `num` coordinate sets (`xc_init`, ...) within the rectangular area defined by `(x0_min, y0_min)` and `(x0_max, y0_max)`. yc_init) serves as the initialization center point for the clustering algorithm; using the K-means clustering algorithm (or other clustering algorithms), all first-level registers cur_reg1s fanned out on this connection are divided into num groups according to the group size Fout_half_max, and the register list of each group and its final geometric center coordinate set (xc_final, yc_final) are obtained; num buffers are inserted on this connection, and each buffer drives the first-level registers in num groups and their corresponding second-level registers; Figure 2 This diagram illustrates clustering and grouping. The clock signal my_clk_net1 is connected to 14 sets of two-level synchronization registers. The first-level registers are numbered reg1_1, reg1_2...reg1_14, far exceeding the number of Fout_max. Figure 2(Calculated as 10), then it needs to be divided into num1 = roundup(28 / 10) = 3 groups; the range of box1 can be determined by these 14 level 1 registers, and then 3 random coordinates are generated as the initial geometric centers of the 3 groups; after grouping by K-means clustering algorithm, it is finally divided into 3 groups. The level 1 register set of the first group is {reg1_1, reg1_2, reg1_3, reg1_6, reg1_8}, {reg1_4, reg1_5, reg1_11, reg1_12, reg1_13}, {reg1_7, reg1_9, reg1_10, reg1_14}; as Figure 2 As shown, in this embodiment, three buffers, BUF_g1, BUF_g2, and BUF_g3, are inserted to drive the three groups of Level 1 registers, respectively. It should be noted that the corresponding Level 2 registers are also ultimately mounted on their respective lines; for example, the Level 2 register reg2_1 corresponding to reg1_1 is mounted under BUF_g1. Figure 2 This detail is not shown in order to emphasize the grouping of the Level 1 registers; S304: Reacquire the clock pin connections of all two-stage synchronization registers and add them to a new connection set all_syn_clk_nets_new. Set the attribute of all connections in the new connection set all_syn_clk_nets_new to the dontTouch state, and also set the directly associated units of all connections in the new connection set to the dontTouch state.

[0024] In this embodiment, step S105 includes: S401, in the physical design status file (db) after the placement and routing process is completed, obtain the full name (full_name) of all two-level synchronization registers and put them into the register list ff_reg_list. Starting from the first group of two-level synchronization registers put into the register list ff_reg_list, denote the first-level register in the two-level synchronization registers as reg1 and the second-level register as reg2. The coordinates of the lower left corner of the first-level register reg1 are (x1, y1) and the coordinates of the second-level register reg2 are (x2, y2). S402, traverse each group of two-level synchronization registers in the register list ff_reg_list. For each group of two-level synchronization registers obtained through traversal: take the lower left corner coordinates (x1, y1) of the first-level register reg1 as the center, and the required distance d between the first-level register reg1 and the second-level register reg2 as the radius to obtain a rectangular area range_box. The coordinates of the lower left corner of the rectangular area range_box are (x1-d, y1-d), and the coordinates of the upper right corner are (x1+d, y1+d). If the second-level register reg2 is within the rectangular area range_box, and the clock pin connections of the first-level register reg1 and the second-level register reg2 are consistent, then the check result of this group of two-level synchronization registers is determined to be passed. If the second-level register reg2 is not within the rectangular area range_box, or the clock pin connections of the first-level register reg1 and the second-level register reg2 are inconsistent, then the check result of this group of two-level synchronization registers is determined to be failed. Write the check result into the check report. In this embodiment, the report format for a pass result is "PASS! reg1 and reg2"; the report format for a fail result is "FAIL! reg1: (x1, y1) net: net1 reg2: (x2, y2) net: net2". In this embodiment, step S106 includes: S501: Determine if there are any failed two-level synchronization registers in the inspection report. If so, repair them: If the failure is due to inconsistent clock pin connections for the first-level register reg1 and the second-level register reg2, reconnect the clock pin connection for the second-level register reg2 to the clock pin connection for the first-level register reg1; if the failure is due to the second-level register reg2 not being within the rectangular area range_box, first determine the new position of the second-level register based on its original position and the position of the first-level register. Then, determine if the movement distance between the original and new positions of the second-level register is greater than a preset threshold. If so, perform timing optimization on the two-level synchronization registers. S502, export the netlist and perform an equivalence check to ensure functional consistency; if it passes, proceed to step S503; otherwise, find the inconsistencies, make the necessary modifications, and execute step S502 again. S503 uses commands provided by the tool to optimize routing.

[0025] In summary, the physical implementation method of the two-level synchronization register based on clustering in this embodiment provides a standardized design process for dynamically intervening in the placement and routing of the two-level synchronization registers according to the timing situation. Through the design process, the placement, clock mounting, inspection and repair of the two-level synchronization registers are realized, so that the two-level synchronization registers meet the conditions of close proximity and clock consistency.

[0026] Furthermore, this embodiment also provides a physical implementation system for a cluster-based two-level synchronization register, including an interconnected microprocessor and a memory, wherein the microprocessor is programmed or configured to execute the physical implementation method of the cluster-based two-level synchronization register.

[0027] Furthermore, this embodiment also provides a computer-readable storage medium storing a computer program for being programmed or configured by a microprocessor to execute the physical implementation method of the clustering-based two-level synchronization register.

[0028] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0029] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A physical implementation method for a two-level synchronization register based on clustering, characterized in that, include: S101: Capture all registers in the physical design state file after cell layout is completed and before clock tree optimization. S102, select two-level synchronization registers from all captured registers; S103, for each group of two-level synchronization registers: determine the new position of the second-level register based on the position of the first-level register and the original position of the second-level register; Check if the clock pin sources of the first-level register and the second-level register are consistent. If they are inconsistent, reattach the clock pin of the second-level register to the clock pin source of the first-level register. Determine if the movement distance between the original position and the new position of the second-level register is greater than a preset threshold. If it is, perform timing optimization on the two-level synchronization registers. S104, eliminates cell overlap between the two-stage synchronization registers, and checks whether the number of fan-outs on the clock pin connection of each two-stage synchronization register exceeds a preset threshold. If it exceeds the preset threshold, it is optimized based on a clustering algorithm. S105, in the physical design status file after the placement and routing process is completed, check whether the positions of each group of two-level synchronization registers are close and whether the sources of the clock pins are consistent, and write the check results into the check report. S106, determine whether there are two-level synchronization registers that failed the inspection in the inspection report. If there are two-level synchronization registers that failed the inspection, repair the two-level synchronization registers that failed the inspection. Step S104 includes: S301 sets all two-level synchronization registers to a movable state, moves two-level synchronization registers with overlapping cells to eliminate cell overlap, and sets all two-level synchronization registers to a non-movable state. S302, obtain the connections of the clock pins of all two-level synchronization registers and add them to the connection set; S303, iterate through each connection in the connection set, and for each connection obtained through iteration: determine whether the fan-out count on the connection exceeds the preset threshold Fout_max. If it exceeds the preset threshold, optimize based on a clustering algorithm. The number of groups (num) and the group size (Fout_half_max) are calculated using the following formula: num = roundup(Fout_net / Fout_max), Fout_half_max = rounddown (Fout_max / 2), In the above formula, `roundup` represents rounding up, `Fout_net` is the number of fan-outs on the connection, `Fout_max` is a preset threshold, and `rounddown` represents rounding down. Based on all the first-level registers `cur_reg1s` fanned out on the connection, the coordinate set of these first-level registers `cur_reg1s` is obtained, and the minimum and maximum values ​​of the x-coordinates `x0_min` and `x0_max`, as well as the minimum and maximum values ​​of the y-coordinates `y0_min` and `y0_max`, are found from the coordinate set. Based on the minimum and maximum values ​​of the x-coordinates `x0_min` and `x0_max`, and the minimum and maximum values ​​of the y-coordinates `y0_min` and `y0_max`, a random number of coordinate sets `num` (xc_init, ...) are generated within the rectangular area defined by (x0_min, y0_min) and (x0_max, y0_max). yc_init) serves as the initialization center point for the clustering algorithm; the clustering algorithm is used to divide all the first-level registers cur_reg1s fanned out on this connection into num groups according to the group size Fout_half_max, and obtains the register list of each group and its final geometric center coordinate set (xc_final, yc_final); num buffers are inserted on this connection, and each buffer drives the first-level registers in num groups and their corresponding second-level registers; S304: Reacquire the clock pin connections of all two-level synchronization registers and add them to a new connection set. Set the properties of all connections in the new connection set to immobile state, and also set the directly associated units of all connections in the new connection set to immobile state.

2. The physical implementation method of a two-level synchronization register based on clustering according to claim 1, characterized in that, Step S102 includes: searching for registers with a specified tag from all captured registers, adding the first-level register to the first-level register list syn_reg_lev1, and adding the second-level register to the second-level register list syn_reg_lev2; traversing the registers in all captured registers that do not contain the specified tag, and for the current register cur_reg1 and its corresponding previous-level register cur_reg0 and next-level register cur_reg2 obtained from the traversal, if there is no functional logic between the output of the current register cur_reg1 and the input of the next-level register cur_reg2, and the clock signal sources of the current register cur_reg1 and the next-level register cur_reg2 are the same, while the clock signal sources of the previous-level register cur_reg0 and the current register cur_reg1 are different, then it is determined that the current register cur_reg1 and the next-level register cur_reg2 belong to two-level synchronous registers, and the current register cur_reg1 is added as a first-level register to the first-level register list syn_reg_lev1, and the next-level register cur_reg2 is added as a second-level register to the second-level register list syn_reg_lev2.

3. The physical implementation method of a two-level synchronization register based on clustering according to claim 1, characterized in that, Step S103, determining the new location of the second-level register based on the location of the first-level register and the original location of the second-level register, includes: S201, obtain the position (x1, y1), length len1, and height h1 of the first-level register reg1; S202, based on the index of the first-level register reg1 in the first-level register list syn_reg_lev1, obtain the corresponding second-level register reg2, and then obtain the position (x2, y2), length len2, and height h2 of the second-level register reg2; S203, the position (x1, y1), length len1, and height h1 of the first-level register reg1, and the position (x2, y2), length len2, and height h2 of the second-level register reg2 determine the initial range of the second-level register reg2's position: box0. The lower left corner coordinates of the range box0 are (box0_llx, box0_lly), and the upper right corner coordinates are (box0_urx, box0_ury). Where: if x2>= If x1 is true, the value of the bottom left x-coordinate box0_llx is x1; otherwise, the value of the bottom left x-coordinate box0_llx is x1-len2. If y2>=y1 is true, the value of the bottom left y-coordinate box0_lly is y1; otherwise, the value of the bottom left y-coordinate box0_lly is y1-h2. The value of the top right x-coordinate box0_urx is the sum of the bottom left x-coordinate box0_llx, length len1, and length len2. The value of the top right y-coordinate box0_ury is the sum of the bottom left y-coordinate box0_lly, height h1, and height h2. S204. Determine whether there is an immovable unit in the initial range box0 of the second-level register reg2. If there is an immovable unit, determine the value of the new position (x2', y2') of the second-level register as (box0_llx, box0_lly). Otherwise, determine the value of the new position (x2', y2') of the second-level register as (box0_llx, box0_lly+h1).

4. The physical implementation method of a two-level synchronization register based on clustering according to claim 1, characterized in that, Step S103, checking whether the clock pin sources of the first-level register and the second-level register are consistent, and if they are inconsistent, reattaching the clock pin of the second-level register to the clock pin source of the first-level register includes: capturing the connection names of the clock pin sources of the first-level register reg1 and the second-level register reg2 respectively, determining whether the connection names of the clock pin sources of the first-level register reg1 and the second-level register reg2 are the same, and if they are not the same, disconnecting the clock pin of the second-level register reg2 from the original connection name, and then connecting the clock pin of the second-level register reg2 to the connection name of the clock pin source of the first-level register reg1.

5. The physical implementation method of a two-level synchronization register based on clustering according to claim 3, characterized in that, In step S103, when determining whether the movement distance between the original and new positions of the second-level register is greater than a preset threshold, the calculation function expression for the movement distance between the original and new positions of the second-level register is: d2=|x2-x2'|+|y2-y2'|; Step S103 includes timing optimization of the two-level synchronization registers: determining whether there are redundant buffers or paired inverters between the first-level register and the second-level register of the two-level synchronization registers. If there are redundant buffers or paired inverters, the redundant buffers or paired inverters are deleted.

6. The physical implementation method of a two-level synchronization register based on clustering according to claim 1, characterized in that, Step S105 includes: S401, in the physical design status file after the placement and routing process is completed, obtain the full names of all two-level synchronization registers and put them into the register list ff_reg_list. Starting from the first group of two-level synchronization registers put into the register list ff_reg_list, denote the first-level register in the two-level synchronization registers as reg1 and the second-level register as reg2. The coordinates of the lower left corner of the first-level register reg1 are (x1, y1) and the coordinates of the second-level register reg2 are (x2, y2). S402, traverse each group of two-level synchronization registers in the register list ff_reg_list. For each group of two-level synchronization registers obtained through traversal: take the lower left corner coordinates (x1, y1) of the first-level register reg1 as the center, and obtain a rectangular area range_box according to the required distance d between the first-level register reg1 and the second-level register reg2. The coordinates of the lower left corner of the rectangular area range_box are (x1-d, y1-d), and the coordinates of the upper right corner are (x1+d, y1+d). If the second-level register reg2 is within the rectangular area range_box, and the clock pin connections of the first-level register reg1 and the second-level register reg2 are consistent, then the check result of this group of two-level synchronization registers is determined to be passed. If the second-level register reg2 is not within the rectangular area range_box, or the clock pin connections of the first-level register reg1 and the second-level register reg2 are inconsistent, then the check result of this group of two-level synchronization registers is determined to be failed. Write the check result into the check report.

7. The physical implementation method of a two-level synchronization register based on clustering according to claim 1, characterized in that, Step S106 includes: S501: Determine if there are any failed two-level synchronization registers in the inspection report. If so, repair them: If the failure is due to inconsistent clock pin connections between the first-level register reg1 and the second-level register reg2, reconnect the clock pin connection of the second-level register reg2 to the clock pin connection of the first-level register reg1; if the failure is due to the second-level register reg2 not being within the rectangular area range_box, first determine the new position of the second-level register based on the position of the first-level register and its original position, then determine if the movement distance between the original and new positions of the second-level register is greater than a preset threshold. If so, perform timing optimization on the two-level synchronization registers. S502, export the netlist and perform an equivalence check to ensure functional consistency; if it passes, proceed to step S503; otherwise, find the inconsistencies, make the necessary modifications, and execute step S502 again. S503 uses the commands provided by the tool to optimize the routing.

8. A physical implementation system of a clustering-based two-level synchronization register, comprising an interconnected microprocessor and a memory, characterized in that, The microprocessor is programmed or configured to execute the physical implementation method of the cluster-based two-level synchronization register as described in any one of claims 1 to 7.

9. A computer-readable storage medium storing a computer program, characterized in that, The computer program is used to be programmed or configured by a microprocessor to execute the physical implementation method of the cluster-based two-level synchronization register according to any one of claims 1 to 7.

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