A rapid calculation method and apparatus for temperature distribution in a three-dimensional integrated system

Abstract

This invention discloses a rapid calculation method and apparatus for the temperature distribution of a three-dimensional integrated system. The rapid calculation method includes: analyzing the structural characteristics of the three-dimensional integrated system and extracting equivalent element models for each layer of stacked chips in the system; solving for the anisotropic equivalent thermal conductivity based on the equivalent element models; constructing an equivalent thermal model using the anisotropic equivalent thermal conductivity; dividing the equivalent thermal model into mesh elements and constructing temperature equations; and calculating the temperature at each mesh element point using the temperature equations, thus obtaining the temperature distribution of the three-dimensional integrated system. The rapid calculation apparatus includes an equivalent thermal conductivity calculation module, an equivalent thermal model establishment module, an adaptive element division module, a heat source excitation and calculation module, and an iteration maintenance and termination module. The rapid calculation method and apparatus of this invention can achieve rapid temperature distribution calculation for structurally complex three-dimensional integrated systems, improving solution efficiency and accuracy.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to a method and apparatus for rapid calculation of temperature distribution in a three-dimensional integrated system. Background Technology

[0002] Three-dimensional integration technology based on through-silicon vias (TSVs) is currently experiencing rapid development. It's a novel packaging method that involves bonding and stacking circuit modules or chips with different functions vertically. Compared to traditional two-dimensional planar packaging, three-dimensional integration technology offers advantages such as reduced latency, improved performance, lower power consumption, smaller package size, and ultimately lower costs. In recent years, the urgent need for high-performance, high-bandwidth, and high-power-density systems in the integrated circuit industry has spurred the rapid development of three-dimensional integration technology. However, due to the increased power density and extremely limited thermal conductivity between stacked layers, the temperature constraints of three-dimensional integrated systems are considered a key factor limiting the technology's development.

[0003] A three-dimensional power distribution network (PDN) mainly consists of an on-chip PDN, power / ground TSVs, and micro-solder balls. Serving as the electrical transmission path for powering active devices and transmitting signals in a three-dimensional integrated system, it primarily uses metal interconnects and penetrates all layers of the system, possessing strong heat dissipation capabilities and significantly alleviating system thermal problems. However, current research lacks a complete and accurate equivalent thermal model that considers the heat dissipation effect of a three-dimensional PDN for rapid calculation of its temperature distribution.

[0004] The structure of three-dimensional integrated systems is quite complex, making it difficult to construct thermal analytical models to solve for their temperature distribution. Although finite element simulation tools can accurately characterize their temperature details, their computational efficiency is too low, which will consume a lot of time in thermal design. Existing numerical calculation methods either cannot characterize the horizontal temperature distribution of three-dimensional integrated systems or are not accurate enough, with large errors. For example, for TSVs, a more accurate model can be obtained in the vertical direction by equating them with lumped thermal resistance, but in the horizontal direction, the relevant model is either not considered or misestimated due to oversimplification. For on-chip PDNs, the current mainstream method is to equate them with a simple series-parallel thermal resistance network, ignoring many related influencing factors, resulting in reduced solution accuracy. Summary of the Invention

[0005] The purpose of this invention is to provide a rapid calculation method and apparatus for temperature distribution in a three-dimensional integrated system. The technical solution adopted by this invention is as follows:

[0006] A rapid method for calculating the temperature distribution of a three-dimensional integrated system includes the following steps:

[0007] S1: Analyze the structural characteristics of the three-dimensional integrated system and extract the equivalent unit model of each layer of the stacked chips in the three-dimensional integrated system;

[0008] S2: Solve for the anisotropic equivalent thermal conductivity based on the equivalent unit model;

[0009] S3: Construct an equivalent thermal model using the anisotropic equivalent thermal conductivity.

[0010] S4: Divide the equivalent thermal model into mesh elements and construct the temperature solution equation;

[0011] S5: Calculate the temperature at each grid cell point using the temperature solving equation to obtain the temperature distribution of the three-dimensional integrated system.

[0012] In one embodiment of the present invention, S1 includes:

[0013] S11: Analyze the composition and distribution of each layer of the stacked chips in the three-dimensional integrated system;

[0014] S12: Divide the composition and distribution of each layer of the stacked chip into a single layer, including a back-end process layer composed of an on-chip power distribution network, an active device layer containing through-silicon vias and a silicon substrate layer, and an inter-chip bonding layer containing micro solder balls.

[0015] S13: Extract the equivalent unit model of the back-end process layer, the active device layer, the silicon substrate layer and the inter-chip bonding layer.

[0016] In one embodiment of the present invention, S2 includes:

[0017] S21: By setting the heat source power density of the boundary surface and its temperature relative to the boundary surface, the average temperature of the boundary surface to which the heat source is applied is calculated to solve the anisotropic equivalent thermal conductivity of the downstream process layer unit.

[0018] S22: Based on the thermal resistance theory, the active device layer unit is equivalent to a thermal resistance network along each heat flow direction to solve its anisotropic equivalent thermal conductivity;

[0019] S23: Based on the thermal resistance theory, the silicon substrate layer unit is equivalent to a thermal resistance network along each heat flow direction to solve its anisotropic equivalent thermal conductivity.

[0020] S24: Based on the thermal resistance theory, the interlayer adhesive layer unit is equivalent to a thermal resistance network along each heat flow direction to solve its anisotropic equivalent thermal conductivity.

[0021] In one embodiment of the present invention, S21 includes:

[0022] The equivalent thermal conductivity of the subsequent process layer in each direction is as follows:

[0023]

[0024]

[0025]

[0026] Where, k x_BEOLcell Let k be the equivalent thermal conductivity of the element along the x-direction. y_BEOLcell Let k be the equivalent thermal conductivity of the unit along the y-direction. z_BEOLcell p is the equivalent thermal conductivity of the element along the z-direction. wire The spacing between adjacent metal interconnects in the same metal wiring layer, where n is the number of metal wiring layers, and t is the distance between adjacent metal interconnects. wire h is the thickness of the metal interconnect. μ-via S represents the height of the micro-via. left S front and S bottom T represents the surface heat source power density applied to the left, front, and lower boundaries of the unit, respectively. left T right T front T behind T bottom and T top These are the surface average temperatures of the left, right, front, rear, lower, and upper boundaries of the unit, respectively.

[0027] In one embodiment of the present invention, S23 includes:

[0028] In the vertical direction, the equivalent thermal conductivity of the silicon substrate layer unit is expressed as:

[0029]

[0030] Where, k z_SUBcell Let r be the equivalent thermal conductivity of the unit along the z-direction, l and w be the spacing between adjacent through-silicon vias in the x and y directions, respectively. TSV t is the radius of the metal filling the through-silicon via. ox k represents the thickness of the silicon dioxide insulating layer in the through-silicon via. Si k SiO2 and k Cu The thermal conductivity of silicon, silicon dioxide, and copper are respectively.

[0031] In the horizontal direction, the silicon substrate unit can be divided into 5 regions, namely q1, q... 2,1 q 2,2 q 2,3 and q3, where q1, q 2,1 q 2,3Both q3 and q4 contain only substrate silicon. 2,2 For the diameter 2(r) of the through-silicon via structure TSV +t ox The square region, q1, q2, and q3, is a composite material consisting of copper filler, silicon dioxide insulating material, and silicon substrate. These regions are connected in series. 2,1 q 2,2 and q 2,3 Since they are connected in parallel, their equivalent thermal conductivities along the x and y directions are respectively:

[0032]

[0033]

[0034]

[0035]

[0036] Where, k x_SUBcell Let k be the equivalent thermal conductivity of the element along the x-direction. y_SUBcell Let be the equivalent thermal conductivity of this unit along the y-direction. l and w are the spacings of adjacent through-silicon vias in the x and y directions, respectively, and r TSV t is the radius of the metal filling the through-silicon via. ox k represents the thickness of the silicon dioxide insulating layer in the through-silicon via. Si k SiO2 and k Cu The thermal conductivity values ​​are for silicon, silicon dioxide, and copper, respectively.

[0037] In one embodiment of the present invention, S3 includes:

[0038] The back-end process layer, the active device layer, the silicon substrate layer, and the inter-chip adhesive layer, which are composed of composite materials, are replaced with single dielectric materials having the anisotropic equivalent thermal conductivity, respectively, to construct the equivalent thermal model of the three-dimensional integrated system.

[0039] In one embodiment of the present invention, S4 includes:

[0040] S41: Considering the trade-off between solution accuracy and efficiency, the equivalent thermal model is meshed:

[0041] In the horizontal direction, the spacing between adjacent through-silicon vias in the stacked chips is used as the fixed size of the grid cells, achieving a trade-off between solution accuracy and efficiency;

[0042] In the vertical direction, fine mesh elements are used at the boundaries of each layer to ensure solution accuracy, while coarse mesh elements are used within each layer to improve solution efficiency.

[0043] S42: Constructing temperature solution equations based on adaptive element difference iterative method.

[0044] In one embodiment of the present invention, S42 includes:

[0045] The three-dimensional steady-state heat conduction equation in a solid is:

[0046]

[0047] in, k is a space-related temperature parameter. x k y and k z , where are the thermal conductivity of the material along the x, y, and z directions, respectively, and S is the power density of the space heat source;

[0048] Integrating the volume element of the above formula, we can obtain

[0049]

[0050] Where (i, j, k) are the coordinates of the center grid point of the discrete unit, and Δx i Δy j and Δz k Let represent the dimensions of the grid cell in the x, y, and z directions, respectively; T(i, j, k) be the temperature at grid cell (i, j, k); S(i, j, k) be the power density of the heat source at grid cell (i, j, k); and k be the temperature at grid point (i, j, k). i，i+1 It is the effective thermal conductivity at the interface between grid cells (i, j, k) and (i+1, j, k), according to Fourier's law. Effective thermal conductivity k at other interfaces i,i-1 ,k j,j+1 ,k j,j-1 ,k k,k+1 and k k,k-1 Defined in a similar manner, the iterative calculation formula can be obtained as follows:

[0051] α(i,j,k)T(i,j,k)=α(i+1,j,k)T(i+1,j,k)+α(i-1,j,k)T(i-1,j,k)

[0052] +α(i,j+1,k)T(i,j+1,k)+α(i,j-1,k)T(i,j-1,k)

[0053] +α(i,j,k+1)T(i,j,k+1)+α(i,j,k-1)T(i,j,k-1)

[0054] +S(i,j,k)Δx i Δy j Δz k ,

[0055] This is the temperature solution equation, where,

[0056]

[0057] T(i+1, j, k) represents the temperature at grid point (i+1, j, k), T(i-1, j, k) represents the temperature at grid point (i-1, j, k), T(i, j+1, k) represents the temperature at grid point (i, j+1, k), T(i, j-1, k) represents the temperature at grid point (i, j-1, k), T(i, j, k+1) represents the temperature at grid point (i, j, k+1), and T(i, j, k-1) represents the temperature at grid point (i, j, k-1).

[0058] In one embodiment of the present invention, S5 includes:

[0059] S51: Set the initial values ​​and boundary conditions for the equivalent thermal model:

[0060] Set the top boundary temperature of the top heat sink to room temperature (300K), and set all other boundaries to adiabatic.

[0061] The initial iteration temperature was set to room temperature of 300K, and the active device was set as the main heat source, while the three-dimensional power distribution network was set as the secondary heat source.

[0062] S52: Set the iteration termination condition for the equivalent thermal model:

[0063] |Av.T-Av.T old |≤e

[0064] in, n x n y and n z These represent the number of grid cells divided into the model along the x, y, and z directions, respectively, and e is the iteration termination error threshold;

[0065] If the iteration termination condition is not met, then let T old After T is obtained, the iteration continues to calculate T(i,j,k) until the condition is met. Then, the iteration stops and the final calculation result is output, thus completing the rapid calculation of the temperature distribution of the three-dimensional integrated system.

[0066] A rapid calculation device for temperature distribution in a three-dimensional integrated system includes: an equivalent thermal conductivity solution module, an equivalent thermal model establishment module, an adaptive element partitioning module, a heat source excitation and calculation module, and an iteration maintenance and termination module.

[0067] The equivalent thermal model establishment module is connected to the equivalent thermal conductivity solution module, the adaptive element partitioning module is connected to the equivalent thermal model establishment module, the heat source excitation and calculation module is connected to the adaptive element partitioning module, and the iteration maintenance and termination module is connected to the heat source excitation and calculation module.

[0068] The equivalent thermal conductivity solving module is used to extract equivalent element models for each layer of the three-dimensional integrated system and solve for their anisotropic equivalent thermal conductivity.

[0069] The equivalent thermal model building module is used to replace material property parameters based on the anisotropic equivalent thermal conductivity to construct an equivalent thermal model;

[0070] The adaptive element partitioning module is used to adaptively partition the equivalent thermal model into mesh elements and construct the temperature solution equation based on the adaptive element differential iteration method.

[0071] The heat source excitation and calculation module is used to apply heat source excitation to the equivalent thermal model, set initial values ​​and boundary conditions, and calculate the temperature distribution of the equivalent thermal model using the temperature solution equation.

[0072] The iteration maintenance and termination module is used to control the iterative solution process. When the iteration termination condition is not met, the result is updated and the iterative calculation continues. When the iteration termination condition is met, the iteration stops and the solution result is output, thus completing the rapid calculation of the temperature distribution of the three-dimensional integrated system.

[0073] The beneficial effects of this invention are:

[0074] The present invention provides a rapid calculation method and apparatus for the temperature distribution of a three-dimensional integrated system. This method performs equivalent thermal modeling of the three-dimensional integrated system and establishes a solution equation based on the adaptive element difference iterative method. The equation is used to iteratively calculate the temperature of each grid cell point. The iteration stops when the termination condition is met, and the final solution result is output, thus completing the rapid calculation of the temperature distribution of the three-dimensional integrated system. This rapid calculation method enables fast temperature distribution calculation for structurally complex three-dimensional integrated systems, improving solution efficiency and reducing the time cost of thermal design. Simultaneously, it offers high accuracy, avoiding performance differences between the actual chip and simulation predictions caused by incorrect estimations of the temperature characteristics of the three-dimensional integrated system. Attached Figure Description

[0075] Figure 1A flowchart illustrating a rapid calculation method for temperature distribution in a three-dimensional integrated system provided in an embodiment of the present invention;

[0076] Figure 2 This is a schematic diagram of the distribution of each layer of a single-layer stacked chip in a three-dimensional integrated system provided in an embodiment of the present invention;

[0077] Figure 3 A three-dimensional structural schematic diagram of the on-chip PDN equivalent unit provided in an embodiment of the present invention;

[0078] Figure 4 A top-view perspective view of the on-chip PDN equivalent unit provided in an embodiment of the present invention;

[0079] Figure 5 A side cross-sectional view of the on-chip PDN equivalent unit provided in an embodiment of the present invention;

[0080] Figure 6 A schematic diagram of the equivalent thermal resistance network of the TSV equivalent unit in the vertical direction provided in an embodiment of the present invention;

[0081] Figure 7 A schematic diagram of the equivalent thermal resistance network of the TSV equivalent unit in the horizontal direction provided in an embodiment of the present invention;

[0082] Figure 8 This is a structural block diagram of a rapid calculation device for temperature distribution in a three-dimensional integrated system provided in an embodiment of the present invention. Detailed Implementation

[0083] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0084] This embodiment provides a rapid method for calculating the temperature distribution of a three-dimensional integrated system, as shown in the appendix. Figure 1 The fast calculation method includes the following steps:

[0085] S1: Analyze the structural characteristics of the three-dimensional integrated system and extract the equivalent unit model of each layer of the stacked chips in the three-dimensional integrated system;

[0086] S2: Solve for the anisotropic equivalent thermal conductivity based on the equivalent element model;

[0087] S3: Construct an equivalent thermal model using anisotropic equivalent thermal conductivity;

[0088] S4: Mesh the equivalent thermal model and construct the temperature solution equation;

[0089] S5: Calculate the temperature at each grid cell point using the temperature solving equation, thus obtaining the temperature distribution of the three-dimensional integrated system.

[0090] In one embodiment of the present invention, S1 includes:

[0091] S11: Analyze the composition and distribution of each layer of stacked chips in a three-dimensional integrated system;

[0092] S12: Delineate the layer composition and distribution of a single-layer stacked chip. Refer to the appendix for the layer distribution of a single-layer stacked chip in a 3D integrated system. Figure 2 It mainly includes the back end of line (BEOL) layer, which is composed of stacked chip PDN consisting of interlayer dielectric (ILD) material and copper metal interconnects, the active device layer containing TSV, the silicon substrate layer, and the inter-chip bonding layer containing micro solder balls.

[0093] S13: Extract the equivalent unit model of the back-end process layer, active device layer, silicon substrate layer and inter-chip bonding layer.

[0094] The equivalent unit of the back-end process layer composed of an on-chip PDN structure provided in the embodiments of the present invention is shown in the attached figure. Figure 3 Appendix Figure 4 and attached Figure 5 The equivalent unit of the silicon substrate layer including the TSV structure provided in the embodiments of the present invention is shown in the attached figure. Figure 6 and attached Figure 7 The active device layer containing TSVs and the inter-chip bonding layer containing micro-solder balls have similar structures to the silicon substrate layer containing TSVs, and therefore their equivalent units are also similar, which will not be described in detail here.

[0095] In an embodiment of the present invention, S2 includes:

[0096] S21: By setting the heat source power density of the boundary surface and its temperature relative to the boundary surface, the average temperature of the boundary surface to which the heat source is applied is calculated to solve the anisotropic equivalent thermal conductivity of the downstream process layer unit.

[0097] S22: Based on the thermal resistance theory, the active device layer unit is equivalent to a thermal resistance network along each heat flow direction to solve its anisotropic equivalent thermal conductivity;

[0098] S23: Based on the thermal resistance theory, the silicon substrate layer unit is equivalent to a thermal resistance network along each heat flow direction to solve its anisotropic equivalent thermal conductivity.

[0099] S24: Based on the thermal resistance theory, the interlayer adhesive layer unit is equivalent to a thermal resistance network along each heat flow direction to solve its anisotropic equivalent thermal conductivity.

[0100] For back-end processing layers composed of on-chip PDNs, due to their intricate and complex structure, the equivalent thermal conductivity in each direction should be calculated by setting boundary conditions and then using the adaptive element differential iteration method to calculate the differences between relevant boundary temperatures. The anisotropic equivalent thermal conductivity of the back-end processing layer elements are as follows:

[0101]

[0102]

[0103]

[0104] Where, k x_BEOLcell Let k be the equivalent thermal conductivity of the element along the x-direction. y_BEOLcell Let k be the equivalent thermal conductivity of the unit along the y-direction. z_BEOLcell Let p be the equivalent thermal conductivity of the element along the z-direction. wire The spacing between adjacent metal interconnects in the same metal wiring layer, where n is the number of metal wiring layers, and t is the distance between adjacent metal interconnects. wire t represents the thickness of the metal interconnect. μ-via S represents the height of the micro-via. left S front and S bottom T represents the surface heat source power density applied to the left, front, and lower boundaries of the unit, respectively. left T right T front T behind T bottom and T top These are the surface average temperatures of the left, right, front, rear, lower, and upper boundaries of the unit, respectively.

[0105] For active device layers and substrate layers containing TSVs, as well as inter-chip bonding layers containing micro solder balls, their structures are roughly similar and relatively simple. Therefore, the methods for solving their anisotropic equivalent thermal conductivity are similar, and they can all be solved by using thermal resistance theory to treat them as equivalent thermal resistance networks along each heat flow direction.

[0106] Taking a substrate containing TSV as an example, in the vertical direction, the TSV-filled metal, the oxide insulating layer, and the silicon substrate can be equivalently represented as three parallel thermal resistors. Therefore, its equivalent thermal conductivity is expressed as:

[0107]

[0108] Where, k z_SUBcell Let r be the equivalent thermal conductivity of the element along the z-direction, l and w be the spacing between adjacent TSVs in the x and y directions, respectively. TSV The radius of the filler metal for TSV, t ox k represents the thickness of the TSV silicon dioxide insulating layer. Si k SiO2 and k Cu The thermal conductivity values ​​are for silicon, silicon dioxide, and copper, respectively.

[0109] In the horizontal direction, the silicon substrate layer unit can be divided into 5 regions, namely q1, q... 2,1 q 2,2 q 2,3 and q3, where q1, q 2,1 q 2,3 Both q3 and q4 contain only substrate silicon. 2,2 The diameter of the through-silicon via structure is 2(r) TSV +t ox The square region, q1, q2, and q3, is a composite material consisting of copper filler, silicon dioxide insulating material, and silicon substrate. These regions are connected in series. 2,1 q 2,2 and q 2,3 Since they are connected in parallel, their equivalent thermal conductivities along the x and y directions are respectively:

[0110]

[0111]

[0112]

[0113]

[0114] Where, k x_SUBcell Let k be the equivalent thermal conductivity of the element along the x-direction. y_SUBcell Let be the equivalent thermal conductivity of this unit along the y-direction. l and w are the distances between adjacent TSVs in the x and y directions, respectively, and r TSV The radius of the filler metal for TSV, t ox k represents the thickness of the TSV silicon dioxide insulating layer. Si k SiO2 and k Cu The thermal conductivity values ​​are for silicon, silicon dioxide, and copper, respectively.

[0115] In an embodiment of the present invention, S3 includes: replacing the back-end process layer, active device layer, silicon substrate layer and inter-chip adhesive layer made of composite materials with a single dielectric material having anisotropic equivalent thermal conductivity, respectively, to construct an equivalent thermal model of the three-dimensional integrated system, thereby simplifying its structure from intricate and complex.

[0116] In an embodiment of the present invention, S4 includes:

[0117] S41: Mesh generation of the equivalent thermal model considering the trade-off between solution accuracy and efficiency:

[0118] In the horizontal direction, the spacing between adjacent through-silicon vias in the stacked chips is used as the fixed size of the grid cells, achieving a trade-off between solution accuracy and efficiency;

[0119] In the vertical direction, fine mesh elements are used at the boundaries of each layer to ensure solution accuracy, while coarse mesh elements are used within each layer to improve solution efficiency.

[0120] S42: Constructing temperature solution equations based on adaptive element difference iterative method.

[0121] The three-dimensional steady-state heat conduction equation in a solid is:

[0122]

[0123] in, k is a space-related temperature parameter. x k y and k z , where are the thermal conductivity of the material along the x, y, and z directions, respectively, and S is the power density of the space heat source;

[0124] Integrating the volume element of the above formula, we can obtain

[0125]

[0126] Where (i, j, k) are the coordinates of the center grid point of the discrete unit, and Δx i Δy j and Δz k Let represent the dimensions of the grid cell in the x, y, and z directions, respectively; T(i, j, k) be the temperature at grid cell (i, j, k); S(i, j, k) be the power density of the heat source at grid cell (i, j, k); and k be the temperature at grid point (i, j, k). i，i+1 It is the effective thermal conductivity at the interface between grid cells (i, j, k) and (i+1, j, k), according to Fourier's law. Effective thermal conductivity k at other interfaces i,i-1 ,k j,j+1 ,k j,j-1 ,k k,k+1 and k k,k-1 Defined in a similar manner, the iterative calculation formula can be obtained as follows:

[0127] α(i,j,k)T(i,j,k)=α(i+1,j,k)T(i+1,j,k)+α(i-1,j,k)T(i-1,j,k)

[0128] +α(i,j+1,k)T(i,j+1,k)+α(i,j-1,k)T(i,j-1,k)

[0129] +α(i,j,k+1)T(i,j,k+1)+α(i,j,k-1)T(i,j,k-1)

[0130] +S(i,j,k)Δx i Δy j Δz k ,

[0131] This is the temperature solution equation, where,

[0132]

[0133] T(i+1, j, k) represents the temperature at grid point (i+1, j, k), T(i-1, j, k) represents the temperature at grid point (i-1, j, k), T(i, j+1, k) represents the temperature at grid point (i, j+1, k), T(i, j-1, k) represents the temperature at grid point (i, j-1, k), T(i, j, k+1) represents the temperature at grid point (i, j, k+1), and T(i, j, k-1) represents the temperature at grid point (i, j, k-1).

[0134] In an embodiment of the present invention, S5 includes:

[0135] S51: Set the initial values ​​and boundary conditions for the equivalent thermal model:

[0136] Considering that most 3D integrated systems use flip-chip packaging, the top boundary temperature of the top heat sink is set to room temperature 300K, and all other boundaries are set to adiabatic. The initial iteration temperature is set to room temperature 300K, and active devices are set as the main heat source, while the 3D power distribution network is set as the secondary heat source.

[0137] S52: Set the iteration termination condition for the equivalent thermal model:

[0138] |Av.T-Av.T old |≤e

[0139] in, n x n y and n z These represent the number of grid cells divided along the x, y, and z directions, respectively, and e is the iteration termination error threshold.

[0140] If the iteration termination condition is not met, then let T old After T is obtained, the iteration continues to calculate T(i,j,k) until the condition is met. Then, the iteration stops and the final calculation result is output, thus completing the rapid calculation of the temperature distribution of the three-dimensional integrated system.

[0141] This invention also provides a rapid calculation device for temperature distribution in a three-dimensional integrated system, as shown in the attached figure. Figure 8 The rapid computing device includes: an equivalent thermal conductivity solution module 1, an equivalent thermal model establishment module 2, an adaptive element partitioning module 3, a heat source excitation and calculation module 4, and an iteration maintenance and termination module 5. Specifically, the equivalent thermal model establishment module 2 is connected to the equivalent thermal conductivity solution module 1, the adaptive element partitioning module 3 is connected to the equivalent thermal model establishment module 2, the heat source excitation and calculation module 4 is connected to the adaptive element partitioning module 3, and the iteration maintenance and termination module 5 is connected to the heat source excitation and calculation module 4.

[0142] The equivalent thermal conductivity solution module 1 is used to extract the equivalent element model of each layer of the three-dimensional integrated system and solve its anisotropic equivalent thermal conductivity; the equivalent thermal model establishment module 2 is used to replace material property parameters according to the anisotropic equivalent thermal conductivity and construct the equivalent thermal model; the adaptive element partitioning module 3 is used to perform adaptive mesh element partitioning on the equivalent thermal model and construct the temperature solution equation based on the adaptive element differential iteration method; the heat source excitation and calculation module 4 is used to apply heat source excitation to the equivalent thermal model, set initial values ​​and boundary conditions, and calculate the temperature distribution of the equivalent thermal model using the temperature solution equation; the iteration maintenance and termination module 5 is used to control the iterative solution process, update the results and continue iterative calculation if the iteration termination condition is not met, stop the iteration and output the solution results when the iteration termination condition is met, and complete the rapid calculation of the temperature distribution of the three-dimensional integrated system.

[0143] This invention employs a step-by-step solution method. First, it solves for the anisotropic equivalent thermal conductivity of each layer of the three-dimensional integrated system. The proposed method has a faster calculation speed and smaller solution error. Then, it uses the obtained results to replace material property parameters, constructs an equivalent thermal model of the three-dimensional integrated system, and divides it into mesh elements. Based on the adaptive element differential iteration method, it solves for the temperature. Therefore, this invention has relatively higher accuracy and efficiency in calculating the temperature distribution of the three-dimensional integrated system.

[0144] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. All content that does not depart from the technical solution of the present invention should be included within the protection scope of the present invention.

Claims

1. A rapid calculation method for temperature distribution in a three-dimensional integrated system, characterized in that, Includes the following steps: S1: Analyze the structural characteristics of the three-dimensional integrated system and extract the equivalent unit model of each layer of the stacked chips in the three-dimensional integrated system; S2: Solve for the anisotropic equivalent thermal conductivity based on the equivalent unit model; S3: Construct an equivalent thermal model using the anisotropic equivalent thermal conductivity. S4: Divide the equivalent thermal model into mesh elements and construct the temperature solution equation; S5: Calculate the temperature at each grid cell point using the temperature solving equation, thus obtaining the temperature distribution of the three-dimensional integrated system; S4 includes: S41: Considering the trade-off between solution accuracy and efficiency, the equivalent thermal model is meshed: In the horizontal direction, the spacing between adjacent through-silicon vias in the stacked chips is used as the fixed size of the grid cells, achieving a trade-off between solution accuracy and efficiency; In the vertical direction, fine mesh elements are used at the boundaries of each layer to ensure solution accuracy, while coarse mesh elements are used within each layer to improve solution efficiency. S42: Constructing temperature solution equations based on adaptive element difference iterative method; The three-dimensional steady-state heat conduction equation in a solid is: in, For space-related temperature parameters, , and respectively material along , and Thermal conductivity in the direction The power density of the space heat source; Integrating the volume element of the above formula, we can obtain in, The coordinates of the center grid point of the discrete element. , and For each of the grid cells, , and Dimensions in the direction For grid cells Temperature at the grid point For grid cells The power density of the heat source, It is a grid cell and The effective thermal conductivity at the interface between the two, according to Fourier's law, Effective thermal conductivity at other interfaces and Defined in a similar manner, the iterative calculation formula can be obtained as follows: ， This is the temperature solution equation, where, For grid cells Temperature at the grid point For grid cells Temperature at the grid point For grid cells Temperature at the grid point For grid cells Temperature at the grid point For grid cells Temperature at the grid point For grid cells Temperature at the grid point.

2. The method for rapid calculation of temperature distribution in a three-dimensional integrated system according to claim 1, characterized in that, S1 includes: S11: Analyze the composition and distribution of each layer of the stacked chips in the three-dimensional integrated system; S12: Divide the composition and distribution of each layer of the stacked chip into a single layer, including a back-end process layer composed of an on-chip power distribution network, an active device layer containing through-silicon vias and a silicon substrate layer, and an inter-chip bonding layer containing micro solder balls. S13: Extract the equivalent unit model of the back-end process layer, the active device layer, the silicon substrate layer and the inter-chip bonding layer.

3. The method for rapid calculation of temperature distribution in a three-dimensional integrated system according to claim 2, characterized in that, S2 includes: S21: By setting the heat source power density of the boundary surface and its temperature relative to the boundary surface, the average temperature of the boundary surface to which the heat source is applied is calculated to solve the anisotropic equivalent thermal conductivity of the downstream process layer unit. S22: Based on the thermal resistance theory, the active device layer unit is equivalent to a thermal resistance network along each heat flow direction to solve its anisotropic equivalent thermal conductivity; S23: Based on the thermal resistance theory, the silicon substrate layer unit is equivalent to a thermal resistance network along each heat flow direction to solve its anisotropic equivalent thermal conductivity. S24: Based on the thermal resistance theory, the interlayer adhesive layer unit is equivalent to a thermal resistance network along each heat flow direction to solve its anisotropic equivalent thermal conductivity.

4. The method for rapid calculation of temperature distribution in a three-dimensional integrated system according to claim 3, characterized in that, S21 includes: The anisotropic equivalent thermal conductivity of the following downstream process layer units are as follows: ， ， ， in, For this unit along x Equivalent thermal conductivity in the direction, For this unit along y Equivalent thermal conductivity in the direction, For this unit along z Equivalent thermal conductivity in the direction, The spacing between adjacent metal interconnects in the same metal wiring layer. This refers to the number of metal wiring layers. The thickness of the metal interconnect. The height of the micro-hole , and These represent the surface heat source power densities applied to the left, front, and lower boundaries of the unit, respectively. , , , , and These are the surface average temperatures of the left, right, front, rear, lower, and upper boundaries of the unit, respectively.

5. The method for rapid calculation of temperature distribution in a three-dimensional integrated system according to claim 3, characterized in that, S23 includes: In the vertical direction, the equivalent thermal conductivity of the silicon substrate layer unit is expressed as: ， in, For this unit along Equivalent thermal conductivity in the direction, and For each adjacent through-silicon via (TSV) and Spacing in the direction, The radius of the metal filling the through-silicon via. The thickness of the silicon dioxide insulating layer for through-silicon vias. , and The thermal conductivity of silicon, silicon dioxide, and copper are respectively. In the horizontal direction, the silicon substrate layer unit can be divided into 5 regions, namely: , , ， and ,in , , and Each contains only substrate silicon. The diameter of the through-silicon via structure The square region, which is of a certain size, is a composite material composed of filled metallic copper, insulating silicon dioxide, and substrate silicon. , and The two are connected in series. , ， If they are in parallel, then their path... direction and The equivalent thermal conductivity in each direction is as follows: in, For this unit along x Equivalent thermal conductivity in the direction, For this unit along y Equivalent thermal conductivity in the direction, , , , , and For each adjacent through-silicon via (TSV) x and y Spacing in the direction, The radius of the metal filling the through-silicon via. The thickness of the silicon dioxide insulating layer for through-silicon vias. , and The thermal conductivity values ​​are for silicon, silicon dioxide, and copper, respectively.

6. The method for rapid calculation of temperature distribution in a three-dimensional integrated system according to claim 1, characterized in that, S3 includes: The back-end process layer, the active device layer, the silicon substrate layer, and the inter-chip adhesive layer, which are composed of composite materials, are replaced with single dielectric materials having the anisotropic equivalent thermal conductivity, respectively, to construct the equivalent thermal model of the three-dimensional integrated system.

7. The method for rapid calculation of temperature distribution in a three-dimensional integrated system according to claim 1, characterized in that, S5 includes: S51: Set the initial values ​​and boundary conditions for the equivalent thermal model: Set the top boundary temperature of the top heat sink to room temperature (300 K), and set all other boundaries to adiabatic. The initial iteration temperature was set to room temperature of 300 K, and the active device was set as the main heat source, while the three-dimensional power distribution network was set as the secondary heat source. S52: Set the iteration termination condition for the equivalent thermal model: in, , , and respectively model along , and The number of grid cells divided by the direction. This is the threshold for the iteration termination error. If the iteration termination condition is not met, then let Then, continue iterative calculations. The iteration continues until the conditions are met, then stops and the final calculation result is output, thus completing the rapid calculation of the temperature distribution of the three-dimensional integrated system.

8. A rapid calculation device for temperature distribution in a three-dimensional integrated system, based on the method described in any one of claims 1 to 7, characterized in that, include: The equivalent thermal conductivity solution module (1), the equivalent thermal model establishment module (2), the adaptive element partitioning module (3), the heat source excitation and calculation module (4), and the iteration maintenance and termination module (5) are all included. The equivalent thermal model establishment module (2) is connected to the equivalent thermal conductivity solution module (1), the adaptive element partitioning module (3) is connected to the equivalent thermal model establishment module (2), the heat source excitation and calculation module (4) is connected to the adaptive element partitioning module (3), and the iteration maintenance and termination module (5) is connected to the heat source excitation and calculation module (4). The equivalent thermal conductivity solution module (1) is used to extract the equivalent unit model of each layer of the three-dimensional integrated system and solve its anisotropic equivalent thermal conductivity. The equivalent thermal model building module (2) is used to replace material property parameters according to the anisotropic equivalent thermal conductivity and build an equivalent thermal model; The adaptive element partitioning module (3) is used to adaptively partition the equivalent thermal model into mesh elements and construct the temperature solution equation based on the adaptive element differential iteration method. The heat source excitation and calculation module (4) is used to apply heat source excitation to the equivalent thermal model, set initial values ​​and boundary conditions, and use the temperature solving equation to calculate the temperature distribution of the equivalent thermal model; The iteration maintenance and termination module (5) is used to control the iterative solution process. When the iteration termination condition is not met, the result is updated and iterative calculation continues. When the iteration termination condition is met, the iteration stops and the solution result is output, thus completing the rapid calculation of the temperature distribution of the three-dimensional integrated system.

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